1;; Mips.md Machine Description for MIPS based processors 2;; Copyright (C) 1989-2020 Free Software Foundation, Inc. 3;; Contributed by A. Lichnewsky, lich@inria.inria.fr 4;; Changes by Michael Meissner, meissner@osf.org 5;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and 6;; Brendan Eich, brendan@microunity.com. 7 8;; This file is part of GCC. 9 10;; GCC is free software; you can redistribute it and/or modify 11;; it under the terms of the GNU General Public License as published by 12;; the Free Software Foundation; either version 3, or (at your option) 13;; any later version. 14 15;; GCC is distributed in the hope that it will be useful, 16;; but WITHOUT ANY WARRANTY; without even the implied warranty of 17;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18;; GNU General Public License for more details. 19 20;; You should have received a copy of the GNU General Public License 21;; along with GCC; see the file COPYING3. If not see 22;; <http://www.gnu.org/licenses/>. 23 24(define_enum "processor" [ 25 r3000 26 4kc 27 4kp 28 5kc 29 5kf 30 20kc 31 24kc 32 24kf2_1 33 24kf1_1 34 74kc 35 74kf2_1 36 74kf1_1 37 74kf3_2 38 loongson_2e 39 loongson_2f 40 gs464 41 gs464e 42 gs264e 43 m4k 44 octeon 45 octeon2 46 octeon3 47 r3900 48 r6000 49 r4000 50 r4100 51 r4111 52 r4120 53 r4130 54 r4300 55 r4600 56 r4650 57 r4700 58 r5000 59 r5400 60 r5500 61 r5900 62 r7000 63 r8000 64 r9000 65 r10000 66 sb1 67 sb1a 68 sr71000 69 xlr 70 xlp 71 p5600 72 m5100 73 i6400 74 p6600 75]) 76 77(define_c_enum "unspec" [ 78 ;; Unaligned accesses. 79 UNSPEC_LOAD_LEFT 80 UNSPEC_LOAD_RIGHT 81 UNSPEC_STORE_LEFT 82 UNSPEC_STORE_RIGHT 83 84 ;; Integer operations that are too cumbersome to describe directly. 85 UNSPEC_WSBH 86 UNSPEC_DSBH 87 UNSPEC_DSHD 88 89 ;; Floating-point moves. 90 UNSPEC_LOAD_LOW 91 UNSPEC_LOAD_HIGH 92 UNSPEC_STORE_WORD 93 UNSPEC_MFHC1 94 UNSPEC_MTHC1 95 96 ;; Floating-point environment. 97 UNSPEC_GET_FCSR 98 UNSPEC_SET_FCSR 99 100 ;; HI/LO moves. 101 UNSPEC_MFHI 102 UNSPEC_MTHI 103 UNSPEC_SET_HILO 104 105 ;; GP manipulation. 106 UNSPEC_LOADGP 107 UNSPEC_COPYGP 108 UNSPEC_MOVE_GP 109 UNSPEC_POTENTIAL_CPRESTORE 110 UNSPEC_CPRESTORE 111 UNSPEC_RESTORE_GP 112 UNSPEC_EH_RETURN 113 UNSPEC_GP 114 UNSPEC_SET_GOT_VERSION 115 UNSPEC_UPDATE_GOT_VERSION 116 117 ;; Symbolic accesses. 118 UNSPEC_LOAD_CALL 119 UNSPEC_LOAD_GOT 120 UNSPEC_TLS_LDM 121 UNSPEC_TLS_GET_TP 122 UNSPEC_UNSHIFTED_HIGH 123 124 ;; MIPS16 constant pools. 125 UNSPEC_ALIGN 126 UNSPEC_CONSTTABLE 127 UNSPEC_CONSTTABLE_END 128 UNSPEC_CONSTTABLE_INT 129 UNSPEC_CONSTTABLE_FLOAT 130 131 ;; Blockage and synchronisation. 132 UNSPEC_BLOCKAGE 133 UNSPEC_CLEAR_HAZARD 134 UNSPEC_RDHWR 135 UNSPEC_SYNCI 136 UNSPEC_SYNC 137 138 ;; Cache manipulation. 139 UNSPEC_MIPS_CACHE 140 UNSPEC_R10K_CACHE_BARRIER 141 142 ;; Interrupt handling. 143 UNSPEC_ERET 144 UNSPEC_DERET 145 UNSPEC_DI 146 UNSPEC_EHB 147 UNSPEC_RDPGPR 148 UNSPEC_COP0 149 150 ;; Used in a call expression in place of args_size. It's present for PIC 151 ;; indirect calls where it contains args_size and the function symbol. 152 UNSPEC_CALL_ATTR 153 154 ;; MIPS16 casesi jump table dispatch. 155 UNSPEC_CASESI_DISPATCH 156 157 ;; Stack checking. 158 UNSPEC_PROBE_STACK_RANGE 159 160 ;; The `.insn' pseudo-op. 161 UNSPEC_INSN_PSEUDO 162]) 163 164(define_constants 165 [(TLS_GET_TP_REGNUM 3) 166 (GET_FCSR_REGNUM 2) 167 (SET_FCSR_REGNUM 4) 168 (PIC_FUNCTION_ADDR_REGNUM 25) 169 (RETURN_ADDR_REGNUM 31) 170 (CPRESTORE_SLOT_REGNUM 76) 171 (GOT_VERSION_REGNUM 79) 172 173 ;; PIC long branch sequences are never longer than 100 bytes. 174 (MAX_PIC_BRANCH_LENGTH 100) 175 ] 176) 177 178(include "predicates.md") 179(include "constraints.md") 180 181;; .................... 182;; 183;; Attributes 184;; 185;; .................... 186 187(define_attr "got" "unset,xgot_high,load" 188 (const_string "unset")) 189 190;; For jal instructions, this attribute is DIRECT when the target address 191;; is symbolic and INDIRECT when it is a register. 192(define_attr "jal" "unset,direct,indirect" 193 (const_string "unset")) 194 195;; This attribute is YES if the instruction is a jal macro (not a 196;; real jal instruction). 197;; 198;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes 199;; an instruction to restore $gp. Direct jals are also macros for 200;; !TARGET_ABSOLUTE_JUMPS because they first load the target address 201;; into a register. 202(define_attr "jal_macro" "no,yes" 203 (cond [(eq_attr "jal" "direct") 204 (symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS 205 ? JAL_MACRO_YES : JAL_MACRO_NO)") 206 (eq_attr "jal" "indirect") 207 (symbol_ref "(TARGET_CALL_CLOBBERED_GP 208 ? JAL_MACRO_YES : JAL_MACRO_NO)")] 209 (const_string "no"))) 210 211;; Classification of moves, extensions and truncations. Most values 212;; are as for "type" (see below) but there are also the following 213;; move-specific values: 214;; 215;; constN move an N-constraint integer into a MIPS16 register 216;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed 217;; to produce a sign-extended DEST, even if SRC is not 218;; properly sign-extended 219;; ext_ins EXT, DEXT, INS or DINS instruction 220;; andi a single ANDI instruction 221;; loadpool move a constant into a MIPS16 register by loading it 222;; from the pool 223;; shift_shift a shift left followed by a shift right 224;; 225;; This attribute is used to determine the instruction's length and 226;; scheduling type. For doubleword moves, the attribute always describes 227;; the split instructions; in some cases, it is more appropriate for the 228;; scheduling type to be "multi" instead. 229(define_attr "move_type" 230 "unknown,load,fpload,store,fpstore,mtc,mfc,mtlo,mflo,imul,move,fmove, 231 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool, 232 shift_shift" 233 (const_string "unknown")) 234 235(define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor,simd_add" 236 (const_string "unknown")) 237 238;; Main data type used by the insn 239(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW, 240 V2DI,V4SI,V8HI,V16QI,V2DF,V4SF" 241 (const_string "unknown")) 242 243;; True if the main data type is twice the size of a word. 244(define_attr "dword_mode" "no,yes" 245 (cond [(and (eq_attr "mode" "DI,DF") 246 (not (match_test "TARGET_64BIT"))) 247 (const_string "yes") 248 249 (and (eq_attr "mode" "TI,TF") 250 (match_test "TARGET_64BIT")) 251 (const_string "yes")] 252 (const_string "no"))) 253 254;; True if the main data type is four times of the size of a word. 255(define_attr "qword_mode" "no,yes" 256 (cond [(and (eq_attr "mode" "TI,TF") 257 (not (match_test "TARGET_64BIT"))) 258 (const_string "yes")] 259 (const_string "no"))) 260 261;; Attributes describing a sync loop. These loops have the form: 262;; 263;; if (RELEASE_BARRIER == YES) sync 264;; 1: OLDVAL = *MEM 265;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2 266;; CMP = 0 [delay slot] 267;; $TMP1 = OLDVAL & EXCLUSIVE_MASK 268;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2) 269;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK) 270;; $AT |= $TMP1 | $TMP3 271;; if (!commit (*MEM = $AT)) goto 1. 272;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot] 273;; CMP = 1 274;; if (ACQUIRE_BARRIER == YES) sync 275;; 2: 276;; 277;; where "$" values are temporaries and where the other values are 278;; specified by the attributes below. Values are specified as operand 279;; numbers and insns are specified as enums. If no operand number is 280;; specified, the following values are used instead: 281;; 282;; - OLDVAL: $AT 283;; - CMP: NONE 284;; - NEWVAL: $AT 285;; - INCLUSIVE_MASK: -1 286;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK 287;; - EXCLUSIVE_MASK: 0 288;; 289;; MEM and INSN1_OP2 are required. 290;; 291;; Ideally, the operand attributes would be integers, with -1 meaning "none", 292;; but the gen* programs don't yet support that. 293(define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none")) 294(define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none")) 295(define_attr "sync_cmp" "none,0,1,2,3,4,5" (const_string "none")) 296(define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none")) 297(define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none")) 298(define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none")) 299(define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none")) 300(define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none")) 301(define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori" 302 (const_string "move")) 303(define_attr "sync_insn2" "nop,and,xor,not" 304 (const_string "nop")) 305;; Memory model specifier. 306;; "0"-"9" values specify the operand that stores the memory model value. 307;; "10" specifies MEMMODEL_ACQ_REL, 308;; "11" specifies MEMMODEL_ACQUIRE. 309(define_attr "sync_memmodel" "" (const_int 10)) 310 311;; Accumulator operand for madd patterns. 312(define_attr "accum_in" "none,0,1,2,3,4,5" (const_string "none")) 313 314;; Classification of each insn. 315;; branch conditional branch 316;; jump unconditional jump 317;; call unconditional call 318;; load load instruction(s) 319;; fpload floating point load 320;; fpidxload floating point indexed load 321;; store store instruction(s) 322;; fpstore floating point store 323;; fpidxstore floating point indexed store 324;; prefetch memory prefetch (register + offset) 325;; prefetchx memory indexed prefetch (register + register) 326;; condmove conditional moves 327;; mtc transfer to coprocessor 328;; mfc transfer from coprocessor 329;; mthi transfer to a hi register 330;; mtlo transfer to a lo register 331;; mfhi transfer from a hi register 332;; mflo transfer from a lo register 333;; const load constant 334;; arith integer arithmetic instructions 335;; logical integer logical instructions 336;; shift integer shift instructions 337;; slt set less than instructions 338;; signext sign extend instructions 339;; clz the clz and clo instructions 340;; pop the pop instruction 341;; trap trap if instructions 342;; imul integer multiply 2 operands 343;; imul3 integer multiply 3 operands 344;; imul3nc integer multiply 3 operands without clobbering HI/LO 345;; imadd integer multiply-add 346;; idiv integer divide 2 operands 347;; idiv3 integer divide 3 operands 348;; move integer register move ({,D}ADD{,U} with rt = 0) 349;; fmove floating point register move 350;; fadd floating point add/subtract 351;; fmul floating point multiply 352;; fmadd floating point multiply-add 353;; fdiv floating point divide 354;; frdiv floating point reciprocal divide 355;; frdiv1 floating point reciprocal divide step 1 356;; frdiv2 floating point reciprocal divide step 2 357;; fabs floating point absolute value 358;; fneg floating point negation 359;; fcmp floating point compare 360;; fcvt floating point convert 361;; fsqrt floating point square root 362;; frsqrt floating point reciprocal square root 363;; frsqrt1 floating point reciprocal square root step1 364;; frsqrt2 floating point reciprocal square root step2 365;; dspmac DSP MAC instructions not saturating the accumulator 366;; dspmacsat DSP MAC instructions that saturate the accumulator 367;; accext DSP accumulator extract instructions 368;; accmod DSP accumulator modify instructions 369;; dspalu DSP ALU instructions not saturating the result 370;; dspalusat DSP ALU instructions that saturate the result 371;; multi multiword sequence (or user asm statements) 372;; atomic atomic memory update instruction 373;; syncloop memory atomic operation implemented as a sync loop 374;; nop no operation 375;; ghost an instruction that produces no real code 376;; multimem microMIPS multiword load and store 377(define_attr "type" 378 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore, 379 prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical, 380 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move, 381 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt, 382 frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat, 383 multi,atomic,syncloop,nop,ghost,multimem, 384 simd_div,simd_fclass,simd_flog2,simd_fadd,simd_fcvt,simd_fmul,simd_fmadd, 385 simd_fdiv,simd_bitins,simd_bitmov,simd_insert,simd_sld,simd_mul,simd_fcmp, 386 simd_fexp2,simd_int_arith,simd_bit,simd_shift,simd_splat,simd_fill, 387 simd_permute,simd_shf,simd_sat,simd_pcnt,simd_copy,simd_branch,simd_cmsa, 388 simd_fminmax,simd_logic,simd_move,simd_load,simd_store" 389 (cond [(eq_attr "jal" "!unset") (const_string "call") 390 (eq_attr "got" "load") (const_string "load") 391 392 (eq_attr "alu_type" "add,sub") (const_string "arith") 393 394 (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical") 395 396 ;; If a doubleword move uses these expensive instructions, 397 ;; it is usually better to schedule them in the same way 398 ;; as the singleword form, rather than as "multi". 399 (eq_attr "move_type" "load") (const_string "load") 400 (eq_attr "move_type" "fpload") (const_string "fpload") 401 (eq_attr "move_type" "store") (const_string "store") 402 (eq_attr "move_type" "fpstore") (const_string "fpstore") 403 (eq_attr "move_type" "mtc") (const_string "mtc") 404 (eq_attr "move_type" "mfc") (const_string "mfc") 405 (eq_attr "move_type" "mtlo") (const_string "mtlo") 406 (eq_attr "move_type" "mflo") (const_string "mflo") 407 408 ;; These types of move are always single insns. 409 (eq_attr "move_type" "imul") (const_string "imul") 410 (eq_attr "move_type" "fmove") (const_string "fmove") 411 (eq_attr "move_type" "loadpool") (const_string "load") 412 (eq_attr "move_type" "signext") (const_string "signext") 413 (eq_attr "move_type" "ext_ins") (const_string "arith") 414 (eq_attr "move_type" "arith") (const_string "arith") 415 (eq_attr "move_type" "logical") (const_string "logical") 416 (eq_attr "move_type" "sll0") (const_string "shift") 417 (eq_attr "move_type" "andi") (const_string "logical") 418 419 ;; These types of move are always split. 420 (eq_attr "move_type" "constN,shift_shift") 421 (const_string "multi") 422 423 ;; These types of move are split for quadword modes only. 424 (and (eq_attr "move_type" "move,const") 425 (eq_attr "qword_mode" "yes")) 426 (const_string "multi") 427 428 ;; These types of move are split for doubleword modes only. 429 (and (eq_attr "move_type" "move,const") 430 (eq_attr "dword_mode" "yes")) 431 (const_string "multi") 432 (eq_attr "move_type" "move") (const_string "move") 433 (eq_attr "move_type" "const") (const_string "const") 434 (eq_attr "sync_mem" "!none") (const_string "syncloop")] 435 (const_string "unknown"))) 436 437(define_attr "compact_form" "always,maybe,never" 438 (cond [(eq_attr "jal" "direct") 439 (const_string "always") 440 (eq_attr "jal" "indirect") 441 (const_string "maybe") 442 (eq_attr "type" "jump") 443 (const_string "maybe")] 444 (const_string "never"))) 445 446;; Mode for conversion types (fcvt) 447;; I2S integer to float single (SI/DI to SF) 448;; I2D integer to float double (SI/DI to DF) 449;; S2I float to integer (SF to SI/DI) 450;; D2I float to integer (DF to SI/DI) 451;; D2S double to float single 452;; S2D float single to double 453 454(define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D" 455 (const_string "unknown")) 456 457;; Is this an extended instruction in mips16 mode? 458(define_attr "extended_mips16" "no,yes" 459 (if_then_else (ior ;; In general, constant-pool loads are extended 460 ;; instructions. We don't yet optimize for 16-bit 461 ;; PC-relative references. 462 (eq_attr "move_type" "sll0,loadpool") 463 (eq_attr "jal" "direct") 464 (eq_attr "got" "load")) 465 (const_string "yes") 466 (const_string "no"))) 467 468(define_attr "compression" "none,all,micromips32,micromips" 469 (const_string "none")) 470 471(define_attr "enabled" "no,yes" 472 (cond [;; The o32 FPXX and FP64A ABI extensions prohibit direct moves between 473 ;; GR_REG and FR_REG for 64-bit values. 474 (and (eq_attr "move_type" "mtc,mfc") 475 (match_test "(TARGET_FLOATXX && !ISA_HAS_MXHC1) 476 || TARGET_O32_FP64A_ABI") 477 (eq_attr "dword_mode" "yes")) 478 (const_string "no") 479 (and (eq_attr "compression" "micromips32,micromips") 480 (match_test "!TARGET_MICROMIPS")) 481 (const_string "no")] 482 (const_string "yes"))) 483 484;; The number of individual instructions that a non-branch pattern generates, 485;; using units of BASE_INSN_LENGTH. 486(define_attr "insn_count" "" 487 (cond [;; "Ghost" instructions occupy no space. 488 (eq_attr "type" "ghost") 489 (const_int 0) 490 491 ;; Extended instructions count as 2. 492 (and (eq_attr "extended_mips16" "yes") 493 (match_test "TARGET_MIPS16")) 494 (const_int 2) 495 496 ;; A GOT load followed by an add of $gp. This is not used for MIPS16. 497 (eq_attr "got" "xgot_high") 498 (const_int 2) 499 500 ;; SHIFT_SHIFTs are decomposed into two separate instructions. 501 ;; They are extended instructions on MIPS16 targets. 502 (eq_attr "move_type" "shift_shift") 503 (if_then_else (match_test "TARGET_MIPS16") 504 (const_int 4) 505 (const_int 2)) 506 507 ;; Check for doubleword moves that are decomposed into two 508 ;; instructions. The individual instructions are unextended 509 ;; MIPS16 ones. 510 (and (eq_attr "move_type" "mtc,mfc,mtlo,mflo,move") 511 (eq_attr "dword_mode" "yes")) 512 (const_int 2) 513 514 ;; Check for quadword moves that are decomposed into four 515 ;; instructions. 516 (and (eq_attr "move_type" "mtc,mfc,move") 517 (eq_attr "qword_mode" "yes")) 518 (const_int 4) 519 520 ;; Constants, loads and stores are handled by external routines. 521 (and (eq_attr "move_type" "const,constN") 522 (eq_attr "dword_mode" "yes")) 523 (symbol_ref "mips_split_const_insns (operands[1])") 524 (eq_attr "move_type" "const,constN") 525 (symbol_ref "mips_const_insns (operands[1])") 526 (eq_attr "move_type" "load,fpload") 527 (symbol_ref "mips_load_store_insns (operands[1], insn)") 528 (eq_attr "move_type" "store,fpstore") 529 (symbol_ref "mips_load_store_insns (operands[0], insn) 530 + (TARGET_FIX_24K ? 1 : 0)") 531 532 ;; In the worst case, a call macro will take 8 instructions: 533 ;; 534 ;; lui $25,%call_hi(FOO) 535 ;; addu $25,$25,$28 536 ;; lw $25,%call_lo(FOO)($25) 537 ;; nop 538 ;; jalr $25 539 ;; nop 540 ;; lw $gp,X($sp) 541 ;; nop 542 (eq_attr "jal_macro" "yes") 543 (const_int 8) 544 545 ;; Various VR4120 errata require a nop to be inserted after a macc 546 ;; instruction. The assembler does this for us, so account for 547 ;; the worst-case length here. 548 (and (eq_attr "type" "imadd") 549 (match_test "TARGET_FIX_VR4120")) 550 (const_int 2) 551 552 ;; VR4120 errata MD(4): if there are consecutive dmult instructions, 553 ;; the result of the second one is missed. The assembler should work 554 ;; around this by inserting a nop after the first dmult. 555 (and (eq_attr "type" "imul,imul3") 556 (eq_attr "mode" "DI") 557 (match_test "TARGET_FIX_VR4120")) 558 (const_int 2) 559 560 (eq_attr "type" "idiv,idiv3") 561 (symbol_ref "mips_idiv_insns (GET_MODE (PATTERN (insn)))") 562 563 ;; simd div have 3 instruction if TARGET_CHECK_ZERO_DIV is true. 564 (eq_attr "type" "simd_div") 565 (if_then_else (match_test "TARGET_CHECK_ZERO_DIV") 566 (const_int 3) 567 (const_int 1)) 568 569 (not (eq_attr "sync_mem" "none")) 570 (symbol_ref "mips_sync_loop_insns (insn, operands)")] 571 (const_int 1))) 572 573;; Length of instruction in bytes. The default is derived from "insn_count", 574;; but there are special cases for branches (which must be handled here) 575;; and for compressed single instructions. 576(define_attr "length" "" 577 (cond [(and (ior (eq_attr "compression" "micromips,all") 578 (and (eq_attr "compression" "micromips32") 579 (eq_attr "mode" "SI,SF"))) 580 (eq_attr "dword_mode" "no") 581 (match_test "TARGET_MICROMIPS")) 582 (const_int 2) 583 584 ;; Direct microMIPS branch instructions have a range of 585 ;; [-0x10000,0xfffe], otherwise the range is [-0x20000,0x1fffc]. 586 ;; If a branch is outside this range, we have a choice of two 587 ;; sequences. 588 ;; 589 ;; For PIC, an out-of-range branch like: 590 ;; 591 ;; bne r1,r2,target 592 ;; dslot 593 ;; 594 ;; becomes the equivalent of: 595 ;; 596 ;; beq r1,r2,1f 597 ;; dslot 598 ;; la $at,target 599 ;; jr $at 600 ;; nop 601 ;; 1: 602 ;; 603 ;; The non-PIC case is similar except that we use a direct 604 ;; jump instead of an la/jr pair. Since the target of this 605 ;; jump is an absolute 28-bit bit address (the other bits 606 ;; coming from the address of the delay slot) this form cannot 607 ;; cross a 256MB boundary. We could provide the option of 608 ;; using la/jr in this case too, but we do not do so at 609 ;; present. 610 ;; 611 ;; The value we specify here does not account for the delay slot 612 ;; instruction, whose length is added separately. If the RTL 613 ;; pattern has no explicit delay slot, mips_adjust_insn_length 614 ;; will add the length of the implicit nop. The range of 615 ;; [-0x20000, 0x1fffc] from the address of the delay slot 616 ;; therefore translates to a range of: 617 ;; 618 ;; [-(0x20000 - sizeof (branch)), 0x1fffc - sizeof (slot)] 619 ;; == [-0x1fffc, 0x1fff8] 620 ;; 621 ;; from the shorten_branches reference address. 622 (and (eq_attr "type" "branch") 623 (not (match_test "TARGET_MIPS16"))) 624 (cond [;; Any variant can handle the 17-bit range. 625 (and (le (minus (match_dup 0) (pc)) (const_int 65532)) 626 (le (minus (pc) (match_dup 0)) (const_int 65534))) 627 (const_int 4) 628 629 ;; The 18-bit range is OK other than for microMIPS. 630 (and (not (match_test "TARGET_MICROMIPS")) 631 (and (le (minus (match_dup 0) (pc)) (const_int 131064)) 632 (le (minus (pc) (match_dup 0)) (const_int 131068)))) 633 (const_int 4) 634 635 ;; The non-PIC case: branch, first delay slot, and J. 636 (match_test "TARGET_ABSOLUTE_JUMPS") 637 (const_int 12)] 638 639 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate. 640 ;; mips_adjust_insn_length substitutes the correct length. 641 ;; 642 ;; Note that we can't simply use (symbol_ref ...) here 643 ;; because genattrtab needs to know the maximum length 644 ;; of an insn. 645 (const_int MAX_PIC_BRANCH_LENGTH)) 646 647 ;; An unextended MIPS16 branch has a range of [-0x100, 0xfe] 648 ;; from the address of the following instruction, which leads 649 ;; to a range of: 650 ;; 651 ;; [-(0x100 - sizeof (branch)), 0xfe] 652 ;; == [-0xfe, 0xfe] 653 ;; 654 ;; from the shorten_branches reference address. Extended branches 655 ;; likewise have a range of [-0x10000, 0xfffe] from the address 656 ;; of the following instruction, which leads to a range of: 657 ;; 658 ;; [-(0x10000 - sizeof (branch)), 0xfffe] 659 ;; == [-0xfffc, 0xfffe] 660 ;; 661 ;; from the reference address. 662 ;; 663 ;; When a branch is out of range, mips_reorg splits it into a form 664 ;; that uses in-range branches. There are four basic sequences: 665 ;; 666 ;; (1) Absolute addressing with a readable text segment 667 ;; (32-bit addresses): 668 ;; 669 ;; b... foo 2 bytes 670 ;; move $1,$2 2 bytes 671 ;; lw $2,label 2 bytes 672 ;; jr $2 2 bytes 673 ;; move $2,$1 2 bytes 674 ;; .align 2 0 or 2 bytes 675 ;; label: 676 ;; .word target 4 bytes 677 ;; foo: 678 ;; (16 bytes in the worst case) 679 ;; 680 ;; (2) Absolute addressing with a readable text segment 681 ;; (64-bit addresses): 682 ;; 683 ;; b... foo 2 bytes 684 ;; move $1,$2 2 bytes 685 ;; ld $2,label 2 bytes 686 ;; jr $2 2 bytes 687 ;; move $2,$1 2 bytes 688 ;; .align 3 0 to 6 bytes 689 ;; label: 690 ;; .dword target 8 bytes 691 ;; foo: 692 ;; (24 bytes in the worst case) 693 ;; 694 ;; (3) Absolute addressing without a readable text segment 695 ;; (which requires 32-bit addresses at present): 696 ;; 697 ;; b... foo 2 bytes 698 ;; move $1,$2 2 bytes 699 ;; lui $2,%hi(target) 4 bytes 700 ;; sll $2,8 2 bytes 701 ;; sll $2,8 2 bytes 702 ;; addiu $2,%lo(target) 4 bytes 703 ;; jr $2 2 bytes 704 ;; move $2,$1 2 bytes 705 ;; foo: 706 ;; (20 bytes) 707 ;; 708 ;; (4) PIC addressing (which requires 32-bit addresses at present): 709 ;; 710 ;; b... foo 2 bytes 711 ;; move $1,$2 2 bytes 712 ;; lw $2,cprestore 0, 2 or 4 bytes 713 ;; lw $2,%got(target)($2) 4 bytes 714 ;; addiu $2,%lo(target) 4 bytes 715 ;; jr $2 2 bytes 716 ;; move $2,$1 2 bytes 717 ;; foo: 718 ;; (20 bytes in the worst case) 719 (and (eq_attr "type" "branch") 720 (match_test "TARGET_MIPS16")) 721 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254)) 722 (le (minus (pc) (match_dup 0)) (const_int 254))) 723 (const_int 2) 724 (and (le (minus (match_dup 0) (pc)) (const_int 65534)) 725 (le (minus (pc) (match_dup 0)) (const_int 65532))) 726 (const_int 4) 727 (and (match_test "TARGET_ABICALLS") 728 (not (match_test "TARGET_ABSOLUTE_ABICALLS"))) 729 (const_int 20) 730 (match_test "Pmode == SImode") 731 (const_int 16) 732 ] (const_int 24))] 733 (symbol_ref "get_attr_insn_count (insn) * BASE_INSN_LENGTH"))) 734 735;; Attribute describing the processor. 736(define_enum_attr "cpu" "processor" 737 (const (symbol_ref "mips_tune"))) 738 739;; The type of hardware hazard associated with this instruction. 740;; DELAY means that the next instruction cannot read the result 741;; of this one. HILO means that the next two instructions cannot 742;; write to HI or LO. 743(define_attr "hazard" "none,delay,hilo,forbidden_slot" 744 (cond [(and (eq_attr "type" "load,fpload,fpidxload") 745 (match_test "ISA_HAS_LOAD_DELAY")) 746 (const_string "delay") 747 748 (and (eq_attr "type" "mfc,mtc") 749 (match_test "ISA_HAS_XFER_DELAY")) 750 (const_string "delay") 751 752 (and (eq_attr "type" "fcmp") 753 (match_test "ISA_HAS_FCMP_DELAY")) 754 (const_string "delay") 755 756 ;; The r4000 multiplication patterns include an mflo instruction. 757 (and (eq_attr "type" "imul") 758 (match_test "TARGET_FIX_R4000")) 759 (const_string "hilo") 760 761 (and (eq_attr "type" "mfhi,mflo") 762 (not (match_test "ISA_HAS_HILO_INTERLOCKS"))) 763 (const_string "hilo")] 764 (const_string "none"))) 765 766;; Can the instruction be put into a delay slot? 767(define_attr "can_delay" "no,yes" 768 (if_then_else (and (eq_attr "type" "!branch,call,jump,simd_branch") 769 (eq_attr "hazard" "none") 770 (match_test "get_attr_insn_count (insn) == 1")) 771 (const_string "yes") 772 (const_string "no"))) 773 774;; Attribute defining whether or not we can use the branch-likely 775;; instructions. 776(define_attr "branch_likely" "no,yes" 777 (if_then_else (match_test "GENERATE_BRANCHLIKELY") 778 (const_string "yes") 779 (const_string "no"))) 780 781;; True if an instruction might assign to hi or lo when reloaded. 782;; This is used by the TUNE_MACC_CHAINS code. 783(define_attr "may_clobber_hilo" "no,yes" 784 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthi,mtlo") 785 (const_string "yes") 786 (const_string "no"))) 787 788;; Describe a user's asm statement. 789(define_asm_attributes 790 [(set_attr "type" "multi") 791 (set_attr "can_delay" "no")]) 792 793;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated 794;; from the same template. 795(define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) 796 797;; A copy of GPR that can be used when a pattern has two independent 798;; modes. 799(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")]) 800 801(define_mode_iterator MOVEP1 [SI SF]) 802(define_mode_iterator MOVEP2 [SI SF]) 803(define_mode_iterator JOIN_MODE [HI 804 SI 805 (SF "TARGET_HARD_FLOAT") 806 (DF "TARGET_HARD_FLOAT 807 && TARGET_DOUBLE_FLOAT")]) 808 809;; This mode iterator allows :HILO to be used as the mode of the 810;; concatenated HI and LO registers. 811(define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")]) 812 813;; This mode iterator allows :P to be used for patterns that operate on 814;; pointer-sized quantities. Exactly one of the two alternatives will match. 815(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) 816 817;; This mode iterator allows :MOVECC to be used anywhere that a 818;; conditional-move-type condition is needed. 819(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") 820 (CC "TARGET_HARD_FLOAT 821 && !TARGET_LOONGSON_2EF 822 && !TARGET_MIPS5900")]) 823 824;; This mode iterator allows :FPCC to be used anywhere that an FP condition 825;; is needed. 826(define_mode_iterator FPCC [(CC "!ISA_HAS_CCF") 827 (CCF "ISA_HAS_CCF")]) 828 829;; 32-bit integer moves for which we provide move patterns. 830(define_mode_iterator IMOVE32 831 [SI 832 (V2HI "TARGET_DSP") 833 (V4QI "TARGET_DSP") 834 (V2HQ "TARGET_DSP") 835 (V2UHQ "TARGET_DSP") 836 (V2HA "TARGET_DSP") 837 (V2UHA "TARGET_DSP") 838 (V4QQ "TARGET_DSP") 839 (V4UQQ "TARGET_DSP")]) 840 841;; 64-bit modes for which we provide move patterns. 842(define_mode_iterator MOVE64 843 [DI DF 844 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT") 845 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI") 846 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI") 847 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI")]) 848 849;; 128-bit modes for which we provide move patterns on 64-bit targets. 850(define_mode_iterator MOVE128 [TI TF]) 851 852;; This mode iterator allows the QI and HI extension patterns to be 853;; defined from the same template. 854(define_mode_iterator SHORT [QI HI]) 855 856;; Likewise the 64-bit truncate-and-shift patterns. 857(define_mode_iterator SUBDI [QI HI SI]) 858 859;; This mode iterator allows :ANYF to be used wherever a scalar or vector 860;; floating-point mode is allowed. 861(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT") 862 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT") 863 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")]) 864 865;; Like ANYF, but only applies to scalar modes. 866(define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT") 867 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")]) 868 869;; A floating-point mode for which moves involving FPRs may need to be split. 870(define_mode_iterator SPLITF 871 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") 872 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") 873 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT") 874 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_MMI") 875 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_MMI") 876 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_MMI") 877 (TF "TARGET_64BIT && TARGET_FLOAT64")]) 878 879;; In GPR templates, a string like "<d>subu" will expand to "subu" in the 880;; 32-bit version and "dsubu" in the 64-bit version. 881(define_mode_attr d [(SI "") (DI "d") 882 (QQ "") (HQ "") (SQ "") (DQ "d") 883 (UQQ "") (UHQ "") (USQ "") (UDQ "d") 884 (HA "") (SA "") (DA "d") 885 (UHA "") (USA "") (UDA "d")]) 886 887;; Same as d but upper-case. 888(define_mode_attr D [(SI "") (DI "D") 889 (QQ "") (HQ "") (SQ "") (DQ "D") 890 (UQQ "") (UHQ "") (USQ "") (UDQ "D") 891 (HA "") (SA "") (DA "D") 892 (UHA "") (USA "") (UDA "D")]) 893 894;; This attribute gives the length suffix for a load or store instruction. 895;; The same suffixes work for zero and sign extensions. 896(define_mode_attr size [(QI "b") (HI "h") (SI "w") (DI "d")]) 897(define_mode_attr SIZE [(QI "B") (HI "H") (SI "W") (DI "D")]) 898 899;; This attributes gives the mode mask of a SHORT. 900(define_mode_attr mask [(QI "0x00ff") (HI "0xffff")]) 901 902;; Mode attributes for GPR loads. 903(define_mode_attr load [(SI "lw") (DI "ld")]) 904;; Instruction names for stores. 905(define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")]) 906 907;; Similarly for MIPS IV indexed FPR loads and stores. 908(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")]) 909(define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")]) 910 911;; The unextended ranges of the MIPS16 addiu and daddiu instructions 912;; are different. Some forms of unextended addiu have an 8-bit immediate 913;; field but the equivalent daddiu has only a 5-bit field. 914(define_mode_attr si8_di5 [(SI "8") (DI "5")]) 915 916;; This attribute gives the best constraint to use for registers of 917;; a given mode. 918(define_mode_attr reg [(SI "d") (DI "d") (CC "z") (CCF "f")]) 919 920;; This attribute gives the format suffix for floating-point operations. 921(define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")]) 922 923;; This attribute gives the upper-case mode name for one unit of a 924;; floating-point mode or vector mode. 925(define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF") (V4SF "SF") 926 (V16QI "QI") (V8HI "HI") (V4SI "SI") (V2DI "DI") 927 (V2DF "DF")]) 928 929;; As above, but in lower case. 930(define_mode_attr unitmode [(SF "sf") (DF "df") (V2SF "sf") (V4SF "sf") 931 (V16QI "qi") (V8QI "qi") (V8HI "hi") (V4HI "hi") 932 (V4SI "si") (V2SI "si") (V2DI "di") (V2DF "df")]) 933 934;; This attribute gives the integer mode that has the same size as a 935;; fixed-point mode. 936(define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI") 937 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI") 938 (HA "HI") (SA "SI") (DA "DI") 939 (UHA "HI") (USA "SI") (UDA "DI") 940 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI") 941 (V2HQ "SI") (V2HA "SI")]) 942 943;; This attribute gives the integer mode that has half the size of 944;; the controlling mode. 945(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI") 946 (V2SI "SI") (V4HI "SI") (V8QI "SI") 947 (TF "DI")]) 948 949;; This attribute works around the early SB-1 rev2 core "F2" erratum: 950;; 951;; In certain cases, div.s and div.ps may have a rounding error 952;; and/or wrong inexact flag. 953;; 954;; Therefore, we only allow div.s if not working around SB-1 rev2 955;; errata or if a slight loss of precision is OK. 956(define_mode_attr divide_condition 957 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations") 958 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")]) 959 960;; This attribute gives the conditions under which SQRT.fmt instructions 961;; can be used. 962(define_mode_attr sqrt_condition 963 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")]) 964 965;; This attribute provides the correct mnemonic for each FP condition mode. 966(define_mode_attr fpcmp [(CC "c") (CCF "cmp")]) 967 968;; This code iterator allows signed and unsigned widening multiplications 969;; to use the same template. 970(define_code_iterator any_extend [sign_extend zero_extend]) 971 972;; This code iterator allows the two right shift instructions to be 973;; generated from the same template. 974(define_code_iterator any_shiftrt [ashiftrt lshiftrt]) 975 976;; This code iterator allows the three shift instructions to be generated 977;; from the same template. 978(define_code_iterator any_shift [ashift ashiftrt lshiftrt]) 979 980;; This code iterator allows unsigned and signed division to be generated 981;; from the same template. 982(define_code_iterator any_div [div udiv]) 983 984;; This code iterator allows unsigned and signed modulus to be generated 985;; from the same template. 986(define_code_iterator any_mod [mod umod]) 987 988;; This code iterator allows addition and subtraction to be generated 989;; from the same template. 990(define_code_iterator addsub [plus minus]) 991 992;; This code iterator allows all native floating-point comparisons to be 993;; generated from the same template. 994(define_code_iterator fcond [unordered uneq unlt unle eq lt le 995 (ordered "ISA_HAS_CCF") 996 (ltgt "ISA_HAS_CCF") 997 (ne "ISA_HAS_CCF")]) 998 999;; This code iterator is used for comparisons that can be implemented 1000;; by swapping the operands. 1001(define_code_iterator swapped_fcond [ge gt unge ungt]) 1002 1003;; Equality operators. 1004(define_code_iterator equality_op [eq ne]) 1005 1006;; These code iterators allow the signed and unsigned scc operations to use 1007;; the same template. 1008(define_code_iterator any_gt [gt gtu]) 1009(define_code_iterator any_ge [ge geu]) 1010(define_code_iterator any_lt [lt ltu]) 1011(define_code_iterator any_le [le leu]) 1012 1013(define_code_iterator any_return [return simple_return]) 1014 1015;; <u> expands to an empty string when doing a signed operation and 1016;; "u" when doing an unsigned operation. 1017(define_code_attr u [(sign_extend "") (zero_extend "u") 1018 (div "") (udiv "u") 1019 (mod "") (umod "u") 1020 (gt "") (gtu "u") 1021 (ge "") (geu "u") 1022 (lt "") (ltu "u") 1023 (le "") (leu "u")]) 1024 1025;; <U> is like <u> except uppercase. 1026(define_code_attr U [(sign_extend "") (zero_extend "U")]) 1027 1028;; <su> is like <u>, but the signed form expands to "s" rather than "". 1029(define_code_attr su [(sign_extend "s") (zero_extend "u")]) 1030 1031;; <optab> expands to the name of the optab for a particular code. 1032(define_code_attr optab [(ashift "ashl") 1033 (ashiftrt "ashr") 1034 (lshiftrt "lshr") 1035 (ior "ior") 1036 (xor "xor") 1037 (and "and") 1038 (plus "add") 1039 (minus "sub") 1040 (return "return") 1041 (simple_return "simple_return")]) 1042 1043;; <insn> expands to the name of the insn that implements a particular code. 1044(define_code_attr insn [(ashift "sll") 1045 (ashiftrt "sra") 1046 (lshiftrt "srl") 1047 (ior "or") 1048 (xor "xor") 1049 (and "and") 1050 (plus "addu") 1051 (minus "subu")]) 1052 1053;; <immediate_insn> expands to the name of the insn that implements 1054;; a particular code to operate on immediate values. 1055(define_code_attr immediate_insn [(ior "ori") 1056 (xor "xori") 1057 (and "andi")]) 1058 1059(define_code_attr shift_compression [(ashift "micromips32") 1060 (lshiftrt "micromips32") 1061 (ashiftrt "none")]) 1062 1063;; <fcond> is the c.cond.fmt condition associated with a particular code. 1064(define_code_attr fcond [(unordered "un") 1065 (uneq "ueq") 1066 (unlt "ult") 1067 (unle "ule") 1068 (eq "eq") 1069 (lt "lt") 1070 (le "le") 1071 (ordered "or") 1072 (ltgt "ne") 1073 (ne "une")]) 1074 1075;; Similar, but for swapped conditions. 1076(define_code_attr swapped_fcond [(ge "le") 1077 (gt "lt") 1078 (unge "ule") 1079 (ungt "ult")]) 1080 1081;; The value of the bit when the branch is taken for branch_bit patterns. 1082;; Comparison is always against zero so this depends on the operator. 1083(define_code_attr bbv [(eq "0") (ne "1")]) 1084 1085;; This is the inverse value of bbv. 1086(define_code_attr bbinv [(eq "1") (ne "0")]) 1087 1088;; The sel mnemonic to use depending on the condition test. 1089(define_code_attr sel [(eq "seleqz") (ne "selnez")]) 1090(define_code_attr selinv [(eq "selnez") (ne "seleqz")]) 1091 1092;; ......................... 1093;; 1094;; Branch, call and jump delay slots 1095;; 1096;; ......................... 1097 1098(define_delay (and (eq_attr "type" "branch") 1099 (not (match_test "TARGET_MIPS16")) 1100 (eq_attr "branch_likely" "yes")) 1101 [(eq_attr "can_delay" "yes") 1102 (nil) 1103 (eq_attr "can_delay" "yes")]) 1104 1105;; Branches that have delay slots and don't have likely variants do 1106;; not annul on false. 1107(define_delay (and (eq_attr "type" "branch,simd_branch") 1108 (not (match_test "TARGET_MIPS16")) 1109 (ior (match_test "TARGET_CB_NEVER") 1110 (and (eq_attr "compact_form" "maybe") 1111 (not (match_test "TARGET_CB_ALWAYS"))) 1112 (eq_attr "compact_form" "never")) 1113 (eq_attr "branch_likely" "no")) 1114 [(eq_attr "can_delay" "yes") 1115 (nil) 1116 (nil)]) 1117 1118(define_delay (and (eq_attr "type" "jump") 1119 (ior (match_test "TARGET_CB_NEVER") 1120 (and (eq_attr "compact_form" "maybe") 1121 (not (match_test "TARGET_CB_ALWAYS"))) 1122 (eq_attr "compact_form" "never"))) 1123 [(eq_attr "can_delay" "yes") 1124 (nil) 1125 (nil)]) 1126 1127;; Call type instructions should never have a compact form as the 1128;; type is only used for MIPS16 patterns. For safety put the compact 1129;; branch detection condition in anyway. 1130(define_delay (and (eq_attr "type" "call") 1131 (eq_attr "jal_macro" "no") 1132 (ior (match_test "TARGET_CB_NEVER") 1133 (and (eq_attr "compact_form" "maybe") 1134 (not (match_test "TARGET_CB_ALWAYS"))) 1135 (eq_attr "compact_form" "never"))) 1136 [(eq_attr "can_delay" "yes") 1137 (nil) 1138 (nil)]) 1139 1140;; Pipeline descriptions. 1141;; 1142;; generic.md provides a fallback for processors without a specific 1143;; pipeline description. It is derived from the old define_function_unit 1144;; version and uses the "alu" and "imuldiv" units declared below. 1145;; 1146;; Some of the processor-specific files are also derived from old 1147;; define_function_unit descriptions and simply override the parts of 1148;; generic.md that don't apply. The other processor-specific files 1149;; are self-contained. 1150(define_automaton "alu,imuldiv") 1151 1152(define_cpu_unit "alu" "alu") 1153(define_cpu_unit "imuldiv" "imuldiv") 1154 1155;; Ghost instructions produce no real code and introduce no hazards. 1156;; They exist purely to express an effect on dataflow. 1157(define_insn_reservation "ghost" 0 1158 (eq_attr "type" "ghost") 1159 "nothing") 1160 1161(include "i6400.md") 1162(include "p5600.md") 1163(include "m5100.md") 1164(include "p6600.md") 1165(include "4k.md") 1166(include "5k.md") 1167(include "20kc.md") 1168(include "24k.md") 1169(include "74k.md") 1170(include "3000.md") 1171(include "4000.md") 1172(include "4100.md") 1173(include "4130.md") 1174(include "4300.md") 1175(include "4600.md") 1176(include "5000.md") 1177(include "5400.md") 1178(include "5500.md") 1179(include "6000.md") 1180(include "7000.md") 1181(include "9000.md") 1182(include "10000.md") 1183(include "loongson2ef.md") 1184(include "gs464.md") 1185(include "gs464e.md") 1186(include "gs264e.md") 1187(include "octeon.md") 1188(include "sb1.md") 1189(include "sr71k.md") 1190(include "xlr.md") 1191(include "xlp.md") 1192(include "generic.md") 1193 1194;; 1195;; .................... 1196;; 1197;; CONDITIONAL TRAPS 1198;; 1199;; .................... 1200;; 1201 1202(define_insn "trap" 1203 [(trap_if (const_int 1) (const_int 0))] 1204 "" 1205{ 1206 if (ISA_HAS_COND_TRAP) 1207 return "teq\t$0,$0"; 1208 else if (TARGET_MIPS16) 1209 return "break 0"; 1210 else 1211 return "break"; 1212} 1213 [(set_attr "type" "trap")]) 1214 1215(define_expand "ctrap<mode>4" 1216 [(trap_if (match_operator 0 "comparison_operator" 1217 [(match_operand:GPR 1 "reg_or_0_operand") 1218 (match_operand:GPR 2 "arith_operand")]) 1219 (match_operand 3 "const_0_operand"))] 1220 "ISA_HAS_COND_TRAPI || ISA_HAS_COND_TRAP" 1221{ 1222 mips_expand_conditional_trap (operands[0]); 1223 DONE; 1224}) 1225 1226(define_insn "*conditional_trap_reg<mode>" 1227 [(trap_if (match_operator:GPR 0 "trap_comparison_operator" 1228 [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 1229 (match_operand:GPR 2 "reg_or_0_operand" "dJ")]) 1230 (const_int 0))] 1231 "ISA_HAS_COND_TRAP && !ISA_HAS_COND_TRAPI" 1232 "t%C0\t%z1,%2" 1233 [(set_attr "type" "trap")]) 1234 1235(define_insn "*conditional_trap<mode>" 1236 [(trap_if (match_operator:GPR 0 "trap_comparison_operator" 1237 [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 1238 (match_operand:GPR 2 "arith_operand" "dI")]) 1239 (const_int 0))] 1240 "ISA_HAS_COND_TRAPI" 1241 "t%C0\t%z1,%2" 1242 [(set_attr "type" "trap")]) 1243 1244;; 1245;; .................... 1246;; 1247;; ADDITION 1248;; 1249;; .................... 1250;; 1251 1252(define_insn "add<mode>3" 1253 [(set (match_operand:ANYF 0 "register_operand" "=f") 1254 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f") 1255 (match_operand:ANYF 2 "register_operand" "f")))] 1256 "" 1257 "add.<fmt>\t%0,%1,%2" 1258 [(set_attr "type" "fadd") 1259 (set_attr "mode" "<UNITMODE>")]) 1260 1261(define_expand "add<mode>3" 1262 [(set (match_operand:GPR 0 "register_operand") 1263 (plus:GPR (match_operand:GPR 1 "register_operand") 1264 (match_operand:GPR 2 "arith_operand")))] 1265 "") 1266 1267(define_insn "*add<mode>3" 1268 [(set (match_operand:GPR 0 "register_operand" "=!u,d,!u,!u,!ks,!d,d") 1269 (plus:GPR (match_operand:GPR 1 "register_operand" "!u,d,!u,!ks,!ks,0,d") 1270 (match_operand:GPR 2 "arith_operand" "!u,d,Uead,Uuw6,Uesp,Usb4,Q")))] 1271 "!TARGET_MIPS16" 1272{ 1273 if (which_alternative == 0 1274 || which_alternative == 1) 1275 return "<d>addu\t%0,%1,%2"; 1276 else 1277 return "<d>addiu\t%0,%1,%2"; 1278} 1279 [(set_attr "alu_type" "add") 1280 (set_attr "compression" "micromips32,*,micromips32,micromips32,micromips32,micromips32,*") 1281 (set_attr "mode" "<MODE>")]) 1282 1283(define_insn "*add<mode>3_mips16" 1284 [(set (match_operand:GPR 0 "register_operand" "=ks,ks,d,d,d,d,d,d,d") 1285 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,ks,ks,0,0,d,d,d") 1286 (match_operand:GPR 2 "arith_operand" "Usd8,Q,Uuw<si8_di5>,Q,Usb<si8_di5>,Q,Usb4,O,d")))] 1287 "TARGET_MIPS16" 1288 "@ 1289 <d>addiu\t%0,%2 1290 <d>addiu\t%0,%2 1291 <d>addiu\t%0,%1,%2 1292 <d>addiu\t%0,%1,%2 1293 <d>addiu\t%0,%2 1294 <d>addiu\t%0,%2 1295 <d>addiu\t%0,%1,%2 1296 <d>addiu\t%0,%1,%2 1297 <d>addu\t%0,%1,%2" 1298 [(set_attr "alu_type" "add") 1299 (set_attr "mode" "<MODE>") 1300 (set_attr "extended_mips16" "no,yes,no,yes,no,yes,no,yes,no")]) 1301 1302;; On the mips16, we can sometimes split an add of a constant which is 1303;; a 4 byte instruction into two adds which are both 2 byte 1304;; instructions. There are two cases: one where we are adding a 1305;; constant plus a register to another register, and one where we are 1306;; simply adding a constant to a register. 1307 1308(define_split 1309 [(set (match_operand:SI 0 "d_operand") 1310 (plus:SI (match_dup 0) 1311 (match_operand:SI 1 "const_int_operand")))] 1312 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 1313 && ((INTVAL (operands[1]) > 0x7f 1314 && INTVAL (operands[1]) <= 0x7f + 0x7f) 1315 || (INTVAL (operands[1]) < - 0x80 1316 && INTVAL (operands[1]) >= - 0x80 - 0x80))" 1317 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 1318 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] 1319{ 1320 HOST_WIDE_INT val = INTVAL (operands[1]); 1321 1322 if (val >= 0) 1323 { 1324 operands[1] = GEN_INT (0x7f); 1325 operands[2] = GEN_INT (val - 0x7f); 1326 } 1327 else 1328 { 1329 operands[1] = GEN_INT (- 0x80); 1330 operands[2] = GEN_INT (val + 0x80); 1331 } 1332}) 1333 1334(define_split 1335 [(set (match_operand:SI 0 "d_operand") 1336 (plus:SI (match_operand:SI 1 "d_operand") 1337 (match_operand:SI 2 "const_int_operand")))] 1338 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 1339 && REGNO (operands[0]) != REGNO (operands[1]) 1340 && ((INTVAL (operands[2]) > 0x7 1341 && INTVAL (operands[2]) <= 0x7 + 0x7f) 1342 || (INTVAL (operands[2]) < - 0x8 1343 && INTVAL (operands[2]) >= - 0x8 - 0x80))" 1344 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2))) 1345 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))] 1346{ 1347 HOST_WIDE_INT val = INTVAL (operands[2]); 1348 1349 if (val >= 0) 1350 { 1351 operands[2] = GEN_INT (0x7); 1352 operands[3] = GEN_INT (val - 0x7); 1353 } 1354 else 1355 { 1356 operands[2] = GEN_INT (- 0x8); 1357 operands[3] = GEN_INT (val + 0x8); 1358 } 1359}) 1360 1361(define_split 1362 [(set (match_operand:DI 0 "d_operand") 1363 (plus:DI (match_dup 0) 1364 (match_operand:DI 1 "const_int_operand")))] 1365 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE 1366 && ((INTVAL (operands[1]) > 0xf 1367 && INTVAL (operands[1]) <= 0xf + 0xf) 1368 || (INTVAL (operands[1]) < - 0x10 1369 && INTVAL (operands[1]) >= - 0x10 - 0x10))" 1370 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1))) 1371 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))] 1372{ 1373 HOST_WIDE_INT val = INTVAL (operands[1]); 1374 1375 if (val >= 0) 1376 { 1377 operands[1] = GEN_INT (0xf); 1378 operands[2] = GEN_INT (val - 0xf); 1379 } 1380 else 1381 { 1382 operands[1] = GEN_INT (- 0x10); 1383 operands[2] = GEN_INT (val + 0x10); 1384 } 1385}) 1386 1387(define_split 1388 [(set (match_operand:DI 0 "d_operand") 1389 (plus:DI (match_operand:DI 1 "d_operand") 1390 (match_operand:DI 2 "const_int_operand")))] 1391 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE 1392 && REGNO (operands[0]) != REGNO (operands[1]) 1393 && ((INTVAL (operands[2]) > 0x7 1394 && INTVAL (operands[2]) <= 0x7 + 0xf) 1395 || (INTVAL (operands[2]) < - 0x8 1396 && INTVAL (operands[2]) >= - 0x8 - 0x10))" 1397 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) 1398 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 1399{ 1400 HOST_WIDE_INT val = INTVAL (operands[2]); 1401 1402 if (val >= 0) 1403 { 1404 operands[2] = GEN_INT (0x7); 1405 operands[3] = GEN_INT (val - 0x7); 1406 } 1407 else 1408 { 1409 operands[2] = GEN_INT (- 0x8); 1410 operands[3] = GEN_INT (val + 0x8); 1411 } 1412}) 1413 1414(define_insn "*addsi3_extended" 1415 [(set (match_operand:DI 0 "register_operand" "=d,d") 1416 (sign_extend:DI 1417 (plus:SI (match_operand:SI 1 "register_operand" "d,d") 1418 (match_operand:SI 2 "arith_operand" "d,Q"))))] 1419 "TARGET_64BIT && !TARGET_MIPS16" 1420 "@ 1421 addu\t%0,%1,%2 1422 addiu\t%0,%1,%2" 1423 [(set_attr "alu_type" "add") 1424 (set_attr "mode" "SI")]) 1425 1426;; Split this insn so that the addiu splitters can have a crack at it. 1427;; Use a conservative length estimate until the split. 1428(define_insn_and_split "*addsi3_extended_mips16" 1429 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 1430 (sign_extend:DI 1431 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d") 1432 (match_operand:SI 2 "arith_operand" "Q,O,d"))))] 1433 "TARGET_64BIT && TARGET_MIPS16" 1434 "#" 1435 "&& reload_completed" 1436 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))] 1437 { operands[3] = gen_lowpart (SImode, operands[0]); } 1438 [(set_attr "alu_type" "add") 1439 (set_attr "mode" "SI") 1440 (set_attr "extended_mips16" "yes")]) 1441 1442;; Combiner patterns for unsigned byte-add. 1443 1444(define_insn "*baddu_si_eb" 1445 [(set (match_operand:SI 0 "register_operand" "=d") 1446 (zero_extend:SI 1447 (subreg:QI 1448 (plus:SI (match_operand:SI 1 "register_operand" "d") 1449 (match_operand:SI 2 "register_operand" "d")) 3)))] 1450 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN" 1451 "baddu\\t%0,%1,%2" 1452 [(set_attr "alu_type" "add")]) 1453 1454(define_insn "*baddu_si_el" 1455 [(set (match_operand:SI 0 "register_operand" "=d") 1456 (zero_extend:SI 1457 (subreg:QI 1458 (plus:SI (match_operand:SI 1 "register_operand" "d") 1459 (match_operand:SI 2 "register_operand" "d")) 0)))] 1460 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN" 1461 "baddu\\t%0,%1,%2" 1462 [(set_attr "alu_type" "add")]) 1463 1464(define_insn "*baddu_di<mode>" 1465 [(set (match_operand:GPR 0 "register_operand" "=d") 1466 (zero_extend:GPR 1467 (truncate:QI 1468 (plus:DI (match_operand:DI 1 "register_operand" "d") 1469 (match_operand:DI 2 "register_operand" "d")))))] 1470 "ISA_HAS_BADDU && TARGET_64BIT" 1471 "baddu\\t%0,%1,%2" 1472 [(set_attr "alu_type" "add")]) 1473 1474;; 1475;; .................... 1476;; 1477;; SUBTRACTION 1478;; 1479;; .................... 1480;; 1481 1482(define_insn "sub<mode>3" 1483 [(set (match_operand:ANYF 0 "register_operand" "=f") 1484 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f") 1485 (match_operand:ANYF 2 "register_operand" "f")))] 1486 "" 1487 "sub.<fmt>\t%0,%1,%2" 1488 [(set_attr "type" "fadd") 1489 (set_attr "mode" "<UNITMODE>")]) 1490 1491(define_insn "sub<mode>3" 1492 [(set (match_operand:GPR 0 "register_operand" "=!u,d") 1493 (minus:GPR (match_operand:GPR 1 "register_operand" "!u,d") 1494 (match_operand:GPR 2 "register_operand" "!u,d")))] 1495 "" 1496 "<d>subu\t%0,%1,%2" 1497 [(set_attr "alu_type" "sub") 1498 (set_attr "compression" "micromips32,*") 1499 (set_attr "mode" "<MODE>")]) 1500 1501(define_insn "*subsi3_extended" 1502 [(set (match_operand:DI 0 "register_operand" "=d") 1503 (sign_extend:DI 1504 (minus:SI (match_operand:SI 1 "register_operand" "d") 1505 (match_operand:SI 2 "register_operand" "d"))))] 1506 "TARGET_64BIT" 1507 "subu\t%0,%1,%2" 1508 [(set_attr "alu_type" "sub") 1509 (set_attr "mode" "DI")]) 1510 1511;; 1512;; .................... 1513;; 1514;; MULTIPLICATION 1515;; 1516;; .................... 1517;; 1518 1519(define_expand "mul<mode>3" 1520 [(set (match_operand:SCALARF 0 "register_operand") 1521 (mult:SCALARF (match_operand:SCALARF 1 "register_operand") 1522 (match_operand:SCALARF 2 "register_operand")))] 1523 "" 1524 "") 1525 1526(define_insn "*mul<mode>3" 1527 [(set (match_operand:SCALARF 0 "register_operand" "=f") 1528 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f") 1529 (match_operand:SCALARF 2 "register_operand" "f")))] 1530 "!TARGET_4300_MUL_FIX" 1531 "mul.<fmt>\t%0,%1,%2" 1532 [(set_attr "type" "fmul") 1533 (set_attr "mode" "<MODE>")]) 1534 1535;; Early VR4300 silicon has a CPU bug where multiplies with certain 1536;; operands may corrupt immediately following multiplies. This is a 1537;; simple fix to insert NOPs. 1538 1539(define_insn "*mul<mode>3_r4300" 1540 [(set (match_operand:SCALARF 0 "register_operand" "=f") 1541 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f") 1542 (match_operand:SCALARF 2 "register_operand" "f")))] 1543 "TARGET_4300_MUL_FIX" 1544 "mul.<fmt>\t%0,%1,%2\;nop" 1545 [(set_attr "type" "fmul") 1546 (set_attr "mode" "<MODE>") 1547 (set_attr "insn_count" "2")]) 1548 1549(define_insn "mulv2sf3" 1550 [(set (match_operand:V2SF 0 "register_operand" "=f") 1551 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f") 1552 (match_operand:V2SF 2 "register_operand" "f")))] 1553 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" 1554 "mul.ps\t%0,%1,%2" 1555 [(set_attr "type" "fmul") 1556 (set_attr "mode" "SF")]) 1557 1558;; The original R4000 has a cpu bug. If a double-word or a variable 1559;; shift executes while an integer multiplication is in progress, the 1560;; shift may give an incorrect result. Avoid this by keeping the mflo 1561;; with the mult on the R4000. 1562;; 1563;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" 1564;; (also valid for MIPS R4000MC processors): 1565;; 1566;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to 1567;; this errata description. 1568;; The following code sequence causes the R4000 to incorrectly 1569;; execute the Double Shift Right Arithmetic 32 (dsra32) 1570;; instruction. If the dsra32 instruction is executed during an 1571;; integer multiply, the dsra32 will only shift by the amount in 1572;; specified in the instruction rather than the amount plus 32 1573;; bits. 1574;; instruction 1: mult rs,rt integer multiply 1575;; instruction 2-12: dsra32 rd,rt,rs doubleword shift 1576;; right arithmetic + 32 1577;; Workaround: A dsra32 instruction placed after an integer 1578;; multiply should not be one of the 11 instructions after the 1579;; multiply instruction." 1580;; 1581;; and: 1582;; 1583;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by 1584;; the following description. 1585;; All extended shifts (shift by n+32) and variable shifts (32 and 1586;; 64-bit versions) may produce incorrect results under the 1587;; following conditions: 1588;; 1) An integer multiply is currently executing 1589;; 2) These types of shift instructions are executed immediately 1590;; following an integer divide instruction. 1591;; Workaround: 1592;; 1) Make sure no integer multiply is running wihen these 1593;; instruction are executed. If this cannot be predicted at 1594;; compile time, then insert a "mfhi" to R0 instruction 1595;; immediately after the integer multiply instruction. This 1596;; will cause the integer multiply to complete before the shift 1597;; is executed. 1598;; 2) Separate integer divide and these two classes of shift 1599;; instructions by another instruction or a noop." 1600;; 1601;; These processors have PRId values of 0x00004220 and 0x00004300, 1602;; respectively. 1603 1604(define_expand "mul<mode>3" 1605 [(set (match_operand:GPR 0 "register_operand") 1606 (mult:GPR (match_operand:GPR 1 "register_operand") 1607 (match_operand:GPR 2 "register_operand")))] 1608 "ISA_HAS_<D>MULT || ISA_HAS_R6<D>MUL" 1609{ 1610 rtx lo; 1611 1612 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>MUL) 1613 emit_insn (gen_mul<mode>3_mul3_nohilo (operands[0], operands[1], 1614 operands[2])); 1615 else if (ISA_HAS_<D>MUL3) 1616 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2])); 1617 else if (TARGET_MIPS16) 1618 { 1619 lo = gen_rtx_REG (<MODE>mode, LO_REGNUM); 1620 emit_insn (gen_mul<mode>3_internal (lo, operands[1], operands[2])); 1621 emit_move_insn (operands[0], lo); 1622 } 1623 else if (TARGET_FIX_R4000) 1624 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2])); 1625 else 1626 emit_insn 1627 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2])); 1628 DONE; 1629}) 1630 1631(define_insn "mul<mode>3_mul3_nohilo" 1632 [(set (match_operand:GPR 0 "register_operand" "=d") 1633 (mult:GPR (match_operand:GPR 1 "register_operand" "d") 1634 (match_operand:GPR 2 "register_operand" "d")))] 1635 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>MUL" 1636{ 1637 if (TARGET_LOONGSON_2EF) 1638 return "<d>multu.g\t%0,%1,%2"; 1639 else if (TARGET_LOONGSON_EXT) 1640 return "gs<d>multu\t%0,%1,%2"; 1641 else 1642 return "<d>mul\t%0,%1,%2"; 1643} 1644 [(set_attr "type" "imul3nc") 1645 (set_attr "mode" "<MODE>")]) 1646 1647(define_insn "mul<mode>3_mul3" 1648 [(set (match_operand:GPR 0 "register_operand" "=d,l") 1649 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d") 1650 (match_operand:GPR 2 "register_operand" "d,d"))) 1651 (clobber (match_scratch:GPR 3 "=l,X"))] 1652 "ISA_HAS_<D>MUL3" 1653{ 1654 if (which_alternative == 1) 1655 return "<d>mult\t%1,%2"; 1656 if (<MODE>mode == SImode && (TARGET_MIPS3900 || TARGET_MIPS5900)) 1657 return "mult\t%0,%1,%2"; 1658 return "<d>mul\t%0,%1,%2"; 1659} 1660 [(set_attr "type" "imul3,imul") 1661 (set_attr "mode" "<MODE>")]) 1662 1663;; If a register gets allocated to LO, and we spill to memory, the reload 1664;; will include a move from LO to a GPR. Merge it into the multiplication 1665;; if it can set the GPR directly. 1666;; 1667;; Operand 0: LO 1668;; Operand 1: GPR (1st multiplication operand) 1669;; Operand 2: GPR (2nd multiplication operand) 1670;; Operand 3: GPR (destination) 1671(define_peephole2 1672 [(parallel 1673 [(set (match_operand:SI 0 "lo_operand") 1674 (mult:SI (match_operand:SI 1 "d_operand") 1675 (match_operand:SI 2 "d_operand"))) 1676 (clobber (scratch:SI))]) 1677 (set (match_operand:SI 3 "d_operand") 1678 (match_dup 0))] 1679 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])" 1680 [(parallel 1681 [(set (match_dup 3) 1682 (mult:SI (match_dup 1) 1683 (match_dup 2))) 1684 (clobber (match_dup 0))])]) 1685 1686(define_insn "mul<mode>3_internal" 1687 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l") 1688 (mult:GPR (match_operand:GPR 1 "register_operand" "d") 1689 (match_operand:GPR 2 "register_operand" "d")))] 1690 "ISA_HAS_<D>MULT && !TARGET_FIX_R4000" 1691 "<d>mult\t%1,%2" 1692 [(set_attr "type" "imul") 1693 (set_attr "mode" "<MODE>")]) 1694 1695(define_insn "mul<mode>3_r4000" 1696 [(set (match_operand:GPR 0 "register_operand" "=d") 1697 (mult:GPR (match_operand:GPR 1 "register_operand" "d") 1698 (match_operand:GPR 2 "register_operand" "d"))) 1699 (clobber (match_scratch:GPR 3 "=l"))] 1700 "ISA_HAS_<D>MULT && TARGET_FIX_R4000" 1701 "<d>mult\t%1,%2\;mflo\t%0" 1702 [(set_attr "type" "imul") 1703 (set_attr "mode" "<MODE>") 1704 (set_attr "insn_count" "2")]) 1705 1706;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead 1707;; of "mult; mflo". They have the same latency, but the first form gives 1708;; us an extra cycle to compute the operands. 1709 1710;; Operand 0: LO 1711;; Operand 1: GPR (1st multiplication operand) 1712;; Operand 2: GPR (2nd multiplication operand) 1713;; Operand 3: GPR (destination) 1714(define_peephole2 1715 [(set (match_operand:SI 0 "lo_operand") 1716 (mult:SI (match_operand:SI 1 "d_operand") 1717 (match_operand:SI 2 "d_operand"))) 1718 (set (match_operand:SI 3 "d_operand") 1719 (match_dup 0))] 1720 "ISA_HAS_MACC && !ISA_HAS_MUL3" 1721 [(set (match_dup 0) 1722 (const_int 0)) 1723 (parallel 1724 [(set (match_dup 0) 1725 (plus:SI (mult:SI (match_dup 1) 1726 (match_dup 2)) 1727 (match_dup 0))) 1728 (set (match_dup 3) 1729 (plus:SI (mult:SI (match_dup 1) 1730 (match_dup 2)) 1731 (match_dup 0)))])]) 1732 1733;; Multiply-accumulate patterns 1734 1735;; This pattern is first matched by combine, which tries to use the 1736;; pattern wherever it can. We don't know until later whether it 1737;; is actually profitable to use MADD over a "MUL; ADDIU" sequence, 1738;; so we need to keep both options open. 1739;; 1740;; The second alternative has a "?" marker because it is generally 1741;; one instruction more costly than the first alternative. This "?" 1742;; marker is enough to convey the relative costs to the register 1743;; allocator. 1744;; 1745;; However, reload counts reloads of operands 4 and 5 in the same way as 1746;; reloads of the other operands, even though operands 4 and 5 need no 1747;; copy instructions. Reload therefore thinks that the second alternative 1748;; is two reloads more costly than the first. We add "*?*?" to the first 1749;; alternative as a counterweight. 1750;; 1751;; LRA simulates reload but the cost of reloading scratches is lower 1752;; than of the classic reload. For the time being, removing the counterweight 1753;; for LRA is more profitable. 1754(define_insn "*mul_acc_si" 1755 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d?") 1756 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d") 1757 (match_operand:SI 2 "register_operand" "d,d,d")) 1758 (match_operand:SI 3 "register_operand" "l,l,d"))) 1759 (clobber (match_scratch:SI 4 "=X,X,l")) 1760 (clobber (match_scratch:SI 5 "=X,X,&d"))] 1761 "GENERATE_MADD_MSUB && !TARGET_MIPS16" 1762 "@ 1763 madd\t%1,%2 1764 madd\t%1,%2 1765 #" 1766 [(set_attr "type" "imadd") 1767 (set_attr "accum_in" "3") 1768 (set_attr "mode" "SI") 1769 (set_attr "insn_count" "1,1,2") 1770 (set (attr "enabled") 1771 (cond [(and (eq_attr "alternative" "0") 1772 (match_test "!mips_lra_flag")) 1773 (const_string "yes") 1774 (and (eq_attr "alternative" "1") 1775 (match_test "mips_lra_flag")) 1776 (const_string "yes") 1777 (eq_attr "alternative" "2") 1778 (const_string "yes")] 1779 (const_string "no")))]) 1780 1781;; The same idea applies here. The middle alternative needs one less 1782;; clobber than the final alternative, so we add "*?" as a counterweight. 1783(define_insn "*mul_acc_si_r3900" 1784 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d*?,d?") 1785 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d,d") 1786 (match_operand:SI 2 "register_operand" "d,d,d,d")) 1787 (match_operand:SI 3 "register_operand" "l,l,l,d"))) 1788 (clobber (match_scratch:SI 4 "=X,X,3,l")) 1789 (clobber (match_scratch:SI 5 "=X,X,X,&d"))] 1790 "TARGET_MIPS3900 && !TARGET_MIPS16" 1791 "@ 1792 madd\t%1,%2 1793 madd\t%1,%2 1794 madd\t%0,%1,%2 1795 #" 1796 [(set_attr "type" "imadd") 1797 (set_attr "accum_in" "3") 1798 (set_attr "mode" "SI") 1799 (set_attr "insn_count" "1,1,1,2") 1800 (set (attr "enabled") 1801 (cond [(and (eq_attr "alternative" "0") 1802 (match_test "!mips_lra_flag")) 1803 (const_string "yes") 1804 (and (eq_attr "alternative" "1") 1805 (match_test "mips_lra_flag")) 1806 (const_string "yes") 1807 (eq_attr "alternative" "2,3") 1808 (const_string "yes")] 1809 (const_string "no")))]) 1810 1811;; Split *mul_acc_si if both the source and destination accumulator 1812;; values are GPRs. 1813(define_split 1814 [(set (match_operand:SI 0 "d_operand") 1815 (plus:SI (mult:SI (match_operand:SI 1 "d_operand") 1816 (match_operand:SI 2 "d_operand")) 1817 (match_operand:SI 3 "d_operand"))) 1818 (clobber (match_operand:SI 4 "lo_operand")) 1819 (clobber (match_operand:SI 5 "d_operand"))] 1820 "reload_completed" 1821 [(parallel [(set (match_dup 5) 1822 (mult:SI (match_dup 1) (match_dup 2))) 1823 (clobber (match_dup 4))]) 1824 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))] 1825 "") 1826 1827(define_insn "*macc" 1828 [(set (match_operand:SI 0 "register_operand" "=l,d") 1829 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") 1830 (match_operand:SI 2 "register_operand" "d,d")) 1831 (match_operand:SI 3 "register_operand" "l,l"))) 1832 (clobber (match_scratch:SI 4 "=X,3"))] 1833 "ISA_HAS_MACC" 1834{ 1835 if (which_alternative == 1) 1836 return "macc\t%0,%1,%2"; 1837 else if (TARGET_MIPS5500) 1838 return "madd\t%1,%2"; 1839 else 1840 /* The VR4130 assumes that there is a two-cycle latency between a macc 1841 that "writes" to $0 and an instruction that reads from it. We avoid 1842 this by assigning to $1 instead. */ 1843 return "%[macc\t%@,%1,%2%]"; 1844} 1845 [(set_attr "type" "imadd") 1846 (set_attr "accum_in" "3") 1847 (set_attr "mode" "SI")]) 1848 1849(define_insn "*msac" 1850 [(set (match_operand:SI 0 "register_operand" "=l,d") 1851 (minus:SI (match_operand:SI 1 "register_operand" "l,l") 1852 (mult:SI (match_operand:SI 2 "register_operand" "d,d") 1853 (match_operand:SI 3 "register_operand" "d,d")))) 1854 (clobber (match_scratch:SI 4 "=X,1"))] 1855 "ISA_HAS_MSAC" 1856{ 1857 if (which_alternative == 1) 1858 return "msac\t%0,%2,%3"; 1859 else if (TARGET_MIPS5500) 1860 return "msub\t%2,%3"; 1861 else 1862 return "msac\t$0,%2,%3"; 1863} 1864 [(set_attr "type" "imadd") 1865 (set_attr "accum_in" "1") 1866 (set_attr "mode" "SI")]) 1867 1868;; An msac-like instruction implemented using negation and a macc. 1869(define_insn_and_split "*msac_using_macc" 1870 [(set (match_operand:SI 0 "register_operand" "=l,d") 1871 (minus:SI (match_operand:SI 1 "register_operand" "l,l") 1872 (mult:SI (match_operand:SI 2 "register_operand" "d,d") 1873 (match_operand:SI 3 "register_operand" "d,d")))) 1874 (clobber (match_scratch:SI 4 "=X,1")) 1875 (clobber (match_scratch:SI 5 "=d,d"))] 1876 "ISA_HAS_MACC && !ISA_HAS_MSAC" 1877 "#" 1878 "&& reload_completed" 1879 [(set (match_dup 5) 1880 (neg:SI (match_dup 3))) 1881 (parallel 1882 [(set (match_dup 0) 1883 (plus:SI (mult:SI (match_dup 2) 1884 (match_dup 5)) 1885 (match_dup 1))) 1886 (clobber (match_dup 4))])] 1887 "" 1888 [(set_attr "type" "imadd") 1889 (set_attr "accum_in" "1") 1890 (set_attr "insn_count" "2")]) 1891 1892;; Patterns generated by the define_peephole2 below. 1893 1894(define_insn "*macc2" 1895 [(set (match_operand:SI 0 "muldiv_target_operand" "=l") 1896 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") 1897 (match_operand:SI 2 "register_operand" "d")) 1898 (match_dup 0))) 1899 (set (match_operand:SI 3 "register_operand" "=d") 1900 (plus:SI (mult:SI (match_dup 1) 1901 (match_dup 2)) 1902 (match_dup 0)))] 1903 "ISA_HAS_MACC && reload_completed" 1904 "macc\t%3,%1,%2" 1905 [(set_attr "type" "imadd") 1906 (set_attr "accum_in" "0") 1907 (set_attr "mode" "SI")]) 1908 1909(define_insn "*msac2" 1910 [(set (match_operand:SI 0 "muldiv_target_operand" "=l") 1911 (minus:SI (match_dup 0) 1912 (mult:SI (match_operand:SI 1 "register_operand" "d") 1913 (match_operand:SI 2 "register_operand" "d")))) 1914 (set (match_operand:SI 3 "register_operand" "=d") 1915 (minus:SI (match_dup 0) 1916 (mult:SI (match_dup 1) 1917 (match_dup 2))))] 1918 "ISA_HAS_MSAC && reload_completed" 1919 "msac\t%3,%1,%2" 1920 [(set_attr "type" "imadd") 1921 (set_attr "accum_in" "0") 1922 (set_attr "mode" "SI")]) 1923 1924;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2> 1925;; Similarly msac. 1926;; 1927;; Operand 0: LO 1928;; Operand 1: macc/msac 1929;; Operand 2: GPR (destination) 1930(define_peephole2 1931 [(parallel 1932 [(set (match_operand:SI 0 "lo_operand") 1933 (match_operand:SI 1 "macc_msac_operand")) 1934 (clobber (scratch:SI))]) 1935 (set (match_operand:SI 2 "d_operand") 1936 (match_dup 0))] 1937 "" 1938 [(parallel [(set (match_dup 0) 1939 (match_dup 1)) 1940 (set (match_dup 2) 1941 (match_dup 1))])]) 1942 1943;; When we have a three-address multiplication instruction, it should 1944;; be faster to do a separate multiply and add, rather than moving 1945;; something into LO in order to use a macc instruction. 1946;; 1947;; This peephole needs a scratch register to cater for the case when one 1948;; of the multiplication operands is the same as the destination. 1949;; 1950;; Operand 0: GPR (scratch) 1951;; Operand 1: LO 1952;; Operand 2: GPR (addend) 1953;; Operand 3: GPR (destination) 1954;; Operand 4: macc/msac 1955;; Operand 5: new multiplication 1956;; Operand 6: new addition/subtraction 1957(define_peephole2 1958 [(match_scratch:SI 0 "d") 1959 (set (match_operand:SI 1 "lo_operand") 1960 (match_operand:SI 2 "d_operand")) 1961 (match_dup 0) 1962 (parallel 1963 [(set (match_operand:SI 3 "d_operand") 1964 (match_operand:SI 4 "macc_msac_operand")) 1965 (clobber (match_dup 1))])] 1966 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])" 1967 [(parallel [(set (match_dup 0) 1968 (match_dup 5)) 1969 (clobber (match_dup 1))]) 1970 (set (match_dup 3) 1971 (match_dup 6))] 1972{ 1973 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1); 1974 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, 1975 operands[2], operands[0]); 1976}) 1977 1978;; Same as above, except LO is the initial target of the macc. 1979;; 1980;; Operand 0: GPR (scratch) 1981;; Operand 1: LO 1982;; Operand 2: GPR (addend) 1983;; Operand 3: macc/msac 1984;; Operand 4: GPR (destination) 1985;; Operand 5: new multiplication 1986;; Operand 6: new addition/subtraction 1987(define_peephole2 1988 [(match_scratch:SI 0 "d") 1989 (set (match_operand:SI 1 "lo_operand") 1990 (match_operand:SI 2 "d_operand")) 1991 (match_dup 0) 1992 (parallel 1993 [(set (match_dup 1) 1994 (match_operand:SI 3 "macc_msac_operand")) 1995 (clobber (scratch:SI))]) 1996 (match_dup 0) 1997 (set (match_operand:SI 4 "d_operand") 1998 (match_dup 1))] 1999 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])" 2000 [(parallel [(set (match_dup 0) 2001 (match_dup 5)) 2002 (clobber (match_dup 1))]) 2003 (set (match_dup 4) 2004 (match_dup 6))] 2005{ 2006 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1); 2007 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, 2008 operands[2], operands[0]); 2009}) 2010 2011;; See the comment above *mul_add_si for details. 2012(define_insn "*mul_sub_si" 2013 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d?") 2014 (minus:SI (match_operand:SI 1 "register_operand" "l,l,d") 2015 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d") 2016 (match_operand:SI 3 "register_operand" "d,d,d")))) 2017 (clobber (match_scratch:SI 4 "=X,X,l")) 2018 (clobber (match_scratch:SI 5 "=X,X,&d"))] 2019 "GENERATE_MADD_MSUB" 2020 "@ 2021 msub\t%2,%3 2022 msub\t%2,%3 2023 #" 2024 [(set_attr "type" "imadd") 2025 (set_attr "accum_in" "1") 2026 (set_attr "mode" "SI") 2027 (set_attr "insn_count" "1,1,2") 2028 (set (attr "enabled") 2029 (cond [(and (eq_attr "alternative" "0") 2030 (match_test "!mips_lra_flag")) 2031 (const_string "yes") 2032 (and (eq_attr "alternative" "1") 2033 (match_test "mips_lra_flag")) 2034 (const_string "yes") 2035 (eq_attr "alternative" "2") 2036 (const_string "yes")] 2037 (const_string "no")))]) 2038 2039;; Split *mul_sub_si if both the source and destination accumulator 2040;; values are GPRs. 2041(define_split 2042 [(set (match_operand:SI 0 "d_operand") 2043 (minus:SI (match_operand:SI 1 "d_operand") 2044 (mult:SI (match_operand:SI 2 "d_operand") 2045 (match_operand:SI 3 "d_operand")))) 2046 (clobber (match_operand:SI 4 "lo_operand")) 2047 (clobber (match_operand:SI 5 "d_operand"))] 2048 "reload_completed" 2049 [(parallel [(set (match_dup 5) 2050 (mult:SI (match_dup 2) (match_dup 3))) 2051 (clobber (match_dup 4))]) 2052 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))] 2053 "") 2054 2055(define_insn "*muls" 2056 [(set (match_operand:SI 0 "register_operand" "=l,d") 2057 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") 2058 (match_operand:SI 2 "register_operand" "d,d")))) 2059 (clobber (match_scratch:SI 3 "=X,l"))] 2060 "ISA_HAS_MULS" 2061 "@ 2062 muls\t$0,%1,%2 2063 muls\t%0,%1,%2" 2064 [(set_attr "type" "imul,imul3") 2065 (set_attr "mode" "SI")]) 2066 2067(define_expand "<u>mulsidi3" 2068 [(set (match_operand:DI 0 "register_operand") 2069 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2070 (any_extend:DI (match_operand:SI 2 "register_operand"))))] 2071 "mips_mulsidi3_gen_fn (<CODE>) != NULL" 2072{ 2073 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>); 2074 emit_insn (fn (operands[0], operands[1], operands[2])); 2075 DONE; 2076}) 2077 2078(define_expand "<u>mulsidi3_32bit_r6" 2079 [(set (match_operand:DI 0 "register_operand") 2080 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2081 (any_extend:DI (match_operand:SI 2 "register_operand"))))] 2082 "!TARGET_64BIT && ISA_HAS_R6MUL" 2083{ 2084 rtx dest = gen_reg_rtx (DImode); 2085 rtx low = mips_subword (dest, 0); 2086 rtx high = mips_subword (dest, 1); 2087 2088 emit_insn (gen_mulsi3_mul3_nohilo (low, operands[1], operands[2])); 2089 emit_insn (gen_<su>mulsi3_highpart_r6 (high, operands[1], operands[2])); 2090 2091 emit_move_insn (mips_subword (operands[0], 0), low); 2092 emit_move_insn (mips_subword (operands[0], 1), high); 2093 DONE; 2094}) 2095 2096(define_expand "<u>mulsidi3_32bit_mips16" 2097 [(set (match_operand:DI 0 "register_operand") 2098 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2099 (any_extend:DI (match_operand:SI 2 "register_operand"))))] 2100 "!TARGET_64BIT && TARGET_MIPS16" 2101{ 2102 rtx hilo; 2103 2104 hilo = gen_rtx_REG (DImode, MD_REG_FIRST); 2105 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2])); 2106 emit_move_insn (operands[0], hilo); 2107 DONE; 2108}) 2109 2110;; As well as being named patterns, these instructions are used by the 2111;; __builtin_mips_mult<u>() functions. We must always make those functions 2112;; available if !TARGET_64BIT && ISA_HAS_DSP. 2113(define_insn "<u>mulsidi3_32bit" 2114 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka") 2115 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2116 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))] 2117 "!TARGET_64BIT && (!TARGET_FIX_R4000 || ISA_HAS_DSP) && ISA_HAS_MULT" 2118{ 2119 if (ISA_HAS_DSP_MULT) 2120 return "mult<u>\t%q0,%1,%2"; 2121 else 2122 return "mult<u>\t%1,%2"; 2123} 2124 [(set_attr "type" "imul") 2125 (set_attr "mode" "SI")]) 2126 2127(define_insn "<u>mulsidi3_32bit_r4000" 2128 [(set (match_operand:DI 0 "register_operand" "=d") 2129 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2130 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) 2131 (clobber (match_scratch:DI 3 "=x"))] 2132 "!TARGET_64BIT && TARGET_FIX_R4000 && !ISA_HAS_DSP && ISA_HAS_MULT" 2133 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0" 2134 [(set_attr "type" "imul") 2135 (set_attr "mode" "SI") 2136 (set_attr "insn_count" "3")]) 2137 2138(define_insn_and_split "<u>mulsidi3_64bit" 2139 [(set (match_operand:DI 0 "register_operand" "=d") 2140 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2141 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) 2142 (clobber (match_scratch:TI 3 "=x")) 2143 (clobber (match_scratch:DI 4 "=d"))] 2144 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DMUL3 2145 && !TARGET_MIPS16 && ISA_HAS_MULT" 2146 "#" 2147 "&& reload_completed" 2148 [(const_int 0)] 2149{ 2150 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1], 2151 operands[2], operands[4])); 2152 DONE; 2153} 2154 [(set_attr "type" "imul") 2155 (set_attr "mode" "SI") 2156 (set (attr "insn_count") 2157 (if_then_else (match_test "ISA_HAS_EXT_INS") 2158 (const_int 4) 2159 (const_int 7)))]) 2160 2161(define_expand "<u>mulsidi3_64bit_mips16" 2162 [(set (match_operand:DI 0 "register_operand") 2163 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2164 (any_extend:DI (match_operand:SI 2 "register_operand"))))] 2165 "TARGET_64BIT && TARGET_MIPS16" 2166{ 2167 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1], 2168 operands[2], gen_reg_rtx (DImode))); 2169 DONE; 2170}) 2171 2172(define_expand "<u>mulsidi3_64bit_split" 2173 [(set (match_operand:DI 0 "register_operand") 2174 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2175 (any_extend:DI (match_operand:SI 2 "register_operand")))) 2176 (clobber (match_operand:DI 3 "register_operand"))] 2177 "" 2178{ 2179 rtx hilo; 2180 2181 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 2182 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2])); 2183 2184 emit_move_insn (operands[0], gen_rtx_REG (DImode, LO_REGNUM)); 2185 emit_insn (gen_mfhidi_ti (operands[3], hilo)); 2186 2187 if (ISA_HAS_EXT_INS) 2188 emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32), 2189 operands[3])); 2190 else 2191 { 2192 /* Zero-extend the low part. */ 2193 mips_emit_binary (ASHIFT, operands[0], operands[0], GEN_INT (32)); 2194 mips_emit_binary (LSHIFTRT, operands[0], operands[0], GEN_INT (32)); 2195 2196 /* Shift the high part into place. */ 2197 mips_emit_binary (ASHIFT, operands[3], operands[3], GEN_INT (32)); 2198 2199 /* OR the two halves together. */ 2200 mips_emit_binary (IOR, operands[0], operands[0], operands[3]); 2201 } 2202 DONE; 2203}) 2204 2205(define_insn "<u>mulsidi3_64bit_hilo" 2206 [(set (match_operand:TI 0 "muldiv_target_operand" "=x") 2207 (unspec:TI 2208 [(mult:DI 2209 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2210 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))] 2211 UNSPEC_SET_HILO))] 2212 "TARGET_64BIT && !TARGET_FIX_R4000" 2213 "mult<u>\t%1,%2" 2214 [(set_attr "type" "imul") 2215 (set_attr "mode" "SI")]) 2216 2217;; See comment before the ISA_HAS_DMUL3 case in mips_mulsidi3_gen_fn. 2218(define_insn "mulsidi3_64bit_dmul" 2219 [(set (match_operand:DI 0 "register_operand" "=d") 2220 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) 2221 (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))) 2222 (clobber (match_scratch:DI 3 "=l"))] 2223 "ISA_HAS_DMUL3" 2224 "dmul\t%0,%1,%2" 2225 [(set_attr "type" "imul3") 2226 (set_attr "mode" "DI")]) 2227 2228(define_insn "mulsidi3_64bit_r6dmul" 2229 [(set (match_operand:DI 0 "register_operand" "=d") 2230 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) 2231 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] 2232 "ISA_HAS_R6DMUL" 2233 "dmul\t%0,%1,%2" 2234 [(set_attr "type" "imul3nc") 2235 (set_attr "mode" "DI")]) 2236 2237;; Widening multiply with negation. 2238(define_insn "*muls<u>_di" 2239 [(set (match_operand:DI 0 "muldiv_target_operand" "=x") 2240 (neg:DI 2241 (mult:DI 2242 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2243 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))] 2244 "!TARGET_64BIT && ISA_HAS_MULS" 2245 "muls<u>\t$0,%1,%2" 2246 [(set_attr "type" "imul") 2247 (set_attr "mode" "SI")]) 2248 2249;; As well as being named patterns, these instructions are used by the 2250;; __builtin_mips_msub<u>() functions. We must always make those functions 2251;; available if !TARGET_64BIT && ISA_HAS_DSP. 2252;; 2253;; This leads to a slight inconsistency. We honor any tuning overrides 2254;; in GENERATE_MADD_MSUB for -mno-dsp, but always ignore them for -mdsp, 2255;; even if !ISA_HAS_DSP_MULT. 2256(define_insn "<u>msubsidi4" 2257 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka") 2258 (minus:DI 2259 (match_operand:DI 3 "muldiv_target_operand" "0") 2260 (mult:DI 2261 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2262 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))] 2263 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)" 2264{ 2265 if (ISA_HAS_DSP_MULT) 2266 return "msub<u>\t%q0,%1,%2"; 2267 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB) 2268 return "msub<u>\t%1,%2"; 2269 else 2270 return "msac<u>\t$0,%1,%2"; 2271} 2272 [(set_attr "type" "imadd") 2273 (set_attr "accum_in" "3") 2274 (set_attr "mode" "SI")]) 2275 2276;; _highpart patterns 2277 2278(define_expand "<su>mulsi3_highpart" 2279 [(set (match_operand:SI 0 "register_operand") 2280 (truncate:SI 2281 (lshiftrt:DI 2282 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2283 (any_extend:DI (match_operand:SI 2 "register_operand"))) 2284 (const_int 32))))] 2285 "" 2286{ 2287 if (ISA_HAS_MULHI) 2288 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0], 2289 operands[1], 2290 operands[2])); 2291 else if (TARGET_MIPS16) 2292 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1], 2293 operands[2])); 2294 else if (ISA_HAS_R6MUL) 2295 emit_insn (gen_<su>mulsi3_highpart_r6 (operands[0], operands[1], 2296 operands[2])); 2297 else 2298 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1], 2299 operands[2])); 2300 DONE; 2301}) 2302 2303(define_insn "<su>mulsi3_highpart_r6" 2304 [(set (match_operand:SI 0 "register_operand" "=d") 2305 (truncate:SI 2306 (lshiftrt:DI 2307 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2308 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 2309 (const_int 32))))] 2310 "ISA_HAS_R6MUL" 2311 "muh<u>\t%0,%1,%2" 2312 [(set_attr "type" "imul3nc") 2313 (set_attr "mode" "SI")]) 2314 2315(define_insn_and_split "<su>mulsi3_highpart_internal" 2316 [(set (match_operand:SI 0 "register_operand" "=d") 2317 (truncate:SI 2318 (lshiftrt:DI 2319 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2320 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 2321 (const_int 32)))) 2322 (clobber (match_scratch:SI 3 "=l"))] 2323 "ISA_HAS_MULT && !ISA_HAS_MULHI && !TARGET_MIPS16" 2324 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; } 2325 "&& reload_completed && !TARGET_FIX_R4000" 2326 [(const_int 0)] 2327{ 2328 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1], 2329 operands[2])); 2330 DONE; 2331} 2332 [(set_attr "type" "imul") 2333 (set_attr "mode" "SI") 2334 (set_attr "insn_count" "2")]) 2335 2336(define_expand "<su>mulsi3_highpart_split" 2337 [(set (match_operand:SI 0 "register_operand") 2338 (truncate:SI 2339 (lshiftrt:DI 2340 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2341 (any_extend:DI (match_operand:SI 2 "register_operand"))) 2342 (const_int 32))))] 2343 "" 2344{ 2345 rtx hilo; 2346 2347 if (TARGET_64BIT) 2348 { 2349 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 2350 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2])); 2351 emit_insn (gen_mfhisi_ti (operands[0], hilo)); 2352 } 2353 else 2354 { 2355 hilo = gen_rtx_REG (DImode, MD_REG_FIRST); 2356 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2])); 2357 emit_insn (gen_mfhisi_di (operands[0], hilo)); 2358 } 2359 DONE; 2360}) 2361 2362(define_insn "<su>mulsi3_highpart_mulhi_internal" 2363 [(set (match_operand:SI 0 "register_operand" "=d") 2364 (truncate:SI 2365 (lshiftrt:DI 2366 (mult:DI 2367 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2368 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 2369 (const_int 32)))) 2370 (clobber (match_scratch:SI 3 "=l"))] 2371 "ISA_HAS_MULHI" 2372 "mulhi<u>\t%0,%1,%2" 2373 [(set_attr "type" "imul3") 2374 (set_attr "mode" "SI")]) 2375 2376(define_insn "*<su>mulsi3_highpart_neg_mulhi_internal" 2377 [(set (match_operand:SI 0 "register_operand" "=d") 2378 (truncate:SI 2379 (lshiftrt:DI 2380 (neg:DI 2381 (mult:DI 2382 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2383 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) 2384 (const_int 32)))) 2385 (clobber (match_scratch:SI 3 "=l"))] 2386 "ISA_HAS_MULHI" 2387 "mulshi<u>\t%0,%1,%2" 2388 [(set_attr "type" "imul3") 2389 (set_attr "mode" "SI")]) 2390 2391;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120 2392;; errata MD(0), which says that dmultu does not always produce the 2393;; correct result. 2394(define_expand "<su>muldi3_highpart" 2395 [(set (match_operand:DI 0 "register_operand") 2396 (truncate:DI 2397 (lshiftrt:TI 2398 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) 2399 (any_extend:TI (match_operand:DI 2 "register_operand"))) 2400 (const_int 64))))] 2401 "ISA_HAS_R6DMUL 2402 || (ISA_HAS_DMULT 2403 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120))" 2404{ 2405 if (TARGET_MIPS16) 2406 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1], 2407 operands[2])); 2408 else if (ISA_HAS_R6DMUL) 2409 emit_insn (gen_<su>muldi3_highpart_r6 (operands[0], operands[1], 2410 operands[2])); 2411 else 2412 emit_insn (gen_<su>muldi3_highpart_internal (operands[0], operands[1], 2413 operands[2])); 2414 DONE; 2415}) 2416 2417(define_insn "<su>muldi3_highpart_r6" 2418 [(set (match_operand:DI 0 "register_operand" "=d") 2419 (truncate:DI 2420 (lshiftrt:TI 2421 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) 2422 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))) 2423 (const_int 64))))] 2424 "ISA_HAS_R6DMUL" 2425 "dmuh<u>\t%0,%1,%2" 2426 [(set_attr "type" "imul3nc") 2427 (set_attr "mode" "DI")]) 2428 2429(define_insn_and_split "<su>muldi3_highpart_internal" 2430 [(set (match_operand:DI 0 "register_operand" "=d") 2431 (truncate:DI 2432 (lshiftrt:TI 2433 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) 2434 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))) 2435 (const_int 64)))) 2436 (clobber (match_scratch:DI 3 "=l"))] 2437 "ISA_HAS_DMULT 2438 && !TARGET_MIPS16 2439 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" 2440 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; } 2441 "&& reload_completed && !TARGET_FIX_R4000" 2442 [(const_int 0)] 2443{ 2444 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1], 2445 operands[2])); 2446 DONE; 2447} 2448 [(set_attr "type" "imul") 2449 (set_attr "mode" "DI") 2450 (set_attr "insn_count" "2")]) 2451 2452(define_expand "<su>muldi3_highpart_split" 2453 [(set (match_operand:DI 0 "register_operand") 2454 (truncate:DI 2455 (lshiftrt:TI 2456 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) 2457 (any_extend:TI (match_operand:DI 2 "register_operand"))) 2458 (const_int 64))))] 2459 "" 2460{ 2461 rtx hilo; 2462 2463 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 2464 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2])); 2465 emit_insn (gen_mfhidi_ti (operands[0], hilo)); 2466 DONE; 2467}) 2468 2469(define_expand "<u>mulditi3" 2470 [(set (match_operand:TI 0 "register_operand") 2471 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) 2472 (any_extend:TI (match_operand:DI 2 "register_operand"))))] 2473 "ISA_HAS_R6DMUL 2474 || (ISA_HAS_DMULT 2475 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120))" 2476{ 2477 rtx hilo, hi, lo; 2478 2479 if (TARGET_MIPS16) 2480 { 2481 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 2482 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2])); 2483 emit_move_insn (operands[0], hilo); 2484 } 2485 else if (TARGET_FIX_R4000) 2486 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2])); 2487 else if (ISA_HAS_DMULT) 2488 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1], 2489 operands[2])); 2490 else 2491 { 2492 hi = mips_subword (operands[0], 1); 2493 lo = mips_subword (operands[0], 0); 2494 emit_insn (gen_muldi3_mul3_nohilo (lo, operands[1], operands[2])); 2495 emit_insn (gen_<su>muldi3_highpart_r6 (hi, operands[1], operands[2])); 2496 } 2497 DONE; 2498}) 2499 2500(define_insn "<u>mulditi3_internal" 2501 [(set (match_operand:TI 0 "muldiv_target_operand" "=x") 2502 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) 2503 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))] 2504 "ISA_HAS_DMULT 2505 && !TARGET_FIX_R4000 2506 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" 2507 "dmult<u>\t%1,%2" 2508 [(set_attr "type" "imul") 2509 (set_attr "mode" "DI")]) 2510 2511(define_insn "<u>mulditi3_r4000" 2512 [(set (match_operand:TI 0 "register_operand" "=d") 2513 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) 2514 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))) 2515 (clobber (match_scratch:TI 3 "=x"))] 2516 "ISA_HAS_DMULT 2517 && TARGET_FIX_R4000 2518 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" 2519 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0" 2520 [(set_attr "type" "imul") 2521 (set_attr "mode" "DI") 2522 (set_attr "insn_count" "3")]) 2523 2524;; The R4650 supports a 32-bit multiply/ 64-bit accumulate 2525;; instruction. The HI/LO registers are used as a 64-bit accumulator. 2526 2527(define_insn "madsi" 2528 [(set (match_operand:SI 0 "register_operand" "+l") 2529 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") 2530 (match_operand:SI 2 "register_operand" "d")) 2531 (match_dup 0)))] 2532 "TARGET_MAD" 2533 "mad\t%1,%2" 2534 [(set_attr "type" "imadd") 2535 (set_attr "accum_in" "0") 2536 (set_attr "mode" "SI")]) 2537 2538;; See the comment above <u>msubsidi4 for the relationship between 2539;; ISA_HAS_DSP and ISA_HAS_DSP_MULT. 2540(define_insn "<u>maddsidi4" 2541 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka") 2542 (plus:DI 2543 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2544 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 2545 (match_operand:DI 3 "muldiv_target_operand" "0")))] 2546 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP) 2547 && !TARGET_64BIT" 2548{ 2549 if (TARGET_MAD) 2550 return "mad<u>\t%1,%2"; 2551 else if (ISA_HAS_DSP_MULT) 2552 return "madd<u>\t%q0,%1,%2"; 2553 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500) 2554 return "madd<u>\t%1,%2"; 2555 else 2556 /* See comment in *macc. */ 2557 return "%[macc<u>\t%@,%1,%2%]"; 2558} 2559 [(set_attr "type" "imadd") 2560 (set_attr "accum_in" "3") 2561 (set_attr "mode" "SI")]) 2562 2563;; Floating point multiply accumulate instructions. 2564 2565(define_expand "fma<mode>4" 2566 [(set (match_operand:ANYF 0 "register_operand") 2567 (fma:ANYF (match_operand:ANYF 1 "register_operand") 2568 (match_operand:ANYF 2 "register_operand") 2569 (match_operand:ANYF 3 "register_operand")))] 2570 "ISA_HAS_FUSED_MADDF || ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4") 2571 2572(define_insn "*fma<mode>4_madd3" 2573 [(set (match_operand:ANYF 0 "register_operand" "=f") 2574 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f") 2575 (match_operand:ANYF 2 "register_operand" "f") 2576 (match_operand:ANYF 3 "register_operand" "0")))] 2577 "ISA_HAS_FUSED_MADD3" 2578 "madd.<fmt>\t%0,%1,%2" 2579 [(set_attr "type" "fmadd") 2580 (set_attr "mode" "<UNITMODE>")]) 2581 2582(define_insn "*fma<mode>4_madd4" 2583 [(set (match_operand:ANYF 0 "register_operand" "=f") 2584 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f") 2585 (match_operand:ANYF 2 "register_operand" "f") 2586 (match_operand:ANYF 3 "register_operand" "f")))] 2587 "ISA_HAS_FUSED_MADD4" 2588 "madd.<fmt>\t%0,%3,%1,%2" 2589 [(set_attr "type" "fmadd") 2590 (set_attr "mode" "<UNITMODE>")]) 2591 2592(define_insn "*fma<mode>4_maddf" 2593 [(set (match_operand:ANYF 0 "register_operand" "=f") 2594 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f") 2595 (match_operand:ANYF 2 "register_operand" "f") 2596 (match_operand:ANYF 3 "register_operand" "0")))] 2597 "ISA_HAS_FUSED_MADDF" 2598 "maddf.<fmt>\t%0,%1,%2" 2599 [(set_attr "type" "fmadd") 2600 (set_attr "mode" "<UNITMODE>")]) 2601 2602;; The fms, fnma, and fnms instructions can be used even when HONOR_NANS 2603;; is true because while IEEE 754-2008 requires the negate operation to 2604;; negate the sign of a NAN and the MIPS neg instruction does not do this, 2605;; the fma part of the instruction has no requirement on how the sign of 2606;; a NAN is handled and so the final sign bit of the entire operation is 2607;; undefined. 2608 2609(define_expand "fms<mode>4" 2610 [(set (match_operand:ANYF 0 "register_operand") 2611 (fma:ANYF (match_operand:ANYF 1 "register_operand") 2612 (match_operand:ANYF 2 "register_operand") 2613 (neg:ANYF (match_operand:ANYF 3 "register_operand"))))] 2614 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4)") 2615 2616(define_insn "*fms<mode>4_msub3" 2617 [(set (match_operand:ANYF 0 "register_operand" "=f") 2618 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f") 2619 (match_operand:ANYF 2 "register_operand" "f") 2620 (neg:ANYF (match_operand:ANYF 3 "register_operand" "0"))))] 2621 "ISA_HAS_FUSED_MADD3" 2622 "msub.<fmt>\t%0,%1,%2" 2623 [(set_attr "type" "fmadd") 2624 (set_attr "mode" "<UNITMODE>")]) 2625 2626(define_insn "*fms<mode>4_msub4" 2627 [(set (match_operand:ANYF 0 "register_operand" "=f") 2628 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f") 2629 (match_operand:ANYF 2 "register_operand" "f") 2630 (neg:ANYF (match_operand:ANYF 3 "register_operand" "f"))))] 2631 "ISA_HAS_FUSED_MADD4" 2632 "msub.<fmt>\t%0,%3,%1,%2" 2633 [(set_attr "type" "fmadd") 2634 (set_attr "mode" "<UNITMODE>")]) 2635 2636;; fnma is defined in GCC as (fma (neg op1) op2 op3) 2637;; (-op1 * op2) + op3 ==> -(op1 * op2) + op3 ==> -((op1 * op2) - op3) 2638;; The mips nmsub instructions implement -((op1 * op2) - op3) 2639;; This transformation means we may return the wrong signed zero 2640;; so we check HONOR_SIGNED_ZEROS. 2641 2642(define_expand "fnma<mode>4" 2643 [(set (match_operand:ANYF 0 "register_operand") 2644 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand")) 2645 (match_operand:ANYF 2 "register_operand") 2646 (match_operand:ANYF 3 "register_operand")))] 2647 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4) 2648 && !HONOR_SIGNED_ZEROS (<MODE>mode)") 2649 2650(define_insn "*fnma<mode>4_nmsub3" 2651 [(set (match_operand:ANYF 0 "register_operand" "=f") 2652 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) 2653 (match_operand:ANYF 2 "register_operand" "f") 2654 (match_operand:ANYF 3 "register_operand" "0")))] 2655 "ISA_HAS_FUSED_MADD3 && !HONOR_SIGNED_ZEROS (<MODE>mode)" 2656 "nmsub.<fmt>\t%0,%1,%2" 2657 [(set_attr "type" "fmadd") 2658 (set_attr "mode" "<UNITMODE>")]) 2659 2660(define_insn "*fnma<mode>4_nmsub4" 2661 [(set (match_operand:ANYF 0 "register_operand" "=f") 2662 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) 2663 (match_operand:ANYF 2 "register_operand" "f") 2664 (match_operand:ANYF 3 "register_operand" "f")))] 2665 "ISA_HAS_FUSED_MADD4 && !HONOR_SIGNED_ZEROS (<MODE>mode)" 2666 "nmsub.<fmt>\t%0,%3,%1,%2" 2667 [(set_attr "type" "fmadd") 2668 (set_attr "mode" "<UNITMODE>")]) 2669 2670;; fnms is defined as: (fma (neg op1) op2 (neg op3)) 2671;; ((-op1) * op2) - op3 ==> -(op1 * op2) - op3 ==> -((op1 * op2) + op3) 2672;; The mips nmadd instructions implement -((op1 * op2) + op3) 2673;; This transformation means we may return the wrong signed zero 2674;; so we check HONOR_SIGNED_ZEROS. 2675 2676(define_expand "fnms<mode>4" 2677 [(set (match_operand:ANYF 0 "register_operand") 2678 (fma:ANYF 2679 (neg:ANYF (match_operand:ANYF 1 "register_operand")) 2680 (match_operand:ANYF 2 "register_operand") 2681 (neg:ANYF (match_operand:ANYF 3 "register_operand"))))] 2682 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4) 2683 && !HONOR_SIGNED_ZEROS (<MODE>mode)") 2684 2685(define_insn "*fnms<mode>4_nmadd3" 2686 [(set (match_operand:ANYF 0 "register_operand" "=f") 2687 (fma:ANYF 2688 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) 2689 (match_operand:ANYF 2 "register_operand" "f") 2690 (neg:ANYF (match_operand:ANYF 3 "register_operand" "0"))))] 2691 "ISA_HAS_FUSED_MADD3 && !HONOR_SIGNED_ZEROS (<MODE>mode)" 2692 "nmadd.<fmt>\t%0,%1,%2" 2693 [(set_attr "type" "fmadd") 2694 (set_attr "mode" "<UNITMODE>")]) 2695 2696(define_insn "*fnms<mode>4_nmadd4" 2697 [(set (match_operand:ANYF 0 "register_operand" "=f") 2698 (fma:ANYF 2699 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) 2700 (match_operand:ANYF 2 "register_operand" "f") 2701 (neg:ANYF (match_operand:ANYF 3 "register_operand" "f"))))] 2702 "ISA_HAS_FUSED_MADD4 && !HONOR_SIGNED_ZEROS (<MODE>mode)" 2703 "nmadd.<fmt>\t%0,%3,%1,%2" 2704 [(set_attr "type" "fmadd") 2705 (set_attr "mode" "<UNITMODE>")]) 2706 2707;; Non-fused Floating point multiply accumulate instructions. 2708 2709;; These instructions are not fused and round in between the multiply 2710;; and the add (or subtract) so they are equivalent to the separate 2711;; multiply and add/sub instructions. 2712 2713(define_insn "*madd4<mode>" 2714 [(set (match_operand:ANYF 0 "register_operand" "=f") 2715 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 2716 (match_operand:ANYF 2 "register_operand" "f")) 2717 (match_operand:ANYF 3 "register_operand" "f")))] 2718 "ISA_HAS_UNFUSED_MADD4" 2719 "madd.<fmt>\t%0,%3,%1,%2" 2720 [(set_attr "type" "fmadd") 2721 (set_attr "mode" "<UNITMODE>")]) 2722 2723(define_insn "*msub4<mode>" 2724 [(set (match_operand:ANYF 0 "register_operand" "=f") 2725 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 2726 (match_operand:ANYF 2 "register_operand" "f")) 2727 (match_operand:ANYF 3 "register_operand" "f")))] 2728 "ISA_HAS_UNFUSED_MADD4" 2729 "msub.<fmt>\t%0,%3,%1,%2" 2730 [(set_attr "type" "fmadd") 2731 (set_attr "mode" "<UNITMODE>")]) 2732 2733;; Like with the fused fms, fnma, and fnms instructions, these unfused 2734;; instructions can be used even if HONOR_NANS is set because while 2735;; IEEE 754-2008 requires the negate operation to negate the sign of a 2736;; NAN and the MIPS neg instruction does not do this, the multiply and 2737;; add (or subtract) part of the instruction has no requirement on how 2738;; the sign of a NAN is handled and so the final sign bit of the entire 2739;; operation is undefined. 2740 2741(define_insn "*nmadd4<mode>" 2742 [(set (match_operand:ANYF 0 "register_operand" "=f") 2743 (neg:ANYF (plus:ANYF 2744 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 2745 (match_operand:ANYF 2 "register_operand" "f")) 2746 (match_operand:ANYF 3 "register_operand" "f"))))] 2747 "ISA_HAS_UNFUSED_MADD4" 2748 "nmadd.<fmt>\t%0,%3,%1,%2" 2749 [(set_attr "type" "fmadd") 2750 (set_attr "mode" "<UNITMODE>")]) 2751 2752(define_insn "*nmsub4<mode>" 2753 [(set (match_operand:ANYF 0 "register_operand" "=f") 2754 (neg:ANYF (minus:ANYF 2755 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 2756 (match_operand:ANYF 2 "register_operand" "f")) 2757 (match_operand:ANYF 3 "register_operand" "f"))))] 2758 "ISA_HAS_UNFUSED_MADD4" 2759 "nmsub.<fmt>\t%0,%3,%1,%2" 2760 [(set_attr "type" "fmadd") 2761 (set_attr "mode" "<UNITMODE>")]) 2762 2763;; Fast-math Non-fused Floating point multiply accumulate instructions. 2764 2765;; These instructions are not fused but the expressions they match are 2766;; not exactly what the instruction implements in the sense that they 2767;; may not generate the properly signed zeros. 2768 2769;; This instruction recognizes ((-op1) * op2) - op3 and generates an 2770;; nmadd which is really -((op1 * op2) + op3). They are equivalent 2771;; except for the sign bit when the result is zero or NaN. 2772 2773(define_insn "*nmadd4<mode>_fastmath" 2774 [(set (match_operand:ANYF 0 "register_operand" "=f") 2775 (minus:ANYF 2776 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) 2777 (match_operand:ANYF 2 "register_operand" "f")) 2778 (match_operand:ANYF 3 "register_operand" "f")))] 2779 "ISA_HAS_UNFUSED_MADD4 2780 && !HONOR_SIGNED_ZEROS (<MODE>mode)" 2781 "nmadd.<fmt>\t%0,%3,%1,%2" 2782 [(set_attr "type" "fmadd") 2783 (set_attr "mode" "<UNITMODE>")]) 2784 2785;; This instruction recognizes (op1 - (op2 * op3) and generates an 2786;; nmsub which is really -((op2 * op3) - op1). They are equivalent 2787;; except for the sign bit when the result is zero or NaN. 2788 2789(define_insn "*nmsub4<mode>_fastmath" 2790 [(set (match_operand:ANYF 0 "register_operand" "=f") 2791 (minus:ANYF 2792 (match_operand:ANYF 1 "register_operand" "f") 2793 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f") 2794 (match_operand:ANYF 3 "register_operand" "f"))))] 2795 "ISA_HAS_UNFUSED_MADD4 2796 && !HONOR_SIGNED_ZEROS (<MODE>mode)" 2797 "nmsub.<fmt>\t%0,%1,%2,%3" 2798 [(set_attr "type" "fmadd") 2799 (set_attr "mode" "<UNITMODE>")]) 2800 2801;; 2802;; .................... 2803;; 2804;; DIVISION and REMAINDER 2805;; 2806;; .................... 2807;; 2808 2809(define_expand "div<mode>3" 2810 [(set (match_operand:ANYF 0 "register_operand") 2811 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand") 2812 (match_operand:ANYF 2 "register_operand")))] 2813 "<divide_condition>" 2814{ 2815 if (const_1_operand (operands[1], <MODE>mode)) 2816 if (!(ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) 2817 && flag_unsafe_math_optimizations)) 2818 operands[1] = force_reg (<MODE>mode, operands[1]); 2819}) 2820 2821;; These patterns work around the early SB-1 rev2 core "F1" erratum: 2822;; 2823;; If an mfc1 or dmfc1 happens to access the floating point register 2824;; file at the same time a long latency operation (div, sqrt, recip, 2825;; sqrt) iterates an intermediate result back through the floating 2826;; point register file bypass, then instead returning the correct 2827;; register value the mfc1 or dmfc1 operation returns the intermediate 2828;; result of the long latency operation. 2829;; 2830;; The workaround is to insert an unconditional 'mov' from/to the 2831;; long latency op destination register. 2832 2833(define_insn "*div<mode>3" 2834 [(set (match_operand:ANYF 0 "register_operand" "=f") 2835 (div:ANYF (match_operand:ANYF 1 "register_operand" "f") 2836 (match_operand:ANYF 2 "register_operand" "f")))] 2837 "<divide_condition>" 2838{ 2839 if (TARGET_FIX_SB1) 2840 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0"; 2841 else 2842 return "div.<fmt>\t%0,%1,%2"; 2843} 2844 [(set_attr "type" "fdiv") 2845 (set_attr "mode" "<UNITMODE>") 2846 (set (attr "insn_count") 2847 (if_then_else (match_test "TARGET_FIX_SB1") 2848 (const_int 2) 2849 (const_int 1)))]) 2850 2851(define_insn "*recip<mode>3" 2852 [(set (match_operand:ANYF 0 "register_operand" "=f") 2853 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") 2854 (match_operand:ANYF 2 "register_operand" "f")))] 2855 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations" 2856{ 2857 if (TARGET_FIX_SB1) 2858 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; 2859 else 2860 return "recip.<fmt>\t%0,%2"; 2861} 2862 [(set_attr "type" "frdiv") 2863 (set_attr "mode" "<UNITMODE>") 2864 (set (attr "insn_count") 2865 (if_then_else (match_test "TARGET_FIX_SB1") 2866 (const_int 2) 2867 (const_int 1)))]) 2868 2869;; VR4120 errata MD(A1): signed division instructions do not work correctly 2870;; with negative operands. We use special libgcc functions instead. 2871(define_expand "divmod<mode>4" 2872 [(parallel 2873 [(set (match_operand:GPR 0 "register_operand") 2874 (div:GPR (match_operand:GPR 1 "register_operand") 2875 (match_operand:GPR 2 "register_operand"))) 2876 (set (match_operand:GPR 3 "register_operand") 2877 (mod:GPR (match_dup 1) 2878 (match_dup 2)))])] 2879 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120" 2880{ 2881 if (TARGET_MIPS16) 2882 { 2883 rtx lo = gen_rtx_REG (<MODE>mode, LO_REGNUM); 2884 emit_insn (gen_divmod<mode>4_mips16 (operands[0], operands[1], 2885 operands[2], operands[3], lo)); 2886 DONE; 2887 } 2888}) 2889 2890(define_insn_and_split "*divmod<mode>4" 2891 [(set (match_operand:GPR 0 "register_operand" "=l") 2892 (div:GPR (match_operand:GPR 1 "register_operand" "d") 2893 (match_operand:GPR 2 "register_operand" "d"))) 2894 (set (match_operand:GPR 3 "register_operand" "=d") 2895 (mod:GPR (match_dup 1) 2896 (match_dup 2)))] 2897 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120 && !TARGET_MIPS16" 2898 "#" 2899 "&& reload_completed" 2900 [(const_int 0)] 2901{ 2902 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2])); 2903 DONE; 2904} 2905 [(set_attr "type" "idiv") 2906 (set_attr "mode" "<MODE>") 2907 (set_attr "insn_count" "2")]) 2908 2909;; Expand generates divmod instructions for individual division and modulus 2910;; operations. We then rely on CSE to reuse earlier divmods where possible. 2911;; This means that, when generating MIPS16 code, it is better not to expose 2912;; the fixed LO register until after CSE has finished. However, it's still 2913;; better to split before register allocation, so that we don't allocate 2914;; one of the scarce MIPS16 registers to an unused result. 2915(define_insn_and_split "divmod<mode>4_mips16" 2916 [(set (match_operand:GPR 0 "register_operand" "=d") 2917 (div:GPR (match_operand:GPR 1 "register_operand" "d") 2918 (match_operand:GPR 2 "register_operand" "d"))) 2919 (set (match_operand:GPR 3 "register_operand" "=d") 2920 (mod:GPR (match_dup 1) 2921 (match_dup 2))) 2922 (clobber (match_operand:GPR 4 "lo_operand" "=l"))] 2923 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120 && TARGET_MIPS16" 2924 "#" 2925 "&& cse_not_expected" 2926 [(const_int 0)] 2927{ 2928 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2])); 2929 emit_move_insn (operands[0], operands[4]); 2930 DONE; 2931} 2932 [(set_attr "type" "idiv") 2933 (set_attr "mode" "<MODE>") 2934 (set_attr "insn_count" "3")]) 2935 2936(define_expand "udivmod<mode>4" 2937 [(parallel 2938 [(set (match_operand:GPR 0 "register_operand") 2939 (udiv:GPR (match_operand:GPR 1 "register_operand") 2940 (match_operand:GPR 2 "register_operand"))) 2941 (set (match_operand:GPR 3 "register_operand") 2942 (umod:GPR (match_dup 1) 2943 (match_dup 2)))])] 2944 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120" 2945{ 2946 if (TARGET_MIPS16) 2947 { 2948 rtx lo = gen_rtx_REG (<MODE>mode, LO_REGNUM); 2949 emit_insn (gen_udivmod<mode>4_mips16 (operands[0], operands[1], 2950 operands[2], operands[3], lo)); 2951 DONE; 2952 } 2953}) 2954 2955(define_insn_and_split "*udivmod<mode>4" 2956 [(set (match_operand:GPR 0 "register_operand" "=l") 2957 (udiv:GPR (match_operand:GPR 1 "register_operand" "d") 2958 (match_operand:GPR 2 "register_operand" "d"))) 2959 (set (match_operand:GPR 3 "register_operand" "=d") 2960 (umod:GPR (match_dup 1) 2961 (match_dup 2)))] 2962 "ISA_HAS_<D>DIV && !TARGET_MIPS16" 2963 "#" 2964 "reload_completed" 2965 [(const_int 0)] 2966{ 2967 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2])); 2968 DONE; 2969} 2970 [(set_attr "type" "idiv") 2971 (set_attr "mode" "<MODE>") 2972 (set_attr "insn_count" "2")]) 2973 2974;; See the comment above "divmod<mode>4_mips16" for the split timing. 2975(define_insn_and_split "udivmod<mode>4_mips16" 2976 [(set (match_operand:GPR 0 "register_operand" "=d") 2977 (udiv:GPR (match_operand:GPR 1 "register_operand" "d") 2978 (match_operand:GPR 2 "register_operand" "d"))) 2979 (set (match_operand:GPR 3 "register_operand" "=d") 2980 (umod:GPR (match_dup 1) 2981 (match_dup 2))) 2982 (clobber (match_operand:GPR 4 "lo_operand" "=l"))] 2983 "ISA_HAS_<D>DIV && TARGET_MIPS16" 2984 "#" 2985 "cse_not_expected" 2986 [(const_int 0)] 2987{ 2988 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2])); 2989 emit_move_insn (operands[0], operands[4]); 2990 DONE; 2991} 2992 [(set_attr "type" "idiv") 2993 (set_attr "mode" "<MODE>") 2994 (set_attr "insn_count" "3")]) 2995 2996(define_expand "<u>divmod<mode>4_split" 2997 [(set (match_operand:GPR 0 "register_operand") 2998 (any_mod:GPR (match_operand:GPR 1 "register_operand") 2999 (match_operand:GPR 2 "register_operand")))] 3000 "" 3001{ 3002 rtx hilo; 3003 3004 if (TARGET_64BIT) 3005 { 3006 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 3007 emit_insn (gen_<u>divmod<mode>4_hilo_ti (hilo, operands[1], 3008 operands[2])); 3009 emit_insn (gen_mfhi<mode>_ti (operands[0], hilo)); 3010 } 3011 else 3012 { 3013 hilo = gen_rtx_REG (DImode, MD_REG_FIRST); 3014 emit_insn (gen_<u>divmod<mode>4_hilo_di (hilo, operands[1], 3015 operands[2])); 3016 emit_insn (gen_mfhi<mode>_di (operands[0], hilo)); 3017 } 3018 DONE; 3019}) 3020 3021(define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>" 3022 [(set (match_operand:HILO 0 "muldiv_target_operand" "=x") 3023 (unspec:HILO 3024 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d") 3025 (match_operand:GPR 2 "register_operand" "d"))] 3026 UNSPEC_SET_HILO))] 3027 "ISA_HAS_<GPR:D>DIV" 3028 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); } 3029 [(set_attr "type" "idiv") 3030 (set_attr "mode" "<GPR:MODE>")]) 3031 3032;; Integer division and modulus. 3033 3034(define_insn "<u>div<mode>3" 3035 [(set (match_operand:GPR 0 "register_operand" "=&d") 3036 (any_div:GPR (match_operand:GPR 1 "register_operand" "d") 3037 (match_operand:GPR 2 "register_operand" "d")))] 3038 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>DIV" 3039 { 3040 if (TARGET_LOONGSON_2EF) 3041 return mips_output_division ("<d>div<u>.g\t%0,%1,%2", operands); 3042 else if (TARGET_LOONGSON_EXT) 3043 return mips_output_division ("gs<d>div<u>\t%0,%1,%2", operands); 3044 else 3045 return mips_output_division ("<d>div<u>\t%0,%1,%2", operands); 3046 } 3047 [(set_attr "type" "idiv3") 3048 (set_attr "mode" "<MODE>")]) 3049 3050(define_insn "<u>mod<mode>3" 3051 [(set (match_operand:GPR 0 "register_operand" "=&d") 3052 (any_mod:GPR (match_operand:GPR 1 "register_operand" "d") 3053 (match_operand:GPR 2 "register_operand" "d")))] 3054 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>DIV" 3055 { 3056 if (TARGET_LOONGSON_2EF) 3057 return mips_output_division ("<d>mod<u>.g\t%0,%1,%2", operands); 3058 else if (TARGET_LOONGSON_EXT) 3059 return mips_output_division ("gs<d>mod<u>\t%0,%1,%2", operands); 3060 else 3061 return mips_output_division ("<d>mod<u>\t%0,%1,%2", operands); 3062 } 3063 [(set_attr "type" "idiv3") 3064 (set_attr "mode" "<MODE>")]) 3065 3066;; 3067;; .................... 3068;; 3069;; SQUARE ROOT 3070;; 3071;; .................... 3072 3073;; These patterns work around the early SB-1 rev2 core "F1" erratum (see 3074;; "*div[sd]f3" comment for details). 3075 3076(define_insn "sqrt<mode>2" 3077 [(set (match_operand:ANYF 0 "register_operand" "=f") 3078 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))] 3079 "<sqrt_condition>" 3080{ 3081 if (TARGET_FIX_SB1) 3082 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0"; 3083 else 3084 return "sqrt.<fmt>\t%0,%1"; 3085} 3086 [(set_attr "type" "fsqrt") 3087 (set_attr "mode" "<UNITMODE>") 3088 (set (attr "insn_count") 3089 (if_then_else (match_test "TARGET_FIX_SB1") 3090 (const_int 2) 3091 (const_int 1)))]) 3092 3093(define_insn "*rsqrt<mode>a" 3094 [(set (match_operand:ANYF 0 "register_operand" "=f") 3095 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") 3096 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))] 3097 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations" 3098{ 3099 if (TARGET_FIX_SB1) 3100 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; 3101 else 3102 return "rsqrt.<fmt>\t%0,%2"; 3103} 3104 [(set_attr "type" "frsqrt") 3105 (set_attr "mode" "<UNITMODE>") 3106 (set (attr "insn_count") 3107 (if_then_else (match_test "TARGET_FIX_SB1") 3108 (const_int 2) 3109 (const_int 1)))]) 3110 3111(define_insn "*rsqrt<mode>b" 3112 [(set (match_operand:ANYF 0 "register_operand" "=f") 3113 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") 3114 (match_operand:ANYF 2 "register_operand" "f"))))] 3115 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations" 3116{ 3117 if (TARGET_FIX_SB1) 3118 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; 3119 else 3120 return "rsqrt.<fmt>\t%0,%2"; 3121} 3122 [(set_attr "type" "frsqrt") 3123 (set_attr "mode" "<UNITMODE>") 3124 (set (attr "insn_count") 3125 (if_then_else (match_test "TARGET_FIX_SB1") 3126 (const_int 2) 3127 (const_int 1)))]) 3128 3129;; 3130;; .................... 3131;; 3132;; ABSOLUTE VALUE 3133;; 3134;; .................... 3135 3136;; Do not use the integer abs macro instruction, since that signals an 3137;; exception on -2147483648 (sigh). 3138 3139;; The "legacy" (as opposed to "2008") form of ABS.fmt is an arithmetic 3140;; instruction that treats all NaN inputs as invalid; it does not clear 3141;; their sign bit. We therefore can't use that form if the signs of 3142;; NaNs matter. 3143 3144(define_insn "abs<mode>2" 3145 [(set (match_operand:ANYF 0 "register_operand" "=f") 3146 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))] 3147 "mips_abs == MIPS_IEEE_754_2008 || !HONOR_NANS (<MODE>mode)" 3148 "abs.<fmt>\t%0,%1" 3149 [(set_attr "type" "fabs") 3150 (set_attr "mode" "<UNITMODE>")]) 3151 3152;; 3153;; ................... 3154;; 3155;; Count leading zeroes. 3156;; 3157;; ................... 3158;; 3159 3160(define_insn "clz<mode>2" 3161 [(set (match_operand:GPR 0 "register_operand" "=d") 3162 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))] 3163 "ISA_HAS_CLZ_CLO" 3164 "<d>clz\t%0,%1" 3165 [(set_attr "type" "clz") 3166 (set_attr "mode" "<MODE>")]) 3167 3168;; 3169;; ................... 3170;; 3171;; Count trailing zeroes. 3172;; 3173;; ................... 3174;; 3175 3176(define_insn "ctz<mode>2" 3177 [(set (match_operand:GPR 0 "register_operand" "=d") 3178 (ctz:GPR (match_operand:GPR 1 "register_operand" "d")))] 3179 "ISA_HAS_CTZ_CTO" 3180 "<d>ctz\t%0,%1" 3181 [(set_attr "type" "clz") 3182 (set_attr "mode" "<MODE>")]) 3183 3184 3185;; 3186;; ................... 3187;; 3188;; Count number of set bits. 3189;; 3190;; ................... 3191;; 3192 3193(define_insn "popcount<mode>2" 3194 [(set (match_operand:GPR 0 "register_operand" "=d") 3195 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))] 3196 "ISA_HAS_POP" 3197 "<d>pop\t%0,%1" 3198 [(set_attr "type" "pop") 3199 (set_attr "mode" "<MODE>")]) 3200 3201;; The POP instruction is special as it does not take into account the upper 3202;; 32bits and is documented that way. 3203(define_insn "*popcountdi2_trunc" 3204 [(set (match_operand:SI 0 "register_operand" "=d") 3205 (popcount:SI (truncate:SI (match_operand:DI 1 "register_operand" "d"))))] 3206 "ISA_HAS_POP && TARGET_64BIT" 3207 "pop\t%0,%1" 3208 [(set_attr "type" "pop") 3209 (set_attr "mode" "SI")]) 3210 3211;; 3212;; .................... 3213;; 3214;; NEGATION and ONE'S COMPLEMENT 3215;; 3216;; .................... 3217 3218(define_insn "negsi2" 3219 [(set (match_operand:SI 0 "register_operand" "=d") 3220 (neg:SI (match_operand:SI 1 "register_operand" "d")))] 3221 "" 3222{ 3223 if (TARGET_MIPS16) 3224 return "neg\t%0,%1"; 3225 else 3226 return "subu\t%0,%.,%1"; 3227} 3228 [(set_attr "alu_type" "sub") 3229 (set_attr "mode" "SI")]) 3230 3231(define_insn "negdi2" 3232 [(set (match_operand:DI 0 "register_operand" "=d") 3233 (neg:DI (match_operand:DI 1 "register_operand" "d")))] 3234 "TARGET_64BIT && !TARGET_MIPS16" 3235 "dsubu\t%0,%.,%1" 3236 [(set_attr "alu_type" "sub") 3237 (set_attr "mode" "DI")]) 3238 3239;; The "legacy" (as opposed to "2008") form of NEG.fmt is an arithmetic 3240;; instruction that treats all NaN inputs as invalid; it does not flip 3241;; their sign bit. We therefore can't use that form if the signs of 3242;; NaNs matter. 3243 3244(define_insn "neg<mode>2" 3245 [(set (match_operand:ANYF 0 "register_operand" "=f") 3246 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))] 3247 "mips_abs == MIPS_IEEE_754_2008 || !HONOR_NANS (<MODE>mode)" 3248 "neg.<fmt>\t%0,%1" 3249 [(set_attr "type" "fneg") 3250 (set_attr "mode" "<UNITMODE>")]) 3251 3252(define_insn "one_cmpl<mode>2" 3253 [(set (match_operand:GPR 0 "register_operand" "=!u,d") 3254 (not:GPR (match_operand:GPR 1 "register_operand" "!u,d")))] 3255 "" 3256{ 3257 if (TARGET_MIPS16) 3258 return "not\t%0,%1"; 3259 else 3260 return "nor\t%0,%.,%1"; 3261} 3262 [(set_attr "alu_type" "not") 3263 (set_attr "compression" "micromips,*") 3264 (set_attr "mode" "<MODE>")]) 3265 3266;; 3267;; .................... 3268;; 3269;; LOGICAL 3270;; 3271;; .................... 3272;; 3273 3274;; Many of these instructions use trivial define_expands, because we 3275;; want to use a different set of constraints when TARGET_MIPS16. 3276 3277(define_expand "and<mode>3" 3278 [(set (match_operand:GPR 0 "register_operand") 3279 (and:GPR (match_operand:GPR 1 "register_operand") 3280 (match_operand:GPR 2 "and_reg_operand")))]) 3281 3282;; The middle-end is not allowed to convert ANDing with 0xffff_ffff into a 3283;; zero_extendsidi2 because of TARGET_TRULY_NOOP_TRUNCATION, so handle these 3284;; here. Note that this variant does not trigger for SI mode because we 3285;; require a 64-bit HOST_WIDE_INT and 0xffff_ffff wouldn't be a canonical 3286;; sign-extended SImode value. 3287;; 3288;; These are possible combinations for operand 1 and 2. The table 3289;; includes both MIPS and MIPS16 cases. (r=register, mem=memory, 3290;; 16=MIPS16, x=match, S=split): 3291;; 3292;; \ op1 r/EXT r/!EXT mem r/16 mem/16 3293;; op2 3294;; 3295;; andi x x 3296;; 0xff x x x x 3297;; 0xffff x x x x 3298;; 0xffff_ffff x S x S x 3299;; low-bitmask x 3300;; register x x 3301;; register =op1 x 3302 3303(define_insn "*and<mode>3" 3304 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,!u,d,d,d,!u,d") 3305 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,!u,d,d,d,0,d") 3306 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Uean,K,Yx,Yw,!u,d")))] 3307 "!TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])" 3308{ 3309 int len; 3310 3311 switch (which_alternative) 3312 { 3313 case 0: 3314 operands[1] = gen_lowpart (QImode, operands[1]); 3315 return "lbu\t%0,%1"; 3316 case 1: 3317 operands[1] = gen_lowpart (HImode, operands[1]); 3318 return "lhu\t%0,%1"; 3319 case 2: 3320 operands[1] = gen_lowpart (SImode, operands[1]); 3321 return "lwu\t%0,%1"; 3322 case 3: 3323 case 4: 3324 return "andi\t%0,%1,%x2"; 3325 case 5: 3326 len = low_bitmask_len (<MODE>mode, INTVAL (operands[2])); 3327 operands[2] = GEN_INT (len); 3328 return "<d>ext\t%0,%1,0,%2"; 3329 case 6: 3330 return "#"; 3331 case 7: 3332 case 8: 3333 return "and\t%0,%1,%2"; 3334 default: 3335 gcc_unreachable (); 3336 } 3337} 3338 [(set_attr "move_type" "load,load,load,andi,andi,ext_ins,shift_shift,logical,logical") 3339 (set_attr "compression" "*,*,*,micromips,*,*,*,micromips,*") 3340 (set_attr "mode" "<MODE>")]) 3341 3342(define_insn "*and<mode>3_mips16" 3343 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d") 3344 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%W,W,W,d,0") 3345 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))] 3346 "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])" 3347{ 3348 switch (which_alternative) 3349 { 3350 case 0: 3351 operands[1] = gen_lowpart (QImode, operands[1]); 3352 return "lbu\t%0,%1"; 3353 case 1: 3354 operands[1] = gen_lowpart (HImode, operands[1]); 3355 return "lhu\t%0,%1"; 3356 case 2: 3357 operands[1] = gen_lowpart (SImode, operands[1]); 3358 return "lwu\t%0,%1"; 3359 case 3: 3360 return "#"; 3361 case 4: 3362 return "and\t%0,%2"; 3363 default: 3364 gcc_unreachable (); 3365 } 3366} 3367 [(set_attr "move_type" "load,load,load,shift_shift,logical") 3368 (set_attr "mode" "<MODE>")]) 3369 3370(define_expand "ior<mode>3" 3371 [(set (match_operand:GPR 0 "register_operand") 3372 (ior:GPR (match_operand:GPR 1 "register_operand") 3373 (match_operand:GPR 2 "uns_arith_operand")))] 3374 "" 3375{ 3376 if (TARGET_MIPS16) 3377 operands[2] = force_reg (<MODE>mode, operands[2]); 3378}) 3379 3380(define_insn "*ior<mode>3" 3381 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d") 3382 (ior:GPR (match_operand:GPR 1 "register_operand" "%0,d,d") 3383 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))] 3384 "!TARGET_MIPS16" 3385 "@ 3386 or\t%0,%1,%2 3387 or\t%0,%1,%2 3388 ori\t%0,%1,%x2" 3389 [(set_attr "alu_type" "or") 3390 (set_attr "compression" "micromips,*,*") 3391 (set_attr "mode" "<MODE>")]) 3392 3393(define_insn "*ior<mode>3_mips16" 3394 [(set (match_operand:GPR 0 "register_operand" "=d") 3395 (ior:GPR (match_operand:GPR 1 "register_operand" "%0") 3396 (match_operand:GPR 2 "register_operand" "d")))] 3397 "TARGET_MIPS16" 3398 "or\t%0,%2" 3399 [(set_attr "alu_type" "or") 3400 (set_attr "mode" "<MODE>")]) 3401 3402(define_expand "xor<mode>3" 3403 [(set (match_operand:GPR 0 "register_operand") 3404 (xor:GPR (match_operand:GPR 1 "register_operand") 3405 (match_operand:GPR 2 "uns_arith_operand")))] 3406 "" 3407 "") 3408 3409(define_insn "*xor<mode>3" 3410 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d") 3411 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d") 3412 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))] 3413 "!TARGET_MIPS16" 3414 "@ 3415 xor\t%0,%1,%2 3416 xor\t%0,%1,%2 3417 xori\t%0,%1,%x2" 3418 [(set_attr "alu_type" "xor") 3419 (set_attr "compression" "micromips,*,*") 3420 (set_attr "mode" "<MODE>")]) 3421 3422(define_insn "*xor<mode>3_mips16" 3423 [(set (match_operand:GPR 0 "register_operand" "=d,t,t,t") 3424 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d,d") 3425 (match_operand:GPR 2 "uns_arith_operand" "d,Uub8,K,d")))] 3426 "TARGET_MIPS16" 3427 "@ 3428 xor\t%0,%2 3429 cmpi\t%1,%2 3430 cmpi\t%1,%2 3431 cmp\t%1,%2" 3432 [(set_attr "alu_type" "xor") 3433 (set_attr "mode" "<MODE>") 3434 (set_attr "extended_mips16" "no,no,yes,no")]) 3435 3436(define_insn "*nor<mode>3" 3437 [(set (match_operand:GPR 0 "register_operand" "=d") 3438 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) 3439 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))] 3440 "!TARGET_MIPS16" 3441 "nor\t%0,%1,%2" 3442 [(set_attr "alu_type" "nor") 3443 (set_attr "mode" "<MODE>")]) 3444 3445;; 3446;; .................... 3447;; 3448;; TRUNCATION 3449;; 3450;; .................... 3451 3452 3453 3454(define_insn "truncdfsf2" 3455 [(set (match_operand:SF 0 "register_operand" "=f") 3456 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] 3457 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 3458 "cvt.s.d\t%0,%1" 3459 [(set_attr "type" "fcvt") 3460 (set_attr "cnv_mode" "D2S") 3461 (set_attr "mode" "SF")]) 3462 3463;; Integer truncation patterns. Truncating SImode values to smaller 3464;; modes is a no-op, as it is for most other GCC ports. Truncating 3465;; DImode values to SImode is not a no-op for TARGET_64BIT since we 3466;; need to make sure that the lower 32 bits are properly sign-extended 3467;; (see TARGET_TRULY_NOOP_TRUNCATION). Truncating DImode values into modes 3468;; smaller than SImode is equivalent to two separate truncations: 3469;; 3470;; A B 3471;; DI ---> HI == DI ---> SI ---> HI 3472;; DI ---> QI == DI ---> SI ---> QI 3473;; 3474;; Step A needs a real instruction but step B does not. 3475 3476(define_insn "truncdi<mode>2" 3477 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m") 3478 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))] 3479 "TARGET_64BIT" 3480 "@ 3481 sll\t%0,%1,0 3482 <store>\t%1,%0" 3483 [(set_attr "move_type" "sll0,store") 3484 (set_attr "mode" "SI")]) 3485 3486;; Combiner patterns to optimize shift/truncate combinations. 3487 3488(define_insn "*ashr_trunc<mode>" 3489 [(set (match_operand:SUBDI 0 "register_operand" "=d") 3490 (truncate:SUBDI 3491 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") 3492 (match_operand:DI 2 "const_arith_operand" ""))))] 3493 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)" 3494 "dsra\t%0,%1,%2" 3495 [(set_attr "type" "shift") 3496 (set_attr "mode" "<MODE>")]) 3497 3498(define_insn "*lshr32_trunc<mode>" 3499 [(set (match_operand:SUBDI 0 "register_operand" "=d") 3500 (truncate:SUBDI 3501 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") 3502 (const_int 32))))] 3503 "TARGET_64BIT && !TARGET_MIPS16" 3504 "dsra\t%0,%1,32" 3505 [(set_attr "type" "shift") 3506 (set_attr "mode" "<MODE>")]) 3507 3508;; Logical shift by more than 32 results in proper SI values so truncation is 3509;; removed by the middle end. Note that a logical shift by 32 is handled by 3510;; the previous pattern. 3511(define_insn "*<optab>_trunc<mode>_exts" 3512 [(set (match_operand:SUBDI 0 "register_operand" "=d") 3513 (truncate:SUBDI 3514 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d") 3515 (match_operand:DI 2 "const_arith_operand" ""))))] 3516 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32" 3517 "exts\t%0,%1,%2,31" 3518 [(set_attr "type" "arith") 3519 (set_attr "mode" "<MODE>")]) 3520 3521;; This could likely be generalized for any SUBDI mode, and any right 3522;; shift, but AFAICT this is used so rarely it is not worth the additional 3523;; complexity. 3524(define_insn "" 3525 [(set (match_operand:SI 0 "register_operand" "=d") 3526 (ashiftrt:SI 3527 (truncate:SI 3528 (ashift:DI (match_operand:DI 1 "register_operand" "d") 3529 (match_operand:DI 2 "const_arith_operand" ""))) 3530 (match_operand:DI 3 "const_arith_operand" "")))] 3531 "(ISA_HAS_EXTS && TARGET_64BIT 3532 && UINTVAL (operands[2]) < 32 && UINTVAL (operands[3]) < 32 3533 && UINTVAL (operands[3]) >= UINTVAL (operands[2]))" 3534 { 3535 rtx xoperands[4]; 3536 xoperands[0] = operands[0]; 3537 xoperands[1] = operands[1]; 3538 3539 /* The length of the field is the size of the outer mode less the outer 3540 shift constant. We fix the outer mode as SImode for simplicity. */ 3541 unsigned int right_shift = INTVAL (operands[3]); 3542 xoperands[3] = GEN_INT (32 - right_shift); 3543 3544 /* The field starts at the outer shift constant less the inner shift 3545 constant. */ 3546 unsigned int left_shift = INTVAL (operands[2]); 3547 xoperands[2] = GEN_INT (right_shift - left_shift); 3548 3549 /* Sanity checks. These constraints are taken from the MIPS ISA 3550 manual. */ 3551 gcc_assert (INTVAL (xoperands[2]) >= 0 && INTVAL (xoperands[2]) < 32); 3552 gcc_assert (INTVAL (xoperands[3]) > 0 && INTVAL (xoperands[3]) <= 32); 3553 gcc_assert (INTVAL (xoperands[2]) + INTVAL (xoperands[3]) > 0 3554 && INTVAL (xoperands[2]) + INTVAL (xoperands[3]) <= 32); 3555 3556 output_asm_insn ("exts\t%0,%1,%2,%m3", xoperands); 3557 return ""; 3558 } 3559 [(set_attr "type" "arith") 3560 (set_attr "mode" "SI")]) 3561 3562;; 3563;; .................... 3564;; 3565;; ZERO EXTENSION 3566;; 3567;; .................... 3568 3569;; Extension insns. 3570 3571(define_expand "zero_extendsidi2" 3572 [(set (match_operand:DI 0 "register_operand") 3573 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))] 3574 "TARGET_64BIT") 3575 3576(define_insn_and_split "*zero_extendsidi2" 3577 [(set (match_operand:DI 0 "register_operand" "=d,d") 3578 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))] 3579 "TARGET_64BIT && !ISA_HAS_EXT_INS" 3580 "@ 3581 # 3582 lwu\t%0,%1" 3583 "&& reload_completed && REG_P (operands[1])" 3584 [(set (match_dup 0) 3585 (ashift:DI (match_dup 1) (const_int 32))) 3586 (set (match_dup 0) 3587 (lshiftrt:DI (match_dup 0) (const_int 32)))] 3588 { operands[1] = gen_lowpart (DImode, operands[1]); } 3589 [(set_attr "move_type" "shift_shift,load") 3590 (set_attr "mode" "DI")]) 3591 3592(define_insn "*zero_extendsidi2_dext" 3593 [(set (match_operand:DI 0 "register_operand" "=d,d") 3594 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))] 3595 "TARGET_64BIT && ISA_HAS_EXT_INS" 3596 "@ 3597 dext\t%0,%1,0,32 3598 lwu\t%0,%1" 3599 [(set_attr "move_type" "arith,load") 3600 (set_attr "mode" "DI")]) 3601 3602;; See the comment before the *and<mode>3 pattern why this is generated by 3603;; combine. 3604 3605(define_split 3606 [(set (match_operand:DI 0 "register_operand") 3607 (and:DI (match_operand:DI 1 "register_operand") 3608 (const_int 4294967295)))] 3609 "TARGET_64BIT && !ISA_HAS_EXT_INS && reload_completed" 3610 [(set (match_dup 0) 3611 (ashift:DI (match_dup 1) (const_int 32))) 3612 (set (match_dup 0) 3613 (lshiftrt:DI (match_dup 0) (const_int 32)))]) 3614 3615(define_expand "zero_extend<SHORT:mode><GPR:mode>2" 3616 [(set (match_operand:GPR 0 "register_operand") 3617 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))] 3618 "" 3619{ 3620 if (TARGET_MIPS16 && !GENERATE_MIPS16E 3621 && !memory_operand (operands[1], <SHORT:MODE>mode)) 3622 { 3623 emit_insn (gen_and<GPR:mode>3 (operands[0], 3624 gen_lowpart (<GPR:MODE>mode, operands[1]), 3625 force_reg (<GPR:MODE>mode, 3626 GEN_INT (<SHORT:mask>)))); 3627 DONE; 3628 } 3629}) 3630 3631(define_insn "*zero_extend<SHORT:mode><GPR:mode>2" 3632 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d") 3633 (zero_extend:GPR 3634 (match_operand:SHORT 1 "nonimmediate_operand" "!u,d,m")))] 3635 "!TARGET_MIPS16" 3636 "@ 3637 andi\t%0,%1,<SHORT:mask> 3638 andi\t%0,%1,<SHORT:mask> 3639 l<SHORT:size>u\t%0,%1" 3640 [(set_attr "move_type" "andi,andi,load") 3641 (set_attr "compression" "micromips,*,*") 3642 (set_attr "mode" "<GPR:MODE>")]) 3643 3644(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e" 3645 [(set (match_operand:GPR 0 "register_operand" "=d") 3646 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))] 3647 "GENERATE_MIPS16E" 3648 "ze<SHORT:size>\t%0" 3649 ;; This instruction is effectively a special encoding of ANDI. 3650 [(set_attr "move_type" "andi") 3651 (set_attr "mode" "<GPR:MODE>")]) 3652 3653(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16" 3654 [(set (match_operand:GPR 0 "register_operand" "=d") 3655 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))] 3656 "TARGET_MIPS16" 3657 "l<SHORT:size>u\t%0,%1" 3658 [(set_attr "move_type" "load") 3659 (set_attr "mode" "<GPR:MODE>")]) 3660 3661(define_expand "zero_extendqihi2" 3662 [(set (match_operand:HI 0 "register_operand") 3663 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))] 3664 "" 3665{ 3666 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode)) 3667 { 3668 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]), 3669 operands[1])); 3670 DONE; 3671 } 3672}) 3673 3674(define_insn "*zero_extendqihi2" 3675 [(set (match_operand:HI 0 "register_operand" "=d,d") 3676 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 3677 "!TARGET_MIPS16" 3678 "@ 3679 andi\t%0,%1,0x00ff 3680 lbu\t%0,%1" 3681 [(set_attr "move_type" "andi,load") 3682 (set_attr "mode" "HI")]) 3683 3684(define_insn "*zero_extendqihi2_mips16" 3685 [(set (match_operand:HI 0 "register_operand" "=d") 3686 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] 3687 "TARGET_MIPS16" 3688 "lbu\t%0,%1" 3689 [(set_attr "move_type" "load") 3690 (set_attr "mode" "HI")]) 3691 3692;; Combiner patterns to optimize truncate/zero_extend combinations. 3693 3694(define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>" 3695 [(set (match_operand:GPR 0 "register_operand" "=d") 3696 (zero_extend:GPR 3697 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))] 3698 "TARGET_64BIT && !TARGET_MIPS16" 3699{ 3700 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode)); 3701 return "andi\t%0,%1,%x2"; 3702} 3703 [(set_attr "alu_type" "and") 3704 (set_attr "mode" "<GPR:MODE>")]) 3705 3706(define_insn "*zero_extendhi_truncqi" 3707 [(set (match_operand:HI 0 "register_operand" "=d") 3708 (zero_extend:HI 3709 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] 3710 "TARGET_64BIT && !TARGET_MIPS16" 3711 "andi\t%0,%1,0xff" 3712 [(set_attr "alu_type" "and") 3713 (set_attr "mode" "HI")]) 3714 3715;; 3716;; .................... 3717;; 3718;; SIGN EXTENSION 3719;; 3720;; .................... 3721 3722;; Extension insns. 3723;; Those for integer source operand are ordered widest source type first. 3724 3725;; When TARGET_64BIT, all SImode integer and accumulator registers 3726;; should already be in sign-extended form (see TARGET_TRULY_NOOP_TRUNCATION 3727;; and truncdisi2). We can therefore get rid of register->register 3728;; instructions if we constrain the source to be in the same register as 3729;; the destination. 3730;; 3731;; Only the pre-reload scheduler sees the type of the register alternatives; 3732;; we split them into nothing before the post-reload scheduler runs. 3733;; These alternatives therefore have type "move" in order to reflect 3734;; what happens if the two pre-reload operands cannot be tied, and are 3735;; instead allocated two separate GPRs. We don't distinguish between 3736;; the GPR and LO cases because we don't usually know during pre-reload 3737;; scheduling whether an operand will be LO or not. 3738(define_insn_and_split "extendsidi2" 3739 [(set (match_operand:DI 0 "register_operand" "=d,l,d") 3740 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,0,m")))] 3741 "TARGET_64BIT" 3742 "@ 3743 # 3744 # 3745 lw\t%0,%1" 3746 "&& reload_completed && register_operand (operands[1], VOIDmode)" 3747 [(const_int 0)] 3748{ 3749 emit_note (NOTE_INSN_DELETED); 3750 DONE; 3751} 3752 [(set_attr "move_type" "move,move,load") 3753 (set_attr "mode" "DI")]) 3754 3755(define_expand "extend<SHORT:mode><GPR:mode>2" 3756 [(set (match_operand:GPR 0 "register_operand") 3757 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))] 3758 "") 3759 3760(define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e" 3761 [(set (match_operand:GPR 0 "register_operand" "=d,d") 3762 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))] 3763 "GENERATE_MIPS16E" 3764 "@ 3765 se<SHORT:size>\t%0 3766 l<SHORT:size>\t%0,%1" 3767 [(set_attr "move_type" "signext,load") 3768 (set_attr "mode" "<GPR:MODE>")]) 3769 3770(define_insn_and_split "*extend<SHORT:mode><GPR:mode>2" 3771 [(set (match_operand:GPR 0 "register_operand" "=d,d") 3772 (sign_extend:GPR 3773 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))] 3774 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E" 3775 "@ 3776 # 3777 l<SHORT:size>\t%0,%1" 3778 "&& reload_completed && REG_P (operands[1])" 3779 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2))) 3780 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))] 3781{ 3782 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]); 3783 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode) 3784 - GET_MODE_BITSIZE (<SHORT:MODE>mode)); 3785} 3786 [(set_attr "move_type" "shift_shift,load") 3787 (set_attr "mode" "<GPR:MODE>")]) 3788 3789(define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>" 3790 [(set (match_operand:GPR 0 "register_operand" "=d,d") 3791 (sign_extend:GPR 3792 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))] 3793 "ISA_HAS_SEB_SEH" 3794 "@ 3795 se<SHORT:size>\t%0,%1 3796 l<SHORT:size>\t%0,%1" 3797 [(set_attr "move_type" "signext,load") 3798 (set_attr "mode" "<GPR:MODE>")]) 3799 3800(define_expand "extendqihi2" 3801 [(set (match_operand:HI 0 "register_operand") 3802 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))] 3803 "") 3804 3805(define_insn "*extendqihi2_mips16e" 3806 [(set (match_operand:HI 0 "register_operand" "=d,d") 3807 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))] 3808 "GENERATE_MIPS16E" 3809 "@ 3810 seb\t%0 3811 lb\t%0,%1" 3812 [(set_attr "move_type" "signext,load") 3813 (set_attr "mode" "SI")]) 3814 3815(define_insn_and_split "*extendqihi2" 3816 [(set (match_operand:HI 0 "register_operand" "=d,d") 3817 (sign_extend:HI 3818 (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 3819 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E" 3820 "@ 3821 # 3822 lb\t%0,%1" 3823 "&& reload_completed && REG_P (operands[1])" 3824 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2))) 3825 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))] 3826{ 3827 operands[0] = gen_lowpart (SImode, operands[0]); 3828 operands[1] = gen_lowpart (SImode, operands[1]); 3829 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode) 3830 - GET_MODE_BITSIZE (QImode)); 3831} 3832 [(set_attr "move_type" "shift_shift,load") 3833 (set_attr "mode" "SI")]) 3834 3835(define_insn "*extendqihi2_seb" 3836 [(set (match_operand:HI 0 "register_operand" "=d,d") 3837 (sign_extend:HI 3838 (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 3839 "ISA_HAS_SEB_SEH" 3840 "@ 3841 seb\t%0,%1 3842 lb\t%0,%1" 3843 [(set_attr "move_type" "signext,load") 3844 (set_attr "mode" "SI")]) 3845 3846;; Combiner patterns for truncate/sign_extend combinations. The SI versions 3847;; use the shift/truncate patterns. 3848 3849(define_insn_and_split "*extenddi_truncate<mode>" 3850 [(set (match_operand:DI 0 "register_operand" "=d") 3851 (sign_extend:DI 3852 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))] 3853 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS" 3854 "#" 3855 "&& reload_completed" 3856 [(set (match_dup 2) 3857 (ashift:DI (match_dup 1) 3858 (match_dup 3))) 3859 (set (match_dup 0) 3860 (ashiftrt:DI (match_dup 2) 3861 (match_dup 3)))] 3862{ 3863 operands[2] = gen_lowpart (DImode, operands[0]); 3864 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode)); 3865} 3866 [(set_attr "move_type" "shift_shift") 3867 (set_attr "mode" "DI")]) 3868 3869(define_insn_and_split "*extendsi_truncate<mode>" 3870 [(set (match_operand:SI 0 "register_operand" "=d") 3871 (sign_extend:SI 3872 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))] 3873 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS" 3874 "#" 3875 "&& reload_completed" 3876 [(set (match_dup 2) 3877 (ashift:DI (match_dup 1) 3878 (match_dup 3))) 3879 (set (match_dup 0) 3880 (truncate:SI (ashiftrt:DI (match_dup 2) 3881 (match_dup 3))))] 3882{ 3883 operands[2] = gen_lowpart (DImode, operands[0]); 3884 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode)); 3885} 3886 [(set_attr "move_type" "shift_shift") 3887 (set_attr "mode" "SI")]) 3888 3889(define_insn_and_split "*extendhi_truncateqi" 3890 [(set (match_operand:HI 0 "register_operand" "=d") 3891 (sign_extend:HI 3892 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] 3893 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS" 3894 "#" 3895 "&& reload_completed" 3896 [(set (match_dup 2) 3897 (ashift:DI (match_dup 1) 3898 (const_int 56))) 3899 (set (match_dup 0) 3900 (truncate:HI (ashiftrt:DI (match_dup 2) 3901 (const_int 56))))] 3902{ 3903 operands[2] = gen_lowpart (DImode, operands[0]); 3904} 3905 [(set_attr "move_type" "shift_shift") 3906 (set_attr "mode" "SI")]) 3907 3908(define_insn "*extend<GPR:mode>_truncate<SHORT:mode>_exts" 3909 [(set (match_operand:GPR 0 "register_operand" "=d") 3910 (sign_extend:GPR 3911 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))] 3912 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS" 3913{ 3914 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode)); 3915 return "exts\t%0,%1,0,%m2"; 3916} 3917 [(set_attr "type" "arith") 3918 (set_attr "mode" "<GPR:MODE>")]) 3919 3920(define_insn "*extendhi_truncateqi_exts" 3921 [(set (match_operand:HI 0 "register_operand" "=d") 3922 (sign_extend:HI 3923 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] 3924 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS" 3925 "exts\t%0,%1,0,7" 3926 [(set_attr "type" "arith") 3927 (set_attr "mode" "SI")]) 3928 3929(define_insn "extendsfdf2" 3930 [(set (match_operand:DF 0 "register_operand" "=f") 3931 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] 3932 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 3933 "cvt.d.s\t%0,%1" 3934 [(set_attr "type" "fcvt") 3935 (set_attr "cnv_mode" "S2D") 3936 (set_attr "mode" "DF")]) 3937 3938;; 3939;; .................... 3940;; 3941;; CONVERSIONS 3942;; 3943;; .................... 3944 3945(define_expand "fix_truncdfsi2" 3946 [(set (match_operand:SI 0 "register_operand") 3947 (fix:SI (match_operand:DF 1 "register_operand")))] 3948 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 3949{ 3950 if (!ISA_HAS_TRUNC_W) 3951 { 3952 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1])); 3953 DONE; 3954 } 3955}) 3956 3957(define_insn "fix_truncdfsi2_insn" 3958 [(set (match_operand:SI 0 "register_operand" "=f") 3959 (fix:SI (match_operand:DF 1 "register_operand" "f")))] 3960 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W" 3961 "trunc.w.d %0,%1" 3962 [(set_attr "type" "fcvt") 3963 (set_attr "mode" "DF") 3964 (set_attr "cnv_mode" "D2I")]) 3965 3966(define_insn "fix_truncdfsi2_macro" 3967 [(set (match_operand:SI 0 "register_operand" "=f") 3968 (fix:SI (match_operand:DF 1 "register_operand" "f"))) 3969 (clobber (match_scratch:DF 2 "=d"))] 3970 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W" 3971{ 3972 if (mips_nomacro.nesting_level > 0) 3973 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro"; 3974 else 3975 return "trunc.w.d %0,%1,%2"; 3976} 3977 [(set_attr "type" "fcvt") 3978 (set_attr "mode" "DF") 3979 (set_attr "cnv_mode" "D2I") 3980 (set_attr "insn_count" "9")]) 3981 3982(define_expand "fix_truncsfsi2" 3983 [(set (match_operand:SI 0 "register_operand") 3984 (fix:SI (match_operand:SF 1 "register_operand")))] 3985 "TARGET_HARD_FLOAT" 3986{ 3987 if (!ISA_HAS_TRUNC_W) 3988 { 3989 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1])); 3990 DONE; 3991 } 3992}) 3993 3994(define_insn "fix_truncsfsi2_insn" 3995 [(set (match_operand:SI 0 "register_operand" "=f") 3996 (fix:SI (match_operand:SF 1 "register_operand" "f")))] 3997 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W" 3998 "trunc.w.s %0,%1" 3999 [(set_attr "type" "fcvt") 4000 (set_attr "mode" "SF") 4001 (set_attr "cnv_mode" "S2I")]) 4002 4003(define_insn "fix_truncsfsi2_macro" 4004 [(set (match_operand:SI 0 "register_operand" "=f") 4005 (fix:SI (match_operand:SF 1 "register_operand" "f"))) 4006 (clobber (match_scratch:SF 2 "=d"))] 4007 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W" 4008{ 4009 if (mips_nomacro.nesting_level > 0) 4010 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro"; 4011 else 4012 return "trunc.w.s %0,%1,%2"; 4013} 4014 [(set_attr "type" "fcvt") 4015 (set_attr "mode" "SF") 4016 (set_attr "cnv_mode" "S2I") 4017 (set_attr "insn_count" "9")]) 4018 4019 4020(define_insn "fix_truncdfdi2" 4021 [(set (match_operand:DI 0 "register_operand" "=f") 4022 (fix:DI (match_operand:DF 1 "register_operand" "f")))] 4023 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 4024 "trunc.l.d %0,%1" 4025 [(set_attr "type" "fcvt") 4026 (set_attr "mode" "DF") 4027 (set_attr "cnv_mode" "D2I")]) 4028 4029 4030(define_insn "fix_truncsfdi2" 4031 [(set (match_operand:DI 0 "register_operand" "=f") 4032 (fix:DI (match_operand:SF 1 "register_operand" "f")))] 4033 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 4034 "trunc.l.s %0,%1" 4035 [(set_attr "type" "fcvt") 4036 (set_attr "mode" "SF") 4037 (set_attr "cnv_mode" "S2I")]) 4038 4039 4040(define_insn "floatsidf2" 4041 [(set (match_operand:DF 0 "register_operand" "=f") 4042 (float:DF (match_operand:SI 1 "register_operand" "f")))] 4043 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 4044 "cvt.d.w\t%0,%1" 4045 [(set_attr "type" "fcvt") 4046 (set_attr "mode" "DF") 4047 (set_attr "cnv_mode" "I2D")]) 4048 4049 4050(define_insn "floatdidf2" 4051 [(set (match_operand:DF 0 "register_operand" "=f") 4052 (float:DF (match_operand:DI 1 "register_operand" "f")))] 4053 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 4054 "cvt.d.l\t%0,%1" 4055 [(set_attr "type" "fcvt") 4056 (set_attr "mode" "DF") 4057 (set_attr "cnv_mode" "I2D")]) 4058 4059 4060(define_insn "floatsisf2" 4061 [(set (match_operand:SF 0 "register_operand" "=f") 4062 (float:SF (match_operand:SI 1 "register_operand" "f")))] 4063 "TARGET_HARD_FLOAT" 4064 "cvt.s.w\t%0,%1" 4065 [(set_attr "type" "fcvt") 4066 (set_attr "mode" "SF") 4067 (set_attr "cnv_mode" "I2S")]) 4068 4069 4070(define_insn "floatdisf2" 4071 [(set (match_operand:SF 0 "register_operand" "=f") 4072 (float:SF (match_operand:DI 1 "register_operand" "f")))] 4073 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 4074 "cvt.s.l\t%0,%1" 4075 [(set_attr "type" "fcvt") 4076 (set_attr "mode" "SF") 4077 (set_attr "cnv_mode" "I2S")]) 4078 4079 4080(define_expand "fixuns_truncdfsi2" 4081 [(set (match_operand:SI 0 "register_operand") 4082 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))] 4083 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 4084{ 4085 rtx reg1 = gen_reg_rtx (DFmode); 4086 rtx reg2 = gen_reg_rtx (DFmode); 4087 rtx reg3 = gen_reg_rtx (SImode); 4088 rtx_code_label *label1 = gen_label_rtx (); 4089 rtx_code_label *label2 = gen_label_rtx (); 4090 rtx test; 4091 REAL_VALUE_TYPE offset; 4092 4093 real_2expN (&offset, 31, DFmode); 4094 4095 if (reg1) /* Turn off complaints about unreached code. */ 4096 { 4097 mips_emit_move (reg1, const_double_from_real_value (offset, DFmode)); 4098 do_pending_stack_adjust (); 4099 4100 test = gen_rtx_GE (VOIDmode, operands[1], reg1); 4101 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1)); 4102 4103 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1])); 4104 emit_jump_insn (gen_rtx_SET (pc_rtx, 4105 gen_rtx_LABEL_REF (VOIDmode, label2))); 4106 emit_barrier (); 4107 4108 emit_label (label1); 4109 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1)); 4110 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode 4111 (BITMASK_HIGH, SImode))); 4112 4113 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2)); 4114 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3)); 4115 4116 emit_label (label2); 4117 4118 /* Allow REG_NOTES to be set on last insn (labels don't have enough 4119 fields, and can't be used for REG_NOTES anyway). */ 4120 emit_use (stack_pointer_rtx); 4121 DONE; 4122 } 4123}) 4124 4125 4126(define_expand "fixuns_truncdfdi2" 4127 [(set (match_operand:DI 0 "register_operand") 4128 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))] 4129 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" 4130{ 4131 rtx reg1 = gen_reg_rtx (DFmode); 4132 rtx reg2 = gen_reg_rtx (DFmode); 4133 rtx reg3 = gen_reg_rtx (DImode); 4134 rtx_code_label *label1 = gen_label_rtx (); 4135 rtx_code_label *label2 = gen_label_rtx (); 4136 rtx test; 4137 REAL_VALUE_TYPE offset; 4138 4139 real_2expN (&offset, 63, DFmode); 4140 4141 mips_emit_move (reg1, const_double_from_real_value (offset, DFmode)); 4142 do_pending_stack_adjust (); 4143 4144 test = gen_rtx_GE (VOIDmode, operands[1], reg1); 4145 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1)); 4146 4147 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1])); 4148 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2))); 4149 emit_barrier (); 4150 4151 emit_label (label1); 4152 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1)); 4153 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH)); 4154 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32))); 4155 4156 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2)); 4157 emit_insn (gen_iordi3 (operands[0], operands[0], reg3)); 4158 4159 emit_label (label2); 4160 4161 /* Allow REG_NOTES to be set on last insn (labels don't have enough 4162 fields, and can't be used for REG_NOTES anyway). */ 4163 emit_use (stack_pointer_rtx); 4164 DONE; 4165}) 4166 4167 4168(define_expand "fixuns_truncsfsi2" 4169 [(set (match_operand:SI 0 "register_operand") 4170 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))] 4171 "TARGET_HARD_FLOAT" 4172{ 4173 rtx reg1 = gen_reg_rtx (SFmode); 4174 rtx reg2 = gen_reg_rtx (SFmode); 4175 rtx reg3 = gen_reg_rtx (SImode); 4176 rtx_code_label *label1 = gen_label_rtx (); 4177 rtx_code_label *label2 = gen_label_rtx (); 4178 rtx test; 4179 REAL_VALUE_TYPE offset; 4180 4181 real_2expN (&offset, 31, SFmode); 4182 4183 mips_emit_move (reg1, const_double_from_real_value (offset, SFmode)); 4184 do_pending_stack_adjust (); 4185 4186 test = gen_rtx_GE (VOIDmode, operands[1], reg1); 4187 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1)); 4188 4189 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1])); 4190 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2))); 4191 emit_barrier (); 4192 4193 emit_label (label1); 4194 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1)); 4195 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode 4196 (BITMASK_HIGH, SImode))); 4197 4198 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2)); 4199 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3)); 4200 4201 emit_label (label2); 4202 4203 /* Allow REG_NOTES to be set on last insn (labels don't have enough 4204 fields, and can't be used for REG_NOTES anyway). */ 4205 emit_use (stack_pointer_rtx); 4206 DONE; 4207}) 4208 4209 4210(define_expand "fixuns_truncsfdi2" 4211 [(set (match_operand:DI 0 "register_operand") 4212 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))] 4213 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" 4214{ 4215 rtx reg1 = gen_reg_rtx (SFmode); 4216 rtx reg2 = gen_reg_rtx (SFmode); 4217 rtx reg3 = gen_reg_rtx (DImode); 4218 rtx_code_label *label1 = gen_label_rtx (); 4219 rtx_code_label *label2 = gen_label_rtx (); 4220 rtx test; 4221 REAL_VALUE_TYPE offset; 4222 4223 real_2expN (&offset, 63, SFmode); 4224 4225 mips_emit_move (reg1, const_double_from_real_value (offset, SFmode)); 4226 do_pending_stack_adjust (); 4227 4228 test = gen_rtx_GE (VOIDmode, operands[1], reg1); 4229 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1)); 4230 4231 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1])); 4232 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2))); 4233 emit_barrier (); 4234 4235 emit_label (label1); 4236 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1)); 4237 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH)); 4238 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32))); 4239 4240 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2)); 4241 emit_insn (gen_iordi3 (operands[0], operands[0], reg3)); 4242 4243 emit_label (label2); 4244 4245 /* Allow REG_NOTES to be set on last insn (labels don't have enough 4246 fields, and can't be used for REG_NOTES anyway). */ 4247 emit_use (stack_pointer_rtx); 4248 DONE; 4249}) 4250 4251;; 4252;; .................... 4253;; 4254;; DATA MOVEMENT 4255;; 4256;; .................... 4257 4258;; Bit field extract patterns which use lwl/lwr or ldl/ldr. 4259 4260(define_expand "extvmisalign<mode>" 4261 [(set (match_operand:GPR 0 "register_operand") 4262 (sign_extract:GPR (match_operand:BLK 1 "memory_operand") 4263 (match_operand 2 "const_int_operand") 4264 (match_operand 3 "const_int_operand")))] 4265 "ISA_HAS_LWL_LWR" 4266{ 4267 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1], 4268 INTVAL (operands[2]), 4269 INTVAL (operands[3]), 4270 /*unsigned=*/ false)) 4271 DONE; 4272 else 4273 FAIL; 4274}) 4275 4276(define_expand "extv<mode>" 4277 [(set (match_operand:GPR 0 "register_operand") 4278 (sign_extract:GPR (match_operand:GPR 1 "register_operand") 4279 (match_operand 2 "const_int_operand") 4280 (match_operand 3 "const_int_operand")))] 4281 "ISA_HAS_EXTS" 4282{ 4283 if (UINTVAL (operands[2]) > 32) 4284 FAIL; 4285}) 4286 4287(define_insn "*extv<mode>" 4288 [(set (match_operand:GPR 0 "register_operand" "=d") 4289 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d") 4290 (match_operand 2 "const_int_operand" "") 4291 (match_operand 3 "const_int_operand" "")))] 4292 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32" 4293 "exts\t%0,%1,%3,%m2" 4294 [(set_attr "type" "arith") 4295 (set_attr "mode" "<MODE>")]) 4296 4297(define_expand "extzvmisalign<mode>" 4298 [(set (match_operand:GPR 0 "register_operand") 4299 (zero_extract:GPR (match_operand:BLK 1 "memory_operand") 4300 (match_operand 2 "const_int_operand") 4301 (match_operand 3 "const_int_operand")))] 4302 "ISA_HAS_LWL_LWR" 4303{ 4304 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1], 4305 INTVAL (operands[2]), 4306 INTVAL (operands[3]), 4307 /*unsigned=*/ true)) 4308 DONE; 4309 else 4310 FAIL; 4311}) 4312 4313(define_expand "extzv<mode>" 4314 [(set (match_operand:GPR 0 "register_operand") 4315 (zero_extract:GPR (match_operand:GPR 1 "register_operand") 4316 (match_operand 2 "const_int_operand") 4317 (match_operand 3 "const_int_operand")))] 4318 "" 4319{ 4320 if (!mips_use_ins_ext_p (operands[1], INTVAL (operands[2]), 4321 INTVAL (operands[3]))) 4322 FAIL; 4323}) 4324 4325(define_insn "*extzv<mode>" 4326 [(set (match_operand:GPR 0 "register_operand" "=d") 4327 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d") 4328 (match_operand 2 "const_int_operand" "") 4329 (match_operand 3 "const_int_operand" "")))] 4330 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]), 4331 INTVAL (operands[3]))" 4332 "<d>ext\t%0,%1,%3,%2" 4333 [(set_attr "type" "arith") 4334 (set_attr "mode" "<MODE>")]) 4335 4336(define_insn "*extzv_truncsi_exts" 4337 [(set (match_operand:SI 0 "register_operand" "=d") 4338 (truncate:SI 4339 (zero_extract:DI (match_operand:DI 1 "register_operand" "d") 4340 (match_operand 2 "const_int_operand" "") 4341 (match_operand 3 "const_int_operand" ""))))] 4342 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)" 4343 "exts\t%0,%1,%3,31" 4344 [(set_attr "type" "arith") 4345 (set_attr "mode" "SI")]) 4346 4347 4348(define_expand "insvmisalign<mode>" 4349 [(set (zero_extract:GPR (match_operand:BLK 0 "memory_operand") 4350 (match_operand 1 "const_int_operand") 4351 (match_operand 2 "const_int_operand")) 4352 (match_operand:GPR 3 "reg_or_0_operand"))] 4353 "ISA_HAS_LWL_LWR" 4354{ 4355 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3], 4356 INTVAL (operands[1]), 4357 INTVAL (operands[2]))) 4358 DONE; 4359 else 4360 FAIL; 4361}) 4362 4363(define_expand "insv<mode>" 4364 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand") 4365 (match_operand 1 "const_int_operand") 4366 (match_operand 2 "const_int_operand")) 4367 (match_operand:GPR 3 "reg_or_0_operand"))] 4368 "" 4369{ 4370 if (!mips_use_ins_ext_p (operands[0], INTVAL (operands[1]), 4371 INTVAL (operands[2]))) 4372 FAIL; 4373}) 4374 4375(define_insn "*insv<mode>" 4376 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d") 4377 (match_operand:SI 1 "const_int_operand" "") 4378 (match_operand:SI 2 "const_int_operand" "")) 4379 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))] 4380 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]), 4381 INTVAL (operands[2]))" 4382 "<d>ins\t%0,%z3,%2,%1" 4383 [(set_attr "type" "arith") 4384 (set_attr "mode" "<MODE>")]) 4385 4386;; Combiner pattern for cins (clear and insert bit field). We can 4387;; implement mask-and-shift-left operation with this. Note that if 4388;; the upper bit of the mask is set in an SImode operation, the mask 4389;; itself will be sign-extended. mask_low_and_shift_len will 4390;; therefore be greater than our threshold of 32. 4391 4392(define_insn "*cins<mode>" 4393 [(set (match_operand:GPR 0 "register_operand" "=d") 4394 (and:GPR 4395 (ashift:GPR (match_operand:GPR 1 "register_operand" "d") 4396 (match_operand:GPR 2 "const_int_operand" "")) 4397 (match_operand:GPR 3 "const_int_operand" "")))] 4398 "ISA_HAS_CINS 4399 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)" 4400{ 4401 operands[3] = 4402 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2])); 4403 return "cins\t%0,%1,%2,%m3"; 4404} 4405 [(set_attr "type" "shift") 4406 (set_attr "mode" "<MODE>")]) 4407 4408;; Unaligned word moves generated by the bit field patterns. 4409;; 4410;; As far as the rtl is concerned, both the left-part and right-part 4411;; instructions can access the whole field. However, the real operand 4412;; refers to just the first or the last byte (depending on endianness). 4413;; We therefore use two memory operands to each instruction, one to 4414;; describe the rtl effect and one to use in the assembly output. 4415;; 4416;; Operands 0 and 1 are the rtl-level target and source respectively. 4417;; This allows us to use the standard length calculations for the "load" 4418;; and "store" type attributes. 4419 4420(define_insn "mov_<load>l" 4421 [(set (match_operand:GPR 0 "register_operand" "=d") 4422 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m") 4423 (match_operand:QI 2 "memory_operand" "ZC")] 4424 UNSPEC_LOAD_LEFT))] 4425 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])" 4426 "<load>l\t%0,%2" 4427 [(set_attr "move_type" "load") 4428 (set_attr "mode" "<MODE>")]) 4429 4430(define_insn "mov_<load>r" 4431 [(set (match_operand:GPR 0 "register_operand" "=d") 4432 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m") 4433 (match_operand:QI 2 "memory_operand" "ZC") 4434 (match_operand:GPR 3 "register_operand" "0")] 4435 UNSPEC_LOAD_RIGHT))] 4436 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])" 4437 "<load>r\t%0,%2" 4438 [(set_attr "move_type" "load") 4439 (set_attr "mode" "<MODE>")]) 4440 4441(define_insn "mov_<store>l" 4442 [(set (match_operand:BLK 0 "memory_operand" "=m") 4443 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 4444 (match_operand:QI 2 "memory_operand" "ZC")] 4445 UNSPEC_STORE_LEFT))] 4446 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])" 4447 "<store>l\t%z1,%2" 4448 [(set_attr "move_type" "store") 4449 (set_attr "mode" "<MODE>")]) 4450 4451(define_insn "mov_<store>r" 4452 [(set (match_operand:BLK 0 "memory_operand" "+m") 4453 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 4454 (match_operand:QI 2 "memory_operand" "ZC") 4455 (match_dup 0)] 4456 UNSPEC_STORE_RIGHT))] 4457 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])" 4458 "<store>r\t%z1,%2" 4459 [(set_attr "move_type" "store") 4460 (set_attr "mode" "<MODE>")]) 4461 4462;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE. 4463;; The required value is: 4464;; 4465;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16) 4466;; 4467;; which translates to: 4468;; 4469;; lui op0,%highest(op1) 4470;; daddiu op0,op0,%higher(op1) 4471;; dsll op0,op0,16 4472;; daddiu op0,op0,%hi(op1) 4473;; dsll op0,op0,16 4474;; 4475;; The split is deferred until after flow2 to allow the peephole2 below 4476;; to take effect. 4477(define_insn_and_split "*lea_high64" 4478 [(set (match_operand:DI 0 "register_operand" "=d") 4479 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))] 4480 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS" 4481 "#" 4482 "&& epilogue_completed" 4483 [(set (match_dup 0) (high:DI (match_dup 2))) 4484 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2))) 4485 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16))) 4486 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3))) 4487 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))] 4488{ 4489 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH); 4490 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID); 4491} 4492 [(set_attr "insn_count" "5")]) 4493 4494;; Use a scratch register to reduce the latency of the above pattern 4495;; on superscalar machines. The optimized sequence is: 4496;; 4497;; lui op1,%highest(op2) 4498;; lui op0,%hi(op2) 4499;; daddiu op1,op1,%higher(op2) 4500;; dsll32 op1,op1,0 4501;; daddu op1,op1,op0 4502(define_peephole2 4503 [(set (match_operand:DI 1 "d_operand") 4504 (high:DI (match_operand:DI 2 "absolute_symbolic_operand"))) 4505 (match_scratch:DI 0 "d")] 4506 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS" 4507 [(set (match_dup 1) (high:DI (match_dup 3))) 4508 (set (match_dup 0) (high:DI (match_dup 4))) 4509 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3))) 4510 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32))) 4511 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))] 4512{ 4513 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH); 4514 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW); 4515}) 4516 4517;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit 4518;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine 4519;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only 4520;; used once. We can then use the sequence: 4521;; 4522;; lui op0,%highest(op1) 4523;; lui op2,%hi(op1) 4524;; daddiu op0,op0,%higher(op1) 4525;; daddiu op2,op2,%lo(op1) 4526;; dsll32 op0,op0,0 4527;; daddu op0,op0,op2 4528;; 4529;; which takes 4 cycles on most superscalar targets. 4530(define_insn_and_split "*lea64" 4531 [(set (match_operand:DI 0 "register_operand" "=d") 4532 (match_operand:DI 1 "absolute_symbolic_operand" "")) 4533 (clobber (match_scratch:DI 2 "=&d"))] 4534 "!TARGET_MIPS16 4535 && TARGET_EXPLICIT_RELOCS 4536 && ABI_HAS_64BIT_SYMBOLS 4537 && cse_not_expected" 4538 "#" 4539 "&& reload_completed" 4540 [(set (match_dup 0) (high:DI (match_dup 3))) 4541 (set (match_dup 2) (high:DI (match_dup 4))) 4542 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3))) 4543 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4))) 4544 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) 4545 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))] 4546{ 4547 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH); 4548 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW); 4549} 4550 [(set_attr "insn_count" "6")]) 4551 4552;; Split HIGHs into: 4553;; 4554;; li op0,%hi(sym) 4555;; sll op0,16 4556;; 4557;; on MIPS16 targets. 4558(define_split 4559 [(set (match_operand:P 0 "d_operand") 4560 (high:P (match_operand:P 1 "symbolic_operand_with_high")))] 4561 "TARGET_MIPS16 && reload_completed" 4562 [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH)) 4563 (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))]) 4564 4565(define_insn "*unshifted_high" 4566 [(set (match_operand:P 0 "d_operand" "=d") 4567 (unspec:P [(match_operand:P 1 "symbolic_operand_with_high")] 4568 UNSPEC_UNSHIFTED_HIGH))] 4569 "" 4570 "li\t%0,%h1" 4571 [(set_attr "extended_mips16" "yes")]) 4572 4573;; Insns to fetch a symbol from a big GOT. 4574 4575(define_insn_and_split "*xgot_hi<mode>" 4576 [(set (match_operand:P 0 "register_operand" "=d") 4577 (high:P (match_operand:P 1 "got_disp_operand" "")))] 4578 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT" 4579 "#" 4580 "&& reload_completed" 4581 [(set (match_dup 0) (high:P (match_dup 2))) 4582 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))] 4583{ 4584 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP); 4585 operands[3] = pic_offset_table_rtx; 4586} 4587 [(set_attr "got" "xgot_high") 4588 (set_attr "mode" "<MODE>")]) 4589 4590(define_insn_and_split "*xgot_lo<mode>" 4591 [(set (match_operand:P 0 "register_operand" "=d") 4592 (lo_sum:P (match_operand:P 1 "register_operand" "d") 4593 (match_operand:P 2 "got_disp_operand" "")))] 4594 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT" 4595 "#" 4596 "&& reload_completed" 4597 [(set (match_dup 0) 4598 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))] 4599 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); } 4600 [(set_attr "got" "load") 4601 (set_attr "mode" "<MODE>")]) 4602 4603;; Insns to fetch a symbol from a normal GOT. 4604 4605(define_insn_and_split "*got_disp<mode>" 4606 [(set (match_operand:P 0 "register_operand" "=d") 4607 (match_operand:P 1 "got_disp_operand" ""))] 4608 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]" 4609 "#" 4610 "&& reload_completed" 4611 [(set (match_dup 0) (match_dup 2))] 4612 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); } 4613 [(set_attr "got" "load") 4614 (set_attr "mode" "<MODE>")]) 4615 4616;; Insns for loading the "page" part of a page/ofst address from the GOT. 4617 4618(define_insn_and_split "*got_page<mode>" 4619 [(set (match_operand:P 0 "register_operand" "=d") 4620 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))] 4621 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]" 4622 "#" 4623 "&& reload_completed" 4624 [(set (match_dup 0) (match_dup 2))] 4625 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); } 4626 [(set_attr "got" "load") 4627 (set_attr "mode" "<MODE>")]) 4628 4629;; Convenience expander that generates the rhs of a load_got<mode> insn. 4630(define_expand "unspec_got_<mode>" 4631 [(unspec:P [(match_operand:P 0) 4632 (match_operand:P 1)] UNSPEC_LOAD_GOT)]) 4633 4634;; Lower-level instructions for loading an address from the GOT. 4635;; We could use MEMs, but an unspec gives more optimization 4636;; opportunities. 4637 4638(define_insn "load_got<mode>" 4639 [(set (match_operand:P 0 "register_operand" "=d") 4640 (unspec:P [(match_operand:P 1 "register_operand" "d") 4641 (match_operand:P 2 "immediate_operand" "")] 4642 UNSPEC_LOAD_GOT))] 4643 "" 4644 "<load>\t%0,%R2(%1)" 4645 [(set_attr "got" "load") 4646 (set_attr "mode" "<MODE>")]) 4647 4648;; Instructions for adding the low 16 bits of an address to a register. 4649;; Operand 2 is the address: mips_print_operand works out which relocation 4650;; should be applied. 4651 4652(define_insn "*low<mode>" 4653 [(set (match_operand:P 0 "register_operand" "=d") 4654 (lo_sum:P (match_operand:P 1 "register_operand" "d") 4655 (match_operand:P 2 "immediate_operand" "")))] 4656 "!TARGET_MIPS16" 4657 "<d>addiu\t%0,%1,%R2" 4658 [(set_attr "alu_type" "add") 4659 (set_attr "mode" "<MODE>")]) 4660 4661(define_insn "*low<mode>_mips16" 4662 [(set (match_operand:P 0 "register_operand" "=d") 4663 (lo_sum:P (match_operand:P 1 "register_operand" "0") 4664 (match_operand:P 2 "immediate_operand" "")))] 4665 "TARGET_MIPS16" 4666 "<d>addiu\t%0,%R2" 4667 [(set_attr "alu_type" "add") 4668 (set_attr "mode" "<MODE>") 4669 (set_attr "extended_mips16" "yes")]) 4670 4671;; Expose MIPS16 uses of the global pointer after reload if the function 4672;; is responsible for setting up the register itself. 4673(define_split 4674 [(set (match_operand:GPR 0 "d_operand") 4675 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))] 4676 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed" 4677 [(set (match_dup 0) (match_dup 1))] 4678 { operands[1] = pic_offset_table_rtx; }) 4679 4680;; Allow combine to split complex const_int load sequences, using operand 2 4681;; to store the intermediate results. See move_operand for details. 4682(define_split 4683 [(set (match_operand:GPR 0 "register_operand") 4684 (match_operand:GPR 1 "splittable_const_int_operand")) 4685 (clobber (match_operand:GPR 2 "register_operand"))] 4686 "" 4687 [(const_int 0)] 4688{ 4689 mips_move_integer (operands[2], operands[0], INTVAL (operands[1])); 4690 DONE; 4691}) 4692 4693;; Likewise, for symbolic operands. 4694(define_split 4695 [(set (match_operand:P 0 "register_operand") 4696 (match_operand:P 1)) 4697 (clobber (match_operand:P 2 "register_operand"))] 4698 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)" 4699 [(set (match_dup 0) (match_dup 3))] 4700{ 4701 mips_split_symbol (operands[2], operands[1], 4702 MAX_MACHINE_MODE, &operands[3]); 4703}) 4704 4705;; 64-bit integer moves 4706 4707;; Unlike most other insns, the move insns can't be split with 4708;; different predicates, because register spilling and other parts of 4709;; the compiler, have memoized the insn number already. 4710 4711(define_expand "movdi" 4712 [(set (match_operand:DI 0 "") 4713 (match_operand:DI 1 ""))] 4714 "" 4715{ 4716 if (mips_legitimize_move (DImode, operands[0], operands[1])) 4717 DONE; 4718}) 4719 4720;; For mips16, we need a special case to handle storing $31 into 4721;; memory, since we don't have a constraint to match $31. This 4722;; instruction can be generated by save_restore_insns. 4723 4724(define_insn "*mov<mode>_ra" 4725 [(set (match_operand:GPR 0 "stack_operand" "=m") 4726 (reg:GPR RETURN_ADDR_REGNUM))] 4727 "TARGET_MIPS16" 4728 "<store>\t$31,%0" 4729 [(set_attr "move_type" "store") 4730 (set_attr "mode" "<MODE>")]) 4731 4732(define_insn "*movdi_32bit" 4733 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m") 4734 (match_operand:DI 1 "move_operand" "d,i,m,d,*J,*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))] 4735 "!TARGET_64BIT && !TARGET_MIPS16 4736 && (register_operand (operands[0], DImode) 4737 || reg_or_0_operand (operands[1], DImode))" 4738 { return mips_output_move (operands[0], operands[1]); } 4739 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore") 4740 (set (attr "mode") 4741 (if_then_else (eq_attr "move_type" "imul") 4742 (const_string "SI") 4743 (const_string "DI")))]) 4744 4745(define_insn "*movdi_32bit_mips16" 4746 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") 4747 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))] 4748 "!TARGET_64BIT && TARGET_MIPS16 4749 && (register_operand (operands[0], DImode) 4750 || register_operand (operands[1], DImode))" 4751 { return mips_output_move (operands[0], operands[1]); } 4752 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") 4753 (set_attr "mode" "DI")]) 4754 4755(define_insn "*movdi_64bit" 4756 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m") 4757 (match_operand:DI 1 "move_operand" "d,Yd,Yf,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] 4758 "TARGET_64BIT && !TARGET_MIPS16 4759 && (register_operand (operands[0], DImode) 4760 || reg_or_0_operand (operands[1], DImode))" 4761 { return mips_output_move (operands[0], operands[1]); } 4762 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mtlo,mflo,mtc,fpload,mfc,fpstore") 4763 (set_attr "mode" "DI")]) 4764 4765(define_insn "*movdi_64bit_mips16" 4766 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d") 4767 (match_operand:DI 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))] 4768 "TARGET_64BIT && TARGET_MIPS16 4769 && (register_operand (operands[0], DImode) 4770 || register_operand (operands[1], DImode))" 4771 { return mips_output_move (operands[0], operands[1]); } 4772 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo") 4773 (set_attr "mode" "DI")]) 4774 4775;; On the mips16, we can split ld $r,N($r) into an add and a load, 4776;; when the original load is a 4 byte instruction but the add and the 4777;; load are 2 2 byte instructions. 4778 4779(define_split 4780 [(set (match_operand:DI 0 "d_operand") 4781 (mem:DI (plus:DI (match_dup 0) 4782 (match_operand:DI 1 "const_int_operand"))))] 4783 "TARGET_64BIT && TARGET_MIPS16 && reload_completed 4784 && !TARGET_DEBUG_D_MODE 4785 && ((INTVAL (operands[1]) < 0 4786 && INTVAL (operands[1]) >= -0x10) 4787 || (INTVAL (operands[1]) >= 32 * 8 4788 && INTVAL (operands[1]) <= 31 * 8 + 0x8) 4789 || (INTVAL (operands[1]) >= 0 4790 && INTVAL (operands[1]) < 32 * 8 4791 && (INTVAL (operands[1]) & 7) != 0))" 4792 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1))) 4793 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))] 4794{ 4795 HOST_WIDE_INT val = INTVAL (operands[1]); 4796 4797 if (val < 0) 4798 operands[2] = const0_rtx; 4799 else if (val >= 32 * 8) 4800 { 4801 int off = val & 7; 4802 4803 operands[1] = GEN_INT (0x8 + off); 4804 operands[2] = GEN_INT (val - off - 0x8); 4805 } 4806 else 4807 { 4808 int off = val & 7; 4809 4810 operands[1] = GEN_INT (off); 4811 operands[2] = GEN_INT (val - off); 4812 } 4813}) 4814 4815;; 32-bit Integer moves 4816 4817;; Unlike most other insns, the move insns can't be split with 4818;; different predicates, because register spilling and other parts of 4819;; the compiler, have memoized the insn number already. 4820 4821(define_expand "mov<mode>" 4822 [(set (match_operand:IMOVE32 0 "") 4823 (match_operand:IMOVE32 1 ""))] 4824 "" 4825{ 4826 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1])) 4827 DONE; 4828}) 4829 4830;; The difference between these two is whether or not ints are allowed 4831;; in FP registers (off by default, use -mdebugh to enable). 4832 4833(define_insn "*mov<mode>_internal" 4834 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,!u,!u,d,e,!u,!ks,d,ZS,ZT,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m") 4835 (match_operand:IMOVE32 1 "move_operand" "d,J,Udb7,Yd,Yf,ZT,ZS,m,!ks,!kbJ,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] 4836 "!TARGET_MIPS16 4837 && (register_operand (operands[0], <MODE>mode) 4838 || reg_or_0_operand (operands[1], <MODE>mode))" 4839 { return mips_output_move (operands[0], operands[1]); } 4840 [(set_attr "move_type" "move,move,const,const,const,load,load,load,store,store,store,mtc,fpload,mfc,fpstore,mfc,mtc,mtlo,mflo,mtc,fpload,mfc,fpstore") 4841 (set_attr "compression" "all,micromips,micromips,*,*,micromips,micromips,*,micromips,micromips,*,*,*,*,*,*,*,*,*,*,*,*,*") 4842 (set_attr "mode" "SI")]) 4843 4844(define_insn "*mov<mode>_mips16" 4845 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d") 4846 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))] 4847 "TARGET_MIPS16 4848 && (register_operand (operands[0], <MODE>mode) 4849 || register_operand (operands[1], <MODE>mode))" 4850 { return mips_output_move (operands[0], operands[1]); } 4851 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo") 4852 (set_attr "mode" "SI")]) 4853 4854;; On the mips16, we can split lw $r,N($r) into an add and a load, 4855;; when the original load is a 4 byte instruction but the add and the 4856;; load are 2 2 byte instructions. 4857 4858(define_split 4859 [(set (match_operand:SI 0 "d_operand") 4860 (mem:SI (plus:SI (match_dup 0) 4861 (match_operand:SI 1 "const_int_operand"))))] 4862 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 4863 && ((INTVAL (operands[1]) < 0 4864 && INTVAL (operands[1]) >= -0x80) 4865 || (INTVAL (operands[1]) >= 32 * 4 4866 && INTVAL (operands[1]) <= 31 * 4 + 0x7c) 4867 || (INTVAL (operands[1]) >= 0 4868 && INTVAL (operands[1]) < 32 * 4 4869 && (INTVAL (operands[1]) & 3) != 0))" 4870 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 4871 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))] 4872{ 4873 HOST_WIDE_INT val = INTVAL (operands[1]); 4874 4875 if (val < 0) 4876 operands[2] = const0_rtx; 4877 else if (val >= 32 * 4) 4878 { 4879 int off = val & 3; 4880 4881 operands[1] = GEN_INT (0x7c + off); 4882 operands[2] = GEN_INT (val - off - 0x7c); 4883 } 4884 else 4885 { 4886 int off = val & 3; 4887 4888 operands[1] = GEN_INT (off); 4889 operands[2] = GEN_INT (val - off); 4890 } 4891}) 4892 4893;; On the mips16, we can split a load of certain constants into a load 4894;; and an add. This turns a 4 byte instruction into 2 2 byte 4895;; instructions. 4896 4897(define_split 4898 [(set (match_operand:SI 0 "d_operand") 4899 (match_operand:SI 1 "const_int_operand"))] 4900 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 4901 && INTVAL (operands[1]) >= 0x100 4902 && INTVAL (operands[1]) <= 0xff + 0x7f" 4903 [(set (match_dup 0) (match_dup 1)) 4904 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] 4905{ 4906 int val = INTVAL (operands[1]); 4907 4908 operands[1] = GEN_INT (0xff); 4909 operands[2] = GEN_INT (val - 0xff); 4910}) 4911 4912;; MIPS4 supports loading and storing a floating point register from 4913;; the sum of two general registers. We use two versions for each of 4914;; these four instructions: one where the two general registers are 4915;; SImode, and one where they are DImode. This is because general 4916;; registers will be in SImode when they hold 32-bit values, but, 4917;; since the 32-bit values are always sign extended, the [ls][wd]xc1 4918;; instructions will still work correctly. 4919 4920;; ??? Perhaps it would be better to support these instructions by 4921;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since 4922;; these instructions can only be used to load and store floating 4923;; point registers, that would probably cause trouble in reload. 4924 4925(define_insn "*<ANYF:loadx>_<P:mode>" 4926 [(set (match_operand:ANYF 0 "register_operand" "=f") 4927 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d") 4928 (match_operand:P 2 "register_operand" "d"))))] 4929 "ISA_HAS_LXC1_SXC1" 4930 "<ANYF:loadx>\t%0,%1(%2)" 4931 [(set_attr "type" "fpidxload") 4932 (set_attr "mode" "<ANYF:UNITMODE>")]) 4933 4934(define_insn "*<ANYF:storex>_<P:mode>" 4935 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d") 4936 (match_operand:P 2 "register_operand" "d"))) 4937 (match_operand:ANYF 0 "register_operand" "f"))] 4938 "ISA_HAS_LXC1_SXC1" 4939 "<ANYF:storex>\t%0,%1(%2)" 4940 [(set_attr "type" "fpidxstore") 4941 (set_attr "mode" "<ANYF:UNITMODE>")]) 4942 4943;; Scaled indexed address load. 4944;; Per md.texi, we only need to look for a pattern with multiply in the 4945;; address expression, not shift. 4946 4947(define_insn "*lwxs" 4948 [(set (match_operand:IMOVE32 0 "register_operand" "=d") 4949 (mem:IMOVE32 4950 (plus:P (mult:P (match_operand:P 1 "register_operand" "d") 4951 (const_int 4)) 4952 (match_operand:P 2 "register_operand" "d"))))] 4953 "ISA_HAS_LWXS" 4954 "lwxs\t%0,%1(%2)" 4955 [(set_attr "type" "load") 4956 (set_attr "mode" "SI")]) 4957 4958;; 16-bit Integer moves 4959 4960;; Unlike most other insns, the move insns can't be split with 4961;; different predicates, because register spilling and other parts of 4962;; the compiler, have memoized the insn number already. 4963;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND. 4964 4965(define_expand "movhi" 4966 [(set (match_operand:HI 0 "") 4967 (match_operand:HI 1 ""))] 4968 "" 4969{ 4970 if (mips_legitimize_move (HImode, operands[0], operands[1])) 4971 DONE; 4972}) 4973 4974(define_insn "*movhi_internal" 4975 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZU,m,*a,*d") 4976 (match_operand:HI 1 "move_operand" "d,J,I,ZU,m,!kbJ,dJ,*d*J,*a"))] 4977 "!TARGET_MIPS16 4978 && (register_operand (operands[0], HImode) 4979 || reg_or_0_operand (operands[1], HImode))" 4980 { return mips_output_move (operands[0], operands[1]); } 4981 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo") 4982 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*") 4983 (set_attr "mode" "HI")]) 4984 4985(define_insn "*movhi_mips16" 4986 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") 4987 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] 4988 "TARGET_MIPS16 4989 && (register_operand (operands[0], HImode) 4990 || register_operand (operands[1], HImode))" 4991 { return mips_output_move (operands[0], operands[1]); } 4992 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") 4993 (set_attr "mode" "HI")]) 4994 4995;; On the mips16, we can split lh $r,N($r) into an add and a load, 4996;; when the original load is a 4 byte instruction but the add and the 4997;; load are 2 2 byte instructions. 4998 4999(define_split 5000 [(set (match_operand:HI 0 "d_operand") 5001 (mem:HI (plus:SI (match_dup 0) 5002 (match_operand:SI 1 "const_int_operand"))))] 5003 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 5004 && ((INTVAL (operands[1]) < 0 5005 && INTVAL (operands[1]) >= -0x80) 5006 || (INTVAL (operands[1]) >= 32 * 2 5007 && INTVAL (operands[1]) <= 31 * 2 + 0x7e) 5008 || (INTVAL (operands[1]) >= 0 5009 && INTVAL (operands[1]) < 32 * 2 5010 && (INTVAL (operands[1]) & 1) != 0))" 5011 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 5012 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))] 5013{ 5014 HOST_WIDE_INT val = INTVAL (operands[1]); 5015 5016 if (val < 0) 5017 operands[2] = const0_rtx; 5018 else if (val >= 32 * 2) 5019 { 5020 int off = val & 1; 5021 5022 operands[1] = GEN_INT (0x7e + off); 5023 operands[2] = GEN_INT (val - off - 0x7e); 5024 } 5025 else 5026 { 5027 int off = val & 1; 5028 5029 operands[1] = GEN_INT (off); 5030 operands[2] = GEN_INT (val - off); 5031 } 5032}) 5033 5034;; 8-bit Integer moves 5035 5036;; Unlike most other insns, the move insns can't be split with 5037;; different predicates, because register spilling and other parts of 5038;; the compiler, have memoized the insn number already. 5039;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND. 5040 5041(define_expand "movqi" 5042 [(set (match_operand:QI 0 "") 5043 (match_operand:QI 1 ""))] 5044 "" 5045{ 5046 if (mips_legitimize_move (QImode, operands[0], operands[1])) 5047 DONE; 5048}) 5049 5050(define_insn "*movqi_internal" 5051 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZV,m,*a,*d") 5052 (match_operand:QI 1 "move_operand" "d,J,I,ZW,m,!kbJ,dJ,*d*J,*a"))] 5053 "!TARGET_MIPS16 5054 && (register_operand (operands[0], QImode) 5055 || reg_or_0_operand (operands[1], QImode))" 5056 { return mips_output_move (operands[0], operands[1]); } 5057 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo") 5058 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*") 5059 (set_attr "mode" "QI")]) 5060 5061(define_insn "*movqi_mips16" 5062 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") 5063 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] 5064 "TARGET_MIPS16 5065 && (register_operand (operands[0], QImode) 5066 || register_operand (operands[1], QImode))" 5067 { return mips_output_move (operands[0], operands[1]); } 5068 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") 5069 (set_attr "mode" "QI")]) 5070 5071;; On the mips16, we can split lb $r,N($r) into an add and a load, 5072;; when the original load is a 4 byte instruction but the add and the 5073;; load are 2 2 byte instructions. 5074 5075(define_split 5076 [(set (match_operand:QI 0 "d_operand") 5077 (mem:QI (plus:SI (match_dup 0) 5078 (match_operand:SI 1 "const_int_operand"))))] 5079 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 5080 && ((INTVAL (operands[1]) < 0 5081 && INTVAL (operands[1]) >= -0x80) 5082 || (INTVAL (operands[1]) >= 32 5083 && INTVAL (operands[1]) <= 31 + 0x7f))" 5084 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 5085 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))] 5086{ 5087 HOST_WIDE_INT val = INTVAL (operands[1]); 5088 5089 if (val < 0) 5090 operands[2] = const0_rtx; 5091 else 5092 { 5093 operands[1] = GEN_INT (0x7f); 5094 operands[2] = GEN_INT (val - 0x7f); 5095 } 5096}) 5097 5098;; 32-bit floating point moves 5099 5100(define_expand "movsf" 5101 [(set (match_operand:SF 0 "") 5102 (match_operand:SF 1 ""))] 5103 "" 5104{ 5105 if (mips_legitimize_move (SFmode, operands[0], operands[1])) 5106 DONE; 5107}) 5108 5109(define_insn "movccf" 5110 [(set (match_operand:CCF 0 "nonimmediate_operand" "=f,f,m") 5111 (match_operand:CCF 1 "nonimmediate_operand" "f,m,f"))] 5112 "ISA_HAS_CCF" 5113 { return mips_output_move (operands[0], operands[1]); } 5114 [(set_attr "move_type" "fmove,fpload,fpstore")]) 5115 5116(define_insn "*movsf_hardfloat" 5117 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") 5118 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))] 5119 "TARGET_HARD_FLOAT 5120 && (register_operand (operands[0], SFmode) 5121 || reg_or_0_operand (operands[1], SFmode))" 5122 { return mips_output_move (operands[0], operands[1]); } 5123 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") 5124 (set_attr "mode" "SF")]) 5125 5126(define_insn "*movsf_softfloat" 5127 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m") 5128 (match_operand:SF 1 "move_operand" "Gd,m,d"))] 5129 "TARGET_SOFT_FLOAT && !TARGET_MIPS16 5130 && (register_operand (operands[0], SFmode) 5131 || reg_or_0_operand (operands[1], SFmode))" 5132 { return mips_output_move (operands[0], operands[1]); } 5133 [(set_attr "move_type" "move,load,store") 5134 (set_attr "mode" "SF")]) 5135 5136(define_insn "*movsf_mips16" 5137 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m") 5138 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))] 5139 "TARGET_MIPS16 5140 && (register_operand (operands[0], SFmode) 5141 || register_operand (operands[1], SFmode))" 5142 { return mips_output_move (operands[0], operands[1]); } 5143 [(set_attr "move_type" "move,move,move,load,store") 5144 (set_attr "mode" "SF")]) 5145 5146;; 64-bit floating point moves 5147 5148(define_expand "movdf" 5149 [(set (match_operand:DF 0 "") 5150 (match_operand:DF 1 ""))] 5151 "" 5152{ 5153 if (mips_legitimize_move (DFmode, operands[0], operands[1])) 5154 DONE; 5155}) 5156 5157(define_insn "*movdf_hardfloat" 5158 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") 5159 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))] 5160 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT 5161 && (register_operand (operands[0], DFmode) 5162 || reg_or_0_operand (operands[1], DFmode))" 5163 { return mips_output_move (operands[0], operands[1]); } 5164 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") 5165 (set_attr "mode" "DF")]) 5166 5167(define_insn "*movdf_softfloat" 5168 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m") 5169 (match_operand:DF 1 "move_operand" "dG,m,dG"))] 5170 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16 5171 && (register_operand (operands[0], DFmode) 5172 || reg_or_0_operand (operands[1], DFmode))" 5173 { return mips_output_move (operands[0], operands[1]); } 5174 [(set_attr "move_type" "move,load,store") 5175 (set_attr "mode" "DF")]) 5176 5177(define_insn "*movdf_mips16" 5178 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m") 5179 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))] 5180 "TARGET_MIPS16 5181 && (register_operand (operands[0], DFmode) 5182 || register_operand (operands[1], DFmode))" 5183 { return mips_output_move (operands[0], operands[1]); } 5184 [(set_attr "move_type" "move,move,move,load,store") 5185 (set_attr "mode" "DF")]) 5186 5187;; 128-bit integer moves 5188 5189(define_expand "movti" 5190 [(set (match_operand:TI 0) 5191 (match_operand:TI 1))] 5192 "TARGET_64BIT" 5193{ 5194 if (mips_legitimize_move (TImode, operands[0], operands[1])) 5195 DONE; 5196}) 5197 5198(define_insn "*movti" 5199 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d") 5200 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*J,*d,*a"))] 5201 "TARGET_64BIT 5202 && !TARGET_MIPS16 5203 && (register_operand (operands[0], TImode) 5204 || reg_or_0_operand (operands[1], TImode))" 5205 { return mips_output_move (operands[0], operands[1]); } 5206 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo") 5207 (set (attr "mode") 5208 (if_then_else (eq_attr "move_type" "imul") 5209 (const_string "SI") 5210 (const_string "TI")))]) 5211 5212(define_insn "*movti_mips16" 5213 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") 5214 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] 5215 "TARGET_64BIT 5216 && TARGET_MIPS16 5217 && (register_operand (operands[0], TImode) 5218 || register_operand (operands[1], TImode))" 5219 "#" 5220 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") 5221 (set_attr "mode" "TI")]) 5222 5223;; 128-bit floating point moves 5224 5225(define_expand "movtf" 5226 [(set (match_operand:TF 0) 5227 (match_operand:TF 1))] 5228 "TARGET_64BIT" 5229{ 5230 if (mips_legitimize_move (TFmode, operands[0], operands[1])) 5231 DONE; 5232}) 5233 5234;; This pattern handles both hard- and soft-float cases. 5235(define_insn "*movtf" 5236 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m") 5237 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))] 5238 "TARGET_64BIT 5239 && !TARGET_MIPS16 5240 && (register_operand (operands[0], TFmode) 5241 || reg_or_0_operand (operands[1], TFmode))" 5242 "#" 5243 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore") 5244 (set_attr "mode" "TF")]) 5245 5246(define_insn "*movtf_mips16" 5247 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m") 5248 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))] 5249 "TARGET_64BIT 5250 && TARGET_MIPS16 5251 && (register_operand (operands[0], TFmode) 5252 || register_operand (operands[1], TFmode))" 5253 "#" 5254 [(set_attr "move_type" "move,move,move,load,store") 5255 (set_attr "mode" "TF")]) 5256 5257(define_split 5258 [(set (match_operand:MOVE64 0 "nonimmediate_operand") 5259 (match_operand:MOVE64 1 "move_operand"))] 5260 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)" 5261 [(const_int 0)] 5262{ 5263 mips_split_move_insn (operands[0], operands[1], curr_insn); 5264 DONE; 5265}) 5266 5267(define_split 5268 [(set (match_operand:MOVE128 0 "nonimmediate_operand") 5269 (match_operand:MOVE128 1 "move_operand"))] 5270 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)" 5271 [(const_int 0)] 5272{ 5273 mips_split_move_insn (operands[0], operands[1], curr_insn); 5274 DONE; 5275}) 5276 5277;; When generating mips16 code, split moves of negative constants into 5278;; a positive "li" followed by a negation. 5279(define_split 5280 [(set (match_operand 0 "d_operand") 5281 (match_operand 1 "const_int_operand"))] 5282 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0" 5283 [(set (match_dup 2) 5284 (match_dup 3)) 5285 (set (match_dup 2) 5286 (neg:SI (match_dup 2)))] 5287{ 5288 operands[2] = gen_lowpart (SImode, operands[0]); 5289 operands[3] = GEN_INT (-INTVAL (operands[1])); 5290}) 5291 5292;; 64-bit paired-single floating point moves 5293 5294(define_expand "movv2sf" 5295 [(set (match_operand:V2SF 0) 5296 (match_operand:V2SF 1))] 5297 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" 5298{ 5299 if (mips_legitimize_move (V2SFmode, operands[0], operands[1])) 5300 DONE; 5301}) 5302 5303(define_insn "*movv2sf" 5304 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") 5305 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))] 5306 "TARGET_HARD_FLOAT 5307 && TARGET_PAIRED_SINGLE_FLOAT 5308 && (register_operand (operands[0], V2SFmode) 5309 || reg_or_0_operand (operands[1], V2SFmode))" 5310 { return mips_output_move (operands[0], operands[1]); } 5311 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") 5312 (set_attr "mode" "DF")]) 5313 5314;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p 5315;; for the reason why we can't just use (reg:GPR HI_REGNUM). 5316;; 5317;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI 5318;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards 5319;; and the errata related to -mfix-vr4130. 5320(define_insn "mfhi<GPR:mode>_<HILO:mode>" 5321 [(set (match_operand:GPR 0 "register_operand" "=d") 5322 (unspec:GPR [(match_operand:HILO 1 "hilo_operand" "x")] 5323 UNSPEC_MFHI))] 5324 "" 5325 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; } 5326 [(set_attr "type" "mfhi") 5327 (set_attr "mode" "<GPR:MODE>")]) 5328 5329;; Set the high part of a HI/LO value, given that the low part has 5330;; already been set. See mips_hard_regno_mode_ok_p for the reason 5331;; why we can't just use (reg:GPR HI_REGNUM). 5332(define_insn "mthi<GPR:mode>_<HILO:mode>" 5333 [(set (match_operand:HILO 0 "register_operand" "=x") 5334 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 5335 (match_operand:GPR 2 "register_operand" "l")] 5336 UNSPEC_MTHI))] 5337 "" 5338 "mthi\t%z1" 5339 [(set_attr "type" "mthi") 5340 (set_attr "mode" "SI")]) 5341 5342;; Emit a doubleword move in which exactly one of the operands is 5343;; a floating-point register. We can't just emit two normal moves 5344;; because of the constraints imposed by the FPU register model; 5345;; see mips_cannot_change_mode_class for details. Instead, we keep 5346;; the FPR whole and use special patterns to refer to each word of 5347;; the other operand. 5348 5349(define_expand "move_doubleword_fpr<mode>" 5350 [(set (match_operand:SPLITF 0) 5351 (match_operand:SPLITF 1))] 5352 "" 5353{ 5354 if (FP_REG_RTX_P (operands[0])) 5355 { 5356 rtx low = mips_subword (operands[1], 0); 5357 rtx high = mips_subword (operands[1], 1); 5358 emit_insn (gen_load_low<mode> (operands[0], low)); 5359 if (ISA_HAS_MXHC1 && !TARGET_64BIT) 5360 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0])); 5361 else 5362 emit_insn (gen_load_high<mode> (operands[0], high, operands[0])); 5363 } 5364 else 5365 { 5366 rtx low = mips_subword (operands[0], 0); 5367 rtx high = mips_subword (operands[0], 1); 5368 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx)); 5369 if (ISA_HAS_MXHC1 && !TARGET_64BIT) 5370 emit_insn (gen_mfhc1<mode> (high, operands[1])); 5371 else 5372 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx)); 5373 } 5374 DONE; 5375}) 5376 5377;; Load the low word of operand 0 with operand 1. 5378(define_insn "load_low<mode>" 5379 [(set (match_operand:SPLITF 0 "register_operand" "=f,f") 5380 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")] 5381 UNSPEC_LOAD_LOW))] 5382 "TARGET_HARD_FLOAT" 5383{ 5384 operands[0] = mips_subword (operands[0], 0); 5385 return mips_output_move (operands[0], operands[1]); 5386} 5387 [(set_attr "move_type" "mtc,fpload") 5388 (set_attr "mode" "<HALFMODE>")]) 5389 5390;; Load the high word of operand 0 from operand 1, preserving the value 5391;; in the low word. 5392(define_insn "load_high<mode>" 5393 [(set (match_operand:SPLITF 0 "register_operand" "=f,f") 5394 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m") 5395 (match_operand:SPLITF 2 "register_operand" "0,0")] 5396 UNSPEC_LOAD_HIGH))] 5397 "TARGET_HARD_FLOAT" 5398{ 5399 operands[0] = mips_subword (operands[0], 1); 5400 return mips_output_move (operands[0], operands[1]); 5401} 5402 [(set_attr "move_type" "mtc,fpload") 5403 (set_attr "mode" "<HALFMODE>")]) 5404 5405;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the 5406;; high word and 0 to store the low word. 5407(define_insn "store_word<mode>" 5408 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m") 5409 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f") 5410 (match_operand 2 "const_int_operand")] 5411 UNSPEC_STORE_WORD))] 5412 "TARGET_HARD_FLOAT" 5413{ 5414 operands[1] = mips_subword (operands[1], INTVAL (operands[2])); 5415 return mips_output_move (operands[0], operands[1]); 5416} 5417 [(set_attr "move_type" "mfc,fpstore") 5418 (set_attr "mode" "<HALFMODE>")]) 5419 5420;; Move operand 1 to the high word of operand 0 using mthc1, preserving the 5421;; value in the low word. 5422(define_insn "mthc1<mode>" 5423 [(set (match_operand:SPLITF 0 "register_operand" "=f") 5424 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ") 5425 (match_operand:SPLITF 2 "register_operand" "0")] 5426 UNSPEC_MTHC1))] 5427 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1" 5428 "mthc1\t%z1,%0" 5429 [(set_attr "move_type" "mtc") 5430 (set_attr "mode" "<HALFMODE>")]) 5431 5432;; Move high word of operand 1 to operand 0 using mfhc1. 5433(define_insn "mfhc1<mode>" 5434 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d") 5435 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")] 5436 UNSPEC_MFHC1))] 5437 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1" 5438 "mfhc1\t%0,%1" 5439 [(set_attr "move_type" "mfc") 5440 (set_attr "mode" "<HALFMODE>")]) 5441 5442;; Move a constant that satisfies CONST_GP_P into operand 0. 5443(define_expand "load_const_gp_<mode>" 5444 [(set (match_operand:P 0 "register_operand" "=d") 5445 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))]) 5446 5447;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset 5448;; of _gp from the start of this function. Operand 1 is the incoming 5449;; function address. 5450(define_insn_and_split "loadgp_newabi_<mode>" 5451 [(set (match_operand:P 0 "register_operand" "=&d") 5452 (unspec:P [(match_operand:P 1) 5453 (match_operand:P 2 "register_operand" "d")] 5454 UNSPEC_LOADGP))] 5455 "mips_current_loadgp_style () == LOADGP_NEWABI" 5456 { return mips_must_initialize_gp_p () ? "#" : ""; } 5457 "&& mips_must_initialize_gp_p ()" 5458 [(set (match_dup 0) (match_dup 3)) 5459 (set (match_dup 0) (match_dup 4)) 5460 (set (match_dup 0) (match_dup 5))] 5461{ 5462 operands[3] = gen_rtx_HIGH (Pmode, operands[1]); 5463 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]); 5464 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]); 5465} 5466 [(set_attr "type" "ghost")]) 5467 5468;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol. 5469(define_insn_and_split "loadgp_absolute_<mode>" 5470 [(set (match_operand:P 0 "register_operand" "=d") 5471 (unspec:P [(match_operand:P 1)] UNSPEC_LOADGP))] 5472 "mips_current_loadgp_style () == LOADGP_ABSOLUTE" 5473 { return mips_must_initialize_gp_p () ? "#" : ""; } 5474 "&& mips_must_initialize_gp_p ()" 5475 [(const_int 0)] 5476{ 5477 mips_emit_move (operands[0], operands[1]); 5478 DONE; 5479} 5480 [(set_attr "type" "ghost")]) 5481 5482;; This blockage instruction prevents the gp load from being 5483;; scheduled after an implicit use of gp. It also prevents 5484;; the load from being deleted as dead. 5485(define_insn "loadgp_blockage" 5486 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)] 5487 "" 5488 "" 5489 [(set_attr "type" "ghost")]) 5490 5491;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol 5492;; and operand 1 is the __GOTT_INDEX__ symbol. 5493(define_insn_and_split "loadgp_rtp_<mode>" 5494 [(set (match_operand:P 0 "register_operand" "=d") 5495 (unspec:P [(match_operand:P 1 "symbol_ref_operand") 5496 (match_operand:P 2 "symbol_ref_operand")] 5497 UNSPEC_LOADGP))] 5498 "mips_current_loadgp_style () == LOADGP_RTP" 5499 { return mips_must_initialize_gp_p () ? "#" : ""; } 5500 "&& mips_must_initialize_gp_p ()" 5501 [(set (match_dup 0) (high:P (match_dup 3))) 5502 (set (match_dup 0) (unspec:P [(match_dup 0) 5503 (match_dup 3)] UNSPEC_LOAD_GOT)) 5504 (set (match_dup 0) (unspec:P [(match_dup 0) 5505 (match_dup 4)] UNSPEC_LOAD_GOT))] 5506{ 5507 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE); 5508 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF); 5509} 5510 [(set_attr "type" "ghost")]) 5511 5512;; Initialize the global pointer for MIPS16 code. Operand 0 is the 5513;; global pointer and operand 1 is the MIPS16 register that holds 5514;; the required value. 5515(define_insn_and_split "copygp_mips16_<mode>" 5516 [(set (match_operand:P 0 "register_operand" "=y") 5517 (unspec:P [(match_operand:P 1 "register_operand" "d")] 5518 UNSPEC_COPYGP))] 5519 "TARGET_MIPS16" 5520 { return mips_must_initialize_gp_p () ? "#" : ""; } 5521 "&& mips_must_initialize_gp_p ()" 5522 [(set (match_dup 0) (match_dup 1))] 5523 "" 5524 [(set_attr "type" "ghost")]) 5525 5526;; A placeholder for where the cprestore instruction should go, 5527;; if we decide we need one. Operand 0 and operand 1 are as for 5528;; "cprestore". Operand 2 is a register that holds the gp value. 5529;; 5530;; The "cprestore" pattern requires operand 2 to be pic_offset_table_rtx, 5531;; otherwise any register that holds the correct value will do. 5532(define_insn_and_split "potential_cprestore_<mode>" 5533 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X") 5534 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i") 5535 (match_operand:P 2 "register_operand" "d,d")] 5536 UNSPEC_POTENTIAL_CPRESTORE)) 5537 (clobber (match_operand:P 3 "scratch_operand" "=X,&d"))] 5538 "!TARGET_CPRESTORE_DIRECTIVE || operands[2] == pic_offset_table_rtx" 5539 { return mips_must_initialize_gp_p () ? "#" : ""; } 5540 "mips_must_initialize_gp_p ()" 5541 [(const_int 0)] 5542{ 5543 mips_save_gp_to_cprestore_slot (operands[0], operands[1], 5544 operands[2], operands[3]); 5545 DONE; 5546} 5547 [(set_attr "type" "ghost")]) 5548 5549;; Emit a .cprestore directive, which normally expands to a single store 5550;; instruction. Operand 0 is a (possibly illegitimate) sp-based MEM 5551;; for the cprestore slot. Operand 1 is the offset of the slot from 5552;; the stack pointer. (This is redundant with operand 0, but it makes 5553;; things a little simpler.) 5554(define_insn "cprestore_<mode>" 5555 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X") 5556 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i") 5557 (reg:P 28)] 5558 UNSPEC_CPRESTORE))] 5559 "TARGET_CPRESTORE_DIRECTIVE" 5560{ 5561 if (mips_nomacro.nesting_level > 0 && which_alternative == 1) 5562 return ".set\tmacro\;.cprestore\t%1\;.set\tnomacro"; 5563 else 5564 return ".cprestore\t%1"; 5565} 5566 [(set_attr "type" "store") 5567 (set_attr "insn_count" "1,3")]) 5568 5569(define_insn "use_cprestore_<mode>" 5570 [(set (reg:P CPRESTORE_SLOT_REGNUM) 5571 (match_operand:P 0 "cprestore_load_slot_operand"))] 5572 "" 5573 "" 5574 [(set_attr "type" "ghost")]) 5575 5576;; Expand in-line code to clear the instruction cache between operand[0] and 5577;; operand[1]. 5578(define_expand "clear_cache" 5579 [(match_operand 0 "pmode_register_operand") 5580 (match_operand 1 "pmode_register_operand")] 5581 "" 5582 " 5583{ 5584 if (TARGET_SYNCI) 5585 { 5586 mips_expand_synci_loop (operands[0], operands[1]); 5587 emit_insn (gen_sync ()); 5588 emit_insn (PMODE_INSN (gen_clear_hazard, ())); 5589 } 5590 else if (mips_cache_flush_func && mips_cache_flush_func[0]) 5591 { 5592 rtx len = gen_reg_rtx (Pmode); 5593 emit_insn (gen_sub3_insn (len, operands[1], operands[0])); 5594 MIPS_ICACHE_SYNC (operands[0], len); 5595 } 5596 DONE; 5597}") 5598 5599(define_insn "sync" 5600 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)] 5601 "GENERATE_SYNC" 5602 { return mips_output_sync (); }) 5603 5604(define_insn "synci" 5605 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")] 5606 UNSPEC_SYNCI)] 5607 "TARGET_SYNCI" 5608 "synci\t0(%0)") 5609 5610(define_insn "rdhwr_synci_step_<mode>" 5611 [(set (match_operand:P 0 "register_operand" "=d") 5612 (unspec_volatile [(const_int 1)] 5613 UNSPEC_RDHWR))] 5614 "ISA_HAS_SYNCI" 5615 "rdhwr\t%0,$1") 5616 5617(define_insn "clear_hazard_<mode>" 5618 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD) 5619 (clobber (reg:P RETURN_ADDR_REGNUM))] 5620 "ISA_HAS_SYNCI" 5621{ 5622 return "%(%<bal\t1f\n" 5623 "\tnop\n" 5624 "1:\t<d>addiu\t$31,$31,12\n" 5625 "\tjr.hb\t$31\n" 5626 "\tnop%>%)"; 5627} 5628 [(set_attr "insn_count" "5")]) 5629 5630;; Cache operations for R4000-style caches. 5631(define_insn "mips_cache" 5632 [(set (mem:BLK (scratch)) 5633 (unspec:BLK [(match_operand:SI 0 "const_int_operand") 5634 (match_operand:QI 1 "address_operand" "ZD")] 5635 UNSPEC_MIPS_CACHE))] 5636 "ISA_HAS_CACHE" 5637 "cache\t%X0,%a1") 5638 5639;; Similar, but with the operands hard-coded to an R10K cache barrier 5640;; operation. We keep the pattern distinct so that we can identify 5641;; cache operations inserted by -mr10k-cache-barrier=, and so that 5642;; the operation is never inserted into a delay slot. 5643(define_insn "r10k_cache_barrier" 5644 [(set (mem:BLK (scratch)) 5645 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))] 5646 "ISA_HAS_CACHE" 5647 "cache\t0x14,0(%$)" 5648 [(set_attr "can_delay" "no")]) 5649 5650;; Block moves, see mips.c for more details. 5651;; Argument 0 is the destination 5652;; Argument 1 is the source 5653;; Argument 2 is the length 5654;; Argument 3 is the alignment 5655 5656(define_expand "cpymemsi" 5657 [(parallel [(set (match_operand:BLK 0 "general_operand") 5658 (match_operand:BLK 1 "general_operand")) 5659 (use (match_operand:SI 2 "")) 5660 (use (match_operand:SI 3 "const_int_operand"))])] 5661 "!TARGET_MIPS16 && !TARGET_MEMCPY" 5662{ 5663 if (mips_expand_block_move (operands[0], operands[1], operands[2])) 5664 DONE; 5665 else 5666 FAIL; 5667}) 5668 5669;; 5670;; .................... 5671;; 5672;; SHIFTS 5673;; 5674;; .................... 5675 5676(define_expand "<optab><mode>3" 5677 [(set (match_operand:GPR 0 "register_operand") 5678 (any_shift:GPR (match_operand:GPR 1 "register_operand") 5679 (match_operand:SI 2 "arith_operand")))] 5680 "" 5681{ 5682 /* On the mips16, a shift of more than 8 is a four byte instruction, 5683 so, for a shift between 8 and 16, it is just as fast to do two 5684 shifts of 8 or less. If there is a lot of shifting going on, we 5685 may win in CSE. Otherwise combine will put the shifts back 5686 together again. This can be called by mips_function_arg, so we must 5687 be careful not to allocate a new register if we've reached the 5688 reload pass. */ 5689 if (TARGET_MIPS16 5690 && optimize 5691 && CONST_INT_P (operands[2]) 5692 && INTVAL (operands[2]) > 8 5693 && INTVAL (operands[2]) <= 16 5694 && !reload_in_progress 5695 && !reload_completed) 5696 { 5697 rtx temp = gen_reg_rtx (<MODE>mode); 5698 5699 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8))); 5700 emit_insn (gen_<optab><mode>3 (operands[0], temp, 5701 GEN_INT (INTVAL (operands[2]) - 8))); 5702 DONE; 5703 } 5704}) 5705 5706(define_insn "*<optab><mode>3" 5707 [(set (match_operand:GPR 0 "register_operand" "=!u,d") 5708 (any_shift:GPR (match_operand:GPR 1 "register_operand" "!u,d") 5709 (match_operand:SI 2 "arith_operand" "Uib3,dI")))] 5710 "!TARGET_MIPS16" 5711{ 5712 if (CONST_INT_P (operands[2])) 5713 operands[2] = GEN_INT (INTVAL (operands[2]) 5714 & (GET_MODE_BITSIZE (<MODE>mode) - 1)); 5715 5716 return "<d><insn>\t%0,%1,%2"; 5717} 5718 [(set_attr "type" "shift") 5719 (set_attr "compression" "<shift_compression>,none") 5720 (set_attr "mode" "<MODE>")]) 5721 5722(define_insn "*<optab>si3_extend" 5723 [(set (match_operand:DI 0 "register_operand" "=d") 5724 (sign_extend:DI 5725 (any_shift:SI (match_operand:SI 1 "register_operand" "d") 5726 (match_operand:SI 2 "arith_operand" "dI"))))] 5727 "TARGET_64BIT && !TARGET_MIPS16" 5728{ 5729 if (CONST_INT_P (operands[2])) 5730 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 5731 5732 return "<insn>\t%0,%1,%2"; 5733} 5734 [(set_attr "type" "shift") 5735 (set_attr "mode" "SI")]) 5736 5737(define_insn "*<optab>si3_mips16" 5738 [(set (match_operand:SI 0 "register_operand" "=d,d,d") 5739 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d,d") 5740 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))] 5741 "TARGET_MIPS16" 5742{ 5743 if (which_alternative == 0) 5744 return "<insn>\t%0,%2"; 5745 5746 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 5747 return "<insn>\t%0,%1,%2"; 5748} 5749 [(set_attr "type" "shift") 5750 (set_attr "mode" "SI") 5751 (set_attr "extended_mips16" "no,no,yes")]) 5752 5753(define_insn "<GPR:d>lsa" 5754 [(set (match_operand:GPR 0 "register_operand" "=d") 5755 (plus:GPR (ashift:GPR (match_operand:GPR 1 "register_operand" "d") 5756 (match_operand 2 "const_immlsa_operand" "")) 5757 (match_operand:GPR 3 "register_operand" "d")))] 5758 "ISA_HAS_<GPR:D>LSA" 5759 "<GPR:d>lsa\t%0,%1,%3,%2" 5760 [(set_attr "type" "arith") 5761 (set_attr "mode" "<GPR:MODE>")]) 5762 5763;; We need separate DImode MIPS16 patterns because of the irregularity 5764;; of right shifts. 5765(define_insn "*ashldi3_mips16" 5766 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 5767 (ashift:DI (match_operand:DI 1 "register_operand" "0,d,d") 5768 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))] 5769 "TARGET_64BIT && TARGET_MIPS16" 5770{ 5771 if (which_alternative == 0) 5772 return "dsll\t%0,%2"; 5773 5774 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 5775 return "dsll\t%0,%1,%2"; 5776} 5777 [(set_attr "type" "shift") 5778 (set_attr "mode" "DI") 5779 (set_attr "extended_mips16" "no,no,yes")]) 5780 5781(define_insn "*ashrdi3_mips16" 5782 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 5783 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0") 5784 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))] 5785 "TARGET_64BIT && TARGET_MIPS16" 5786{ 5787 if (CONST_INT_P (operands[2])) 5788 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 5789 5790 return "dsra\t%0,%2"; 5791} 5792 [(set_attr "type" "shift") 5793 (set_attr "mode" "DI") 5794 (set_attr "extended_mips16" "no,no,yes")]) 5795 5796(define_insn "*lshrdi3_mips16" 5797 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 5798 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0") 5799 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))] 5800 "TARGET_64BIT && TARGET_MIPS16" 5801{ 5802 if (CONST_INT_P (operands[2])) 5803 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 5804 5805 return "dsrl\t%0,%2"; 5806} 5807 [(set_attr "type" "shift") 5808 (set_attr "mode" "DI") 5809 (set_attr "extended_mips16" "no,no,yes")]) 5810 5811;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts. 5812 5813(define_split 5814 [(set (match_operand:GPR 0 "d_operand") 5815 (any_shift:GPR (match_operand:GPR 1 "d_operand") 5816 (match_operand:GPR 2 "const_int_operand")))] 5817 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 5818 && INTVAL (operands[2]) > 8 5819 && INTVAL (operands[2]) <= 16" 5820 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8))) 5821 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))] 5822 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); }) 5823 5824;; If we load a byte on the mips16 as a bitfield, the resulting 5825;; sequence of instructions is too complicated for combine, because it 5826;; involves four instructions: a load, a shift, a constant load into a 5827;; register, and an and (the key problem here is that the mips16 does 5828;; not have and immediate). We recognize a shift of a load in order 5829;; to make it simple enough for combine to understand. 5830;; 5831;; The instruction count here is the worst case. 5832(define_insn_and_split "" 5833 [(set (match_operand:SI 0 "register_operand" "=d") 5834 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") 5835 (match_operand:SI 2 "immediate_operand" "I")))] 5836 "TARGET_MIPS16" 5837 "#" 5838 "" 5839 [(set (match_dup 0) (match_dup 1)) 5840 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] 5841 "" 5842 [(set_attr "type" "load") 5843 (set_attr "mode" "SI") 5844 (set (attr "insn_count") 5845 (symbol_ref "mips_load_store_insns (operands[1], insn) + 2"))]) 5846 5847(define_insn "rotr<mode>3" 5848 [(set (match_operand:GPR 0 "register_operand" "=d") 5849 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d") 5850 (match_operand:SI 2 "arith_operand" "dI")))] 5851 "ISA_HAS_ROR" 5852{ 5853 if (CONST_INT_P (operands[2])) 5854 operands[2] = GEN_INT (INTVAL (operands[2]) 5855 & (GET_MODE_BITSIZE (<MODE>mode) - 1)); 5856 5857 return "<d>ror\t%0,%1,%2"; 5858} 5859 [(set_attr "type" "shift") 5860 (set_attr "mode" "<MODE>")]) 5861 5862(define_insn "bswaphi2" 5863 [(set (match_operand:HI 0 "register_operand" "=d") 5864 (bswap:HI (match_operand:HI 1 "register_operand" "d")))] 5865 "ISA_HAS_WSBH" 5866 "wsbh\t%0,%1" 5867 [(set_attr "type" "shift")]) 5868 5869(define_insn_and_split "bswapsi2" 5870 [(set (match_operand:SI 0 "register_operand" "=d") 5871 (bswap:SI (match_operand:SI 1 "register_operand" "d")))] 5872 "ISA_HAS_WSBH && ISA_HAS_ROR" 5873 "#" 5874 "" 5875 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH)) 5876 (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))] 5877 "" 5878 [(set_attr "insn_count" "2")]) 5879 5880(define_insn_and_split "bswapdi2" 5881 [(set (match_operand:DI 0 "register_operand" "=d") 5882 (bswap:DI (match_operand:DI 1 "register_operand" "d")))] 5883 "TARGET_64BIT && ISA_HAS_WSBH" 5884 "#" 5885 "" 5886 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH)) 5887 (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))] 5888 "" 5889 [(set_attr "insn_count" "2")]) 5890 5891(define_insn "wsbh" 5892 [(set (match_operand:SI 0 "register_operand" "=d") 5893 (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))] 5894 "ISA_HAS_WSBH" 5895 "wsbh\t%0,%1" 5896 [(set_attr "type" "shift")]) 5897 5898(define_insn "dsbh" 5899 [(set (match_operand:DI 0 "register_operand" "=d") 5900 (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))] 5901 "TARGET_64BIT && ISA_HAS_WSBH" 5902 "dsbh\t%0,%1" 5903 [(set_attr "type" "shift")]) 5904 5905(define_insn "dshd" 5906 [(set (match_operand:DI 0 "register_operand" "=d") 5907 (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))] 5908 "TARGET_64BIT && ISA_HAS_WSBH" 5909 "dshd\t%0,%1" 5910 [(set_attr "type" "shift")]) 5911 5912;; 5913;; .................... 5914;; 5915;; CONDITIONAL BRANCHES 5916;; 5917;; .................... 5918 5919;; Conditional branches on floating-point equality tests. 5920 5921(define_insn "*branch_fp_<mode>" 5922 [(set (pc) 5923 (if_then_else 5924 (match_operator 1 "equality_operator" 5925 [(match_operand:FPCC 2 "register_operand" "<reg>") 5926 (const_int 0)]) 5927 (label_ref (match_operand 0 "" "")) 5928 (pc)))] 5929 "TARGET_HARD_FLOAT" 5930{ 5931 return mips_output_conditional_branch (insn, operands, 5932 MIPS_BRANCH ("b%F1", "%Z2%0"), 5933 MIPS_BRANCH ("b%W1", "%Z2%0")); 5934} 5935 [(set_attr "type" "branch")]) 5936 5937(define_insn "*branch_fp_inverted_<mode>" 5938 [(set (pc) 5939 (if_then_else 5940 (match_operator 1 "equality_operator" 5941 [(match_operand:FPCC 2 "register_operand" "<reg>") 5942 (const_int 0)]) 5943 (pc) 5944 (label_ref (match_operand 0 "" ""))))] 5945 "TARGET_HARD_FLOAT" 5946{ 5947 return mips_output_conditional_branch (insn, operands, 5948 MIPS_BRANCH ("b%W1", "%Z2%0"), 5949 MIPS_BRANCH ("b%F1", "%Z2%0")); 5950} 5951 [(set_attr "type" "branch")]) 5952 5953;; Conditional branches on ordered comparisons with zero. 5954 5955(define_insn "*branch_order<mode>" 5956 [(set (pc) 5957 (if_then_else 5958 (match_operator 1 "order_operator" 5959 [(match_operand:GPR 2 "register_operand" "d,d") 5960 (match_operand:GPR 3 "reg_or_0_operand" "J,d")]) 5961 (label_ref (match_operand 0 "" "")) 5962 (pc)))] 5963 "!TARGET_MIPS16" 5964 { return mips_output_order_conditional_branch (insn, operands, false); } 5965 [(set_attr "type" "branch") 5966 (set_attr "compact_form" "maybe,always") 5967 (set_attr "hazard" "forbidden_slot")]) 5968 5969(define_insn "*branch_order<mode>_inverted" 5970 [(set (pc) 5971 (if_then_else 5972 (match_operator 1 "order_operator" 5973 [(match_operand:GPR 2 "register_operand" "d,d") 5974 (match_operand:GPR 3 "reg_or_0_operand" "J,d")]) 5975 (pc) 5976 (label_ref (match_operand 0 "" ""))))] 5977 "!TARGET_MIPS16" 5978 { return mips_output_order_conditional_branch (insn, operands, true); } 5979 [(set_attr "type" "branch") 5980 (set_attr "compact_form" "maybe,always") 5981 (set_attr "hazard" "forbidden_slot")]) 5982 5983;; Conditional branch on equality comparison. 5984 5985(define_insn "*branch_equality<mode>" 5986 [(set (pc) 5987 (if_then_else 5988 (match_operator 1 "equality_operator" 5989 [(match_operand:GPR 2 "register_operand" "d") 5990 (match_operand:GPR 3 "reg_or_0_operand" "dJ")]) 5991 (label_ref (match_operand 0 "" "")) 5992 (pc)))] 5993 "!TARGET_MIPS16" 5994 { return mips_output_equal_conditional_branch (insn, operands, false); } 5995 [(set_attr "type" "branch") 5996 (set_attr "compact_form" "maybe") 5997 (set_attr "hazard" "forbidden_slot")]) 5998 5999(define_insn "*branch_equality<mode>_inverted" 6000 [(set (pc) 6001 (if_then_else 6002 (match_operator 1 "equality_operator" 6003 [(match_operand:GPR 2 "register_operand" "d") 6004 (match_operand:GPR 3 "reg_or_0_operand" "dJ")]) 6005 (pc) 6006 (label_ref (match_operand 0 "" ""))))] 6007 "!TARGET_MIPS16" 6008 { return mips_output_equal_conditional_branch (insn, operands, true); } 6009 [(set_attr "type" "branch") 6010 (set_attr "compact_form" "maybe") 6011 (set_attr "hazard" "forbidden_slot")]) 6012 6013;; MIPS16 branches 6014 6015(define_insn "*branch_equality<mode>_mips16" 6016 [(set (pc) 6017 (if_then_else 6018 (match_operator 1 "equality_operator" 6019 [(match_operand:GPR 2 "register_operand" "d,t") 6020 (const_int 0)]) 6021 (label_ref (match_operand 0 "" "")) 6022 (pc)))] 6023 "TARGET_MIPS16" 6024 "@ 6025 b%C1z\t%2,%0 6026 bt%C1z\t%0" 6027 [(set_attr "type" "branch")]) 6028 6029(define_insn "*branch_equality<mode>_mips16_inverted" 6030 [(set (pc) 6031 (if_then_else 6032 (match_operator 1 "equality_operator" 6033 [(match_operand:GPR 2 "register_operand" "d,t") 6034 (const_int 0)]) 6035 (pc) 6036 (label_ref (match_operand 0 "" ""))))] 6037 "TARGET_MIPS16" 6038 "@ 6039 b%N1z\t%2,%0 6040 bt%N1z\t%0" 6041 [(set_attr "type" "branch")]) 6042 6043(define_expand "cbranch<mode>4" 6044 [(set (pc) 6045 (if_then_else (match_operator 0 "comparison_operator" 6046 [(match_operand:GPR 1 "register_operand") 6047 (match_operand:GPR 2 "nonmemory_operand")]) 6048 (label_ref (match_operand 3 "")) 6049 (pc)))] 6050 "" 6051{ 6052 mips_expand_conditional_branch (operands); 6053 DONE; 6054}) 6055 6056(define_expand "cbranch<mode>4" 6057 [(set (pc) 6058 (if_then_else (match_operator 0 "comparison_operator" 6059 [(match_operand:SCALARF 1 "register_operand") 6060 (match_operand:SCALARF 2 "register_operand")]) 6061 (label_ref (match_operand 3 "")) 6062 (pc)))] 6063 "" 6064{ 6065 mips_expand_conditional_branch (operands); 6066 DONE; 6067}) 6068 6069;; Used to implement built-in functions. 6070(define_expand "condjump" 6071 [(set (pc) 6072 (if_then_else (match_operand 0) 6073 (label_ref (match_operand 1)) 6074 (pc)))]) 6075 6076;; Branch if bit is set/clear. 6077 6078(define_insn "*branch_bit<bbv><mode>" 6079 [(set (pc) 6080 (if_then_else 6081 (equality_op (zero_extract:GPR 6082 (match_operand:GPR 1 "register_operand" "d") 6083 (const_int 1) 6084 (match_operand 2 "const_int_operand" "")) 6085 (const_int 0)) 6086 (label_ref (match_operand 0 "")) 6087 (pc)))] 6088 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" 6089{ 6090 return 6091 mips_output_conditional_branch (insn, operands, 6092 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"), 6093 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0")); 6094} 6095 [(set_attr "type" "branch") 6096 (set_attr "branch_likely" "no")]) 6097 6098(define_insn "*branch_bit<bbv><mode>_inverted" 6099 [(set (pc) 6100 (if_then_else 6101 (equality_op (zero_extract:GPR 6102 (match_operand:GPR 1 "register_operand" "d") 6103 (const_int 1) 6104 (match_operand 2 "const_int_operand" "")) 6105 (const_int 0)) 6106 (pc) 6107 (label_ref (match_operand 0 ""))))] 6108 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" 6109{ 6110 return 6111 mips_output_conditional_branch (insn, operands, 6112 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"), 6113 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0")); 6114} 6115 [(set_attr "type" "branch") 6116 (set_attr "branch_likely" "no")]) 6117 6118;; 6119;; .................... 6120;; 6121;; SETTING A REGISTER FROM A COMPARISON 6122;; 6123;; .................... 6124 6125;; Destination is always set in SI mode. 6126 6127(define_expand "cstore<mode>4" 6128 [(set (match_operand:SI 0 "register_operand") 6129 (match_operator:SI 1 "mips_cstore_operator" 6130 [(match_operand:GPR 2 "register_operand") 6131 (match_operand:GPR 3 "nonmemory_operand")]))] 6132 "" 6133{ 6134 mips_expand_scc (operands); 6135 DONE; 6136}) 6137 6138(define_insn "*seq_zero_<GPR:mode><GPR2:mode>" 6139 [(set (match_operand:GPR2 0 "register_operand" "=d") 6140 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d") 6141 (const_int 0)))] 6142 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE" 6143 "sltu\t%0,%1,1" 6144 [(set_attr "type" "slt") 6145 (set_attr "mode" "<GPR:MODE>")]) 6146 6147(define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16" 6148 [(set (match_operand:GPR2 0 "register_operand" "=t") 6149 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d") 6150 (const_int 0)))] 6151 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE" 6152 "sltu\t%1,1" 6153 [(set_attr "type" "slt") 6154 (set_attr "mode" "<GPR:MODE>")]) 6155 6156;; Generate sltiu unless using seq results in better code. 6157(define_insn "*seq_<GPR:mode><GPR2:mode>_seq" 6158 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d") 6159 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d") 6160 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))] 6161 "ISA_HAS_SEQ_SNE" 6162 "@ 6163 seq\t%0,%1,%2 6164 sltiu\t%0,%1,1 6165 seqi\t%0,%1,%2" 6166 [(set_attr "type" "slt") 6167 (set_attr "mode" "<GPR:MODE>")]) 6168 6169(define_insn "*sne_zero_<GPR:mode><GPR2:mode>" 6170 [(set (match_operand:GPR2 0 "register_operand" "=d") 6171 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d") 6172 (const_int 0)))] 6173 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE" 6174 "sltu\t%0,%.,%1" 6175 [(set_attr "type" "slt") 6176 (set_attr "mode" "<GPR:MODE>")]) 6177 6178;; Generate sltu unless using sne results in better code. 6179(define_insn "*sne_<GPR:mode><GPR2:mode>_sne" 6180 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d") 6181 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d") 6182 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))] 6183 "ISA_HAS_SEQ_SNE" 6184 "@ 6185 sne\t%0,%1,%2 6186 sltu\t%0,%.,%1 6187 snei\t%0,%1,%2" 6188 [(set_attr "type" "slt") 6189 (set_attr "mode" "<GPR:MODE>")]) 6190 6191(define_insn "*sgt<u>_<GPR:mode><GPR2:mode>" 6192 [(set (match_operand:GPR2 0 "register_operand" "=d") 6193 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d") 6194 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))] 6195 "!TARGET_MIPS16" 6196 "slt<u>\t%0,%z2,%1" 6197 [(set_attr "type" "slt") 6198 (set_attr "mode" "<GPR:MODE>")]) 6199 6200(define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16" 6201 [(set (match_operand:GPR2 0 "register_operand" "=t") 6202 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d") 6203 (match_operand:GPR 2 "register_operand" "d")))] 6204 "TARGET_MIPS16" 6205 "slt<u>\t%2,%1" 6206 [(set_attr "type" "slt") 6207 (set_attr "mode" "<GPR:MODE>")]) 6208 6209(define_insn "*sge<u>_<GPR:mode><GPR2:mode>" 6210 [(set (match_operand:GPR2 0 "register_operand" "=d") 6211 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d") 6212 (const_int 1)))] 6213 "!TARGET_MIPS16" 6214 "slt<u>\t%0,%.,%1" 6215 [(set_attr "type" "slt") 6216 (set_attr "mode" "<GPR:MODE>")]) 6217 6218(define_insn "*slt<u>_<GPR:mode><GPR2:mode>" 6219 [(set (match_operand:GPR2 0 "register_operand" "=d") 6220 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d") 6221 (match_operand:GPR 2 "arith_operand" "dI")))] 6222 "!TARGET_MIPS16" 6223 "slt<u>\t%0,%1,%2" 6224 [(set_attr "type" "slt") 6225 (set_attr "mode" "<GPR:MODE>")]) 6226 6227(define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16" 6228 [(set (match_operand:GPR2 0 "register_operand" "=t,t,t") 6229 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d,d") 6230 (match_operand:GPR 2 "arith_operand" "d,Uub8,I")))] 6231 "TARGET_MIPS16" 6232 "slt<u>\t%1,%2" 6233 [(set_attr "type" "slt") 6234 (set_attr "mode" "<GPR:MODE>") 6235 (set_attr "extended_mips16" "no,no,yes")]) 6236 6237(define_insn "*sle<u>_<GPR:mode><GPR2:mode>" 6238 [(set (match_operand:GPR2 0 "register_operand" "=d") 6239 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d") 6240 (match_operand:GPR 2 "sle_operand" "")))] 6241 "!TARGET_MIPS16" 6242{ 6243 operands[2] = GEN_INT (INTVAL (operands[2]) + 1); 6244 return "slt<u>\t%0,%1,%2"; 6245} 6246 [(set_attr "type" "slt") 6247 (set_attr "mode" "<GPR:MODE>")]) 6248 6249(define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16" 6250 [(set (match_operand:GPR2 0 "register_operand" "=t,t") 6251 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d,d") 6252 (match_operand:GPR 2 "sle_operand" "Udb8,i")))] 6253 "TARGET_MIPS16" 6254{ 6255 operands[2] = GEN_INT (INTVAL (operands[2]) + 1); 6256 return "slt<u>\t%1,%2"; 6257} 6258 [(set_attr "type" "slt") 6259 (set_attr "mode" "<GPR:MODE>") 6260 (set_attr "extended_mips16" "no,yes")]) 6261 6262;; 6263;; .................... 6264;; 6265;; FLOATING POINT COMPARISONS 6266;; 6267;; .................... 6268 6269(define_insn "s<code>_<SCALARF:mode>_using_<FPCC:mode>" 6270 [(set (match_operand:FPCC 0 "register_operand" "=<reg>") 6271 (fcond:FPCC (match_operand:SCALARF 1 "register_operand" "f") 6272 (match_operand:SCALARF 2 "register_operand" "f")))] 6273 "" 6274 "<fpcmp>.<fcond>.<fmt>\t%Z0%1,%2" 6275 [(set_attr "type" "fcmp") 6276 (set_attr "mode" "FPSW")]) 6277 6278(define_insn "s<code>_<SCALARF:mode>_using_<FPCC:mode>" 6279 [(set (match_operand:FPCC 0 "register_operand" "=<reg>") 6280 (swapped_fcond:FPCC (match_operand:SCALARF 1 "register_operand" "f") 6281 (match_operand:SCALARF 2 "register_operand" "f")))] 6282 "" 6283 "<fpcmp>.<swapped_fcond>.<fmt>\t%Z0%2,%1" 6284 [(set_attr "type" "fcmp") 6285 (set_attr "mode" "FPSW")]) 6286 6287;; 6288;; .................... 6289;; 6290;; UNCONDITIONAL BRANCHES 6291;; 6292;; .................... 6293 6294;; Unconditional branches. 6295 6296(define_expand "jump" 6297 [(set (pc) 6298 (label_ref (match_operand 0)))]) 6299 6300(define_insn "*jump_absolute" 6301 [(set (pc) 6302 (label_ref (match_operand 0)))] 6303 "!TARGET_MIPS16 && TARGET_ABSOLUTE_JUMPS" 6304{ 6305 if (get_attr_length (insn) <= 8) 6306 { 6307 if (TARGET_CB_MAYBE) 6308 return MIPS_ABSOLUTE_JUMP ("%*b%:\t%l0"); 6309 else 6310 return MIPS_ABSOLUTE_JUMP ("%*b\t%l0%/"); 6311 } 6312 else 6313 { 6314 if (TARGET_CB_MAYBE && !final_sequence) 6315 return MIPS_ABSOLUTE_JUMP ("%*bc\t%l0"); 6316 else 6317 return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/"); 6318 } 6319} 6320 [(set_attr "type" "branch") 6321 (set_attr "compact_form" "maybe")]) 6322 6323(define_insn "*jump_pic" 6324 [(set (pc) 6325 (label_ref (match_operand 0)))] 6326 "!TARGET_MIPS16 && !TARGET_ABSOLUTE_JUMPS" 6327{ 6328 if (get_attr_length (insn) <= 8) 6329 { 6330 if (TARGET_CB_MAYBE) 6331 return "%*b%:\t%l0"; 6332 else 6333 return "%*b\t%l0%/"; 6334 } 6335 else 6336 { 6337 mips_output_load_label (operands[0]); 6338 if (TARGET_CB_MAYBE) 6339 return "%*jr%:\t%@%]"; 6340 else 6341 return "%*jr\t%@%/%]"; 6342 } 6343} 6344 [(set_attr "type" "branch") 6345 (set_attr "compact_form" "maybe")]) 6346 6347;; We need a different insn for the mips16, because a mips16 branch 6348;; does not have a delay slot. 6349 6350(define_insn "*jump_mips16" 6351 [(set (pc) 6352 (label_ref (match_operand 0 "" "")))] 6353 "TARGET_MIPS16" 6354 "b\t%l0" 6355 [(set_attr "type" "branch") 6356 (set (attr "length") 6357 ;; This calculation is like the normal branch one, but the 6358 ;; range of the unextended instruction is [-0x800, 0x7fe] rather 6359 ;; than [-0x100, 0xfe]. This translates to a range of: 6360 ;; 6361 ;; [-(0x800 - sizeof (branch)), 0x7fe] 6362 ;; == [-0x7fe, 0x7fe] 6363 ;; 6364 ;; from the shorten_branches reference address. Long-branch 6365 ;; sequences will replace this one, so the minimum length 6366 ;; is one instruction shorter than for conditional branches. 6367 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 2046)) 6368 (le (minus (pc) (match_dup 0)) (const_int 2046))) 6369 (const_int 2) 6370 (and (le (minus (match_dup 0) (pc)) (const_int 65534)) 6371 (le (minus (pc) (match_dup 0)) (const_int 65532))) 6372 (const_int 4) 6373 (and (match_test "TARGET_ABICALLS") 6374 (not (match_test "TARGET_ABSOLUTE_ABICALLS"))) 6375 (const_int 18) 6376 (match_test "Pmode == SImode") 6377 (const_int 14) 6378 ] (const_int 22)))]) 6379 6380(define_expand "indirect_jump" 6381 [(set (pc) (match_operand 0 "register_operand"))] 6382 "" 6383{ 6384 operands[0] = force_reg (Pmode, operands[0]); 6385 emit_jump_insn (PMODE_INSN (gen_indirect_jump, (operands[0]))); 6386 DONE; 6387}) 6388 6389(define_insn "indirect_jump_<mode>" 6390 [(set (pc) (match_operand:P 0 "register_operand" "d"))] 6391 "" 6392 { 6393 return mips_output_jump (operands, 0, -1, false); 6394 } 6395 [(set_attr "type" "jump") 6396 (set_attr "mode" "none")]) 6397 6398;; A combined jump-and-move instruction, used for MIPS16 long-branch 6399;; sequences. Having a dedicated pattern is more convenient than 6400;; creating a SEQUENCE for this special case. 6401(define_insn "indirect_jump_and_restore_<mode>" 6402 [(set (pc) (match_operand:P 1 "register_operand" "d")) 6403 (set (match_operand:P 0 "register_operand" "=d") 6404 (match_operand:P 2 "register_operand" "y"))] 6405 "" 6406 "%(%<jr\t%1\;move\t%0,%2%>%)" 6407 [(set_attr "type" "multi") 6408 (set_attr "extended_mips16" "yes")]) 6409 6410(define_expand "tablejump" 6411 [(set (pc) 6412 (match_operand 0 "register_operand")) 6413 (use (label_ref (match_operand 1 "")))] 6414 "!TARGET_MIPS16_SHORT_JUMP_TABLES" 6415{ 6416 if (TARGET_GPWORD) 6417 operands[0] = expand_binop (Pmode, add_optab, operands[0], 6418 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN); 6419 else if (TARGET_RTP_PIC) 6420 { 6421 /* When generating RTP PIC, we use case table entries that are relative 6422 to the start of the function. Add the function's address to the 6423 value we loaded. */ 6424 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM); 6425 operands[0] = expand_binop (ptr_mode, add_optab, operands[0], 6426 start, 0, 0, OPTAB_WIDEN); 6427 } 6428 6429 emit_jump_insn (PMODE_INSN (gen_tablejump, (operands[0], operands[1]))); 6430 DONE; 6431}) 6432 6433(define_insn "tablejump_<mode>" 6434 [(set (pc) 6435 (match_operand:P 0 "register_operand" "d")) 6436 (use (label_ref (match_operand 1 "" "")))] 6437 "" 6438 { 6439 return mips_output_jump (operands, 0, -1, false); 6440 } 6441 [(set_attr "type" "jump") 6442 (set_attr "mode" "none")]) 6443 6444;; For MIPS16, we don't know whether a given jump table will use short or 6445;; word-sized offsets until late in compilation, when we are able to determine 6446;; the sizes of the insns which comprise the containing function. This 6447;; necessitates the use of the casesi rather than the tablejump pattern, since 6448;; the latter tries to calculate the index of the offset to jump through early 6449;; in compilation, i.e. at expand time, when nothing is known about the 6450;; eventual function layout. 6451 6452(define_expand "casesi" 6453 [(match_operand:SI 0 "register_operand" "") ; index to jump on 6454 (match_operand:SI 1 "const_int_operand" "") ; lower bound 6455 (match_operand:SI 2 "const_int_operand" "") ; total range 6456 (match_operand 3 "" "") ; table label 6457 (match_operand 4 "" "")] ; out of range label 6458 "TARGET_MIPS16_SHORT_JUMP_TABLES" 6459{ 6460 if (operands[1] != const0_rtx) 6461 { 6462 rtx reg = gen_reg_rtx (SImode); 6463 rtx offset = gen_int_mode (-INTVAL (operands[1]), SImode); 6464 6465 if (!arith_operand (offset, SImode)) 6466 offset = force_reg (SImode, offset); 6467 6468 emit_insn (gen_addsi3 (reg, operands[0], offset)); 6469 operands[0] = reg; 6470 } 6471 6472 if (!arith_operand (operands[0], SImode)) 6473 operands[0] = force_reg (SImode, operands[0]); 6474 6475 emit_cmp_and_jump_insns (operands[0], operands[2], GTU, 6476 NULL_RTX, SImode, 1, operands[4]); 6477 emit_jump_insn (PMODE_INSN (gen_casesi_internal_mips16, 6478 (operands[0], operands[3]))); 6479 DONE; 6480}) 6481 6482(define_insn "casesi_internal_mips16_<mode>" 6483 [(set (pc) 6484 (unspec:P [(match_operand:SI 0 "register_operand" "d") 6485 (label_ref (match_operand 1 "" ""))] 6486 UNSPEC_CASESI_DISPATCH)) 6487 (clobber (match_scratch:P 2 "=d")) 6488 (clobber (match_scratch:P 3 "=d"))] 6489 "TARGET_MIPS16_SHORT_JUMP_TABLES" 6490{ 6491 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1]))); 6492 6493 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); 6494 6495 switch (GET_MODE (diff_vec)) 6496 { 6497 case E_HImode: 6498 output_asm_insn ("sll\t%3,%0,1", operands); 6499 output_asm_insn ("<d>la\t%2,%1", operands); 6500 output_asm_insn ("<d>addu\t%3,%2,%3", operands); 6501 output_asm_insn ("lh\t%3,0(%3)", operands); 6502 break; 6503 6504 case E_SImode: 6505 output_asm_insn ("sll\t%3,%0,2", operands); 6506 output_asm_insn ("<d>la\t%2,%1", operands); 6507 output_asm_insn ("<d>addu\t%3,%2,%3", operands); 6508 output_asm_insn ("lw\t%3,0(%3)", operands); 6509 break; 6510 6511 default: 6512 gcc_unreachable (); 6513 } 6514 6515 output_asm_insn ("<d>addu\t%2,%2,%3", operands); 6516 6517 if (GENERATE_MIPS16E) 6518 return "jrc\t%2"; 6519 else 6520 return "jr\t%2"; 6521} 6522 [(set (attr "insn_count") 6523 (if_then_else (match_test "GENERATE_MIPS16E") 6524 (const_string "6") 6525 (const_string "7")))]) 6526 6527;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well. 6528;; While it is possible to either pull it off the stack (in the 6529;; o32 case) or recalculate it given t9 and our target label, 6530;; it takes 3 or 4 insns to do so. 6531 6532(define_expand "builtin_setjmp_setup" 6533 [(use (match_operand 0 "register_operand"))] 6534 "TARGET_USE_GOT" 6535{ 6536 rtx addr; 6537 6538 addr = plus_constant (Pmode, operands[0], GET_MODE_SIZE (Pmode) * 3); 6539 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx); 6540 DONE; 6541}) 6542 6543;; Restore the gp that we saved above. Despite the earlier comment, it seems 6544;; that older code did recalculate the gp from $25. Continue to jump through 6545;; $25 for compatibility (we lose nothing by doing so). 6546 6547(define_expand "builtin_longjmp" 6548 [(use (match_operand 0 "register_operand"))] 6549 "TARGET_USE_GOT" 6550{ 6551 /* The elements of the buffer are, in order: */ 6552 int W = GET_MODE_SIZE (Pmode); 6553 rtx fp = gen_rtx_MEM (Pmode, operands[0]); 6554 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 1*W)); 6555 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 2*W)); 6556 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 3*W)); 6557 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); 6558 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx. 6559 The target is bound to be using $28 as the global pointer 6560 but the current function might not be. */ 6561 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM); 6562 6563 /* This bit is similar to expand_builtin_longjmp except that it 6564 restores $gp as well. */ 6565 mips_emit_move (hard_frame_pointer_rtx, fp); 6566 mips_emit_move (pv, lab); 6567 emit_stack_restore (SAVE_NONLOCAL, stack); 6568 mips_emit_move (gp, gpv); 6569 emit_use (hard_frame_pointer_rtx); 6570 emit_use (stack_pointer_rtx); 6571 emit_use (gp); 6572 emit_indirect_jump (pv); 6573 DONE; 6574}) 6575 6576;; 6577;; .................... 6578;; 6579;; Function prologue/epilogue 6580;; 6581;; .................... 6582;; 6583 6584(define_expand "prologue" 6585 [(const_int 1)] 6586 "" 6587{ 6588 mips_expand_prologue (); 6589 DONE; 6590}) 6591 6592;; Block any insns from being moved before this point, since the 6593;; profiling call to mcount can use various registers that aren't 6594;; saved or used to pass arguments. 6595 6596(define_insn "blockage" 6597 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)] 6598 "" 6599 "" 6600 [(set_attr "type" "ghost") 6601 (set_attr "mode" "none")]) 6602 6603(define_insn "probe_stack_range_<P:mode>" 6604 [(set (match_operand:P 0 "register_operand" "=d") 6605 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0") 6606 (match_operand:P 2 "register_operand" "d")] 6607 UNSPEC_PROBE_STACK_RANGE))] 6608 "" 6609 { return mips_output_probe_stack_range (operands[0], operands[2]); } 6610 [(set_attr "type" "unknown") 6611 (set_attr "can_delay" "no") 6612 (set_attr "mode" "<MODE>")]) 6613 6614(define_expand "epilogue" 6615 [(const_int 2)] 6616 "" 6617{ 6618 mips_expand_epilogue (false); 6619 DONE; 6620}) 6621 6622(define_expand "sibcall_epilogue" 6623 [(const_int 2)] 6624 "" 6625{ 6626 mips_expand_epilogue (true); 6627 DONE; 6628}) 6629 6630;; Trivial return. Make it look like a normal return insn as that 6631;; allows jump optimizations to work better. 6632 6633(define_expand "return" 6634 [(simple_return)] 6635 "mips_can_use_return_insn ()" 6636 { mips_expand_before_return (); }) 6637 6638(define_expand "simple_return" 6639 [(simple_return)] 6640 "" 6641 { mips_expand_before_return (); }) 6642 6643(define_insn "*<optab>" 6644 [(any_return)] 6645 "" 6646 { 6647 operands[0] = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); 6648 return mips_output_jump (operands, 0, -1, false); 6649 } 6650 [(set_attr "type" "jump") 6651 (set_attr "mode" "none")]) 6652 6653;; Normal return. 6654 6655(define_insn "<optab>_internal" 6656 [(any_return) 6657 (use (match_operand 0 "pmode_register_operand" ""))] 6658 "" 6659 { 6660 return mips_output_jump (operands, 0, -1, false); 6661 } 6662 [(set_attr "type" "jump") 6663 (set_attr "mode" "none")]) 6664 6665;; Exception return. 6666(define_insn "mips_eret" 6667 [(return) 6668 (unspec_volatile [(const_int 0)] UNSPEC_ERET)] 6669 "" 6670 "eret" 6671 [(set_attr "type" "trap") 6672 (set_attr "mode" "none")]) 6673 6674;; Debug exception return. 6675(define_insn "mips_deret" 6676 [(return) 6677 (unspec_volatile [(const_int 0)] UNSPEC_DERET)] 6678 "" 6679 "deret" 6680 [(set_attr "type" "trap") 6681 (set_attr "mode" "none")]) 6682 6683;; Disable interrupts. 6684(define_insn "mips_di" 6685 [(unspec_volatile [(const_int 0)] UNSPEC_DI)] 6686 "" 6687 "di" 6688 [(set_attr "type" "trap") 6689 (set_attr "mode" "none")]) 6690 6691;; Execution hazard barrier. 6692(define_insn "mips_ehb" 6693 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)] 6694 "" 6695 "ehb" 6696 [(set_attr "type" "trap") 6697 (set_attr "mode" "none")]) 6698 6699;; Read GPR from previous shadow register set. 6700(define_insn "mips_rdpgpr_<mode>" 6701 [(set (match_operand:P 0 "register_operand" "=d") 6702 (unspec_volatile:P [(match_operand:P 1 "register_operand" "d")] 6703 UNSPEC_RDPGPR))] 6704 "" 6705 "rdpgpr\t%0,%1" 6706 [(set_attr "type" "move") 6707 (set_attr "mode" "<MODE>")]) 6708 6709;; Move involving COP0 registers. 6710(define_insn "cop0_move" 6711 [(set (match_operand:SI 0 "register_operand" "=B,d") 6712 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")] 6713 UNSPEC_COP0))] 6714 "" 6715{ return mips_output_move (operands[0], operands[1]); } 6716 [(set_attr "type" "mtc,mfc") 6717 (set_attr "mode" "SI")]) 6718 6719;; This is used in compiling the unwind routines. 6720(define_expand "eh_return" 6721 [(use (match_operand 0 "general_operand"))] 6722 "" 6723{ 6724 if (GET_MODE (operands[0]) != word_mode) 6725 operands[0] = convert_to_mode (word_mode, operands[0], 0); 6726 if (TARGET_64BIT) 6727 emit_insn (gen_eh_set_lr_di (operands[0])); 6728 else 6729 emit_insn (gen_eh_set_lr_si (operands[0])); 6730 DONE; 6731}) 6732 6733;; Clobber the return address on the stack. We can't expand this 6734;; until we know where it will be put in the stack frame. 6735 6736(define_insn "eh_set_lr_si" 6737 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN) 6738 (clobber (match_scratch:SI 1 "=&d"))] 6739 "! TARGET_64BIT" 6740 "#") 6741 6742(define_insn "eh_set_lr_di" 6743 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN) 6744 (clobber (match_scratch:DI 1 "=&d"))] 6745 "TARGET_64BIT" 6746 "#") 6747 6748(define_split 6749 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN) 6750 (clobber (match_scratch 1))] 6751 "reload_completed" 6752 [(const_int 0)] 6753{ 6754 mips_set_return_address (operands[0], operands[1]); 6755 DONE; 6756}) 6757 6758(define_expand "exception_receiver" 6759 [(const_int 0)] 6760 "TARGET_USE_GOT" 6761{ 6762 /* See the comment above load_call<mode> for details. */ 6763 emit_insn (gen_set_got_version ()); 6764 6765 /* If we have a call-clobbered $gp, restore it from its save slot. */ 6766 if (HAVE_restore_gp_si) 6767 emit_insn (gen_restore_gp_si ()); 6768 else if (HAVE_restore_gp_di) 6769 emit_insn (gen_restore_gp_di ()); 6770 DONE; 6771}) 6772 6773(define_expand "nonlocal_goto_receiver" 6774 [(const_int 0)] 6775 "TARGET_USE_GOT" 6776{ 6777 /* See the comment above load_call<mode> for details. */ 6778 emit_insn (gen_set_got_version ()); 6779 DONE; 6780}) 6781 6782;; Restore $gp from its .cprestore stack slot. The instruction remains 6783;; volatile until all uses of $28 are exposed. 6784(define_insn_and_split "restore_gp_<mode>" 6785 [(set (reg:P 28) 6786 (unspec_volatile:P [(const_int 0)] UNSPEC_RESTORE_GP)) 6787 (clobber (match_scratch:P 0 "=&d"))] 6788 "TARGET_CALL_CLOBBERED_GP" 6789 "#" 6790 "&& epilogue_completed" 6791 [(const_int 0)] 6792{ 6793 mips_restore_gp_from_cprestore_slot (operands[0]); 6794 DONE; 6795} 6796 [(set_attr "type" "ghost")]) 6797 6798;; Move between $gp and its register save slot. 6799(define_insn_and_split "move_gp<mode>" 6800 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,m") 6801 (unspec:GPR [(match_operand:GPR 1 "move_operand" "m,d")] 6802 UNSPEC_MOVE_GP))] 6803 "" 6804 { return mips_must_initialize_gp_p () ? "#" : ""; } 6805 "mips_must_initialize_gp_p ()" 6806 [(const_int 0)] 6807{ 6808 mips_emit_move (operands[0], operands[1]); 6809 DONE; 6810} 6811 [(set_attr "type" "ghost")]) 6812 6813;; 6814;; .................... 6815;; 6816;; FUNCTION CALLS 6817;; 6818;; .................... 6819 6820;; Instructions to load a call address from the GOT. The address might 6821;; point to a function or to a lazy binding stub. In the latter case, 6822;; the stub will use the dynamic linker to resolve the function, which 6823;; in turn will change the GOT entry to point to the function's real 6824;; address. 6825;; 6826;; This means that every call, even pure and constant ones, can 6827;; potentially modify the GOT entry. And once a stub has been called, 6828;; we must not call it again. 6829;; 6830;; We represent this restriction using an imaginary, fixed, call-saved 6831;; register called GOT_VERSION_REGNUM. The idea is to make the register 6832;; live throughout the function and to change its value after every 6833;; potential call site. This stops any rtx value that uses the register 6834;; from being computed before an earlier call. To do this, we: 6835;; 6836;; - Ensure that the register is live on entry to the function, 6837;; so that it is never thought to be used uninitalized. 6838;; 6839;; - Ensure that the register is live on exit from the function, 6840;; so that it is live throughout. 6841;; 6842;; - Make each call (lazily-bound or not) use the current value 6843;; of GOT_VERSION_REGNUM, so that updates of the register are 6844;; not moved across call boundaries. 6845;; 6846;; - Add "ghost" definitions of the register to the beginning of 6847;; blocks reached by EH and ABNORMAL_CALL edges, because those 6848;; edges may involve calls that normal paths don't. (E.g. the 6849;; unwinding code that handles a non-call exception may change 6850;; lazily-bound GOT entries.) We do this by making the 6851;; exception_receiver and nonlocal_goto_receiver expanders emit 6852;; a set_got_version instruction. 6853;; 6854;; - After each call (lazily-bound or not), use a "ghost" 6855;; update_got_version instruction to change the register's value. 6856;; This instruction mimics the _possible_ effect of the dynamic 6857;; resolver during the call and it remains live even if the call 6858;; itself becomes dead. 6859;; 6860;; - Leave GOT_VERSION_REGNUM out of all register classes. 6861;; The register is therefore not a valid register_operand 6862;; and cannot be moved to or from other registers. 6863 6864(define_insn "load_call<mode>" 6865 [(set (match_operand:P 0 "register_operand" "=d") 6866 (unspec:P [(match_operand:P 1 "register_operand" "d") 6867 (match_operand:P 2 "immediate_operand" "") 6868 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))] 6869 "TARGET_USE_GOT" 6870 "<load>\t%0,%R2(%1)" 6871 [(set_attr "got" "load") 6872 (set_attr "mode" "<MODE>")]) 6873 6874(define_insn "set_got_version" 6875 [(set (reg:SI GOT_VERSION_REGNUM) 6876 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))] 6877 "TARGET_USE_GOT" 6878 "" 6879 [(set_attr "type" "ghost")]) 6880 6881(define_insn "update_got_version" 6882 [(set (reg:SI GOT_VERSION_REGNUM) 6883 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))] 6884 "TARGET_USE_GOT" 6885 "" 6886 [(set_attr "type" "ghost")]) 6887 6888;; Sibling calls. All these patterns use jump instructions. 6889 6890;; If TARGET_SIBCALLS, call_insn_operand will only accept constant 6891;; addresses if a direct jump is acceptable. Since the 'S' constraint 6892;; is defined in terms of call_insn_operand, the same is true of the 6893;; constraints. 6894 6895;; When we use an indirect jump, we need a register that will be 6896;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces 6897;; us to use $25 for this purpose -- and $25 is never clobbered by the 6898;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG 6899;; as well. 6900 6901(define_expand "sibcall" 6902 [(parallel [(call (match_operand 0 "") 6903 (match_operand 1 "")) 6904 (use (match_operand 2 "")) ;; next_arg_reg 6905 (use (match_operand 3 ""))])] ;; struct_value_size_rtx 6906 "TARGET_SIBCALLS" 6907{ 6908 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0), 6909 operands[1], operands[2], false); 6910 DONE; 6911}) 6912 6913(define_insn "sibcall_internal" 6914 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S")) 6915 (match_operand 1 "" ""))] 6916 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)" 6917 { return mips_output_jump (operands, 0, 1, false); } 6918 [(set_attr "jal" "indirect,direct") 6919 (set_attr "jal_macro" "no")]) 6920 6921(define_expand "sibcall_value" 6922 [(parallel [(set (match_operand 0 "") 6923 (call (match_operand 1 "") 6924 (match_operand 2 ""))) 6925 (use (match_operand 3 ""))])] ;; next_arg_reg 6926 "TARGET_SIBCALLS" 6927{ 6928 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0), 6929 operands[2], operands[3], false); 6930 DONE; 6931}) 6932 6933(define_insn "sibcall_value_internal" 6934 [(set (match_operand 0 "register_operand" "") 6935 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S")) 6936 (match_operand 2 "" "")))] 6937 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)" 6938 { return mips_output_jump (operands, 1, 2, false); } 6939 [(set_attr "jal" "indirect,direct") 6940 (set_attr "jal_macro" "no")]) 6941 6942(define_insn "sibcall_value_multiple_internal" 6943 [(set (match_operand 0 "register_operand" "") 6944 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S")) 6945 (match_operand 2 "" ""))) 6946 (set (match_operand 3 "register_operand" "") 6947 (call (mem:SI (match_dup 1)) 6948 (match_dup 2)))] 6949 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)" 6950 { return mips_output_jump (operands, 1, 2, false); } 6951 [(set_attr "jal" "indirect,direct") 6952 (set_attr "jal_macro" "no")]) 6953 6954(define_expand "call" 6955 [(parallel [(call (match_operand 0 "") 6956 (match_operand 1 "")) 6957 (use (match_operand 2 "")) ;; next_arg_reg 6958 (use (match_operand 3 ""))])] ;; struct_value_size_rtx 6959 "" 6960{ 6961 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0), 6962 operands[1], operands[2], false); 6963 DONE; 6964}) 6965 6966;; This instruction directly corresponds to an assembly-language "jal". 6967;; There are four cases: 6968;; 6969;; - -mno-abicalls: 6970;; Both symbolic and register destinations are OK. The pattern 6971;; always expands to a single mips instruction. 6972;; 6973;; - -mabicalls/-mno-explicit-relocs: 6974;; Again, both symbolic and register destinations are OK. 6975;; The call is treated as a multi-instruction black box. 6976;; 6977;; - -mabicalls/-mexplicit-relocs with n32 or n64: 6978;; Only "jal $25" is allowed. This expands to a single "jalr $25" 6979;; instruction. 6980;; 6981;; - -mabicalls/-mexplicit-relocs with o32 or o64: 6982;; Only "jal $25" is allowed. The call is actually two instructions: 6983;; "jalr $25" followed by an insn to reload $gp. 6984;; 6985;; In the last case, we can generate the individual instructions with 6986;; a define_split. There are several things to be wary of: 6987;; 6988;; - We can't expose the load of $gp before reload. If we did, 6989;; it might get removed as dead, but reload can introduce new 6990;; uses of $gp by rematerializing constants. 6991;; 6992;; - We shouldn't restore $gp after calls that never return. 6993;; It isn't valid to insert instructions between a noreturn 6994;; call and the following barrier. 6995;; 6996;; - The splitter deliberately changes the liveness of $gp. The unsplit 6997;; instruction preserves $gp and so have no effect on its liveness. 6998;; But once we generate the separate insns, it becomes obvious that 6999;; $gp is not live on entry to the call. 7000;; 7001(define_insn_and_split "call_internal" 7002 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S")) 7003 (match_operand 1 "" "")) 7004 (clobber (reg:SI RETURN_ADDR_REGNUM))] 7005 "" 7006 { 7007 return (TARGET_SPLIT_CALLS ? "#" 7008 : mips_output_jump (operands, 0, 1, true)); 7009 } 7010 "reload_completed && TARGET_SPLIT_CALLS" 7011 [(const_int 0)] 7012{ 7013 mips_split_call (curr_insn, gen_call_split (operands[0], operands[1])); 7014 DONE; 7015} 7016 [(set_attr "jal" "indirect,direct")]) 7017 7018(define_insn "call_split" 7019 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S")) 7020 (match_operand 1 "" "")) 7021 (clobber (reg:SI RETURN_ADDR_REGNUM)) 7022 (clobber (reg:SI 28))] 7023 "TARGET_SPLIT_CALLS" 7024 { return mips_output_jump (operands, 0, 1, true); } 7025 [(set_attr "jal" "indirect,direct") 7026 (set_attr "jal_macro" "no")]) 7027 7028;; A pattern for calls that must be made directly. It is used for 7029;; MIPS16 calls that the linker may need to redirect to a hard-float 7030;; stub; the linker relies on the call relocation type to detect when 7031;; such redirection is needed. 7032(define_insn_and_split "call_internal_direct" 7033 [(call (mem:SI (match_operand 0 "const_call_insn_operand")) 7034 (match_operand 1)) 7035 (const_int 1) 7036 (clobber (reg:SI RETURN_ADDR_REGNUM))] 7037 "" 7038 { 7039 return (TARGET_SPLIT_CALLS ? "#" 7040 : mips_output_jump (operands, 0, -1, true)); 7041 } 7042 "reload_completed && TARGET_SPLIT_CALLS" 7043 [(const_int 0)] 7044{ 7045 mips_split_call (curr_insn, 7046 gen_call_direct_split (operands[0], operands[1])); 7047 DONE; 7048} 7049 [(set_attr "jal" "direct")]) 7050 7051(define_insn "call_direct_split" 7052 [(call (mem:SI (match_operand 0 "const_call_insn_operand")) 7053 (match_operand 1)) 7054 (const_int 1) 7055 (clobber (reg:SI RETURN_ADDR_REGNUM)) 7056 (clobber (reg:SI 28))] 7057 "TARGET_SPLIT_CALLS" 7058 { return mips_output_jump (operands, 0, -1, true); } 7059 [(set_attr "jal" "direct") 7060 (set_attr "jal_macro" "no")]) 7061 7062(define_expand "call_value" 7063 [(parallel [(set (match_operand 0 "") 7064 (call (match_operand 1 "") 7065 (match_operand 2 ""))) 7066 (use (match_operand 3 ""))])] ;; next_arg_reg 7067 "" 7068{ 7069 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0), 7070 operands[2], operands[3], false); 7071 DONE; 7072}) 7073 7074;; See comment for call_internal. 7075(define_insn_and_split "call_value_internal" 7076 [(set (match_operand 0 "register_operand" "") 7077 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 7078 (match_operand 2 "" ""))) 7079 (clobber (reg:SI RETURN_ADDR_REGNUM))] 7080 "" 7081 { 7082 return (TARGET_SPLIT_CALLS ? "#" 7083 : mips_output_jump (operands, 1, 2, true)); 7084 } 7085 "reload_completed && TARGET_SPLIT_CALLS" 7086 [(const_int 0)] 7087{ 7088 mips_split_call (curr_insn, 7089 gen_call_value_split (operands[0], operands[1], 7090 operands[2])); 7091 DONE; 7092} 7093 [(set_attr "jal" "indirect,direct")]) 7094 7095(define_insn "call_value_split" 7096 [(set (match_operand 0 "register_operand" "") 7097 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 7098 (match_operand 2 "" ""))) 7099 (clobber (reg:SI RETURN_ADDR_REGNUM)) 7100 (clobber (reg:SI 28))] 7101 "TARGET_SPLIT_CALLS" 7102 { return mips_output_jump (operands, 1, 2, true); } 7103 [(set_attr "jal" "indirect,direct") 7104 (set_attr "jal_macro" "no")]) 7105 7106;; See call_internal_direct. 7107(define_insn_and_split "call_value_internal_direct" 7108 [(set (match_operand 0 "register_operand") 7109 (call (mem:SI (match_operand 1 "const_call_insn_operand")) 7110 (match_operand 2))) 7111 (const_int 1) 7112 (clobber (reg:SI RETURN_ADDR_REGNUM))] 7113 "" 7114 { 7115 return (TARGET_SPLIT_CALLS ? "#" 7116 : mips_output_jump (operands, 1, -1, true)); 7117 } 7118 "reload_completed && TARGET_SPLIT_CALLS" 7119 [(const_int 0)] 7120{ 7121 mips_split_call (curr_insn, 7122 gen_call_value_direct_split (operands[0], operands[1], 7123 operands[2])); 7124 DONE; 7125} 7126 [(set_attr "jal" "direct")]) 7127 7128(define_insn "call_value_direct_split" 7129 [(set (match_operand 0 "register_operand") 7130 (call (mem:SI (match_operand 1 "const_call_insn_operand")) 7131 (match_operand 2))) 7132 (const_int 1) 7133 (clobber (reg:SI RETURN_ADDR_REGNUM)) 7134 (clobber (reg:SI 28))] 7135 "TARGET_SPLIT_CALLS" 7136 { return mips_output_jump (operands, 1, -1, true); } 7137 [(set_attr "jal" "direct") 7138 (set_attr "jal_macro" "no")]) 7139 7140;; See comment for call_internal. 7141(define_insn_and_split "call_value_multiple_internal" 7142 [(set (match_operand 0 "register_operand" "") 7143 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 7144 (match_operand 2 "" ""))) 7145 (set (match_operand 3 "register_operand" "") 7146 (call (mem:SI (match_dup 1)) 7147 (match_dup 2))) 7148 (clobber (reg:SI RETURN_ADDR_REGNUM))] 7149 "" 7150 { 7151 return (TARGET_SPLIT_CALLS ? "#" 7152 : mips_output_jump (operands, 1, 2, true)); 7153 } 7154 "reload_completed && TARGET_SPLIT_CALLS" 7155 [(const_int 0)] 7156{ 7157 mips_split_call (curr_insn, 7158 gen_call_value_multiple_split (operands[0], operands[1], 7159 operands[2], operands[3])); 7160 DONE; 7161} 7162 [(set_attr "jal" "indirect,direct")]) 7163 7164(define_insn "call_value_multiple_split" 7165 [(set (match_operand 0 "register_operand" "") 7166 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 7167 (match_operand 2 "" ""))) 7168 (set (match_operand 3 "register_operand" "") 7169 (call (mem:SI (match_dup 1)) 7170 (match_dup 2))) 7171 (clobber (reg:SI RETURN_ADDR_REGNUM)) 7172 (clobber (reg:SI 28))] 7173 "TARGET_SPLIT_CALLS" 7174 { return mips_output_jump (operands, 1, 2, true); } 7175 [(set_attr "jal" "indirect,direct") 7176 (set_attr "jal_macro" "no")]) 7177 7178;; Call subroutine returning any type. 7179 7180(define_expand "untyped_call" 7181 [(parallel [(call (match_operand 0 "") 7182 (const_int 0)) 7183 (match_operand 1 "") 7184 (match_operand 2 "")])] 7185 "" 7186{ 7187 int i; 7188 7189 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 7190 7191 for (i = 0; i < XVECLEN (operands[2], 0); i++) 7192 { 7193 rtx set = XVECEXP (operands[2], 0, i); 7194 mips_emit_move (SET_DEST (set), SET_SRC (set)); 7195 } 7196 7197 emit_insn (gen_blockage ()); 7198 DONE; 7199}) 7200 7201;; 7202;; .................... 7203;; 7204;; MISC. 7205;; 7206;; .................... 7207;; 7208 7209 7210(define_insn "prefetch" 7211 [(prefetch (match_operand:QI 0 "address_operand" "ZD") 7212 (match_operand 1 "const_int_operand" "n") 7213 (match_operand 2 "const_int_operand" "n"))] 7214 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS" 7215{ 7216 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT) 7217 { 7218 /* Loongson 2[ef] and Loongson ext use load to $0 for prefetching. */ 7219 if (TARGET_64BIT) 7220 return "ld\t$0,%a0"; 7221 else 7222 return "lw\t$0,%a0"; 7223 } 7224 /* Loongson ext2 implementation pref instructions. */ 7225 if (TARGET_LOONGSON_EXT2) 7226 { 7227 operands[1] = mips_loongson_ext2_prefetch_cookie (operands[1], 7228 operands[2]); 7229 return "pref\t%1, %a0"; 7230 } 7231 operands[1] = mips_prefetch_cookie (operands[1], operands[2]); 7232 return "pref\t%1,%a0"; 7233} 7234 [(set_attr "type" "prefetch")]) 7235 7236(define_insn "*prefetch_indexed_<mode>" 7237 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d") 7238 (match_operand:P 1 "register_operand" "d")) 7239 (match_operand 2 "const_int_operand" "n") 7240 (match_operand 3 "const_int_operand" "n"))] 7241 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 7242{ 7243 if (TARGET_LOONGSON_EXT) 7244 { 7245 /* Loongson Loongson ext use index load to $0 for prefetching. */ 7246 if (TARGET_64BIT) 7247 return "gsldx\t$0,0(%0,%1)"; 7248 else 7249 return "gslwx\t$0,0(%0,%1)"; 7250 } 7251 /* Loongson ext2 implementation pref instructions. */ 7252 if (TARGET_LOONGSON_EXT2) 7253 { 7254 operands[2] = mips_loongson_ext2_prefetch_cookie (operands[2], 7255 operands[3]); 7256 return "prefx\t%2,%1(%0)"; 7257 } 7258 operands[2] = mips_prefetch_cookie (operands[2], operands[3]); 7259 return "prefx\t%2,%1(%0)"; 7260} 7261 [(set_attr "type" "prefetchx")]) 7262 7263(define_insn "nop" 7264 [(const_int 0)] 7265 "" 7266 "%(nop%)" 7267 [(set_attr "type" "nop") 7268 (set_attr "mode" "none")]) 7269 7270;; Like nop, but commented out when outside a .set noreorder block. 7271(define_insn "hazard_nop" 7272 [(const_int 1)] 7273 "" 7274 { 7275 if (mips_noreorder.nesting_level > 0) 7276 return "nop"; 7277 else 7278 return "#nop"; 7279 } 7280 [(set_attr "type" "nop")]) 7281 7282;; The `.insn' pseudo-op. 7283(define_insn "insn_pseudo" 7284 [(unspec_volatile [(const_int 0)] UNSPEC_INSN_PSEUDO)] 7285 "" 7286 ".insn" 7287 [(set_attr "mode" "none") 7288 (set_attr "insn_count" "0")]) 7289 7290;; MIPS4 Conditional move instructions. 7291 7292(define_insn "*mov<GPR:mode>_on_<MOVECC:mode>" 7293 [(set (match_operand:GPR 0 "register_operand" "=d,d") 7294 (if_then_else:GPR 7295 (match_operator 4 "equality_operator" 7296 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>") 7297 (const_int 0)]) 7298 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") 7299 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))] 7300 "ISA_HAS_CONDMOVE" 7301 "@ 7302 mov%T4\t%0,%z2,%1 7303 mov%t4\t%0,%z3,%1" 7304 [(set_attr "type" "condmove") 7305 (set_attr "mode" "<GPR:MODE>")]) 7306 7307(define_insn "*mov<GPR:mode>_on_<GPR2:mode>_ne" 7308 [(set (match_operand:GPR 0 "register_operand" "=d,d") 7309 (if_then_else:GPR 7310 (match_operand:GPR2 1 "register_operand" "<GPR2:reg>,<GPR2:reg>") 7311 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") 7312 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))] 7313 "ISA_HAS_CONDMOVE" 7314 "@ 7315 movn\t%0,%z2,%1 7316 movz\t%0,%z3,%1" 7317 [(set_attr "type" "condmove") 7318 (set_attr "mode" "<GPR:MODE>")]) 7319 7320(define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>" 7321 [(set (match_operand:SCALARF 0 "register_operand" "=f,f") 7322 (if_then_else:SCALARF 7323 (match_operator 4 "equality_operator" 7324 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>") 7325 (const_int 0)]) 7326 (match_operand:SCALARF 2 "register_operand" "f,0") 7327 (match_operand:SCALARF 3 "register_operand" "0,f")))] 7328 "ISA_HAS_FP_CONDMOVE" 7329 "@ 7330 mov%T4.<fmt>\t%0,%2,%1 7331 mov%t4.<fmt>\t%0,%3,%1" 7332 [(set_attr "type" "condmove") 7333 (set_attr "mode" "<SCALARF:MODE>")]) 7334 7335(define_insn "*sel<code><GPR:mode>_using_<GPR2:mode>" 7336 [(set (match_operand:GPR 0 "register_operand" "=d,d") 7337 (if_then_else:GPR 7338 (equality_op:GPR2 (match_operand:GPR2 1 "register_operand" "d,d") 7339 (const_int 0)) 7340 (match_operand:GPR 2 "reg_or_0_operand" "d,J") 7341 (match_operand:GPR 3 "reg_or_0_operand" "J,d")))] 7342 "ISA_HAS_SEL 7343 && (register_operand (operands[2], <GPR:MODE>mode) 7344 != register_operand (operands[3], <GPR:MODE>mode))" 7345 "@ 7346 <sel>\t%0,%2,%1 7347 <selinv>\t%0,%3,%1" 7348 [(set_attr "type" "condmove") 7349 (set_attr "mode" "<GPR:MODE>")]) 7350 7351;; sel.fmt copies the 3rd argument when the 1st is non-zero and the 2nd 7352;; argument if the 1st is zero. This means operand 2 and 3 are 7353;; inverted in the instruction. 7354 7355(define_insn "*sel<mode>" 7356 [(set (match_operand:SCALARF 0 "register_operand" "=f,f,f") 7357 (if_then_else:SCALARF 7358 (ne:CCF (match_operand:CCF 1 "register_operand" "0,f,f") 7359 (const_int 0)) 7360 (match_operand:SCALARF 2 "reg_or_0_operand" "f,G,f") 7361 (match_operand:SCALARF 3 "reg_or_0_operand" "f,f,G")))] 7362 "ISA_HAS_SEL && ISA_HAS_CCF" 7363 "@ 7364 sel.<fmt>\t%0,%3,%2 7365 seleqz.<fmt>\t%0,%3,%1 7366 selnez.<fmt>\t%0,%2,%1" 7367 [(set_attr "type" "condmove") 7368 (set_attr "mode" "<SCALARF:MODE>")]) 7369 7370;; These are the main define_expand's used to make conditional moves. 7371 7372(define_expand "mov<mode>cc" 7373 [(set (match_dup 4) (match_operand 1 "comparison_operator")) 7374 (set (match_operand:GPR 0 "register_operand") 7375 (if_then_else:GPR (match_dup 5) 7376 (match_operand:GPR 2 "reg_or_0_operand") 7377 (match_operand:GPR 3 "reg_or_0_operand")))] 7378 "ISA_HAS_CONDMOVE || ISA_HAS_SEL" 7379{ 7380 if (!ISA_HAS_FP_CONDMOVE 7381 && !INTEGRAL_MODE_P (GET_MODE (XEXP (operands[1], 0)))) 7382 FAIL; 7383 7384 mips_expand_conditional_move (operands); 7385 DONE; 7386}) 7387 7388(define_expand "mov<mode>cc" 7389 [(set (match_dup 4) (match_operand 1 "comparison_operator")) 7390 (set (match_operand:SCALARF 0 "register_operand") 7391 (if_then_else:SCALARF (match_dup 5) 7392 (match_operand:SCALARF 2 "reg_or_0_operand") 7393 (match_operand:SCALARF 3 "reg_or_0_operand")))] 7394 "ISA_HAS_FP_CONDMOVE 7395 || (ISA_HAS_SEL && ISA_HAS_CCF)" 7396{ 7397 if (ISA_HAS_SEL && !FLOAT_MODE_P (GET_MODE (XEXP (operands[1], 0)))) 7398 FAIL; 7399 7400 /* Workaround an LRA bug which means that tied operands in the sel.fmt 7401 pattern lead to the double precision destination of sel.d getting 7402 reloaded with the full register file usable and the restrictions on 7403 whether the CCFmode input can be used in odd-numbered single-precision 7404 registers are ignored. For consistency reasons the CCF mode values 7405 must be guaranteed to only exist in the even-registers because of 7406 the unusual duality between single and double precision values. */ 7407 if (ISA_HAS_SEL && <MODE>mode == DFmode 7408 && (!TARGET_ODD_SPREG || TARGET_FLOATXX)) 7409 FAIL; 7410 7411 mips_expand_conditional_move (operands); 7412 DONE; 7413}) 7414 7415;; 7416;; .................... 7417;; 7418;; mips16 inline constant tables 7419;; 7420;; .................... 7421;; 7422 7423(define_insn "consttable" 7424 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 7425 UNSPEC_CONSTTABLE)] 7426 "" 7427 "" 7428 [(set_attr "mode" "none") 7429 (set_attr "insn_count" "0")]) 7430 7431(define_insn "consttable_end" 7432 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 7433 UNSPEC_CONSTTABLE_END)] 7434 "" 7435 "" 7436 [(set_attr "mode" "none") 7437 (set_attr "insn_count" "0")]) 7438 7439(define_insn "consttable_tls_reloc" 7440 [(unspec_volatile [(match_operand 0 "tls_reloc_operand" "") 7441 (match_operand 1 "const_int_operand" "")] 7442 UNSPEC_CONSTTABLE_INT)] 7443 "TARGET_MIPS16_PCREL_LOADS" 7444 { return mips_output_tls_reloc_directive (&operands[0]); } 7445 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))]) 7446 7447(define_insn "consttable_int" 7448 [(unspec_volatile [(match_operand 0 "consttable_operand" "") 7449 (match_operand 1 "const_int_operand" "")] 7450 UNSPEC_CONSTTABLE_INT)] 7451 "TARGET_MIPS16" 7452{ 7453 assemble_integer (mips_strip_unspec_address (operands[0]), 7454 INTVAL (operands[1]), 7455 BITS_PER_UNIT * INTVAL (operands[1]), 1); 7456 return ""; 7457} 7458 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))]) 7459 7460(define_insn "consttable_float" 7461 [(unspec_volatile [(match_operand 0 "consttable_operand" "")] 7462 UNSPEC_CONSTTABLE_FLOAT)] 7463 "TARGET_MIPS16" 7464{ 7465 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE); 7466 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]), 7467 as_a <scalar_float_mode> (GET_MODE (operands[0])), 7468 GET_MODE_BITSIZE (GET_MODE (operands[0]))); 7469 return ""; 7470} 7471 [(set (attr "length") 7472 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))]) 7473 7474(define_insn "align" 7475 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)] 7476 "" 7477 ".align\t%0" 7478 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))]) 7479 7480(define_split 7481 [(match_operand 0 "small_data_pattern")] 7482 "reload_completed" 7483 [(match_dup 0)] 7484 { operands[0] = mips_rewrite_small_data (operands[0]); }) 7485 7486;; 7487;; .................... 7488;; 7489;; MIPS16e Save/Restore 7490;; 7491;; .................... 7492;; 7493 7494(define_insn "*mips16e_save_restore" 7495 [(match_parallel 0 "" 7496 [(set (match_operand:SI 1 "register_operand") 7497 (plus:SI (match_dup 1) 7498 (match_operand:SI 2 "const_int_operand")))])] 7499 "operands[1] == stack_pointer_rtx 7500 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)" 7501 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); } 7502 [(set_attr "type" "arith") 7503 (set_attr "extended_mips16" "yes")]) 7504 7505;; Thread-Local Storage 7506 7507;; The TLS base pointer is accessed via "rdhwr $3, $29". No current 7508;; MIPS architecture defines this register, and no current 7509;; implementation provides it; instead, any OS which supports TLS is 7510;; expected to trap and emulate this instruction. rdhwr is part of the 7511;; MIPS 32r2 specification, but we use it on any architecture because 7512;; we expect it to be emulated. Use .set to force the assembler to 7513;; accept it. 7514;; 7515;; We do not use a constraint to force the destination to be $3 7516;; because $3 can appear explicitly as a function return value. 7517;; If we leave the use of $3 implicit in the constraints until 7518;; reload, we may end up making a $3 return value live across 7519;; the instruction, leading to a spill failure when reloading it. 7520(define_insn_and_split "tls_get_tp_<mode>" 7521 [(set (match_operand:P 0 "register_operand" "=d") 7522 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP)) 7523 (clobber (reg:P TLS_GET_TP_REGNUM))] 7524 "HAVE_AS_TLS && !TARGET_MIPS16" 7525 "#" 7526 "&& reload_completed" 7527 [(set (reg:P TLS_GET_TP_REGNUM) 7528 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP)) 7529 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))] 7530 "" 7531 [(set_attr "type" "unknown") 7532 (set_attr "mode" "<MODE>") 7533 (set_attr "insn_count" "2")]) 7534 7535(define_insn "*tls_get_tp_<mode>_split" 7536 [(set (reg:P TLS_GET_TP_REGNUM) 7537 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))] 7538 "HAVE_AS_TLS && !TARGET_MIPS16" 7539 { 7540 if (mips_isa_rev >= 2) 7541 return "rdhwr\t$3,$29"; 7542 7543 return ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"; 7544 } 7545 [(set_attr "type" "unknown") 7546 ; Since rdhwr always generates a trap for now, putting it in a delay 7547 ; slot would make the kernel's emulation of it much slower. 7548 (set_attr "can_delay" "no") 7549 (set_attr "mode" "<MODE>")]) 7550 7551;; In MIPS16 mode, the TLS base pointer is accessed by a 7552;; libgcc helper function __mips16_rdhwr(), as 'rdhwr' is not 7553;; accessible in MIPS16. 7554;; 7555;; This is not represented as a call insn, to avoid the 7556;; unnecesarry clobbering of caller-save registers by a 7557;; function consisting only of: "rdhwr $3,$29; j $31; nop;" 7558;; 7559;; A $25 clobber is added to cater for a $25 load stub added by the 7560;; linker to __mips16_rdhwr when the call is made from non-PIC code. 7561 7562(define_insn_and_split "tls_get_tp_mips16_<mode>" 7563 [(set (match_operand:P 0 "register_operand" "=d") 7564 (unspec:P [(match_operand:P 1 "call_insn_operand" "dS")] 7565 UNSPEC_TLS_GET_TP)) 7566 (clobber (reg:P TLS_GET_TP_REGNUM)) 7567 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7568 (clobber (reg:P RETURN_ADDR_REGNUM))] 7569 "HAVE_AS_TLS && TARGET_MIPS16" 7570 "#" 7571 "&& reload_completed" 7572 [(parallel [(set (reg:P TLS_GET_TP_REGNUM) 7573 (unspec:P [(match_dup 1)] UNSPEC_TLS_GET_TP)) 7574 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7575 (clobber (reg:P RETURN_ADDR_REGNUM))]) 7576 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))] 7577 "" 7578 [(set_attr "type" "multi") 7579 (set_attr "insn_count" "4") 7580 (set_attr "mode" "<MODE>")]) 7581 7582(define_insn "*tls_get_tp_mips16_call_<mode>" 7583 [(set (reg:P TLS_GET_TP_REGNUM) 7584 (unspec:P [(match_operand:P 0 "call_insn_operand" "dS")] 7585 UNSPEC_TLS_GET_TP)) 7586 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7587 (clobber (reg:P RETURN_ADDR_REGNUM))] 7588 "HAVE_AS_TLS && TARGET_MIPS16" 7589 { return mips_output_jump (operands, 0, -1, true); } 7590 [(set_attr "type" "call") 7591 (set_attr "insn_count" "3") 7592 (set_attr "mode" "<MODE>")]) 7593 7594;; Named pattern for expanding thread pointer reference. 7595(define_expand "get_thread_pointer<mode>" 7596 [(match_operand:P 0 "register_operand" "=d")] 7597 "HAVE_AS_TLS" 7598{ 7599 mips_expand_thread_pointer (operands[0]); 7600 DONE; 7601}) 7602 7603;; __builtin_mips_get_fcsr: move the FCSR into operand 0. 7604(define_expand "mips_get_fcsr" 7605 [(set (match_operand:SI 0 "register_operand") 7606 (unspec_volatile:SI [(const_int 0)] UNSPEC_GET_FCSR))] 7607 "TARGET_HARD_FLOAT_ABI" 7608{ 7609 if (TARGET_MIPS16) 7610 { 7611 mips16_expand_get_fcsr (operands[0]); 7612 DONE; 7613 } 7614}) 7615 7616(define_insn "*mips_get_fcsr" 7617 [(set (match_operand:SI 0 "register_operand" "=d") 7618 (unspec_volatile:SI [(const_int 0)] UNSPEC_GET_FCSR))] 7619 "TARGET_HARD_FLOAT" 7620 "cfc1\t%0,$31") 7621 7622;; See tls_get_tp_mips16_<mode> for why this form is used. 7623(define_insn "mips_get_fcsr_mips16_<mode>" 7624 [(set (reg:SI GET_FCSR_REGNUM) 7625 (unspec:SI [(match_operand:P 0 "call_insn_operand" "dS")] 7626 UNSPEC_GET_FCSR)) 7627 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7628 (clobber (reg:P RETURN_ADDR_REGNUM))] 7629 "TARGET_HARD_FLOAT_ABI && TARGET_MIPS16" 7630 { return mips_output_jump (operands, 0, -1, true); } 7631 [(set_attr "type" "call") 7632 (set_attr "insn_count" "3")]) 7633 7634;; __builtin_mips_set_fcsr: move operand 0 into the FCSR. 7635(define_expand "mips_set_fcsr" 7636 [(unspec_volatile [(match_operand:SI 0 "register_operand")] 7637 UNSPEC_SET_FCSR)] 7638 "TARGET_HARD_FLOAT_ABI" 7639{ 7640 if (TARGET_MIPS16) 7641 { 7642 mips16_expand_set_fcsr (operands[0]); 7643 DONE; 7644 } 7645}) 7646 7647(define_insn "*mips_set_fcsr" 7648 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] 7649 UNSPEC_SET_FCSR)] 7650 "TARGET_HARD_FLOAT" 7651 "ctc1\t%0,$31") 7652 7653;; See tls_get_tp_mips16_<mode> for why this form is used. 7654(define_insn "mips_set_fcsr_mips16_<mode>" 7655 [(unspec_volatile:SI [(match_operand:P 0 "call_insn_operand" "dS") 7656 (reg:SI SET_FCSR_REGNUM)] UNSPEC_SET_FCSR) 7657 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7658 (clobber (reg:P RETURN_ADDR_REGNUM))] 7659 "TARGET_HARD_FLOAT_ABI && TARGET_MIPS16" 7660 { return mips_output_jump (operands, 0, -1, true); } 7661 [(set_attr "type" "call") 7662 (set_attr "insn_count" "3")]) 7663 7664;; Match paired HI/SI/SF/DFmode load/stores. 7665(define_insn "*join2_load_store<JOIN_MODE:mode>" 7666 [(set (match_operand:JOIN_MODE 0 "nonimmediate_operand" "=d,f,m,m") 7667 (match_operand:JOIN_MODE 1 "nonimmediate_operand" "m,m,d,f")) 7668 (set (match_operand:JOIN_MODE 2 "nonimmediate_operand" "=d,f,m,m") 7669 (match_operand:JOIN_MODE 3 "nonimmediate_operand" "m,m,d,f"))] 7670 "ENABLE_LD_ST_PAIRS && reload_completed" 7671 { 7672 bool load_p = (which_alternative == 0 || which_alternative == 1); 7673 /* Reg-renaming pass reuses base register if it is dead after bonded loads. 7674 Hardware does not bond those loads, even when they are consecutive. 7675 However, order of the loads need to be checked for correctness. */ 7676 if (!load_p || !reg_overlap_mentioned_p (operands[0], operands[1])) 7677 { 7678 output_asm_insn (mips_output_move (operands[0], operands[1]), 7679 operands); 7680 output_asm_insn (mips_output_move (operands[2], operands[3]), 7681 &operands[2]); 7682 } 7683 else 7684 { 7685 output_asm_insn (mips_output_move (operands[2], operands[3]), 7686 &operands[2]); 7687 output_asm_insn (mips_output_move (operands[0], operands[1]), 7688 operands); 7689 } 7690 return ""; 7691 } 7692 [(set_attr "move_type" "load,fpload,store,fpstore") 7693 (set_attr "insn_count" "2,2,2,2")]) 7694 7695;; 2 HI/SI/SF/DF loads are joined. 7696;; P5600 does not support bonding of two LBs, hence QI mode is not included. 7697;; The loads must be non-volatile as they might be reordered at the time of asm 7698;; generation. 7699(define_peephole2 7700 [(set (match_operand:JOIN_MODE 0 "register_operand") 7701 (match_operand:JOIN_MODE 1 "non_volatile_mem_operand")) 7702 (set (match_operand:JOIN_MODE 2 "register_operand") 7703 (match_operand:JOIN_MODE 3 "non_volatile_mem_operand"))] 7704 "ENABLE_LD_ST_PAIRS 7705 && mips_load_store_bonding_p (operands, <JOIN_MODE:MODE>mode, true)" 7706 [(parallel [(set (match_dup 0) 7707 (match_dup 1)) 7708 (set (match_dup 2) 7709 (match_dup 3))])] 7710 "") 7711 7712;; 2 HI/SI/SF/DF stores are joined. 7713;; P5600 does not support bonding of two SBs, hence QI mode is not included. 7714(define_peephole2 7715 [(set (match_operand:JOIN_MODE 0 "memory_operand") 7716 (match_operand:JOIN_MODE 1 "register_operand")) 7717 (set (match_operand:JOIN_MODE 2 "memory_operand") 7718 (match_operand:JOIN_MODE 3 "register_operand"))] 7719 "ENABLE_LD_ST_PAIRS 7720 && mips_load_store_bonding_p (operands, <JOIN_MODE:MODE>mode, false)" 7721 [(parallel [(set (match_dup 0) 7722 (match_dup 1)) 7723 (set (match_dup 2) 7724 (match_dup 3))])] 7725 "") 7726 7727;; Match paired HImode loads. 7728(define_insn "*join2_loadhi" 7729 [(set (match_operand:SI 0 "register_operand" "=r") 7730 (any_extend:SI (match_operand:HI 1 "non_volatile_mem_operand" "m"))) 7731 (set (match_operand:SI 2 "register_operand" "=r") 7732 (any_extend:SI (match_operand:HI 3 "non_volatile_mem_operand" "m")))] 7733 "ENABLE_LD_ST_PAIRS && reload_completed" 7734 { 7735 /* Reg-renaming pass reuses base register if it is dead after bonded loads. 7736 Hardware does not bond those loads, even when they are consecutive. 7737 However, order of the loads need to be checked for correctness. */ 7738 if (!reg_overlap_mentioned_p (operands[0], operands[1])) 7739 { 7740 output_asm_insn ("lh<u>\t%0,%1", operands); 7741 output_asm_insn ("lh<u>\t%2,%3", operands); 7742 } 7743 else 7744 { 7745 output_asm_insn ("lh<u>\t%2,%3", operands); 7746 output_asm_insn ("lh<u>\t%0,%1", operands); 7747 } 7748 7749 return ""; 7750 } 7751 [(set_attr "move_type" "load") 7752 (set_attr "insn_count" "2")]) 7753 7754 7755;; 2 HI loads are joined. 7756(define_peephole2 7757 [(set (match_operand:SI 0 "register_operand") 7758 (any_extend:SI (match_operand:HI 1 "non_volatile_mem_operand"))) 7759 (set (match_operand:SI 2 "register_operand") 7760 (any_extend:SI (match_operand:HI 3 "non_volatile_mem_operand")))] 7761 "ENABLE_LD_ST_PAIRS 7762 && mips_load_store_bonding_p (operands, HImode, true)" 7763 [(parallel [(set (match_dup 0) 7764 (any_extend:SI (match_dup 1))) 7765 (set (match_dup 2) 7766 (any_extend:SI (match_dup 3)))])] 7767 "") 7768 7769 7770;; Synchronization instructions. 7771 7772(include "sync.md") 7773 7774; The MIPS Paired-Single Floating Point and MIPS-3D Instructions. 7775 7776(include "mips-ps-3d.md") 7777 7778; The MIPS DSP Instructions. 7779 7780(include "mips-dsp.md") 7781 7782; The MIPS DSP REV 2 Instructions. 7783 7784(include "mips-dspr2.md") 7785 7786; MIPS fixed-point instructions. 7787(include "mips-fixed.md") 7788 7789; microMIPS patterns. 7790(include "micromips.md") 7791 7792; Loongson MultiMedia extensions Instructions (MMI) patterns. 7793(include "loongson-mmi.md") 7794 7795; The MIPS MSA Instructions. 7796(include "mips-msa.md") 7797 7798(define_c_enum "unspec" [ 7799 UNSPEC_ADDRESS_FIRST 7800]) 7801