1 /* Debug register code for the i386.
2 
3    Copyright (C) 2009, 2010, 2011 Free Software Foundation, Inc.
4 
5    This file is part of GDB.
6 
7    This program is free software; you can redistribute it and/or modify
8    it under the terms of the GNU General Public License as published by
9    the Free Software Foundation; either version 3 of the License, or
10    (at your option) any later version.
11 
12    This program is distributed in the hope that it will be useful,
13    but WITHOUT ANY WARRANTY; without even the implied warranty of
14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15    GNU General Public License for more details.
16 
17    You should have received a copy of the GNU General Public License
18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
19 
20 #include "server.h"
21 #include "target.h"
22 #include "i386-low.h"
23 
24 /* Support for 8-byte wide hw watchpoints.  */
25 #ifndef TARGET_HAS_DR_LEN_8
26 /* NOTE: sizeof (long) == 4 on win64.  */
27 #define TARGET_HAS_DR_LEN_8 (sizeof (void *) == 8)
28 #endif
29 
30 enum target_hw_bp_type
31   {
32     hw_write   = 0,	/* Common  HW watchpoint */
33     hw_read    = 1,	/* Read    HW watchpoint */
34     hw_access  = 2,	/* Access  HW watchpoint */
35     hw_execute = 3	/* Execute HW breakpoint */
36   };
37 
38 /* DR7 Debug Control register fields.  */
39 
40 /* How many bits to skip in DR7 to get to R/W and LEN fields.  */
41 #define DR_CONTROL_SHIFT	16
42 /* How many bits in DR7 per R/W and LEN field for each watchpoint.  */
43 #define DR_CONTROL_SIZE		4
44 
45 /* Watchpoint/breakpoint read/write fields in DR7.  */
46 #define DR_RW_EXECUTE	(0x0)	/* Break on instruction execution.  */
47 #define DR_RW_WRITE	(0x1)	/* Break on data writes.  */
48 #define DR_RW_READ	(0x3)	/* Break on data reads or writes.  */
49 
50 /* This is here for completeness.  No platform supports this
51    functionality yet (as of March 2001).  Note that the DE flag in the
52    CR4 register needs to be set to support this.  */
53 #ifndef DR_RW_IORW
54 #define DR_RW_IORW	(0x2)	/* Break on I/O reads or writes.  */
55 #endif
56 
57 /* Watchpoint/breakpoint length fields in DR7.  The 2-bit left shift
58    is so we could OR this with the read/write field defined above.  */
59 #define DR_LEN_1	(0x0 << 2) /* 1-byte region watch or breakpoint.  */
60 #define DR_LEN_2	(0x1 << 2) /* 2-byte region watch.  */
61 #define DR_LEN_4	(0x3 << 2) /* 4-byte region watch.  */
62 #define DR_LEN_8	(0x2 << 2) /* 8-byte region watch (AMD64).  */
63 
64 /* Local and Global Enable flags in DR7.
65 
66    When the Local Enable flag is set, the breakpoint/watchpoint is
67    enabled only for the current task; the processor automatically
68    clears this flag on every task switch.  When the Global Enable flag
69    is set, the breakpoint/watchpoint is enabled for all tasks; the
70    processor never clears this flag.
71 
72    Currently, all watchpoint are locally enabled.  If you need to
73    enable them globally, read the comment which pertains to this in
74    i386_insert_aligned_watchpoint below.  */
75 #define DR_LOCAL_ENABLE_SHIFT	0 /* Extra shift to the local enable bit.  */
76 #define DR_GLOBAL_ENABLE_SHIFT	1 /* Extra shift to the global enable bit.  */
77 #define DR_ENABLE_SIZE		2 /* Two enable bits per debug register.  */
78 
79 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
80    flags).  These are only required on i386, to allow detection of the
81    exact instruction which caused a watchpoint to break; i486 and
82    later processors do that automatically.  We set these flags for
83    backwards compatibility.  */
84 #define DR_LOCAL_SLOWDOWN	(0x100)
85 #define DR_GLOBAL_SLOWDOWN	(0x200)
86 
87 /* Fields reserved by Intel.  This includes the GD (General Detect
88    Enable) flag, which causes a debug exception to be generated when a
89    MOV instruction accesses one of the debug registers.
90 
91    FIXME: My Intel manual says we should use 0xF800, not 0xFC00.  */
92 #define DR_CONTROL_RESERVED	(0xFC00)
93 
94 /* Auxiliary helper macros.  */
95 
96 /* A value that masks all fields in DR7 that are reserved by Intel.  */
97 #define I386_DR_CONTROL_MASK	(~DR_CONTROL_RESERVED)
98 
99 /* The I'th debug register is vacant if its Local and Global Enable
100    bits are reset in the Debug Control register.  */
101 #define I386_DR_VACANT(state, i) \
102   (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
103 
104 /* Locally enable the break/watchpoint in the I'th debug register.  */
105 #define I386_DR_LOCAL_ENABLE(state, i) \
106   do { \
107     (state)->dr_control_mirror |= \
108       (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
109   } while (0)
110 
111 /* Globally enable the break/watchpoint in the I'th debug register.  */
112 #define I386_DR_GLOBAL_ENABLE(state, i) \
113   do { \
114     (state)->dr_control_mirror |= \
115       (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
116   } while (0)
117 
118 /* Disable the break/watchpoint in the I'th debug register.  */
119 #define I386_DR_DISABLE(state, i) \
120   do { \
121     (state)->dr_control_mirror &= \
122       ~(3 << (DR_ENABLE_SIZE * (i))); \
123   } while (0)
124 
125 /* Set in DR7 the RW and LEN fields for the I'th debug register.  */
126 #define I386_DR_SET_RW_LEN(state, i,rwlen) \
127   do { \
128     (state)->dr_control_mirror &= \
129       ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
130     (state)->dr_control_mirror |= \
131       ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
132   } while (0)
133 
134 /* Get from DR7 the RW and LEN fields for the I'th debug register.  */
135 #define I386_DR_GET_RW_LEN(dr7, i) \
136   (((dr7) \
137     >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
138 
139 /* Did the watchpoint whose address is in the I'th register break?  */
140 #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i)))
141 
142 /* A macro to loop over all debug registers.  */
143 #define ALL_DEBUG_REGISTERS(i)	for (i = 0; i < DR_NADDR; i++)
144 
145 /* Types of operations supported by i386_handle_nonaligned_watchpoint.  */
146 typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t;
147 
148 /* Implementation.  */
149 
150 /* Clear the reference counts and forget everything we knew about the
151    debug registers.  */
152 
153 void
i386_low_init_dregs(struct i386_debug_reg_state * state)154 i386_low_init_dregs (struct i386_debug_reg_state *state)
155 {
156   int i;
157 
158   ALL_DEBUG_REGISTERS (i)
159     {
160       state->dr_mirror[i] = 0;
161       state->dr_ref_count[i] = 0;
162     }
163   state->dr_control_mirror = 0;
164   state->dr_status_mirror  = 0;
165 }
166 
167 /* Print the values of the mirrored debug registers.  This is enabled via
168    the "set debug-hw-points 1" monitor command.  */
169 
170 static void
i386_show_dr(struct i386_debug_reg_state * state,const char * func,CORE_ADDR addr,int len,enum target_hw_bp_type type)171 i386_show_dr (struct i386_debug_reg_state *state,
172 	      const char *func, CORE_ADDR addr,
173 	      int len, enum target_hw_bp_type type)
174 {
175   int i;
176 
177   fprintf (stderr, "%s", func);
178   if (addr || len)
179     fprintf (stderr, " (addr=%lx, len=%d, type=%s)",
180 	     (unsigned long) addr, len,
181 	     type == hw_write ? "data-write"
182 	     : (type == hw_read ? "data-read"
183 		: (type == hw_access ? "data-read/write"
184 		   : (type == hw_execute ? "instruction-execute"
185 		      /* FIXME: if/when I/O read/write
186 			 watchpoints are supported, add them
187 			 here.  */
188 		      : "??unknown??"))));
189   fprintf (stderr, ":\n");
190   fprintf (stderr, "\tCONTROL (DR7): %08x          STATUS (DR6): %08x\n",
191 	   state->dr_control_mirror, state->dr_status_mirror);
192   ALL_DEBUG_REGISTERS (i)
193     {
194       fprintf (stderr, "\
195 \tDR%d: addr=0x%s, ref.count=%d  DR%d: addr=0x%s, ref.count=%d\n",
196 	      i, paddress (state->dr_mirror[i]),
197 	      state->dr_ref_count[i],
198 	      i + 1, paddress (state->dr_mirror[i + 1]),
199 	      state->dr_ref_count[i + 1]);
200       i++;
201     }
202 }
203 
204 /* Return the value of a 4-bit field for DR7 suitable for watching a
205    region of LEN bytes for accesses of type TYPE.  LEN is assumed to
206    have the value of 1, 2, or 4.  */
207 
208 static unsigned
i386_length_and_rw_bits(int len,enum target_hw_bp_type type)209 i386_length_and_rw_bits (int len, enum target_hw_bp_type type)
210 {
211   unsigned rw;
212 
213   switch (type)
214     {
215       case hw_execute:
216 	rw = DR_RW_EXECUTE;
217 	break;
218       case hw_write:
219 	rw = DR_RW_WRITE;
220 	break;
221       case hw_read:
222 	fatal ("The i386 doesn't support data-read watchpoints.\n");
223       case hw_access:
224 	rw = DR_RW_READ;
225 	break;
226 #if 0
227 	/* Not yet supported.  */
228       case hw_io_access:
229 	rw = DR_RW_IORW;
230 	break;
231 #endif
232       default:
233 	error ("\
234 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n",
235 			(int) type);
236     }
237 
238   switch (len)
239     {
240       case 1:
241 	return (DR_LEN_1 | rw);
242       case 2:
243 	return (DR_LEN_2 | rw);
244       case 4:
245 	return (DR_LEN_4 | rw);
246 	/* ELSE FALL THROUGH */
247       case 8:
248         if (TARGET_HAS_DR_LEN_8)
249  	  return (DR_LEN_8 | rw);
250       default:
251 	error ("\
252 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n", len);
253     }
254 }
255 
256 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
257    according to the length of the region to watch.  LEN_RW_BITS is the
258    value of the bits from DR7 which describes the length and access
259    type of the region to be watched by this watchpoint.  Return 0 on
260    success, -1 on failure.  */
261 
262 static int
i386_insert_aligned_watchpoint(struct i386_debug_reg_state * state,CORE_ADDR addr,unsigned len_rw_bits)263 i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state,
264 				CORE_ADDR addr, unsigned len_rw_bits)
265 {
266   int i;
267 
268   /* First, look for an occupied debug register with the same address
269      and the same RW and LEN definitions.  If we find one, we can
270      reuse it for this watchpoint as well (and save a register).  */
271   ALL_DEBUG_REGISTERS (i)
272     {
273       if (!I386_DR_VACANT (state, i)
274 	  && state->dr_mirror[i] == addr
275 	  && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits)
276 	{
277 	  state->dr_ref_count[i]++;
278 	  return 0;
279 	}
280     }
281 
282   /* Next, look for a vacant debug register.  */
283   ALL_DEBUG_REGISTERS (i)
284     {
285       if (I386_DR_VACANT (state, i))
286 	break;
287     }
288 
289   /* No more debug registers!  */
290   if (i >= DR_NADDR)
291     return -1;
292 
293   /* Now set up the register I to watch our region.  */
294 
295   /* Record the info in our local mirrored array.  */
296   state->dr_mirror[i] = addr;
297   state->dr_ref_count[i] = 1;
298   I386_DR_SET_RW_LEN (state, i, len_rw_bits);
299   /* Note: we only enable the watchpoint locally, i.e. in the current
300      task.  Currently, no i386 target allows or supports global
301      watchpoints; however, if any target would want that in the
302      future, GDB should probably provide a command to control whether
303      to enable watchpoints globally or locally, and the code below
304      should use global or local enable and slow-down flags as
305      appropriate.  */
306   I386_DR_LOCAL_ENABLE (state, i);
307   state->dr_control_mirror |= DR_LOCAL_SLOWDOWN;
308   state->dr_control_mirror &= I386_DR_CONTROL_MASK;
309 
310   /* Finally, actually pass the info to the inferior.  */
311   i386_dr_low_set_addr (state, i);
312   i386_dr_low_set_control (state);
313 
314   return 0;
315 }
316 
317 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
318    according to the length of the region to watch.  LEN_RW_BITS is the
319    value of the bits from DR7 which describes the length and access
320    type of the region watched by this watchpoint.  Return 0 on
321    success, -1 on failure.  */
322 
323 static int
i386_remove_aligned_watchpoint(struct i386_debug_reg_state * state,CORE_ADDR addr,unsigned len_rw_bits)324 i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state,
325 				CORE_ADDR addr, unsigned len_rw_bits)
326 {
327   int i, retval = -1;
328 
329   ALL_DEBUG_REGISTERS (i)
330     {
331       if (!I386_DR_VACANT (state, i)
332 	  && state->dr_mirror[i] == addr
333 	  && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits)
334 	{
335 	  if (--state->dr_ref_count[i] == 0) /* No longer in use?  */
336 	    {
337 	      /* Reset our mirror.  */
338 	      state->dr_mirror[i] = 0;
339 	      I386_DR_DISABLE (state, i);
340 	      /* Reset it in the inferior.  */
341 	      i386_dr_low_set_control (state);
342 	      i386_dr_low_set_addr (state, i);
343 	    }
344 	  retval = 0;
345 	}
346     }
347 
348   return retval;
349 }
350 
351 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
352    number of debug registers required to watch a region at address
353    ADDR whose length is LEN for accesses of type TYPE.  Return 0 on
354    successful insertion or removal, a positive number when queried
355    about the number of registers, or -1 on failure.  If WHAT is not a
356    valid value, bombs through internal_error.  */
357 
358 static int
i386_handle_nonaligned_watchpoint(struct i386_debug_reg_state * state,i386_wp_op_t what,CORE_ADDR addr,int len,enum target_hw_bp_type type)359 i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state,
360 				   i386_wp_op_t what, CORE_ADDR addr, int len,
361 				   enum target_hw_bp_type type)
362 {
363   int retval = 0, status = 0;
364   int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4;
365 
366   static const int size_try_array[8][8] =
367   {
368     {1, 1, 1, 1, 1, 1, 1, 1},	/* Trying size one.  */
369     {2, 1, 2, 1, 2, 1, 2, 1},	/* Trying size two.  */
370     {2, 1, 2, 1, 2, 1, 2, 1},	/* Trying size three.  */
371     {4, 1, 2, 1, 4, 1, 2, 1},	/* Trying size four.  */
372     {4, 1, 2, 1, 4, 1, 2, 1},	/* Trying size five.  */
373     {4, 1, 2, 1, 4, 1, 2, 1},	/* Trying size six.  */
374     {4, 1, 2, 1, 4, 1, 2, 1},	/* Trying size seven.  */
375     {8, 1, 2, 1, 4, 1, 2, 1},	/* Trying size eight.  */
376   };
377 
378   while (len > 0)
379     {
380       int align = addr % max_wp_len;
381       /* Four (eight on AMD64) is the maximum length a debug register
382 	 can watch.  */
383       int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1);
384       int size = size_try_array[try][align];
385 
386       if (what == WP_COUNT)
387 	{
388 	  /* size_try_array[] is defined such that each iteration
389 	     through the loop is guaranteed to produce an address and a
390 	     size that can be watched with a single debug register.
391 	     Thus, for counting the registers required to watch a
392 	     region, we simply need to increment the count on each
393 	     iteration.  */
394 	  retval++;
395 	}
396       else
397 	{
398 	  unsigned len_rw = i386_length_and_rw_bits (size, type);
399 
400 	  if (what == WP_INSERT)
401 	    status = i386_insert_aligned_watchpoint (state, addr, len_rw);
402 	  else if (what == WP_REMOVE)
403 	    status = i386_remove_aligned_watchpoint (state, addr, len_rw);
404 	  else
405 	    fatal ("\
406 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n",
407 		   (int) what);
408 
409 	  /* We keep the loop going even after a failure, because some
410 	     of the other aligned watchpoints might still succeed
411 	     (e.g. if they watch addresses that are already watched,
412 	     in which case we just increment the reference counts of
413 	     occupied debug registers).  If we break out of the loop
414 	     too early, we could cause those addresses watched by
415 	     other watchpoints to be disabled when breakpoint.c reacts
416 	     to our failure to insert this watchpoint and tries to
417 	     remove it.  */
418 	  if (status)
419 	    retval = status;
420 	}
421 
422       addr += size;
423       len -= size;
424     }
425 
426   return retval;
427 }
428 
429 #define Z_PACKET_WRITE_WP '2'
430 #define Z_PACKET_READ_WP '3'
431 #define Z_PACKET_ACCESS_WP '4'
432 
433 /* Map the protocol watchpoint type TYPE to enum target_hw_bp_type.  */
434 
435 static enum target_hw_bp_type
Z_packet_to_hw_type(char type)436 Z_packet_to_hw_type (char type)
437 {
438   switch (type)
439     {
440     case Z_PACKET_WRITE_WP:
441       return hw_write;
442     case Z_PACKET_READ_WP:
443       return hw_read;
444     case Z_PACKET_ACCESS_WP:
445       return hw_access;
446     default:
447       fatal ("Z_packet_to_hw_type: bad watchpoint type %c", type);
448     }
449 }
450 
451 /* Insert a watchpoint to watch a memory region which starts at
452    address ADDR and whose length is LEN bytes.  Watch memory accesses
453    of the type TYPE_FROM_PACKET.  Return 0 on success, -1 on failure.  */
454 
455 int
i386_low_insert_watchpoint(struct i386_debug_reg_state * state,char type_from_packet,CORE_ADDR addr,int len)456 i386_low_insert_watchpoint (struct i386_debug_reg_state *state,
457 			    char type_from_packet, CORE_ADDR addr, int len)
458 {
459   int retval;
460   enum target_hw_bp_type type = Z_packet_to_hw_type (type_from_packet);
461 
462   if (type == hw_read)
463     return 1; /* unsupported */
464 
465   if (((len != 1 && len != 2 && len != 4)
466        && !(TARGET_HAS_DR_LEN_8 && len == 8))
467       || addr % len != 0)
468     {
469       retval = i386_handle_nonaligned_watchpoint (state, WP_INSERT,
470 						  addr, len, type);
471     }
472   else
473     {
474       unsigned len_rw = i386_length_and_rw_bits (len, type);
475 
476       retval = i386_insert_aligned_watchpoint (state, addr, len_rw);
477     }
478 
479   if (debug_hw_points)
480     i386_show_dr (state, "insert_watchpoint", addr, len, type);
481 
482   return retval;
483 }
484 
485 /* Remove a watchpoint that watched the memory region which starts at
486    address ADDR, whose length is LEN bytes, and for accesses of the
487    type TYPE_FROM_PACKET.  Return 0 on success, -1 on failure.  */
488 
489 int
i386_low_remove_watchpoint(struct i386_debug_reg_state * state,char type_from_packet,CORE_ADDR addr,int len)490 i386_low_remove_watchpoint (struct i386_debug_reg_state *state,
491 			    char type_from_packet, CORE_ADDR addr, int len)
492 {
493   int retval;
494   enum target_hw_bp_type type = Z_packet_to_hw_type (type_from_packet);
495 
496   if (((len != 1 && len != 2 && len != 4)
497        && !(TARGET_HAS_DR_LEN_8 && len == 8))
498       || addr % len != 0)
499     {
500       retval = i386_handle_nonaligned_watchpoint (state, WP_REMOVE,
501 						  addr, len, type);
502     }
503   else
504     {
505       unsigned len_rw = i386_length_and_rw_bits (len, type);
506 
507       retval = i386_remove_aligned_watchpoint (state, addr, len_rw);
508     }
509 
510   if (debug_hw_points)
511     i386_show_dr (state, "remove_watchpoint", addr, len, type);
512 
513   return retval;
514 }
515 
516 /* Return non-zero if we can watch a memory region that starts at
517    address ADDR and whose length is LEN bytes.  */
518 
519 int
i386_low_region_ok_for_watchpoint(struct i386_debug_reg_state * state,CORE_ADDR addr,int len)520 i386_low_region_ok_for_watchpoint (struct i386_debug_reg_state *state,
521 				   CORE_ADDR addr, int len)
522 {
523   int nregs;
524 
525   /* Compute how many aligned watchpoints we would need to cover this
526      region.  */
527   nregs = i386_handle_nonaligned_watchpoint (state, WP_COUNT,
528 					     addr, len, hw_write);
529   return nregs <= DR_NADDR ? 1 : 0;
530 }
531 
532 /* If the inferior has some break/watchpoint that triggered, set the
533    address associated with that break/watchpoint and return true.
534    Otherwise, return false.  */
535 
536 int
i386_low_stopped_data_address(struct i386_debug_reg_state * state,CORE_ADDR * addr_p)537 i386_low_stopped_data_address (struct i386_debug_reg_state *state,
538 			       CORE_ADDR *addr_p)
539 {
540   CORE_ADDR addr = 0;
541   int i;
542   int rc = 0;
543   unsigned status;
544   unsigned control;
545 
546   /* Get the current values the inferior has.  If the thread was
547      running when we last changed watchpoints, the mirror no longer
548      represents what was set in this LWP's debug registers.  */
549   status = i386_dr_low_get_status ();
550   control = i386_dr_low_get_control ();
551 
552   ALL_DEBUG_REGISTERS (i)
553     {
554       if (I386_DR_WATCH_HIT (status, i)
555 	  /* This second condition makes sure DRi is set up for a data
556 	     watchpoint, not a hardware breakpoint.  The reason is
557 	     that GDB doesn't call the target_stopped_data_address
558 	     method except for data watchpoints.  In other words, I'm
559 	     being paranoiac.  */
560 	  && I386_DR_GET_RW_LEN (control, i) != 0)
561 	{
562 	  addr = i386_dr_low_get_addr (i);
563 	  rc = 1;
564 	  if (debug_hw_points)
565 	    i386_show_dr (state, "watchpoint_hit", addr, -1, hw_write);
566 	}
567     }
568 
569   if (debug_hw_points && addr == 0)
570     i386_show_dr (state, "stopped_data_addr", 0, 0, hw_write);
571 
572   if (rc)
573     *addr_p = addr;
574   return rc;
575 }
576 
577 /* Return true if the inferior has some watchpoint that triggered.
578    Otherwise return false.  */
579 
580 int
i386_low_stopped_by_watchpoint(struct i386_debug_reg_state * state)581 i386_low_stopped_by_watchpoint (struct i386_debug_reg_state *state)
582 {
583   CORE_ADDR addr = 0;
584   return i386_low_stopped_data_address (state, &addr);
585 }
586