1 /* Copyright (c) 2002, 2003, 2004, 2005 2 Juergen Schilling <juergen.schilling@honeywell.com> 3 Eric B. Weddington 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 * Redistributions of source code must retain the above copyright 10 notice, this list of conditions and the following disclaimer. 11 12 * Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in 14 the documentation and/or other materials provided with the 15 distribution. 16 17 * Neither the name of the copyright holders nor the names of 18 contributors may be used to endorse or promote products derived 19 from this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. */ 32 33 /* $Id: iom169.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 34 35 /* iom169.h - definitions for ATmega169 */ 36 37 /* This should be up to date with data sheet version 2514J-AVR-12/03. */ 38 39 #ifndef _AVR_IOM169_H_ 40 #define _AVR_IOM169_H_ 1 41 42 /* This file should only be included from <avr/io.h>, never directly. */ 43 44 #ifndef _AVR_IO_H_ 45 # error "Include <avr/io.h> instead of this file." 46 #endif 47 48 #ifndef _AVR_IOXXX_H_ 49 # define _AVR_IOXXX_H_ "iom169.h" 50 #else 51 # error "Attempt to include more than one <avr/ioXXX.h> file." 52 #endif 53 54 /* I/O registers */ 55 56 /* Port A */ 57 #define PINA _SFR_IO8(0x00) 58 #define DDRA _SFR_IO8(0x01) 59 #define PORTA _SFR_IO8(0x02) 60 61 /* Port B */ 62 #define PINB _SFR_IO8(0x03) 63 #define DDRB _SFR_IO8(0x04) 64 #define PORTB _SFR_IO8(0x05) 65 66 /* Port C */ 67 #define PINC _SFR_IO8(0x06) 68 #define DDRC _SFR_IO8(0x07) 69 #define PORTC _SFR_IO8(0x08) 70 71 /* Port D */ 72 #define PIND _SFR_IO8(0x09) 73 #define DDRD _SFR_IO8(0x0A) 74 #define PORTD _SFR_IO8(0x0B) 75 76 /* Port E */ 77 #define PINE _SFR_IO8(0x0C) 78 #define DDRE _SFR_IO8(0x0D) 79 #define PORTE _SFR_IO8(0x0E) 80 81 /* Port F */ 82 #define PINF _SFR_IO8(0x0F) 83 #define DDRF _SFR_IO8(0x10) 84 #define PORTF _SFR_IO8(0x11) 85 86 /* Port G */ 87 #define PING _SFR_IO8(0x12) 88 #define DDRG _SFR_IO8(0x13) 89 #define PORTG _SFR_IO8(0x14) 90 91 /* Timer/Counter 0 interrupt Flag Register */ 92 #define TIFR0 _SFR_IO8(0x15) 93 94 /* Timer/Counter 1 interrupt Flag Register */ 95 #define TIFR1 _SFR_IO8(0x16) 96 97 /* Timer/Counter 2 interrupt Flag Register */ 98 #define TIFR2 _SFR_IO8(0x17) 99 100 /* External Interrupt Flag Register */ 101 #define EIFR _SFR_IO8(0x1C) 102 103 /* External Interrupt Mask Register */ 104 #define EIMSK _SFR_IO8(0x1D) 105 106 /* General Purpose I/O Register 0 */ 107 #define GPIOR0 _SFR_IO8(0x1E) 108 109 #define EECR _SFR_IO8(0x1F) 110 111 #define EEDR _SFR_IO8(0X20) 112 113 /* Combine EEARL and EEARH */ 114 #define EEAR _SFR_IO16(0x21) 115 #define EEARL _SFR_IO8(0x21) 116 #define EEARH _SFR_IO8(0X22) 117 118 /* 6-char sequence denoting where to find the EEPROM registers in memory space. 119 Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM 120 subroutines. 121 First two letters: EECR address. 122 Second two letters: EEDR address. 123 Last two letters: EEAR address. */ 124 #define __EEPROM_REG_LOCATIONS__ 1F2021 125 126 /* General Timer/Counter Control Register */ 127 #define GTCCR _SFR_IO8(0x23) 128 129 /* Timer/Counter Control Register A */ 130 #define TCCR0A _SFR_IO8(0x24) 131 132 /* Timer/Counter Register */ 133 #define TCNT0 _SFR_IO8(0x26) 134 135 /* Output Compare Register A */ 136 #define OCR0A _SFR_IO8(0x27) 137 138 /* General Purpose I/O Register 1 */ 139 #define GPIOR1 _SFR_IO8(0x2A) 140 141 /* General Purpose I/O Register 2 */ 142 #define GPIOR2 _SFR_IO8(0x2B) 143 144 /* SPI Control Register */ 145 #define SPCR _SFR_IO8(0x2C) 146 147 /* SPI Status Register */ 148 #define SPSR _SFR_IO8(0x2D) 149 150 /* SPI Data Register */ 151 #define SPDR _SFR_IO8(0x2E) 152 153 /* Analog Comperator Control and Status Register */ 154 #define ACSR _SFR_IO8(0x30) 155 156 /* On-chip Debug Register */ 157 #define OCDR _SFR_IO8(0x31) 158 159 /* Sleep Mode Control Register */ 160 #define SMCR _SFR_IO8(0x33) 161 162 /* MCU Status Register */ 163 #define MCUSR _SFR_IO8(0x34) 164 165 /* MCU Control Rgeister */ 166 #define MCUCR _SFR_IO8(0x35) 167 168 /* Store Program Memory Control and Status Register */ 169 #define SPMCSR _SFR_IO8(0x37) 170 171 /* Watchdog Timer Control Register */ 172 #define WDTCR _SFR_MEM8(0x60) 173 174 /* Clock Prescale Register */ 175 #define CLKPR _SFR_MEM8(0x61) 176 177 #define PRR _SFR_MEM8(0x64) 178 #define PRADC 0 179 #define PRUSART0 1 180 #define PRSPI 2 181 #define PRTIM1 3 182 #define PRLCD 4 183 184 #define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRLCD)) 185 #define __AVR_HAVE_PRR_PRADC 186 #define __AVR_HAVE_PRR_PRUSART0 187 #define __AVR_HAVE_PRR_PRSPI 188 #define __AVR_HAVE_PRR_PRTIM1 189 #define __AVR_HAVE_PRR_PRLCD 190 191 /* Oscillator Calibration Register */ 192 #define OSCCAL _SFR_MEM8(0x66) 193 194 /* External Interrupt Control Register A */ 195 #define EICRA _SFR_MEM8(0x69) 196 197 /* Pin Change Mask Register */ 198 #define PCMSK _SFR_MEM16(0x6B) 199 #define PCMSK0 _SFR_MEM8(0x6B) 200 #define PCMSK1 _SFR_MEM8(0x6C) 201 202 /* Timer/Counter 0 Interrupt Mask Register */ 203 #define TIMSK0 _SFR_MEM8(0x6E) 204 205 /* Timer/Counter 1 Interrupt Mask Register */ 206 #define TIMSK1 _SFR_MEM8(0x6F) 207 208 /* Timer/Counter 2 Interrupt Mask Register */ 209 #define TIMSK2 _SFR_MEM8(0x70) 210 211 /* ADC Data Register */ 212 #ifndef __ASSEMBLER__ 213 #define ADC _SFR_MEM16(0x78) 214 #endif 215 #define ADCW _SFR_MEM16(0x78) 216 #define ADCL _SFR_MEM8(0x78) 217 #define ADCH _SFR_MEM8(0x79) 218 219 /* ADC Control and Status Register A */ 220 #define ADCSRA _SFR_MEM8(0x7A) 221 222 /* ADC Control and Status Register B */ 223 #define ADCSRB _SFR_MEM8(0x7B) 224 225 /* ADC Multiplex Selection Register */ 226 #define ADMUX _SFR_MEM8(0x7C) 227 228 /* NOTE: DIDR0 and DIDR1 are swapped in the register summary of the data sheet 229 (2514D-AVR-01/03), but seem to be correct in the discussions of the 230 registers. */ 231 232 /* Digital Input Disable Register 0 */ 233 #define DIDR0 _SFR_MEM8(0x7E) 234 235 /* Digital Input Disable Register 1 */ 236 #define DIDR1 _SFR_MEM8(0x7F) 237 238 /* Timer/Counter1 Control Register A */ 239 #define TCCR1A _SFR_MEM8(0x80) 240 241 /* Timer/Counter1 Control Register B */ 242 #define TCCR1B _SFR_MEM8(0x81) 243 244 /* Timer/Counter1 Control Register C */ 245 #define TCCR1C _SFR_MEM8(0x82) 246 247 /* Timer/Counter1 Register */ 248 #define TCNT1 _SFR_MEM16(0x84) 249 #define TCNT1L _SFR_MEM8(0x84) 250 #define TCNT1H _SFR_MEM8(0x85) 251 252 /* Timer/Counter1 Input Capture Register */ 253 #define ICR1 _SFR_MEM16(0x86) 254 #define ICR1L _SFR_MEM8(0x86) 255 #define ICR1H _SFR_MEM8(0x87) 256 257 /* Timer/Counter1 Output Compare Register A */ 258 #define OCR1A _SFR_MEM16(0x88) 259 #define OCR1AL _SFR_MEM8(0x88) 260 #define OCR1AH _SFR_MEM8(0x89) 261 262 /* Timer/Counter1 Output Compare Registare B */ 263 #define OCR1B _SFR_MEM16(0x8A) 264 #define OCR1BL _SFR_MEM8(0x8A) 265 #define OCR1BH _SFR_MEM8(0x8B) 266 267 /* Timer/Counter2 Control Register A */ 268 #define TCCR2A _SFR_MEM8(0xB0) 269 270 /* Timer/Counter2 Register */ 271 #define TCNT2 _SFR_MEM8(0xB2) 272 273 /* Timer/Counter2 Output Compare Register */ 274 #define OCR2A _SFR_MEM8(0xB3) 275 276 /* Asynchronous Status Register */ 277 #define ASSR _SFR_MEM8(0xB6) 278 279 /* USI Control Register */ 280 #define USICR _SFR_MEM8(0xB8) 281 282 /* USI Status Register */ 283 #define USISR _SFR_MEM8(0xB9) 284 285 /* USI Data Register */ 286 #define USIDR _SFR_MEM8(0xBA) 287 288 /* USART0 Control and Status Register A */ 289 #define UCSRA _SFR_MEM8(0xC0) 290 291 /* USART0 Control and Status Register B */ 292 #define UCSRB _SFR_MEM8(0xC1) 293 294 /* USART0 Control and Status Register C */ 295 #define UCSRC _SFR_MEM8(0xC2) 296 297 /* USART0 Baud Rate Register */ 298 #define UBRR _SFR_MEM16(0xC4) 299 #define UBRRL _SFR_MEM8(0xC4) 300 #define UBRRH _SFR_MEM8(0xC5) 301 302 /* USART0 I/O Data Register */ 303 #define UDR _SFR_MEM8(0xC6) 304 305 /* LCD Control and Status Register A */ 306 #define LCDCRA _SFR_MEM8(0xE4) 307 308 /* LCD Control and Status Register B */ 309 #define LCDCRB _SFR_MEM8(0xE5) 310 311 /* LCD Frame Rate Register */ 312 #define LCDFRR _SFR_MEM8(0xE6) 313 314 /* LCD Contrast Control Register */ 315 #define LCDCCR _SFR_MEM8(0xE7) 316 317 /* LCD Memory mapping */ 318 #define LCDDR0 _SFR_MEM8(0xEC) 319 #define LCDDR1 _SFR_MEM8(0xED) 320 #define LCDDR2 _SFR_MEM8(0xEE) 321 #define LCDDR3 _SFR_MEM8(0xEF) 322 #define LCDDR5 _SFR_MEM8(0xF1) 323 #define LCDDR6 _SFR_MEM8(0xF2) 324 #define LCDDR7 _SFR_MEM8(0xF3) 325 #define LCDDR8 _SFR_MEM8(0xF4) 326 #define LCDDR10 _SFR_MEM8(0xF6) 327 #define LCDDR11 _SFR_MEM8(0xF7) 328 #define LCDDR12 _SFR_MEM8(0xF8) 329 #define LCDDR13 _SFR_MEM8(0xF9) 330 #define LCDDR15 _SFR_MEM8(0xFB) 331 #define LCDDR16 _SFR_MEM8(0xFC) 332 #define LCDDR17 _SFR_MEM8(0xFD) 333 #define LCDDR18 _SFR_MEM8(0xFE) 334 335 /* Interrupt vectors */ 336 337 /* External Interrupt Request 0 */ 338 #define INT0_vect_num 1 339 #define INT0_vect _VECTOR(1) 340 #define SIG_INTERRUPT0 _VECTOR(1) 341 342 /* Pin Change Interrupt Request 0 */ 343 #define PCINT0_vect_num 2 344 #define PCINT0_vect _VECTOR(2) 345 #define SIG_PIN_CHANGE0 _VECTOR(2) 346 347 /* Pin Change Interrupt Request 1 */ 348 #define PCINT1_vect_num 3 349 #define PCINT1_vect _VECTOR(3) 350 #define SIG_PIN_CHANGE1 _VECTOR(3) 351 352 /* Timer/Counter2 Compare Match */ 353 #define TIMER2_COMP_vect_num 4 354 #define TIMER2_COMP_vect _VECTOR(4) 355 #define SIG_OUTPUT_COMPARE2 _VECTOR(4) 356 357 /* Timer/Counter2 Overflow */ 358 #define TIMER2_OVF_vect_num 5 359 #define TIMER2_OVF_vect _VECTOR(5) 360 #define SIG_OVERFLOW2 _VECTOR(5) 361 362 /* Timer/Counter1 Capture Event */ 363 #define TIMER1_CAPT_vect_num 6 364 #define TIMER1_CAPT_vect _VECTOR(6) 365 #define SIG_INPUT_CAPTURE1 _VECTOR(6) 366 367 /* Timer/Counter1 Compare Match A */ 368 #define TIMER1_COMPA_vect_num 7 369 #define TIMER1_COMPA_vect _VECTOR(7) 370 #define SIG_OUTPUT_COMPARE1A _VECTOR(7) 371 372 /* Timer/Counter Compare Match B */ 373 #define TIMER1_COMPB_vect_num 8 374 #define TIMER1_COMPB_vect _VECTOR(8) 375 #define SIG_OUTPUT_COMPARE1B _VECTOR(8) 376 377 /* Timer/Counter1 Overflow */ 378 #define TIMER1_OVF_vect_num 9 379 #define TIMER1_OVF_vect _VECTOR(9) 380 #define SIG_OVERFLOW1 _VECTOR(9) 381 382 /* Timer/Counter0 Compare Match */ 383 #define TIMER0_COMP_vect_num 10 384 #define TIMER0_COMP_vect _VECTOR(10) 385 #define SIG_OUTPUT_COMPARE0 _VECTOR(10) 386 387 /* Timer/Counter0 Overflow */ 388 #define TIMER0_OVF_vect_num 11 389 #define TIMER0_OVF_vect _VECTOR(11) 390 #define SIG_OVERFLOW0 _VECTOR(11) 391 392 /* SPI Serial Transfer Complete */ 393 #define SPI_STC_vect_num 12 394 #define SPI_STC_vect _VECTOR(12) 395 #define SIG_SPI _VECTOR(12) 396 397 /* USART0, Rx Complete */ 398 #define USART0_RX_vect_num 13 399 #define USART0_RX_vect _VECTOR(13) 400 #define SIG_USART_RECV _VECTOR(13) 401 402 /* USART0 Data register Empty */ 403 #define USART0_UDRE_vect_num 14 404 #define USART0_UDRE_vect _VECTOR(14) 405 #define SIG_USART_DATA _VECTOR(14) 406 407 /* USART0, Tx Complete */ 408 #define USART0_TX_vect_num 15 409 #define USART0_TX_vect _VECTOR(15) 410 #define SIG_USART_TRANS _VECTOR(15) 411 412 /* USI Start Condition */ 413 #define USI_START_vect_num 16 414 #define USI_START_vect _VECTOR(16) 415 #define SIG_USI_START _VECTOR(16) 416 417 /* USI Overflow */ 418 #define USI_OVERFLOW_vect_num 17 419 #define USI_OVERFLOW_vect _VECTOR(17) 420 #define SIG_USI_OVERFLOW _VECTOR(17) 421 422 /* Analog Comparator */ 423 #define ANALOG_COMP_vect_num 18 424 #define ANALOG_COMP_vect _VECTOR(18) 425 #define SIG_COMPARATOR _VECTOR(18) 426 427 /* ADC Conversion Complete */ 428 #define ADC_vect_num 19 429 #define ADC_vect _VECTOR(19) 430 #define SIG_ADC _VECTOR(19) 431 432 /* EEPROM Ready */ 433 #define EE_READY_vect_num 20 434 #define EE_READY_vect _VECTOR(20) 435 #define SIG_EEPROM_READY _VECTOR(20) 436 437 /* Store Program Memory Read */ 438 #define SPM_READY_vect_num 21 439 #define SPM_READY_vect _VECTOR(21) 440 #define SIG_SPM_READY _VECTOR(21) 441 442 /* LCD Start of Frame */ 443 #define LCD_vect_num 22 444 #define LCD_vect _VECTOR(22) 445 #define SIG_LCD _VECTOR(22) 446 447 #define _VECTORS_SIZE 92 448 449 /* Bit numbers */ 450 451 /* 452 PA7 = SEG3 453 PA6 = SEG2 454 PA5 = SEG1 455 PA4 = SEG0 456 PA3 = COM3 457 PA2 = COM2 458 PA1 = COM1 459 PA0 = COM0 460 */ 461 462 /* PORTA */ 463 #define PA7 7 464 #define PA6 6 465 #define PA5 5 466 #define PA4 4 467 #define PA3 3 468 #define PA2 2 469 #define PA1 1 470 #define PA0 0 471 472 /* DDRA */ 473 #define DDA7 7 474 #define DDA6 6 475 #define DDA5 5 476 #define DDA4 4 477 #define DDA3 3 478 #define DDA2 2 479 #define DDA1 1 480 #define DDA0 0 481 482 /* PINA */ 483 #define PINA7 7 484 #define PINA6 6 485 #define PINA5 5 486 #define PINA4 4 487 #define PINA3 3 488 #define PINA2 2 489 #define PINA1 1 490 #define PINA0 0 491 492 /* 493 PB7 = OC2A / PCINT15 494 PB6 = OC1B / PCINT14 495 PB5 = OC1A / PCINT13 496 PB4 = OC0A / PCINT12 497 PB3 = MISO / PCINT11 498 PB2 = MOSI / PCINT10 499 PB1 = SCK / PCINT9 500 PB0 = SS# / PCINT8 501 */ 502 503 /* PORTB */ 504 #define PB7 7 505 #define PB6 6 506 #define PB5 5 507 #define PB4 4 508 #define PB3 3 509 #define PB2 2 510 #define PB1 1 511 #define PB0 0 512 513 /* DDRB */ 514 #define DDB7 7 515 #define DDB6 6 516 #define DDB5 5 517 #define DDB4 4 518 #define DDB3 3 519 #define DDB2 2 520 #define DDB1 1 521 #define DDB0 0 522 523 /* PINB */ 524 #define PINB7 7 525 #define PINB6 6 526 #define PINB5 5 527 #define PINB4 4 528 #define PINB3 3 529 #define PINB2 2 530 #define PINB1 1 531 #define PINB0 0 532 533 /* 534 PC7 = SEG5 535 PC6 = SEG6 536 PC5 = SEG7 537 PC4 = SEG8 538 PC3 = SEG9 539 PC2 = SEG10 540 PC1 = SEG11 541 PC0 = SEG12 542 */ 543 544 /* PORTC */ 545 #define PC7 7 546 #define PC6 6 547 #define PC5 5 548 #define PC4 4 549 #define PC3 3 550 #define PC2 2 551 #define PC1 1 552 #define PC0 0 553 554 /* DDRC */ 555 #define DDC7 7 556 #define DDC6 6 557 #define DDC5 5 558 #define DDC4 4 559 #define DDC3 3 560 #define DDC2 2 561 #define DDC1 1 562 #define DDC0 0 563 564 /* PINC */ 565 #define PINC7 7 566 #define PINC6 6 567 #define PINC5 5 568 #define PINC4 4 569 #define PINC3 3 570 #define PINC2 2 571 #define PINC1 1 572 #define PINC0 0 573 574 /* 575 PD7 = SEG15 576 PD6 = SEG16 577 PD5 = SEG17 578 PD4 = SEG18 579 PD3 = SEG19 580 PD2 = SEG20 581 PD1 = INT0 / SEG21 582 PD0 = ICP / SEG22 583 */ 584 585 /* PORTD */ 586 #define PD7 7 587 #define PD6 6 588 #define PD5 5 589 #define PD4 4 590 #define PD3 3 591 #define PD2 2 592 #define PD1 1 593 #define PD0 0 594 595 /* DDRD */ 596 #define DDD7 7 597 #define DDD6 6 598 #define DDD5 5 599 #define DDD4 4 600 #define DDD3 3 601 #define DDD2 2 602 #define DDD1 1 603 #define DDD0 0 604 605 /* PIND */ 606 #define PIND7 7 607 #define PIND6 6 608 #define PIND5 5 609 #define PIND4 4 610 #define PIND3 3 611 #define PIND2 2 612 #define PIND1 1 613 #define PIND0 0 614 615 /* 616 PE7 = CLK0 / PCINT7 617 PE6 = DO / PCINT6 618 PE5 = DI / SDA / PCINT5 619 PE4 = USCK / SCL / PCINT4 620 PE3 = AIN1 / PCINT3 621 PE2 = XCK / AIN0 / PCINT2 622 PE1 = TXD / PCINT1 623 PE0 = RXD / PCINT0 624 */ 625 626 /* PORTE */ 627 #define PE7 7 628 #define PE6 6 629 #define PE5 5 630 #define PE4 4 631 #define PE3 3 632 #define PE2 2 633 #define PE1 1 634 #define PE0 0 635 636 /* DDRE */ 637 #define DDE7 7 638 #define DDE6 6 639 #define DDE5 5 640 #define DDE4 4 641 #define DDE3 3 642 #define DDE2 2 643 #define DDE1 1 644 #define DDE0 0 645 646 /* PINE */ 647 #define PINE7 7 648 #define PINE6 6 649 #define PINE5 5 650 #define PINE4 4 651 #define PINE3 3 652 #define PINE2 2 653 #define PINE1 1 654 #define PINE0 0 655 656 /* 657 PF7 = ADC7 / TDI 658 PF6 = ADC6 / TDO 659 PF5 = ADC5 / TMS 660 PF4 = ADC4 / TCK 661 PF3 = ADC3 662 PF2 = ADC2 663 PF1 = ADC1 664 PF0 = ADC0 665 */ 666 667 /* PORTF */ 668 #define PF7 7 669 #define PF6 6 670 #define PF5 5 671 #define PF4 4 672 #define PF3 3 673 #define PF2 2 674 #define PF1 1 675 #define PF0 0 676 677 /* DDRF */ 678 #define DDF7 7 679 #define DDF6 6 680 #define DDF5 5 681 #define DDF4 4 682 #define DDF3 3 683 #define DDF2 2 684 #define DDF1 1 685 #define DDF0 0 686 687 /* PINF */ 688 #define PINF7 7 689 #define PINF6 6 690 #define PINF5 5 691 #define PINF4 4 692 #define PINF3 3 693 #define PINF2 2 694 #define PINF1 1 695 #define PINF0 0 696 697 /* 698 PG5 = RESET# 699 PG4 = T0 / SEG23 700 PG3 = T1 / SEG24 701 PG2 = SEG4 702 PG1 = SEG13 703 PG0 = SEG14 704 */ 705 706 /* PORTG */ 707 #define PG4 4 708 #define PG3 3 709 #define PG2 2 710 #define PG1 1 711 #define PG0 0 712 713 /* DDRG */ 714 #define DDG4 4 715 #define DDG3 3 716 #define DDG2 2 717 #define DDG1 1 718 #define DDG0 0 719 720 /* PING */ 721 #define PING5 5 722 #define PING4 4 723 #define PING3 3 724 #define PING2 2 725 #define PING1 1 726 #define PING0 0 727 728 /* TIFR0 */ 729 #define OCF0A 1 730 #define TOV0 0 731 732 /* TIFR1 */ 733 #define ICF1 5 734 #define OCF1B 2 735 #define OCF1A 1 736 #define TOV1 0 737 738 /* TIFR2 */ 739 #define OCF2A 1 740 #define TOV2 0 741 742 /* EIFR */ 743 #define PCIF1 7 744 #define PCIF0 6 745 #define INTF0 0 746 747 /* EIMSK */ 748 #define PCIE1 7 749 #define PCIE0 6 750 #define INT0 0 751 752 /* EECR */ 753 #define EERIE 3 754 #define EEMWE 2 755 #define EEWE 1 756 #define EERE 0 757 758 /* GTCCR */ 759 #define TSM 7 760 #define PSR2 1 761 #define PSR10 0 762 763 /* TCCR0A */ 764 #define FOC0A 7 765 #define WGM00 6 766 #define COM0A1 5 767 #define COM0A0 4 768 #define WGM01 3 769 #define CS02 2 770 #define CS01 1 771 #define CS00 0 772 773 /* SPCR */ 774 #define SPIE 7 775 #define SPE 6 776 #define DORD 5 777 #define MSTR 4 778 #define CPOL 3 779 #define CPHA 2 780 #define SPR1 1 781 #define SPR0 0 782 783 /* SPSR */ 784 #define SPIF 7 785 #define WCOL 6 786 #define SPI2X 0 787 788 /* ACSR */ 789 #define ACD 7 790 #define ACBG 6 791 #define ACO 5 792 #define ACI 4 793 #define ACIE 3 794 #define ACIC 2 795 #define ACIS1 1 796 #define ACIS0 0 797 798 /* OCDR */ 799 #define IDRD 7 800 #define OCD 7 801 #define OCDR6 6 802 #define OCDR5 5 803 #define OCDR4 4 804 #define OCDR3 3 805 #define OCDR2 2 806 #define OCDR1 1 807 #define OCDR0 0 808 809 /* SMCR */ 810 #define SM2 3 811 #define SM1 2 812 #define SM0 1 813 #define SE 0 814 815 /* MCUSR */ 816 #define JTRF 4 817 #define WDRF 3 818 #define BORF 2 819 #define EXTRF 1 820 #define PORF 0 821 822 /* MCUCR */ 823 #define JTD 7 824 #define PUD 4 825 #define IVSEL 1 826 #define IVCE 0 827 828 /* SPMCSR */ 829 #define SPMIE 7 830 #define RWWSB 6 831 #define RWWSRE 4 832 #define BLBSET 3 833 #define PGWRT 2 834 #define PGERS 1 835 #define SPMEN 0 836 837 /* WDTCR */ 838 #define WDCE 4 839 #define WDE 3 840 #define WDP2 2 841 #define WDP1 1 842 #define WDP0 0 843 844 /* CLKPR */ 845 #define CLKPCE 7 846 #define CLKPS3 3 847 #define CLKPS2 2 848 #define CLKPS1 1 849 #define CLKPS0 0 850 851 /* EICRA */ 852 #define ISC01 1 853 #define ISC00 0 854 855 /* PCMSK0 */ 856 #define PCINT7 7 857 #define PCINT6 6 858 #define PCINT5 5 859 #define PCINT4 4 860 #define PCINT3 3 861 #define PCINT2 2 862 #define PCINT1 1 863 #define PCINT0 0 864 865 /* PCMSK1 */ 866 #define PCINT15 7 867 #define PCINT14 6 868 #define PCINT13 5 869 #define PCINT12 4 870 #define PCINT11 3 871 #define PCINT10 2 872 #define PCINT9 1 873 #define PCINT8 0 874 875 /* TIMSK0 */ 876 #define OCIE0A 1 877 #define TOIE0 0 878 879 /* TIMSK1 */ 880 #define ICIE1 5 881 #define OCIE1B 2 882 #define OCIE1A 1 883 #define TOIE1 0 884 885 /* TIMSK2 */ 886 #define OCIE2A 1 887 #define TOIE2 0 888 889 /* ADCSRA */ 890 #define ADEN 7 891 #define ADSC 6 892 #define ADATE 5 893 #define ADIF 4 894 #define ADIE 3 895 #define ADPS2 2 896 #define ADPS1 1 897 #define ADPS0 0 898 899 /* ADCSRB */ 900 #define ACME 6 901 #define ADTS2 2 902 #define ADTS1 1 903 #define ADTS0 0 904 905 /* ADMUX */ 906 #define REFS1 7 907 #define REFS0 6 908 #define ADLAR 5 909 #define MUX4 4 910 #define MUX3 3 911 #define MUX2 2 912 #define MUX1 1 913 #define MUX0 0 914 915 /* DIDR1 */ 916 #define AIN1D 1 917 #define AIN0D 0 918 919 /* DIDR0 */ 920 #define ADC7D 7 921 #define ADC6D 6 922 #define ADC5D 5 923 #define ADC4D 4 924 #define ADC3D 3 925 #define ADC2D 2 926 #define ADC1D 1 927 #define ADC0D 0 928 929 /* TCCR1A */ 930 #define COM1A1 7 931 #define COM1A0 6 932 #define COM1B1 5 933 #define COM1B0 4 934 #define WGM11 1 935 #define WGM10 0 936 937 /* TCCR1B */ 938 #define ICNC1 7 939 #define ICES1 6 940 #define WGM13 4 941 #define WGM12 3 942 #define CS12 2 943 #define CS11 1 944 #define CS10 0 945 946 /* TCCR1C */ 947 #define FOC1A 7 948 #define FOC1B 6 949 950 /* TCCR2A */ 951 #define FOC2A 7 952 #define WGM20 6 953 #define COM2A1 5 954 #define COM2A0 4 955 #define WGM21 3 956 #define CS22 2 957 #define CS21 1 958 #define CS20 0 959 960 /* ASSR */ 961 #define EXCLK 4 962 #define AS2 3 963 #define TCN2UB 2 964 #define OCR2UB 1 965 #define TCR2UB 0 966 967 /* USICR */ 968 #define USISIE 7 969 #define USIOIE 6 970 #define USIWM1 5 971 #define USIWM0 4 972 #define USICS1 3 973 #define USICS0 2 974 #define USICLK 1 975 #define USITC 0 976 977 /* USISR */ 978 #define USISIF 7 979 #define USIOIF 6 980 #define USIPF 5 981 #define USIDC 4 982 #define USICNT3 3 983 #define USICNT2 2 984 #define USICNT1 1 985 #define USICNT0 0 986 987 /* UCSRA */ 988 #define RXC 7 989 #define TXC 6 990 #define UDRE 5 991 #define FE 4 992 #define DOR 3 993 #define UPE 2 994 #define U2X 1 995 #define MPCM 0 996 997 /* UCSRB */ 998 #define RXCIE 7 999 #define TXCIE 6 1000 #define UDRIE 5 1001 #define RXEN 4 1002 #define TXEN 3 1003 #define UCSZ2 2 1004 #define RXB8 1 1005 #define TXB8 0 1006 1007 /* UCSRC */ 1008 #define UMSEL 6 1009 #define UPM1 5 1010 #define UPM0 4 1011 #define USBS 3 1012 #define UCSZ1 2 1013 #define UCSZ0 1 1014 #define UCPOL 0 1015 1016 /* LCDCRA */ 1017 #define LCDEN 7 1018 #define LCDAB 6 1019 #define LCDIF 4 1020 #define LCDIE 3 1021 #define LCDBD 2 /* Only in Rev. F */ 1022 #define LCDCCD 1 /* Only in Rev. F */ 1023 #define LCDBL 0 1024 1025 /* LCDCRB */ 1026 #define LCDCS 7 1027 #define LCD2B 6 1028 #define LCDMUX1 5 1029 #define LCDMUX0 4 1030 #define LCDPM2 2 1031 #define LCDPM1 1 1032 #define LCDPM0 0 1033 1034 /* LCDFRR */ 1035 #define LCDPS2 6 1036 #define LCDPS1 5 1037 #define LCDPS0 4 1038 #define LCDCD2 2 1039 #define LCDCD1 1 1040 #define LCDCD0 0 1041 1042 /* LCDCCR */ 1043 #define LCDDC2 7 1044 #define LCDDC1 6 1045 #define LCDDC0 5 1046 #define LCDMDT 4 /* Only in Rev. F */ 1047 #define LCDCC3 3 1048 #define LCDCC2 2 1049 #define LCDCC1 1 1050 #define LCDCC0 0 1051 1052 /* LCDDR0-18 */ 1053 #define SEG24 0 1054 1055 #define SEG23 7 1056 #define SEG22 6 1057 #define SEG21 5 1058 #define SEG20 4 1059 #define SEG19 3 1060 #define SEG18 2 1061 #define SEG17 1 1062 #define SEG16 0 1063 1064 #define SEG15 7 1065 #define SEG14 6 1066 #define SEG13 5 1067 #define SEG12 4 1068 #define SEG11 3 1069 #define SEG10 2 1070 #define SEG9 1 1071 #define SEG8 0 1072 1073 #define SEG7 7 1074 #define SEG6 6 1075 #define SEG5 5 1076 #define SEG4 4 1077 #define SEG3 3 1078 #define SEG2 2 1079 #define SEG1 1 1080 #define SEG0 0 1081 1082 /* Constants */ 1083 #define SPM_PAGESIZE 128 1084 #define RAMSTART 0x100 1085 #define RAMEND 0x4FF 1086 #define XRAMEND RAMEND 1087 #define E2END 0x1FF 1088 #define E2PAGESIZE 4 1089 #define FLASHEND 0x3FFF 1090 1091 1092 /* Fuses */ 1093 1094 #define FUSE_MEMORY_SIZE 3 1095 1096 /* Low Fuse Byte */ 1097 #define FUSE_CKSEL0 (unsigned char)~_BV(0) 1098 #define FUSE_CKSEL1 (unsigned char)~_BV(1) 1099 #define FUSE_CKSEL2 (unsigned char)~_BV(2) 1100 #define FUSE_CKSEL3 (unsigned char)~_BV(3) 1101 #define FUSE_SUT0 (unsigned char)~_BV(4) 1102 #define FUSE_SUT1 (unsigned char)~_BV(5) 1103 #define FUSE_CKOUT (unsigned char)~_BV(6) 1104 #define FUSE_CKDIV8 (unsigned char)~_BV(7) 1105 #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) 1106 1107 /* High Fuse Byte */ 1108 #define FUSE_BOOTRST (unsigned char)~_BV(0) 1109 #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) 1110 #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) 1111 #define FUSE_EESAVE (unsigned char)~_BV(3) 1112 #define FUSE_WDTON (unsigned char)~_BV(4) 1113 #define FUSE_SPIEN (unsigned char)~_BV(5) 1114 #define FUSE_JTAGEN (unsigned char)~_BV(6) 1115 #define FUSE_OCDEN (unsigned char)~_BV(7) 1116 #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) 1117 1118 /* Extended Fuse Byte */ 1119 #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) 1120 #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) 1121 #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) 1122 #define EFUSE_DEFAULT (0xFF) 1123 1124 1125 /* Lock Bits */ 1126 #define __LOCK_BITS_EXIST 1127 #define __BOOT_LOCK_BITS_0_EXIST 1128 #define __BOOT_LOCK_BITS_1_EXIST 1129 1130 1131 /* Signature */ 1132 #define SIGNATURE_0 0x1E 1133 #define SIGNATURE_1 0x94 1134 #define SIGNATURE_2 0x05 1135 1136 1137 /* Deprecated items */ 1138 #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) 1139 1140 #pragma GCC system_header 1141 1142 #pragma GCC poison SIG_INTERRUPT0 1143 #pragma GCC poison SIG_PIN_CHANGE0 1144 #pragma GCC poison SIG_PIN_CHANGE1 1145 #pragma GCC poison SIG_OUTPUT_COMPARE2 1146 #pragma GCC poison SIG_OVERFLOW2 1147 #pragma GCC poison SIG_INPUT_CAPTURE1 1148 #pragma GCC poison SIG_OUTPUT_COMPARE1A 1149 #pragma GCC poison SIG_OUTPUT_COMPARE1B 1150 #pragma GCC poison SIG_OVERFLOW1 1151 #pragma GCC poison SIG_OUTPUT_COMPARE0 1152 #pragma GCC poison SIG_OVERFLOW0 1153 #pragma GCC poison SIG_SPI 1154 #pragma GCC poison SIG_USART_RECV 1155 #pragma GCC poison SIG_USART_DATA 1156 #pragma GCC poison SIG_USART_TRANS 1157 #pragma GCC poison SIG_USI_START 1158 #pragma GCC poison SIG_USI_OVERFLOW 1159 #pragma GCC poison SIG_COMPARATOR 1160 #pragma GCC poison SIG_ADC 1161 #pragma GCC poison SIG_EEPROM_READY 1162 #pragma GCC poison SIG_SPM_READY 1163 #pragma GCC poison SIG_LCD 1164 1165 #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ 1166 1167 1168 1169 #define SLEEP_MODE_IDLE (0x00<<1) 1170 #define SLEEP_MODE_ADC (0x01<<1) 1171 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 1172 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 1173 #define SLEEP_MODE_STANDBY (0x06<<1) 1174 1175 1176 #endif /* _AVR_IOM169_H_ */ 1177