1 /* Copyright (c) 2013 Atmel Corporation 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: iom2564rfr2.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 32 33 /* avr/iom2564rfr2.h - definitions for ATmega2564RFR2 */ 34 35 #ifndef _AVR_IOM2564RFR2_H_ 36 #define _AVR_IOM2564RFR2_H_ 1 37 38 /* This file should only be included from <avr/io.h>, never directly. */ 39 40 #ifndef _AVR_IO_H_ 41 # error "Include <avr/io.h> instead of this file." 42 #endif 43 44 #ifndef _AVR_IOXXX_H_ 45 # define _AVR_IOXXX_H_ "iom2564rfr2.h" 46 #else 47 # error "Attempt to include more than one <avr/ioXXX.h> file." 48 #endif 49 50 #include <avr/sfr_defs.h> 51 52 #ifndef __ASSEMBLER__ 53 # define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) 54 # define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) 55 # define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) 56 #endif /* __ASSEMBLER__ */ 57 58 /* 59 * USAGE: 60 * 61 * simple register assignment: 62 * TIFR1 = 0x17 63 * subregister assignment: 64 * TIFR1_struct.ocf1a = 1 65 * (subregister names are converted to small letters) 66 */ 67 68 69 /* Port A Input Pins Address */ 70 #define PINA _SFR_IO8(0x00) 71 72 /* PINA */ 73 74 #define PINA0 0 75 #define PINA1 1 76 #define PINA2 2 77 #define PINA3 3 78 #define PINA4 4 79 #define PINA5 5 80 #define PINA6 6 81 #define PINA7 7 82 83 /* Port A Data Direction Register */ 84 #define DDRA _SFR_IO8(0x01) 85 86 /* DDRA */ 87 88 #define DDA0 0 89 #define DDA1 1 90 #define DDA2 2 91 #define DDA3 3 92 #define DDA4 4 93 #define DDA5 5 94 #define DDA6 6 95 #define DDA7 7 96 97 /* Port A Data Register */ 98 #define PORTA _SFR_IO8(0x02) 99 100 /* PORTA */ 101 102 #define PORTA0 0 103 #define PA0 0 104 #define PORTA1 1 105 #define PA1 1 106 #define PORTA2 2 107 #define PA2 2 108 #define PORTA3 3 109 #define PA3 3 110 #define PORTA4 4 111 #define PA4 4 112 #define PORTA5 5 113 #define PA5 5 114 #define PORTA6 6 115 #define PA6 6 116 #define PORTA7 7 117 #define PA7 7 118 119 /* Port B Input Pins Address */ 120 #define PINB _SFR_IO8(0x03) 121 122 /* PINB */ 123 124 #define PINB0 0 125 #define PINB1 1 126 #define PINB2 2 127 #define PINB3 3 128 #define PINB4 4 129 #define PINB5 5 130 #define PINB6 6 131 #define PINB7 7 132 133 /* Port B Data Direction Register */ 134 #define DDRB _SFR_IO8(0x04) 135 136 /* DDRB */ 137 138 #define DDB0 0 139 #define DDB1 1 140 #define DDB2 2 141 #define DDB3 3 142 #define DDB4 4 143 #define DDB5 5 144 #define DDB6 6 145 #define DDB7 7 146 147 /* Port B Data Register */ 148 #define PORTB _SFR_IO8(0x05) 149 150 /* PORTB */ 151 152 #define PORTB0 0 153 #define PB0 0 154 #define PORTB1 1 155 #define PB1 1 156 #define PORTB2 2 157 #define PB2 2 158 #define PORTB3 3 159 #define PB3 3 160 #define PORTB4 4 161 #define PB4 4 162 #define PORTB5 5 163 #define PB5 5 164 #define PORTB6 6 165 #define PB6 6 166 #define PORTB7 7 167 #define PB7 7 168 169 /* Port C Input Pins Address */ 170 #define PINC _SFR_IO8(0x06) 171 172 /* PINC */ 173 174 #define PINC0 0 175 #define PINC1 1 176 #define PINC2 2 177 #define PINC3 3 178 #define PINC4 4 179 #define PINC5 5 180 #define PINC6 6 181 #define PINC7 7 182 183 /* Port C Data Direction Register */ 184 #define DDRC _SFR_IO8(0x07) 185 186 /* DDRC */ 187 188 #define DDC0 0 189 #define DDC1 1 190 #define DDC2 2 191 #define DDC3 3 192 #define DDC4 4 193 #define DDC5 5 194 #define DDC6 6 195 #define DDC7 7 196 197 /* Port C Data Register */ 198 #define PORTC _SFR_IO8(0x08) 199 200 /* PORTC */ 201 202 #define PORTC0 0 203 #define PC0 0 204 #define PORTC1 1 205 #define PC1 1 206 #define PORTC2 2 207 #define PC2 2 208 #define PORTC3 3 209 #define PC3 3 210 #define PORTC4 4 211 #define PC4 4 212 #define PORTC5 5 213 #define PC5 5 214 #define PORTC6 6 215 #define PC6 6 216 #define PORTC7 7 217 #define PC7 7 218 219 /* Port D Input Pins Address */ 220 #define PIND _SFR_IO8(0x09) 221 222 /* PIND */ 223 224 #define PIND0 0 225 #define PIND1 1 226 #define PIND2 2 227 #define PIND3 3 228 #define PIND4 4 229 #define PIND5 5 230 #define PIND6 6 231 #define PIND7 7 232 233 /* Port D Data Direction Register */ 234 #define DDRD _SFR_IO8(0x0A) 235 236 /* DDRD */ 237 238 #define DDD0 0 239 #define DDD1 1 240 #define DDD2 2 241 #define DDD3 3 242 #define DDD4 4 243 #define DDD5 5 244 #define DDD6 6 245 #define DDD7 7 246 247 /* Port D Data Register */ 248 #define PORTD _SFR_IO8(0x0B) 249 250 /* PORTD */ 251 252 #define PORTD0 0 253 #define PD0 0 254 #define PORTD1 1 255 #define PD1 1 256 #define PORTD2 2 257 #define PD2 2 258 #define PORTD3 3 259 #define PD3 3 260 #define PORTD4 4 261 #define PD4 4 262 #define PORTD5 5 263 #define PD5 5 264 #define PORTD6 6 265 #define PD6 6 266 #define PORTD7 7 267 #define PD7 7 268 269 /* Port E Input Pins Address */ 270 #define PINE _SFR_IO8(0x0C) 271 272 /* PINE */ 273 274 #define PINE0 0 275 #define PINE1 1 276 #define PINE2 2 277 #define PINE3 3 278 #define PINE4 4 279 #define PINE5 5 280 #define PINE6 6 281 #define PINE7 7 282 283 /* Port E Data Direction Register */ 284 #define DDRE _SFR_IO8(0x0D) 285 286 /* DDRE */ 287 288 #define DDE0 0 289 #define DDE1 1 290 #define DDE2 2 291 #define DDE3 3 292 #define DDE4 4 293 #define DDE5 5 294 #define DDE6 6 295 #define DDE7 7 296 297 /* Port E Data Register */ 298 #define PORTE _SFR_IO8(0x0E) 299 300 /* PORTE */ 301 302 #define PORTE0 0 303 #define PE0 0 304 #define PORTE1 1 305 #define PE1 1 306 #define PORTE2 2 307 #define PE2 2 308 #define PORTE3 3 309 #define PE3 3 310 #define PORTE4 4 311 #define PE4 4 312 #define PORTE5 5 313 #define PE5 5 314 #define PORTE6 6 315 #define PE6 6 316 #define PORTE7 7 317 #define PE7 7 318 319 /* Port F Input Pins Address */ 320 #define PINF _SFR_IO8(0x0F) 321 322 /* PINF */ 323 324 #define PINF0 0 325 #define PINF1 1 326 #define PINF2 2 327 #define PINF3 3 328 #define PINF4 4 329 #define PINF5 5 330 #define PINF6 6 331 #define PINF7 7 332 333 /* Port F Data Direction Register */ 334 #define DDRF _SFR_IO8(0x10) 335 336 /* DDRF */ 337 338 #define DDF0 0 339 #define DDF1 1 340 #define DDF2 2 341 #define DDF3 3 342 #define DDF4 4 343 #define DDF5 5 344 #define DDF6 6 345 #define DDF7 7 346 347 /* Port F Data Register */ 348 #define PORTF _SFR_IO8(0x11) 349 350 /* PORTF */ 351 352 #define PORTF0 0 353 #define PF0 0 354 #define PORTF1 1 355 #define PF1 1 356 #define PORTF2 2 357 #define PF2 2 358 #define PORTF3 3 359 #define PF3 3 360 #define PORTF4 4 361 #define PF4 4 362 #define PORTF5 5 363 #define PF5 5 364 #define PORTF6 6 365 #define PF6 6 366 #define PORTF7 7 367 #define PF7 7 368 369 /* Port G Input Pins Address */ 370 #define PING _SFR_IO8(0x12) 371 372 /* PING */ 373 374 #define PING0 0 375 #define PING1 1 376 #define PING2 2 377 #define PING3 3 378 #define PING4 4 379 #define PING5 5 380 381 /* Port G Data Direction Register */ 382 #define DDRG _SFR_IO8(0x13) 383 384 /* DDRG */ 385 386 #define DDG0 0 387 #define DDG1 1 388 #define DDG2 2 389 #define DDG3 3 390 #define DDG4 4 391 #define DDG5 5 392 393 /* Port G Data Register */ 394 #define PORTG _SFR_IO8(0x14) 395 396 /* PORTG */ 397 398 #define PORTG0 0 399 #define PG0 0 400 #define PORTG1 1 401 #define PG1 1 402 #define PORTG2 2 403 #define PG2 2 404 #define PORTG3 3 405 #define PG3 3 406 #define PORTG4 4 407 #define PG4 4 408 #define PORTG5 5 409 #define PG5 5 410 411 /* Timer/Counter0 Interrupt Flag Register */ 412 #define TIFR0 _SFR_IO8(0x15) 413 414 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 415 416 struct __reg_TIFR0 { 417 unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ 418 unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ 419 unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ 420 unsigned int : 5; 421 }; 422 423 #define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) 424 425 #endif /* __ASSEMBLER__ */ 426 427 /* TIFR0 */ 428 429 #define TOV0 0 430 #define OCF0A 1 431 #define OCF0B 2 432 433 /* Timer/Counter1 Interrupt Flag Register */ 434 #define TIFR1 _SFR_IO8(0x16) 435 436 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 437 438 struct __reg_TIFR1 { 439 unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ 440 unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ 441 unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ 442 unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ 443 unsigned int : 1; 444 unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ 445 unsigned int : 2; 446 }; 447 448 #define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) 449 450 #endif /* __ASSEMBLER__ */ 451 452 /* TIFR1 */ 453 454 #define TOV1 0 455 #define OCF1A 1 456 #define OCF1B 2 457 #define OCF1C 3 458 #define ICF1 5 459 460 /* Timer/Counter Interrupt Flag Register */ 461 #define TIFR2 _SFR_IO8(0x17) 462 463 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 464 465 struct __reg_TIFR2 { 466 unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ 467 unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ 468 unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ 469 unsigned int : 5; 470 }; 471 472 #define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) 473 474 #endif /* __ASSEMBLER__ */ 475 476 /* TIFR2 */ 477 478 #define TOV2 0 479 #define OCF2A 1 480 #define OCF2B 2 481 482 /* Timer/Counter3 Interrupt Flag Register */ 483 #define TIFR3 _SFR_IO8(0x18) 484 485 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 486 487 struct __reg_TIFR3 { 488 unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ 489 unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ 490 unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ 491 unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ 492 unsigned int : 1; 493 unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ 494 unsigned int : 2; 495 }; 496 497 #define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) 498 499 #endif /* __ASSEMBLER__ */ 500 501 /* TIFR3 */ 502 503 #define TOV3 0 504 #define OCF3A 1 505 #define OCF3B 2 506 #define OCF3C 3 507 #define ICF3 5 508 509 /* Timer/Counter4 Interrupt Flag Register */ 510 #define TIFR4 _SFR_IO8(0x19) 511 512 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 513 514 struct __reg_TIFR4 { 515 unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ 516 unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ 517 unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ 518 unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ 519 unsigned int : 1; 520 unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ 521 unsigned int : 2; 522 }; 523 524 #define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) 525 526 #endif /* __ASSEMBLER__ */ 527 528 /* TIFR4 */ 529 530 #define TOV4 0 531 #define OCF4A 1 532 #define OCF4B 2 533 #define OCF4C 3 534 #define ICF4 5 535 536 /* Timer/Counter5 Interrupt Flag Register */ 537 #define TIFR5 _SFR_IO8(0x1A) 538 539 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 540 541 struct __reg_TIFR5 { 542 unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ 543 unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ 544 unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ 545 unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ 546 unsigned int : 1; 547 unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ 548 unsigned int : 2; 549 }; 550 551 #define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) 552 553 #endif /* __ASSEMBLER__ */ 554 555 /* TIFR5 */ 556 557 #define TOV5 0 558 #define OCF5A 1 559 #define OCF5B 2 560 #define OCF5C 3 561 #define ICF5 5 562 563 /* Pin Change Interrupt Flag Register */ 564 #define PCIFR _SFR_IO8(0x1B) 565 566 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 567 568 struct __reg_PCIFR { 569 unsigned int pcif : 3; /* Pin Change Interrupt Flags */ 570 unsigned int : 5; 571 }; 572 573 #define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) 574 575 #endif /* __ASSEMBLER__ */ 576 577 /* PCIFR */ 578 579 #define PCIF0 0 580 #define PCIF1 1 581 #define PCIF2 2 582 583 /* External Interrupt Flag Register */ 584 #define EIFR _SFR_IO8(0x1C) 585 586 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 587 588 struct __reg_EIFR { 589 unsigned int intf : 8; /* External Interrupt Flag */ 590 }; 591 592 #define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) 593 594 #endif /* __ASSEMBLER__ */ 595 596 /* EIFR */ 597 598 #define INTF0 0 599 #define INTF1 1 600 #define INTF2 2 601 #define INTF3 3 602 #define INTF4 4 603 #define INTF5 5 604 #define INTF6 6 605 #define INTF7 7 606 607 /* External Interrupt Mask Register */ 608 #define EIMSK _SFR_IO8(0x1D) 609 610 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 611 612 struct __reg_EIMSK { 613 unsigned int intm : 8; /* External Interrupt Request Enable */ 614 }; 615 616 #define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) 617 618 #endif /* __ASSEMBLER__ */ 619 620 /* EIMSK */ 621 622 #define INT0 0 623 #define INT1 1 624 #define INT2 2 625 #define INT3 3 626 #define INT4 4 627 #define INT5 5 628 #define INT6 6 629 #define INT7 7 630 631 /* General Purpose IO Register 0 */ 632 #define GPIOR0 _SFR_IO8(0x1E) 633 634 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 635 636 struct __reg_GPIOR0 { 637 unsigned int gpior00 : 1; /* General Purpose I/O Register 0 Value */ 638 unsigned int gpior01 : 1; /* General Purpose I/O Register 0 Value */ 639 unsigned int gpior02 : 1; /* General Purpose I/O Register 0 Value */ 640 unsigned int gpior03 : 1; /* General Purpose I/O Register 0 Value */ 641 unsigned int gpior04 : 1; /* General Purpose I/O Register 0 Value */ 642 unsigned int gpior05 : 1; /* General Purpose I/O Register 0 Value */ 643 unsigned int gpior06 : 1; /* General Purpose I/O Register 0 Value */ 644 unsigned int gpior07 : 1; /* General Purpose I/O Register 0 Value */ 645 }; 646 647 #define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) 648 649 #endif /* __ASSEMBLER__ */ 650 651 /* GPIOR0 */ 652 653 #define GPIOR00 0 654 #define GPIOR01 1 655 #define GPIOR02 2 656 #define GPIOR03 3 657 #define GPIOR04 4 658 #define GPIOR05 5 659 #define GPIOR06 6 660 #define GPIOR07 7 661 662 /* 6-char sequence denoting where to find the EEPROM registers in memory space. 663 Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM 664 subroutines. 665 First two letters: EECR address. 666 Second two letters: EEDR address. 667 Last two letters: EEAR address. */ 668 669 #define __EEPROM_REG_LOCATIONS__ 1F2021 670 671 /* EEPROM Control Register */ 672 #define EECR _SFR_IO8(0x1F) 673 674 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 675 676 struct __reg_EECR { 677 unsigned int eere : 1; /* EEPROM Read Enable */ 678 unsigned int eepe : 1; /* EEPROM Programming Enable */ 679 unsigned int eempe : 1; /* EEPROM Master Write Enable */ 680 unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ 681 unsigned int eepm : 2; /* EEPROM Programming Mode */ 682 unsigned int : 2; 683 }; 684 685 #define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) 686 687 #endif /* __ASSEMBLER__ */ 688 689 /* EECR */ 690 691 #define EERE 0 692 #define EEPE 1 693 #define EEMPE 2 694 #define EERIE 3 695 #define EEPM0 4 696 #define EEPM1 5 697 698 /* EEPROM Data Register */ 699 #define EEDR _SFR_IO8(0x20) 700 701 /* EEDR */ 702 703 #define EEDR0 0 704 #define EEDR1 1 705 #define EEDR2 2 706 #define EEDR3 3 707 #define EEDR4 4 708 #define EEDR5 5 709 #define EEDR6 6 710 #define EEDR7 7 711 712 /* EEPROM Address Register Bytes */ 713 #define EEAR _SFR_IO16(0x21) 714 #define EEARL _SFR_IO8(0x21) 715 #define EEARH _SFR_IO8(0x22) 716 717 /* General Timer/Counter Control Register */ 718 #define GTCCR _SFR_IO8(0x23) 719 720 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 721 722 struct __reg_GTCCR { 723 unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ 724 unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ 725 unsigned int : 5; 726 unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ 727 }; 728 729 #define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) 730 731 #endif /* __ASSEMBLER__ */ 732 733 /* GTCCR */ 734 735 #define PSRSYNC 0 736 #define PSR10 0 737 #define PSRASY 1 738 #define PSR2 1 739 #define TSM 7 740 741 /* Timer/Counter0 Control Register A */ 742 #define TCCR0A _SFR_IO8(0x24) 743 744 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 745 746 struct __reg_TCCR0A { 747 unsigned int wgm0 : 2; /* Waveform Generation Mode */ 748 unsigned int : 2; 749 unsigned int com0b : 2; /* Compare Match Output B Mode */ 750 unsigned int com0a : 2; /* Compare Match Output A Mode */ 751 }; 752 753 #define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) 754 755 #endif /* __ASSEMBLER__ */ 756 757 /* TCCR0A */ 758 759 #define WGM00 0 760 #define WGM01 1 761 #define COM0B0 4 762 #define COM0B1 5 763 #define COM0A0 6 764 #define COM0A1 7 765 766 /* Timer/Counter0 Control Register B */ 767 #define TCCR0B _SFR_IO8(0x25) 768 769 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 770 771 struct __reg_TCCR0B { 772 unsigned int cs0 : 3; /* Clock Select */ 773 unsigned int wgm02 : 1; /* Waveform Generation Mode */ 774 unsigned int : 2; 775 unsigned int foc0b : 1; /* Force Output Compare B */ 776 unsigned int foc0a : 1; /* Force Output Compare A */ 777 }; 778 779 #define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) 780 781 #endif /* __ASSEMBLER__ */ 782 783 /* TCCR0B */ 784 785 #define CS00 0 786 #define CS01 1 787 #define CS02 2 788 #define WGM02 3 789 #define FOC0B 6 790 #define FOC0A 7 791 792 /* Timer/Counter0 Register */ 793 #define TCNT0 _SFR_IO8(0x26) 794 795 /* TCNT0 */ 796 797 #define TCNT0_0 0 798 #define TCNT0_1 1 799 #define TCNT0_2 2 800 #define TCNT0_3 3 801 #define TCNT0_4 4 802 #define TCNT0_5 5 803 #define TCNT0_6 6 804 #define TCNT0_7 7 805 806 /* Timer/Counter0 Output Compare Register */ 807 #define OCR0A _SFR_IO8(0x27) 808 809 /* OCR0A */ 810 811 #define OCR0A_0 0 812 #define OCR0A_1 1 813 #define OCR0A_2 2 814 #define OCR0A_3 3 815 #define OCR0A_4 4 816 #define OCR0A_5 5 817 #define OCR0A_6 6 818 #define OCR0A_7 7 819 820 /* Timer/Counter0 Output Compare Register B */ 821 #define OCR0B _SFR_IO8(0x28) 822 823 /* OCR0B */ 824 825 #define OCR0B_0 0 826 #define OCR0B_1 1 827 #define OCR0B_2 2 828 #define OCR0B_3 3 829 #define OCR0B_4 4 830 #define OCR0B_5 5 831 #define OCR0B_6 6 832 #define OCR0B_7 7 833 834 /* General Purpose IO Register 1 */ 835 #define GPIOR1 _SFR_IO8(0x2A) 836 837 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 838 839 struct __reg_GPIOR1 { 840 unsigned int gpior : 8; /* General Purpose I/O Register 1 Value */ 841 }; 842 843 #define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) 844 845 #endif /* __ASSEMBLER__ */ 846 847 /* GPIOR1 */ 848 849 #define GPIOR10 0 850 #define GPIOR11 1 851 #define GPIOR12 2 852 #define GPIOR13 3 853 #define GPIOR14 4 854 #define GPIOR15 5 855 #define GPIOR16 6 856 #define GPIOR17 7 857 858 /* General Purpose I/O Register 2 */ 859 #define GPIOR2 _SFR_IO8(0x2B) 860 861 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 862 863 struct __reg_GPIOR2 { 864 unsigned int gpior : 8; /* General Purpose I/O Register 2 Value */ 865 }; 866 867 #define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) 868 869 #endif /* __ASSEMBLER__ */ 870 871 /* GPIOR2 */ 872 873 #define GPIOR20 0 874 #define GPIOR21 1 875 #define GPIOR22 2 876 #define GPIOR23 3 877 #define GPIOR24 4 878 #define GPIOR25 5 879 #define GPIOR26 6 880 #define GPIOR27 7 881 882 /* SPI Control Register */ 883 #define SPCR _SFR_IO8(0x2C) 884 885 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 886 887 struct __reg_SPCR { 888 unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ 889 unsigned int cpha : 1; /* Clock Phase */ 890 unsigned int cpol : 1; /* Clock polarity */ 891 unsigned int mstr : 1; /* Master/Slave Select */ 892 unsigned int dord : 1; /* Data Order */ 893 unsigned int spe : 1; /* SPI Enable */ 894 unsigned int spie : 1; /* SPI Interrupt Enable */ 895 }; 896 897 #define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) 898 899 #endif /* __ASSEMBLER__ */ 900 901 /* SPCR */ 902 903 #define SPR0 0 904 #define SPR1 1 905 #define CPHA 2 906 #define CPOL 3 907 #define MSTR 4 908 #define DORD 5 909 #define SPE 6 910 #define SPIE 7 911 912 /* SPI Status Register */ 913 #define SPSR _SFR_IO8(0x2D) 914 915 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 916 917 struct __reg_SPSR { 918 unsigned int spi2x : 1; /* Double SPI Speed Bit */ 919 unsigned int : 5; 920 unsigned int wcol : 1; /* Write Collision Flag */ 921 unsigned int spif : 1; /* SPI Interrupt Flag */ 922 }; 923 924 #define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) 925 926 #endif /* __ASSEMBLER__ */ 927 928 /* SPSR */ 929 930 #define SPI2X 0 931 #define WCOL 6 932 #define SPIF 7 933 934 /* SPI Data Register */ 935 #define SPDR _SFR_IO8(0x2E) 936 937 /* SPDR */ 938 939 #define SPDR0 0 940 #define SPDR1 1 941 #define SPDR2 2 942 #define SPDR3 3 943 #define SPDR4 4 944 #define SPDR5 5 945 #define SPDR6 6 946 #define SPDR7 7 947 948 /* Analog Comparator Control And Status Register */ 949 #define ACSR _SFR_IO8(0x30) 950 951 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 952 953 struct __reg_ACSR { 954 unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ 955 unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ 956 unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ 957 unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ 958 unsigned int aco : 1; /* Analog Compare Output */ 959 unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ 960 unsigned int acd : 1; /* Analog Comparator Disable */ 961 }; 962 963 #define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) 964 965 #endif /* __ASSEMBLER__ */ 966 967 /* ACSR */ 968 969 #define ACIS0 0 970 #define ACIS1 1 971 #define ACIC 2 972 #define ACIE 3 973 #define ACI 4 974 #define ACO 5 975 #define ACBG 6 976 #define ACD 7 977 978 /* On-Chip Debug Register */ 979 #define OCDR _SFR_IO8(0x31) 980 981 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 982 983 struct __reg_OCDR { 984 unsigned int ocdr : 8; /* On-Chip Debug Register Data */ 985 }; 986 987 #define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) 988 989 #endif /* __ASSEMBLER__ */ 990 991 /* OCDR */ 992 993 #define OCDR0 0 994 #define OCDR1 1 995 #define OCDR2 2 996 #define OCDR3 3 997 #define OCDR4 4 998 #define OCDR5 5 999 #define OCDR6 6 1000 #define OCDR7 7 1001 #define IDRD 7 1002 1003 /* Sleep Mode Control Register */ 1004 #define SMCR _SFR_IO8(0x33) 1005 1006 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1007 1008 struct __reg_SMCR { 1009 unsigned int se : 1; /* Sleep Enable */ 1010 unsigned int sm : 3; /* Sleep Mode Select bits */ 1011 unsigned int : 4; 1012 }; 1013 1014 #define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) 1015 1016 #endif /* __ASSEMBLER__ */ 1017 1018 /* SMCR */ 1019 1020 #define SE 0 1021 #define SM0 1 1022 #define SM1 2 1023 #define SM2 3 1024 1025 /* MCU Status Register */ 1026 #define MCUSR _SFR_IO8(0x34) 1027 1028 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1029 1030 struct __reg_MCUSR { 1031 unsigned int porf : 1; /* Power-on Reset Flag */ 1032 unsigned int extrf : 1; /* External Reset Flag */ 1033 unsigned int borf : 1; /* Brown-out Reset Flag */ 1034 unsigned int wdrf : 1; /* Watchdog Reset Flag */ 1035 unsigned int jtrf : 1; /* JTAG Reset Flag */ 1036 unsigned int : 3; 1037 }; 1038 1039 #define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) 1040 1041 #endif /* __ASSEMBLER__ */ 1042 1043 /* MCUSR */ 1044 1045 #define PORF 0 1046 #define EXTRF 1 1047 #define BORF 2 1048 #define WDRF 3 1049 #define JTRF 4 1050 1051 /* MCU Control Register */ 1052 #define MCUCR _SFR_IO8(0x35) 1053 1054 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1055 1056 struct __reg_MCUCR { 1057 unsigned int ivce : 1; /* Interrupt Vector Change Enable */ 1058 unsigned int ivsel : 1; /* Interrupt Vector Select */ 1059 unsigned int : 2; 1060 unsigned int pud : 1; /* Pull-up Disable */ 1061 unsigned int : 2; 1062 unsigned int jtd : 1; /* JTAG Interface Disable */ 1063 }; 1064 1065 #define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) 1066 1067 #endif /* __ASSEMBLER__ */ 1068 1069 /* MCUCR */ 1070 1071 #define IVCE 0 1072 #define IVSEL 1 1073 #define PUD 4 1074 #define JTD 7 1075 1076 /* Store Program Memory Control Register */ 1077 #define SPMCSR _SFR_IO8(0x37) 1078 1079 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1080 1081 struct __reg_SPMCSR { 1082 unsigned int spmen : 1; /* Store Program Memory Enable */ 1083 unsigned int pgers : 1; /* Page Erase */ 1084 unsigned int pgwrt : 1; /* Page Write */ 1085 unsigned int blbset : 1; /* Boot Lock Bit Set */ 1086 unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ 1087 unsigned int sigrd : 1; /* Signature Row Read */ 1088 unsigned int rwwsb : 1; /* Read While Write Section Busy */ 1089 unsigned int spmie : 1; /* SPM Interrupt Enable */ 1090 }; 1091 1092 #define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) 1093 1094 #endif /* __ASSEMBLER__ */ 1095 1096 /* SPMCSR */ 1097 1098 #define SPMEN 0 1099 #define PGERS 1 1100 #define PGWRT 2 1101 #define BLBSET 3 1102 #define RWWSRE 4 1103 #define SIGRD 5 1104 #define RWWSB 6 1105 #define SPMIE 7 1106 1107 /* Extended Z-pointer Register for ELPM/SPM */ 1108 #define RAMPZ _SFR_IO8(0x3B) 1109 1110 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1111 1112 struct __reg_RAMPZ { 1113 unsigned int rampz : 2; /* Extended Z-Pointer Value */ 1114 unsigned int : 6; 1115 }; 1116 1117 #define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ) 1118 1119 #endif /* __ASSEMBLER__ */ 1120 1121 /* RAMPZ */ 1122 1123 #define RAMPZ0 0 1124 #define RAMPZ1 1 1125 1126 /* Extended Indirect Register */ 1127 #define EIND _SFR_IO8(0x3C) 1128 1129 /* EIND */ 1130 1131 #define EIND0 0 1132 1133 /* Stack Pointer */ 1134 #define SP _SFR_IO16(0x3D) 1135 #define SPL _SFR_IO8(0x3D) 1136 #define SPH _SFR_IO8(0x3E) 1137 1138 /* Status Register */ 1139 #define SREG _SFR_IO8(0x3F) 1140 1141 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1142 1143 struct __reg_SREG { 1144 unsigned int c : 1; /* Carry Flag */ 1145 unsigned int z : 1; /* Zero Flag */ 1146 unsigned int n : 1; /* Negative Flag */ 1147 unsigned int v : 1; /* Two's Complement Overflow Flag */ 1148 unsigned int s : 1; /* Sign Bit */ 1149 unsigned int h : 1; /* Half Carry Flag */ 1150 unsigned int t : 1; /* Bit Copy Storage */ 1151 unsigned int i : 1; /* Global Interrupt Enable */ 1152 }; 1153 1154 #define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) 1155 1156 #endif /* __ASSEMBLER__ */ 1157 1158 /* SREG */ 1159 1160 #define SREG_C 0 1161 #define SREG_Z 1 1162 #define SREG_N 2 1163 #define SREG_V 3 1164 #define SREG_S 4 1165 #define SREG_H 5 1166 #define SREG_T 6 1167 #define SREG_I 7 1168 1169 /* Watchdog Timer Control Register */ 1170 #define WDTCSR _SFR_MEM8(0x60) 1171 1172 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1173 1174 struct __reg_WDTCSR { 1175 unsigned int wdp : 3; /* Watchdog Timer Prescaler Bits */ 1176 unsigned int wde : 1; /* Watch Dog Enable */ 1177 unsigned int wdce : 1; /* Watchdog Change Enable */ 1178 unsigned int : 1; 1179 unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ 1180 unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ 1181 }; 1182 1183 #define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) 1184 1185 #endif /* __ASSEMBLER__ */ 1186 1187 /* WDTCSR */ 1188 1189 #define WDP0 0 1190 #define WDP1 1 1191 #define WDP2 2 1192 #define WDE 3 1193 #define WDCE 4 1194 #define WDP3 5 1195 #define WDIE 6 1196 #define WDIF 7 1197 1198 /* Clock Prescale Register */ 1199 #define CLKPR _SFR_MEM8(0x61) 1200 1201 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1202 1203 struct __reg_CLKPR { 1204 unsigned int clkps : 4; /* Clock Prescaler Select Bits */ 1205 unsigned int : 3; 1206 unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ 1207 }; 1208 1209 #define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) 1210 1211 #endif /* __ASSEMBLER__ */ 1212 1213 /* CLKPR */ 1214 1215 #define CLKPS0 0 1216 #define CLKPS1 1 1217 #define CLKPS2 2 1218 #define CLKPS3 3 1219 #define CLKPCE 7 1220 1221 /* Power Reduction Register 2 */ 1222 #define PRR2 _SFR_MEM8(0x63) 1223 1224 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1225 1226 struct __reg_PRR2 { 1227 unsigned int prram : 4; /* Power Reduction SRAMs */ 1228 unsigned int : 4; 1229 }; 1230 1231 #define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) 1232 1233 #endif /* __ASSEMBLER__ */ 1234 1235 /* PRR2 */ 1236 1237 #define PRRAM0 0 1238 #define PRRAM1 1 1239 #define PRRAM2 2 1240 #define PRRAM3 3 1241 1242 #define __AVR_HAVE_PRR2 ((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3)) 1243 #define __AVR_HAVE_PRR2_PRRAM0 1244 #define __AVR_HAVE_PRR2_PRRAM1 1245 #define __AVR_HAVE_PRR2_PRRAM2 1246 #define __AVR_HAVE_PRR2_PRRAM3 1247 1248 /* Power Reduction Register0 */ 1249 #define PRR0 _SFR_MEM8(0x64) 1250 1251 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1252 1253 struct __reg_PRR0 { 1254 unsigned int pradc : 1; /* Power Reduction ADC */ 1255 unsigned int prusart0 : 1; /* Power Reduction USART */ 1256 unsigned int prspi : 1; /* Power Reduction Serial Peripheral Interface */ 1257 unsigned int prtim1 : 1; /* Power Reduction Timer/Counter1 */ 1258 unsigned int prpga : 1; /* Power Reduction PGA */ 1259 unsigned int prtim0 : 1; /* Power Reduction Timer/Counter0 */ 1260 unsigned int prtim2 : 1; /* Power Reduction Timer/Counter2 */ 1261 unsigned int prtwi : 1; /* Power Reduction TWI */ 1262 }; 1263 1264 #define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0) 1265 1266 #endif /* __ASSEMBLER__ */ 1267 1268 /* PRR0 */ 1269 1270 #define PRADC 0 1271 #define PRUSART0 1 1272 #define PRSPI 2 1273 #define PRTIM1 3 1274 #define PRPGA 4 1275 #define PRTIM0 5 1276 #define PRTIM2 6 1277 #define PRTWI 7 1278 1279 #define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPGA)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI)) 1280 #define __AVR_HAVE_PRR0_PRADC 1281 #define __AVR_HAVE_PRR0_PRUSART0 1282 #define __AVR_HAVE_PRR0_PRSPI 1283 #define __AVR_HAVE_PRR0_PRTIM1 1284 #define __AVR_HAVE_PRR0_PRPGA 1285 #define __AVR_HAVE_PRR0_PRTIM0 1286 #define __AVR_HAVE_PRR0_PRTIM2 1287 #define __AVR_HAVE_PRR0_PRTWI 1288 1289 /* Power Reduction Register 1 */ 1290 #define PRR1 _SFR_MEM8(0x65) 1291 1292 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1293 1294 struct __reg_PRR1 { 1295 unsigned int prusart1 : 1; /* Power Reduction USART1 */ 1296 unsigned int : 2; 1297 unsigned int prtim3 : 1; /* Power Reduction Timer/Counter3 */ 1298 unsigned int prtim4 : 1; /* Power Reduction Timer/Counter4 */ 1299 unsigned int prtim5 : 1; /* Power Reduction Timer/Counter5 */ 1300 unsigned int prtrx24 : 1; /* Power Reduction Transceiver */ 1301 unsigned int : 1; 1302 }; 1303 1304 #define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1) 1305 1306 #endif /* __ASSEMBLER__ */ 1307 1308 /* PRR1 */ 1309 1310 #define PRUSART1 0 1311 #define PRTIM3 3 1312 #define PRTIM4 4 1313 #define PRTIM5 5 1314 #define PRTRX24 6 1315 1316 #define __AVR_HAVE_PRR1 ((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24)) 1317 #define __AVR_HAVE_PRR1_PRUSART1 1318 #define __AVR_HAVE_PRR1_PRTIM3 1319 #define __AVR_HAVE_PRR1_PRTIM4 1320 #define __AVR_HAVE_PRR1_PRTIM5 1321 #define __AVR_HAVE_PRR1_PRTRX24 1322 1323 /* Oscillator Calibration Value */ 1324 #define OSCCAL _SFR_MEM8(0x66) 1325 1326 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1327 1328 struct __reg_OSCCAL { 1329 unsigned int cal : 8; /* Oscillator Calibration Tuning Value */ 1330 }; 1331 1332 #define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL) 1333 1334 #endif /* __ASSEMBLER__ */ 1335 1336 /* OSCCAL */ 1337 1338 #define CAL0 0 1339 #define CAL1 1 1340 #define CAL2 2 1341 #define CAL3 3 1342 #define CAL4 4 1343 #define CAL5 5 1344 #define CAL6 6 1345 #define CAL7 7 1346 1347 /* Reference Voltage Calibration Register */ 1348 #define BGCR _SFR_MEM8(0x67) 1349 1350 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1351 1352 struct __reg_BGCR { 1353 unsigned int bgcal : 3; /* Coarse Calibration Bits */ 1354 unsigned int bgcal_fine : 4; /* Fine Calibration Bits */ 1355 unsigned int : 1; 1356 }; 1357 1358 #define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR) 1359 1360 #endif /* __ASSEMBLER__ */ 1361 1362 /* BGCR */ 1363 1364 #define BGCAL0 0 1365 #define BGCAL1 1 1366 #define BGCAL2 2 1367 #define BGCAL_FINE0 3 1368 #define BGCAL_FINE1 4 1369 #define BGCAL_FINE2 5 1370 #define BGCAL_FINE3 6 1371 1372 /* Pin Change Interrupt Control Register */ 1373 #define PCICR _SFR_MEM8(0x68) 1374 1375 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1376 1377 struct __reg_PCICR { 1378 unsigned int pcie : 3; /* Pin Change Interrupt Enables */ 1379 unsigned int : 5; 1380 }; 1381 1382 #define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR) 1383 1384 #endif /* __ASSEMBLER__ */ 1385 1386 /* PCICR */ 1387 1388 #define PCIE0 0 1389 #define PCIE1 1 1390 #define PCIE2 2 1391 1392 /* External Interrupt Control Register A */ 1393 #define EICRA _SFR_MEM8(0x69) 1394 1395 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1396 1397 struct __reg_EICRA { 1398 unsigned int isc0 : 2; /* External Interrupt 0 Sense Control Bit */ 1399 unsigned int isc1 : 2; /* External Interrupt 1 Sense Control Bit */ 1400 unsigned int isc2 : 2; /* External Interrupt 2 Sense Control Bit */ 1401 unsigned int isc3 : 2; /* External Interrupt 3 Sense Control Bit */ 1402 }; 1403 1404 #define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA) 1405 1406 #endif /* __ASSEMBLER__ */ 1407 1408 /* EICRA */ 1409 1410 #define ISC00 0 1411 #define ISC01 1 1412 #define ISC10 2 1413 #define ISC11 3 1414 #define ISC20 4 1415 #define ISC21 5 1416 #define ISC30 6 1417 #define ISC31 7 1418 1419 /* External Interrupt Control Register B */ 1420 #define EICRB _SFR_MEM8(0x6A) 1421 1422 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1423 1424 struct __reg_EICRB { 1425 unsigned int isc4 : 2; /* External Interrupt 4 Sense Control Bit */ 1426 unsigned int isc5 : 2; /* External Interrupt 5 Sense Control Bit */ 1427 unsigned int isc6 : 2; /* External Interrupt 6 Sense Control Bit */ 1428 unsigned int isc7 : 2; /* External Interrupt 7 Sense Control Bit */ 1429 }; 1430 1431 #define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB) 1432 1433 #endif /* __ASSEMBLER__ */ 1434 1435 /* EICRB */ 1436 1437 #define ISC40 0 1438 #define ISC41 1 1439 #define ISC50 2 1440 #define ISC51 3 1441 #define ISC60 4 1442 #define ISC61 5 1443 #define ISC70 6 1444 #define ISC71 7 1445 1446 /* Pin Change Mask Register 0 */ 1447 #define PCMSK0 _SFR_MEM8(0x6B) 1448 1449 /* PCMSK0 */ 1450 1451 #define PCINT0 0 1452 #define PCINT1 1 1453 #define PCINT2 2 1454 #define PCINT3 3 1455 #define PCINT4 4 1456 #define PCINT5 5 1457 #define PCINT6 6 1458 #define PCINT7 7 1459 1460 /* Pin Change Mask Register 1 */ 1461 #define PCMSK1 _SFR_MEM8(0x6C) 1462 1463 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1464 1465 struct __reg_PCMSK1 { 1466 unsigned int pcint : 8; /* Pin Change Enable Mask */ 1467 }; 1468 1469 #define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1) 1470 1471 #endif /* __ASSEMBLER__ */ 1472 1473 /* PCMSK1 */ 1474 1475 #define PCINT8 0 1476 #define PCINT9 1 1477 #define PCINT10 2 1478 #define PCINT11 3 1479 #define PCINT12 4 1480 #define PCINT13 5 1481 #define PCINT14 6 1482 #define PCINT15 7 1483 1484 /* Pin Change Mask Register 2 */ 1485 #define PCMSK2 _SFR_MEM8(0x6D) 1486 1487 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1488 1489 struct __reg_PCMSK2 { 1490 unsigned int pcint : 8; /* Pin Change Enable Mask */ 1491 }; 1492 1493 #define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2) 1494 1495 #endif /* __ASSEMBLER__ */ 1496 1497 /* PCMSK2 */ 1498 1499 #define PCINT16 0 1500 #define PCINT17 1 1501 #define PCINT18 2 1502 #define PCINT19 3 1503 #define PCINT20 4 1504 #define PCINT21 5 1505 #define PCINT22 6 1506 #define PCINT23 7 1507 1508 /* Timer/Counter0 Interrupt Mask Register */ 1509 #define TIMSK0 _SFR_MEM8(0x6E) 1510 1511 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1512 1513 struct __reg_TIMSK0 { 1514 unsigned int toie0 : 1; /* Timer/Counter0 Overflow Interrupt Enable */ 1515 unsigned int ocie0a : 1; /* Timer/Counter0 Output Compare Match A Interrupt Enable */ 1516 unsigned int ocie0b : 1; /* Timer/Counter0 Output Compare Match B Interrupt Enable */ 1517 unsigned int : 5; 1518 }; 1519 1520 #define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0) 1521 1522 #endif /* __ASSEMBLER__ */ 1523 1524 /* TIMSK0 */ 1525 1526 #define TOIE0 0 1527 #define OCIE0A 1 1528 #define OCIE0B 2 1529 1530 /* Timer/Counter1 Interrupt Mask Register */ 1531 #define TIMSK1 _SFR_MEM8(0x6F) 1532 1533 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1534 1535 struct __reg_TIMSK1 { 1536 unsigned int toie1 : 1; /* Timer/Counter1 Overflow Interrupt Enable */ 1537 unsigned int ocie1a : 1; /* Timer/Counter1 Output Compare A Match Interrupt Enable */ 1538 unsigned int ocie1b : 1; /* Timer/Counter1 Output Compare B Match Interrupt Enable */ 1539 unsigned int ocie1c : 1; /* Timer/Counter1 Output Compare C Match Interrupt Enable */ 1540 unsigned int : 1; 1541 unsigned int icie1 : 1; /* Timer/Counter1 Input Capture Interrupt Enable */ 1542 unsigned int : 2; 1543 }; 1544 1545 #define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1) 1546 1547 #endif /* __ASSEMBLER__ */ 1548 1549 /* TIMSK1 */ 1550 1551 #define TOIE1 0 1552 #define OCIE1A 1 1553 #define OCIE1B 2 1554 #define OCIE1C 3 1555 #define ICIE1 5 1556 1557 /* Timer/Counter Interrupt Mask register */ 1558 #define TIMSK2 _SFR_MEM8(0x70) 1559 1560 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1561 1562 struct __reg_TIMSK2 { 1563 unsigned int toie2 : 1; /* Timer/Counter2 Overflow Interrupt Enable */ 1564 unsigned int ocie2a : 1; /* Timer/Counter2 Output Compare Match A Interrupt Enable */ 1565 unsigned int ocie2b : 1; /* Timer/Counter2 Output Compare Match B Interrupt Enable */ 1566 unsigned int : 5; 1567 }; 1568 1569 #define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2) 1570 1571 #endif /* __ASSEMBLER__ */ 1572 1573 /* TIMSK2 */ 1574 1575 #define TOIE2 0 1576 #define TOIE2A 0 1577 #define OCIE2A 1 1578 #define OCIE2B 2 1579 1580 /* Timer/Counter3 Interrupt Mask Register */ 1581 #define TIMSK3 _SFR_MEM8(0x71) 1582 1583 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1584 1585 struct __reg_TIMSK3 { 1586 unsigned int toie3 : 1; /* Timer/Counter3 Overflow Interrupt Enable */ 1587 unsigned int ocie3a : 1; /* Timer/Counter3 Output Compare A Match Interrupt Enable */ 1588 unsigned int ocie3b : 1; /* Timer/Counter3 Output Compare B Match Interrupt Enable */ 1589 unsigned int ocie3c : 1; /* Timer/Counter3 Output Compare C Match Interrupt Enable */ 1590 unsigned int : 1; 1591 unsigned int icie3 : 1; /* Timer/Counter3 Input Capture Interrupt Enable */ 1592 unsigned int : 2; 1593 }; 1594 1595 #define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3) 1596 1597 #endif /* __ASSEMBLER__ */ 1598 1599 /* TIMSK3 */ 1600 1601 #define TOIE3 0 1602 #define OCIE3A 1 1603 #define OCIE3B 2 1604 #define OCIE3C 3 1605 #define ICIE3 5 1606 1607 /* Timer/Counter4 Interrupt Mask Register */ 1608 #define TIMSK4 _SFR_MEM8(0x72) 1609 1610 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1611 1612 struct __reg_TIMSK4 { 1613 unsigned int toie4 : 1; /* Timer/Counter4 Overflow Interrupt Enable */ 1614 unsigned int ocie4a : 1; /* Timer/Counter4 Output Compare A Match Interrupt Enable */ 1615 unsigned int ocie4b : 1; /* Timer/Counter4 Output Compare B Match Interrupt Enable */ 1616 unsigned int ocie4c : 1; /* Timer/Counter4 Output Compare C Match Interrupt Enable */ 1617 unsigned int : 1; 1618 unsigned int icie4 : 1; /* Timer/Counter4 Input Capture Interrupt Enable */ 1619 unsigned int : 2; 1620 }; 1621 1622 #define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4) 1623 1624 #endif /* __ASSEMBLER__ */ 1625 1626 /* TIMSK4 */ 1627 1628 #define TOIE4 0 1629 #define OCIE4A 1 1630 #define OCIE4B 2 1631 #define OCIE4C 3 1632 #define ICIE4 5 1633 1634 /* Timer/Counter5 Interrupt Mask Register */ 1635 #define TIMSK5 _SFR_MEM8(0x73) 1636 1637 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1638 1639 struct __reg_TIMSK5 { 1640 unsigned int toie5 : 1; /* Timer/Counter5 Overflow Interrupt Enable */ 1641 unsigned int ocie5a : 1; /* Timer/Counter5 Output Compare A Match Interrupt Enable */ 1642 unsigned int ocie5b : 1; /* Timer/Counter5 Output Compare B Match Interrupt Enable */ 1643 unsigned int ocie5c : 1; /* Timer/Counter5 Output Compare C Match Interrupt Enable */ 1644 unsigned int : 1; 1645 unsigned int icie5 : 1; /* Timer/Counter5 Input Capture Interrupt Enable */ 1646 unsigned int : 2; 1647 }; 1648 1649 #define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5) 1650 1651 #endif /* __ASSEMBLER__ */ 1652 1653 /* TIMSK5 */ 1654 1655 #define TOIE5 0 1656 #define OCIE5A 1 1657 #define OCIE5B 2 1658 #define OCIE5C 3 1659 #define ICIE5 5 1660 1661 /* Flash Extended-Mode Control-Register */ 1662 #define NEMCR _SFR_MEM8(0x75) 1663 1664 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1665 1666 struct __reg_NEMCR { 1667 unsigned int : 4; 1668 unsigned int aeam : 2; /* Address for Extended Address Mode of Extra Rows */ 1669 unsigned int eneam : 1; /* Enable Extended Address Mode for Extra Rows */ 1670 unsigned int : 1; 1671 }; 1672 1673 #define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR) 1674 1675 #endif /* __ASSEMBLER__ */ 1676 1677 /* NEMCR */ 1678 1679 #define AEAM0 4 1680 #define AEAM1 5 1681 #define ENEAM 6 1682 1683 /* The ADC Control and Status Register C */ 1684 #define ADCSRC _SFR_MEM8(0x77) 1685 1686 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1687 1688 struct __reg_ADCSRC { 1689 unsigned int adsut : 5; /* ADC Start-up Time */ 1690 unsigned int res0 : 1; /* Reserved */ 1691 unsigned int adtht : 2; /* ADC Track-and-Hold Time */ 1692 }; 1693 1694 #define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC) 1695 1696 #endif /* __ASSEMBLER__ */ 1697 1698 /* ADCSRC */ 1699 1700 #define ADSUT0 0 1701 #define ADSUT1 1 1702 #define ADSUT2 2 1703 #define ADSUT3 3 1704 #define ADSUT4 4 1705 #define ADTHT0 6 1706 #define ADTHT1 7 1707 1708 /* ADC Data Register Bytes */ 1709 #ifndef __ASSEMBLER__ 1710 #define ADC _SFR_MEM16(0x78) 1711 #define ADCL _SFR_MEM8(0x78) 1712 #define ADCH _SFR_MEM8(0x79) 1713 #endif /* __ASSEMBLER__ */ 1714 #define ADCW _SFR_MEM16(0x78) 1715 #define ADCWL _SFR_MEM8(0x78) 1716 #define ADCWH _SFR_MEM8(0x79) 1717 1718 /* The ADC Control and Status Register A */ 1719 #define ADCSRA _SFR_MEM8(0x7A) 1720 1721 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1722 1723 struct __reg_ADCSRA { 1724 unsigned int adps : 3; /* ADC Prescaler Select Bits */ 1725 unsigned int adie : 1; /* ADC Interrupt Enable */ 1726 unsigned int adif : 1; /* ADC Interrupt Flag */ 1727 unsigned int adate : 1; /* ADC Auto Trigger Enable */ 1728 unsigned int adsc : 1; /* ADC Start Conversion */ 1729 unsigned int aden : 1; /* ADC Enable */ 1730 }; 1731 1732 #define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA) 1733 1734 #endif /* __ASSEMBLER__ */ 1735 1736 /* ADCSRA */ 1737 1738 #define ADPS0 0 1739 #define ADPS1 1 1740 #define ADPS2 2 1741 #define ADIE 3 1742 #define ADIF 4 1743 #define ADATE 5 1744 #define ADSC 6 1745 #define ADEN 7 1746 1747 /* ADC Control and Status Register B */ 1748 #define ADCSRB _SFR_MEM8(0x7B) 1749 1750 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1751 1752 struct __reg_ADCSRB { 1753 unsigned int adts : 3; /* ADC Auto Trigger Source */ 1754 unsigned int mux5 : 1; /* Analog Channel and Gain Selection Bits */ 1755 unsigned int acch : 1; /* Analog Channel Change */ 1756 unsigned int refok : 1; /* Reference Voltage OK */ 1757 unsigned int acme : 1; /* Analog Comparator Multiplexer Enable */ 1758 unsigned int avddok : 1; /* AVDD Supply Voltage OK */ 1759 }; 1760 1761 #define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB) 1762 1763 #endif /* __ASSEMBLER__ */ 1764 1765 /* ADCSRB */ 1766 1767 #define ADTS0 0 1768 #define ADTS1 1 1769 #define ADTS2 2 1770 #define MUX5 3 1771 #define ACCH 4 1772 #define REFOK 5 1773 #define ACME 6 1774 #define AVDDOK 7 1775 1776 /* The ADC Multiplexer Selection Register */ 1777 #define ADMUX _SFR_MEM8(0x7C) 1778 1779 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1780 1781 struct __reg_ADMUX { 1782 unsigned int mux : 5; /* Analog Channel and Gain Selection Bits */ 1783 unsigned int adlar : 1; /* ADC Left Adjust Result */ 1784 unsigned int refs : 2; /* Reference Selection Bits */ 1785 }; 1786 1787 #define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX) 1788 1789 #endif /* __ASSEMBLER__ */ 1790 1791 /* ADMUX */ 1792 1793 #define MUX0 0 1794 #define MUX1 1 1795 #define MUX2 2 1796 #define MUX3 3 1797 #define MUX4 4 1798 #define ADLAR 5 1799 #define REFS0 6 1800 #define REFS1 7 1801 1802 /* Digital Input Disable Register 2 */ 1803 #define DIDR2 _SFR_MEM8(0x7D) 1804 1805 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1806 1807 struct __reg_DIDR2 { 1808 unsigned int adc8d : 1; /* Reserved Bits */ 1809 unsigned int adc9d : 1; /* Reserved Bits */ 1810 unsigned int adc10d : 1; /* Reserved Bits */ 1811 unsigned int adc11d : 1; /* Reserved Bits */ 1812 unsigned int adc12d : 1; /* Reserved Bits */ 1813 unsigned int adc13d : 1; /* Reserved Bits */ 1814 unsigned int adc14d : 1; /* Reserved Bits */ 1815 unsigned int adc15d : 1; /* Reserved Bits */ 1816 }; 1817 1818 #define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2) 1819 1820 #endif /* __ASSEMBLER__ */ 1821 1822 /* DIDR2 */ 1823 1824 #define ADC8D 0 1825 #define ADC9D 1 1826 #define ADC10D 2 1827 #define ADC11D 3 1828 #define ADC12D 4 1829 #define ADC13D 5 1830 #define ADC14D 6 1831 #define ADC15D 7 1832 1833 /* Digital Input Disable Register 0 */ 1834 #define DIDR0 _SFR_MEM8(0x7E) 1835 1836 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1837 1838 struct __reg_DIDR0 { 1839 unsigned int adc0d : 1; /* Disable ADC7:0 Digital Input */ 1840 unsigned int adc1d : 1; /* Disable ADC7:0 Digital Input */ 1841 unsigned int adc2d : 1; /* Disable ADC7:0 Digital Input */ 1842 unsigned int adc3d : 1; /* Disable ADC7:0 Digital Input */ 1843 unsigned int adc4d : 1; /* Disable ADC7:0 Digital Input */ 1844 unsigned int adc5d : 1; /* Disable ADC7:0 Digital Input */ 1845 unsigned int adc6d : 1; /* Disable ADC7:0 Digital Input */ 1846 unsigned int adc7d : 1; /* Disable ADC7:0 Digital Input */ 1847 }; 1848 1849 #define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0) 1850 1851 #endif /* __ASSEMBLER__ */ 1852 1853 /* DIDR0 */ 1854 1855 #define ADC0D 0 1856 #define ADC1D 1 1857 #define ADC2D 2 1858 #define ADC3D 3 1859 #define ADC4D 4 1860 #define ADC5D 5 1861 #define ADC6D 6 1862 #define ADC7D 7 1863 1864 /* Digital Input Disable Register 1 */ 1865 #define DIDR1 _SFR_MEM8(0x7F) 1866 1867 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1868 1869 struct __reg_DIDR1 { 1870 unsigned int ain0d : 1; /* AIN0 Digital Input Disable */ 1871 unsigned int ain1d : 1; /* AIN1 Digital Input Disable */ 1872 unsigned int : 6; 1873 }; 1874 1875 #define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1) 1876 1877 #endif /* __ASSEMBLER__ */ 1878 1879 /* DIDR1 */ 1880 1881 #define AIN0D 0 1882 #define AIN1D 1 1883 1884 /* Timer/Counter1 Control Register A */ 1885 #define TCCR1A _SFR_MEM8(0x80) 1886 1887 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1888 1889 struct __reg_TCCR1A { 1890 unsigned int wgm1 : 2; /* Waveform Generation Mode */ 1891 unsigned int com1c : 2; /* Compare Output Mode for Channel C */ 1892 unsigned int com1b : 2; /* Compare Output Mode for Channel B */ 1893 unsigned int com1a : 2; /* Compare Output Mode for Channel A */ 1894 }; 1895 1896 #define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A) 1897 1898 #endif /* __ASSEMBLER__ */ 1899 1900 /* TCCR1A */ 1901 1902 #define WGM10 0 1903 #define WGM11 1 1904 #define COM1C0 2 1905 #define COM1C1 3 1906 #define COM1B0 4 1907 #define COM1B1 5 1908 #define COM1A0 6 1909 #define COM1A1 7 1910 1911 /* Timer/Counter1 Control Register B */ 1912 #define TCCR1B _SFR_MEM8(0x81) 1913 1914 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1915 1916 struct __reg_TCCR1B { 1917 unsigned int cs1 : 3; /* Clock Select */ 1918 unsigned int wgm1 : 2; /* Waveform Generation Mode */ 1919 unsigned int : 1; 1920 unsigned int ices1 : 1; /* Input Capture 1 Edge Select */ 1921 unsigned int icnc1 : 1; /* Input Capture 1 Noise Canceller */ 1922 }; 1923 1924 #define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B) 1925 1926 #endif /* __ASSEMBLER__ */ 1927 1928 /* TCCR1B */ 1929 1930 #define CS10 0 1931 #define CS11 1 1932 #define CS12 2 1933 #define WGM12 3 1934 #define WGM13 4 1935 #define ICES1 6 1936 #define ICNC1 7 1937 1938 /* Timer/Counter1 Control Register C */ 1939 #define TCCR1C _SFR_MEM8(0x82) 1940 1941 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1942 1943 struct __reg_TCCR1C { 1944 unsigned int : 5; 1945 unsigned int foc1c : 1; /* Force Output Compare for Channel C */ 1946 unsigned int foc1b : 1; /* Force Output Compare for Channel B */ 1947 unsigned int foc1a : 1; /* Force Output Compare for Channel A */ 1948 }; 1949 1950 #define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C) 1951 1952 #endif /* __ASSEMBLER__ */ 1953 1954 /* TCCR1C */ 1955 1956 #define FOC1C 5 1957 #define FOC1B 6 1958 #define FOC1A 7 1959 1960 /* Timer/Counter1 Bytes */ 1961 #define TCNT1 _SFR_MEM16(0x84) 1962 #define TCNT1L _SFR_MEM8(0x84) 1963 #define TCNT1H _SFR_MEM8(0x85) 1964 1965 /* Timer/Counter1 Input Capture Register Bytes */ 1966 #define ICR1 _SFR_MEM16(0x86) 1967 #define ICR1L _SFR_MEM8(0x86) 1968 #define ICR1H _SFR_MEM8(0x87) 1969 1970 /* Timer/Counter1 Output Compare Register A Bytes */ 1971 #define OCR1A _SFR_MEM16(0x88) 1972 #define OCR1AL _SFR_MEM8(0x88) 1973 #define OCR1AH _SFR_MEM8(0x89) 1974 1975 /* Timer/Counter1 Output Compare Register B Bytes */ 1976 #define OCR1B _SFR_MEM16(0x8A) 1977 #define OCR1BL _SFR_MEM8(0x8A) 1978 #define OCR1BH _SFR_MEM8(0x8B) 1979 1980 /* Timer/Counter1 Output Compare Register C Bytes */ 1981 #define OCR1C _SFR_MEM16(0x8C) 1982 #define OCR1CL _SFR_MEM8(0x8C) 1983 #define OCR1CH _SFR_MEM8(0x8D) 1984 1985 /* Timer/Counter3 Control Register A */ 1986 #define TCCR3A _SFR_MEM8(0x90) 1987 1988 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1989 1990 struct __reg_TCCR3A { 1991 unsigned int wgm3 : 2; /* Waveform Generation Mode */ 1992 unsigned int com3c : 2; /* Compare Output Mode for Channel C */ 1993 unsigned int com3b : 2; /* Compare Output Mode for Channel B */ 1994 unsigned int com3a : 2; /* Compare Output Mode for Channel A */ 1995 }; 1996 1997 #define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A) 1998 1999 #endif /* __ASSEMBLER__ */ 2000 2001 /* TCCR3A */ 2002 2003 #define WGM30 0 2004 #define WGM31 1 2005 #define COM3C0 2 2006 #define COM3C1 3 2007 #define COM3B0 4 2008 #define COM3B1 5 2009 #define COM3A0 6 2010 #define COM3A1 7 2011 2012 /* Timer/Counter3 Control Register B */ 2013 #define TCCR3B _SFR_MEM8(0x91) 2014 2015 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2016 2017 struct __reg_TCCR3B { 2018 unsigned int cs3 : 3; /* Clock Select */ 2019 unsigned int wgm3 : 2; /* Waveform Generation Mode */ 2020 unsigned int : 1; 2021 unsigned int ices3 : 1; /* Input Capture 3 Edge Select */ 2022 unsigned int icnc3 : 1; /* Input Capture 3 Noise Canceller */ 2023 }; 2024 2025 #define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B) 2026 2027 #endif /* __ASSEMBLER__ */ 2028 2029 /* TCCR3B */ 2030 2031 #define CS30 0 2032 #define CS31 1 2033 #define CS32 2 2034 #define WGM32 3 2035 #define WGM33 4 2036 #define ICES3 6 2037 #define ICNC3 7 2038 2039 /* Timer/Counter3 Control Register C */ 2040 #define TCCR3C _SFR_MEM8(0x92) 2041 2042 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2043 2044 struct __reg_TCCR3C { 2045 unsigned int : 5; 2046 unsigned int foc3c : 1; /* Force Output Compare for Channel C */ 2047 unsigned int foc3b : 1; /* Force Output Compare for Channel B */ 2048 unsigned int foc3a : 1; /* Force Output Compare for Channel A */ 2049 }; 2050 2051 #define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C) 2052 2053 #endif /* __ASSEMBLER__ */ 2054 2055 /* TCCR3C */ 2056 2057 #define FOC3C 5 2058 #define FOC3B 6 2059 #define FOC3A 7 2060 2061 /* Timer/Counter3 Bytes */ 2062 #define TCNT3 _SFR_MEM16(0x94) 2063 #define TCNT3L _SFR_MEM8(0x94) 2064 #define TCNT3H _SFR_MEM8(0x95) 2065 2066 /* Timer/Counter3 Input Capture Register Bytes */ 2067 #define ICR3 _SFR_MEM16(0x96) 2068 #define ICR3L _SFR_MEM8(0x96) 2069 #define ICR3H _SFR_MEM8(0x97) 2070 2071 /* Timer/Counter3 Output Compare Register A Bytes */ 2072 #define OCR3A _SFR_MEM16(0x98) 2073 #define OCR3AL _SFR_MEM8(0x98) 2074 #define OCR3AH _SFR_MEM8(0x99) 2075 2076 /* Timer/Counter3 Output Compare Register B Bytes */ 2077 #define OCR3B _SFR_MEM16(0x9A) 2078 #define OCR3BL _SFR_MEM8(0x9A) 2079 #define OCR3BH _SFR_MEM8(0x9B) 2080 2081 /* Timer/Counter3 Output Compare Register C Bytes */ 2082 #define OCR3C _SFR_MEM16(0x9C) 2083 #define OCR3CL _SFR_MEM8(0x9C) 2084 #define OCR3CH _SFR_MEM8(0x9D) 2085 2086 /* Timer/Counter4 Control Register A */ 2087 #define TCCR4A _SFR_MEM8(0xA0) 2088 2089 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2090 2091 struct __reg_TCCR4A { 2092 unsigned int wgm4 : 2; /* Waveform Generation Mode */ 2093 unsigned int com4c : 2; /* Compare Output Mode for Channel C */ 2094 unsigned int com4b : 2; /* Compare Output Mode for Channel B */ 2095 unsigned int com4a : 2; /* Compare Output Mode for Channel A */ 2096 }; 2097 2098 #define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A) 2099 2100 #endif /* __ASSEMBLER__ */ 2101 2102 /* TCCR4A */ 2103 2104 #define WGM40 0 2105 #define WGM41 1 2106 #define COM4C0 2 2107 #define COM4C1 3 2108 #define COM4B0 4 2109 #define COM4B1 5 2110 #define COM4A0 6 2111 #define COM4A1 7 2112 2113 /* Timer/Counter4 Control Register B */ 2114 #define TCCR4B _SFR_MEM8(0xA1) 2115 2116 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2117 2118 struct __reg_TCCR4B { 2119 unsigned int cs4 : 3; /* Clock Select */ 2120 unsigned int wgm4 : 2; /* Waveform Generation Mode */ 2121 unsigned int : 1; 2122 unsigned int ices4 : 1; /* Input Capture 4 Edge Select */ 2123 unsigned int icnc4 : 1; /* Input Capture 4 Noise Canceller */ 2124 }; 2125 2126 #define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B) 2127 2128 #endif /* __ASSEMBLER__ */ 2129 2130 /* TCCR4B */ 2131 2132 #define CS40 0 2133 #define CS41 1 2134 #define CS42 2 2135 #define WGM42 3 2136 #define WGM43 4 2137 #define ICES4 6 2138 #define ICNC4 7 2139 2140 /* Timer/Counter4 Control Register C */ 2141 #define TCCR4C _SFR_MEM8(0xA2) 2142 2143 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2144 2145 struct __reg_TCCR4C { 2146 unsigned int : 5; 2147 unsigned int foc4c : 1; /* Force Output Compare for Channel C */ 2148 unsigned int foc4b : 1; /* Force Output Compare for Channel B */ 2149 unsigned int foc4a : 1; /* Force Output Compare for Channel A */ 2150 }; 2151 2152 #define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C) 2153 2154 #endif /* __ASSEMBLER__ */ 2155 2156 /* TCCR4C */ 2157 2158 #define FOC4C 5 2159 #define FOC4B 6 2160 #define FOC4A 7 2161 2162 /* Timer/Counter4 Bytes */ 2163 #define TCNT4 _SFR_MEM16(0xA4) 2164 #define TCNT4L _SFR_MEM8(0xA4) 2165 #define TCNT4H _SFR_MEM8(0xA5) 2166 2167 /* Timer/Counter4 Input Capture Register Bytes */ 2168 #define ICR4 _SFR_MEM16(0xA6) 2169 #define ICR4L _SFR_MEM8(0xA6) 2170 #define ICR4H _SFR_MEM8(0xA7) 2171 2172 /* Timer/Counter4 Output Compare Register A Bytes */ 2173 #define OCR4A _SFR_MEM16(0xA8) 2174 #define OCR4AL _SFR_MEM8(0xA8) 2175 #define OCR4AH _SFR_MEM8(0xA9) 2176 2177 /* Timer/Counter4 Output Compare Register B Bytes */ 2178 #define OCR4B _SFR_MEM16(0xAA) 2179 #define OCR4BL _SFR_MEM8(0xAA) 2180 #define OCR4BH _SFR_MEM8(0xAB) 2181 2182 /* Timer/Counter4 Output Compare Register C Bytes */ 2183 #define OCR4C _SFR_MEM16(0xAC) 2184 #define OCR4CL _SFR_MEM8(0xAC) 2185 #define OCR4CH _SFR_MEM8(0xAD) 2186 2187 /* Timer/Counter2 Control Register A */ 2188 #define TCCR2A _SFR_MEM8(0xB0) 2189 2190 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2191 2192 struct __reg_TCCR2A { 2193 unsigned int wgm2 : 2; /* Waveform Generation Mode */ 2194 unsigned int : 2; 2195 unsigned int com2b : 2; /* Compare Match Output B Mode */ 2196 unsigned int com2a : 2; /* Compare Match Output A Mode */ 2197 }; 2198 2199 #define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A) 2200 2201 #endif /* __ASSEMBLER__ */ 2202 2203 /* TCCR2A */ 2204 2205 #define WGM20 0 2206 #define WGM21 1 2207 #define COM2B0 4 2208 #define COM2B1 5 2209 #define COM2A0 6 2210 #define COM2A1 7 2211 2212 /* Timer/Counter2 Control Register B */ 2213 #define TCCR2B _SFR_MEM8(0xB1) 2214 2215 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2216 2217 struct __reg_TCCR2B { 2218 unsigned int cs2 : 3; /* Clock Select */ 2219 unsigned int wgm22 : 1; /* Waveform Generation Mode */ 2220 unsigned int : 2; 2221 unsigned int foc2b : 1; /* Force Output Compare B */ 2222 unsigned int foc2a : 1; /* Force Output Compare A */ 2223 }; 2224 2225 #define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B) 2226 2227 #endif /* __ASSEMBLER__ */ 2228 2229 /* TCCR2B */ 2230 2231 #define CS20 0 2232 #define CS21 1 2233 #define CS22 2 2234 #define WGM22 3 2235 #define FOC2B 6 2236 #define FOC2A 7 2237 2238 /* Timer/Counter2 */ 2239 #define TCNT2 _SFR_MEM8(0xB2) 2240 2241 /* TCNT2 */ 2242 2243 #define TCNT20 0 2244 #define TCNT21 1 2245 #define TCNT22 2 2246 #define TCNT23 3 2247 #define TCNT24 4 2248 #define TCNT25 5 2249 #define TCNT26 6 2250 #define TCNT27 7 2251 2252 /* Timer/Counter2 Output Compare Register A */ 2253 #define OCR2A _SFR_MEM8(0xB3) 2254 2255 /* OCR2A */ 2256 2257 #define OCR2A0 0 2258 #define OCR2A1 1 2259 #define OCR2A2 2 2260 #define OCR2A3 3 2261 #define OCR2A4 4 2262 #define OCR2A5 5 2263 #define OCR2A6 6 2264 #define OCR2A7 7 2265 2266 /* Timer/Counter2 Output Compare Register B */ 2267 #define OCR2B _SFR_MEM8(0xB4) 2268 2269 /* OCR2B */ 2270 2271 #define OCR2B0 0 2272 #define OCR2B1 1 2273 #define OCR2B2 2 2274 #define OCR2B3 3 2275 #define OCR2B4 4 2276 #define OCR2B5 5 2277 #define OCR2B6 6 2278 #define OCR2B7 7 2279 2280 /* Asynchronous Status Register */ 2281 #define ASSR _SFR_MEM8(0xB6) 2282 2283 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2284 2285 struct __reg_ASSR { 2286 unsigned int tcr2bub : 1; /* Timer/Counter2 Control Register B Update Busy */ 2287 unsigned int tcr2aub : 1; /* Timer/Counter2 Control Register A Update Busy */ 2288 unsigned int ocr2bub : 1; /* Timer/Counter2 Output Compare Register B Update Busy */ 2289 unsigned int ocr2aub : 1; /* Timer/Counter2 Output Compare Register A Update Busy */ 2290 unsigned int tcn2ub : 1; /* Timer/Counter2 Update Busy */ 2291 unsigned int as2 : 1; /* Timer/Counter2 Asynchronous Mode */ 2292 unsigned int exclk : 1; /* Enable External Clock Input */ 2293 unsigned int exclkamr : 1; /* Enable External Clock Input for AMR */ 2294 }; 2295 2296 #define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR) 2297 2298 #endif /* __ASSEMBLER__ */ 2299 2300 /* ASSR */ 2301 2302 #define TCR2BUB 0 2303 #define TCR2AUB 1 2304 #define OCR2BUB 2 2305 #define OCR2AUB 3 2306 #define TCN2UB 4 2307 #define AS2 5 2308 #define EXCLK 6 2309 #define EXCLKAMR 7 2310 2311 /* TWI Bit Rate Register */ 2312 #define TWBR _SFR_MEM8(0xB8) 2313 2314 /* TWBR */ 2315 2316 #define TWBR0 0 2317 #define TWBR1 1 2318 #define TWBR2 2 2319 #define TWBR3 3 2320 #define TWBR4 4 2321 #define TWBR5 5 2322 #define TWBR6 6 2323 #define TWBR7 7 2324 2325 /* TWI Status Register */ 2326 #define TWSR _SFR_MEM8(0xB9) 2327 2328 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2329 2330 struct __reg_TWSR { 2331 unsigned int twps : 2; /* TWI Prescaler Bits */ 2332 unsigned int : 1; 2333 unsigned int tws : 5; /* TWI Status */ 2334 }; 2335 2336 #define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR) 2337 2338 #endif /* __ASSEMBLER__ */ 2339 2340 /* TWSR */ 2341 2342 #define TWPS0 0 2343 #define TWPS1 1 2344 #define TWS3 3 2345 #define TWS4 4 2346 #define TWS5 5 2347 #define TWS6 6 2348 #define TWS7 7 2349 2350 /* TWI (Slave) Address Register */ 2351 #define TWAR _SFR_MEM8(0xBA) 2352 2353 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2354 2355 struct __reg_TWAR { 2356 unsigned int twgce : 1; /* TWI General Call Recognition Enable Bit */ 2357 unsigned int twa : 7; /* TWI (Slave) Address */ 2358 }; 2359 2360 #define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR) 2361 2362 #endif /* __ASSEMBLER__ */ 2363 2364 /* TWAR */ 2365 2366 #define TWGCE 0 2367 #define TWA0 1 2368 #define TWA1 2 2369 #define TWA2 3 2370 #define TWA3 4 2371 #define TWA4 5 2372 #define TWA5 6 2373 #define TWA6 7 2374 2375 /* TWI Data Register */ 2376 #define TWDR _SFR_MEM8(0xBB) 2377 2378 /* TWDR */ 2379 2380 #define TWD0 0 2381 #define TWD1 1 2382 #define TWD2 2 2383 #define TWD3 3 2384 #define TWD4 4 2385 #define TWD5 5 2386 #define TWD6 6 2387 #define TWD7 7 2388 2389 /* TWI Control Register */ 2390 #define TWCR _SFR_MEM8(0xBC) 2391 2392 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2393 2394 struct __reg_TWCR { 2395 unsigned int twie : 1; /* TWI Interrupt Enable */ 2396 unsigned int : 1; 2397 unsigned int twen : 1; /* TWI Enable Bit */ 2398 unsigned int twwc : 1; /* TWI Write Collision Flag */ 2399 unsigned int twsto : 1; /* TWI STOP Condition Bit */ 2400 unsigned int twsta : 1; /* TWI START Condition Bit */ 2401 unsigned int twea : 1; /* TWI Enable Acknowledge Bit */ 2402 unsigned int twint : 1; /* TWI Interrupt Flag */ 2403 }; 2404 2405 #define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR) 2406 2407 #endif /* __ASSEMBLER__ */ 2408 2409 /* TWCR */ 2410 2411 #define TWIE 0 2412 #define TWEN 2 2413 #define TWWC 3 2414 #define TWSTO 4 2415 #define TWSTA 5 2416 #define TWEA 6 2417 #define TWINT 7 2418 2419 /* TWI (Slave) Address Mask Register */ 2420 #define TWAMR _SFR_MEM8(0xBD) 2421 2422 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2423 2424 struct __reg_TWAMR { 2425 unsigned int : 1; 2426 unsigned int twam : 7; /* TWI Address Mask */ 2427 }; 2428 2429 #define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR) 2430 2431 #endif /* __ASSEMBLER__ */ 2432 2433 /* TWAMR */ 2434 2435 #define TWAM0 1 2436 #define TWAMR0 1 2437 #define TWAM1 2 2438 #define TWAMR1 2 2439 #define TWAM2 3 2440 #define TWAMR2 3 2441 #define TWAM3 4 2442 #define TWAMR3 4 2443 #define TWAM4 5 2444 #define TWAMR4 5 2445 #define TWAM5 6 2446 #define TWAMR5 6 2447 #define TWAM6 7 2448 #define TWAMR6 7 2449 2450 /* Transceiver Interrupt Enable Register 1 */ 2451 #define IRQ_MASK1 _SFR_MEM8(0xBE) 2452 2453 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2454 2455 struct __reg_IRQ_MASK1 { 2456 unsigned int tx_start_en : 1; /* Transmit Start Interrupt enable */ 2457 unsigned int maf_0_ami_en : 1; /* Address Match Interrupt enable Address filter 0 */ 2458 unsigned int maf_1_ami_en : 1; /* Address Match Interrupt enable Address filter 1 */ 2459 unsigned int maf_2_ami_en : 1; /* Address Match Interrupt enable Address filter 2 */ 2460 unsigned int maf_3_ami_en : 1; /* Address Match Interrupt enable Address filter 3 */ 2461 unsigned int : 3; 2462 }; 2463 2464 #define IRQ_MASK1_struct _SFR_MEM8_STRUCT(0xbe, struct __reg_IRQ_MASK1) 2465 2466 #endif /* __ASSEMBLER__ */ 2467 2468 /* IRQ_MASK1 */ 2469 2470 #define TX_START_EN 0 2471 #define MAF_0_AMI_EN 1 2472 #define MAF_1_AMI_EN 2 2473 #define MAF_2_AMI_EN 3 2474 #define MAF_3_AMI_EN 4 2475 2476 /* Transceiver Interrupt Status Register 1 */ 2477 #define IRQ_STATUS1 _SFR_MEM8(0xBF) 2478 2479 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2480 2481 struct __reg_IRQ_STATUS1 { 2482 unsigned int tx_start : 1; /* Transmit Start Interrupt Status */ 2483 unsigned int maf_0_ami : 1; /* Address Match Interrupt Status Address filter 0 */ 2484 unsigned int maf_1_ami : 1; /* Address Match Interrupt Status Address filter 1 */ 2485 unsigned int maf_2_ami : 1; /* Address Match Interrupt Status Address filter 2 */ 2486 unsigned int maf_3_ami : 1; /* Address Match Interrupt Status Address filter 3 */ 2487 unsigned int : 3; 2488 }; 2489 2490 #define IRQ_STATUS1_struct _SFR_MEM8_STRUCT(0xbf, struct __reg_IRQ_STATUS1) 2491 2492 #endif /* __ASSEMBLER__ */ 2493 2494 /* IRQ_STATUS1 */ 2495 2496 #define TX_START 0 2497 #define MAF_0_AMI 1 2498 #define MAF_1_AMI 2 2499 #define MAF_2_AMI 3 2500 #define MAF_3_AMI 4 2501 2502 /* USART0 Control and Status Register A */ 2503 #define UCSR0A _SFR_MEM8(0xC0) 2504 2505 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2506 2507 struct __reg_UCSR0A { 2508 unsigned int mpcm0 : 1; /* Multi-processor Communication Mode */ 2509 unsigned int u2x0 : 1; /* Double the USART Transmission Speed */ 2510 unsigned int upe0 : 1; /* USART Parity Error */ 2511 unsigned int dor0 : 1; /* Data OverRun */ 2512 unsigned int fe0 : 1; /* Frame Error */ 2513 unsigned int udre0 : 1; /* USART Data Register Empty */ 2514 unsigned int txc0 : 1; /* USART Transmit Complete */ 2515 unsigned int rxc0 : 1; /* USART Receive Complete */ 2516 }; 2517 2518 #define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A) 2519 2520 #endif /* __ASSEMBLER__ */ 2521 2522 /* UCSR0A */ 2523 2524 #define MPCM0 0 2525 #define U2X0 1 2526 #define UPE0 2 2527 #define DOR0 3 2528 #define FE0 4 2529 #define UDRE0 5 2530 #define TXC0 6 2531 #define RXC0 7 2532 2533 /* USART0 Control and Status Register B */ 2534 #define UCSR0B _SFR_MEM8(0xC1) 2535 2536 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2537 2538 struct __reg_UCSR0B { 2539 unsigned int txb80 : 1; /* Transmit Data Bit 8 */ 2540 unsigned int rxb80 : 1; /* Receive Data Bit 8 */ 2541 unsigned int ucsz02 : 1; /* Character Size */ 2542 unsigned int txen0 : 1; /* Transmitter Enable */ 2543 unsigned int rxen0 : 1; /* Receiver Enable */ 2544 unsigned int udrie0 : 1; /* USART Data Register Empty Interrupt Enable */ 2545 unsigned int txcie0 : 1; /* TX Complete Interrupt Enable */ 2546 unsigned int rxcie0 : 1; /* RX Complete Interrupt Enable */ 2547 }; 2548 2549 #define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B) 2550 2551 #endif /* __ASSEMBLER__ */ 2552 2553 /* UCSR0B */ 2554 2555 #define TXB80 0 2556 #define RXB80 1 2557 #define UCSZ02 2 2558 #define TXEN0 3 2559 #define RXEN0 4 2560 #define UDRIE0 5 2561 #define TXCIE0 6 2562 #define RXCIE0 7 2563 2564 /* USART0 Control and Status Register C */ 2565 #define UCSR0C _SFR_MEM8(0xC2) 2566 2567 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2568 2569 struct __reg_UCSR0C { 2570 unsigned int ucpol0 : 1; /* Clock Polarity */ 2571 unsigned int ucsz0 : 2; /* Character Size */ 2572 unsigned int ucpha0 : 1; /* Clock Phase */ 2573 unsigned int udord0 : 1; /* Data Order */ 2574 unsigned int usbs0 : 1; /* Stop Bit Select */ 2575 unsigned int upm0 : 2; /* Parity Mode */ 2576 unsigned int umsel0 : 2; /* USART Mode Select */ 2577 }; 2578 2579 #define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C) 2580 2581 #endif /* __ASSEMBLER__ */ 2582 2583 /* UCSR0C */ 2584 2585 #define UCPOL0 0 2586 #define UCPHA0 1 2587 #define UCPHA0 1 2588 #define UCSZ00 1 2589 #define UDORD0 2 2590 #define UDORD0 2 2591 #define UCSZ01 2 2592 #define USBS0 3 2593 #define UPM00 4 2594 #define UPM01 5 2595 #define UMSEL00 6 2596 #define UMSEL0 6 2597 #define UMSEL01 7 2598 #define UMSEL1 7 2599 2600 /* USART0 Baud Rate Register Bytes */ 2601 #define UBRR0 _SFR_MEM16(0xC4) 2602 #define UBRR0L _SFR_MEM8(0xC4) 2603 #define UBRR0H _SFR_MEM8(0xC5) 2604 2605 /* USART0 I/O Data Register */ 2606 #define UDR0 _SFR_MEM8(0xC6) 2607 2608 /* UDR0 */ 2609 2610 #define UDR00 0 2611 #define UDR01 1 2612 #define UDR02 2 2613 #define UDR03 3 2614 #define UDR04 4 2615 #define UDR05 5 2616 #define UDR06 6 2617 #define UDR07 7 2618 2619 /* USART1 Control and Status Register A */ 2620 #define UCSR1A _SFR_MEM8(0xC8) 2621 2622 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2623 2624 struct __reg_UCSR1A { 2625 unsigned int mpcm1 : 1; /* Multi-processor Communication Mode */ 2626 unsigned int u2x1 : 1; /* Double the USART Transmission Speed */ 2627 unsigned int upe1 : 1; /* USART Parity Error */ 2628 unsigned int dor1 : 1; /* Data OverRun */ 2629 unsigned int fe1 : 1; /* Frame Error */ 2630 unsigned int udre1 : 1; /* USART Data Register Empty */ 2631 unsigned int txc1 : 1; /* USART Transmit Complete */ 2632 unsigned int rxc1 : 1; /* USART Receive Complete */ 2633 }; 2634 2635 #define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A) 2636 2637 #endif /* __ASSEMBLER__ */ 2638 2639 /* UCSR1A */ 2640 2641 #define MPCM1 0 2642 #define U2X1 1 2643 #define UPE1 2 2644 #define DOR1 3 2645 #define FE1 4 2646 #define UDRE1 5 2647 #define TXC1 6 2648 #define RXC1 7 2649 2650 /* USART1 Control and Status Register B */ 2651 #define UCSR1B _SFR_MEM8(0xC9) 2652 2653 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2654 2655 struct __reg_UCSR1B { 2656 unsigned int txb81 : 1; /* Transmit Data Bit 8 */ 2657 unsigned int rxb81 : 1; /* Receive Data Bit 8 */ 2658 unsigned int ucsz12 : 1; /* Character Size */ 2659 unsigned int txen1 : 1; /* Transmitter Enable */ 2660 unsigned int rxen1 : 1; /* Receiver Enable */ 2661 unsigned int udrie1 : 1; /* USART Data Register Empty Interrupt Enable */ 2662 unsigned int txcie1 : 1; /* TX Complete Interrupt Enable */ 2663 unsigned int rxcie1 : 1; /* RX Complete Interrupt Enable */ 2664 }; 2665 2666 #define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B) 2667 2668 #endif /* __ASSEMBLER__ */ 2669 2670 /* UCSR1B */ 2671 2672 #define TXB81 0 2673 #define RXB81 1 2674 #define UCSZ12 2 2675 #define TXEN1 3 2676 #define RXEN1 4 2677 #define UDRIE1 5 2678 #define TXCIE1 6 2679 #define RXCIE1 7 2680 2681 /* USART1 Control and Status Register C */ 2682 #define UCSR1C _SFR_MEM8(0xCA) 2683 2684 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2685 2686 struct __reg_UCSR1C { 2687 unsigned int ucpol1 : 1; /* Clock Polarity */ 2688 unsigned int ucsz1 : 2; /* Character Size */ 2689 unsigned int ucpha1 : 1; /* Clock Phase */ 2690 unsigned int udord1 : 1; /* Data Order */ 2691 unsigned int usbs1 : 1; /* Stop Bit Select */ 2692 unsigned int upm1 : 2; /* Parity Mode */ 2693 unsigned int umsel1 : 2; /* USART Mode Select */ 2694 }; 2695 2696 #define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C) 2697 2698 #endif /* __ASSEMBLER__ */ 2699 2700 /* UCSR1C */ 2701 2702 #define UCPOL1 0 2703 #define UCPHA1 1 2704 #define UCPHA1 1 2705 #define UCSZ10 1 2706 #define UDORD1 2 2707 #define UDORD1 2 2708 #define UCSZ11 2 2709 #define USBS1 3 2710 #define UPM10 4 2711 #define UPM11 5 2712 #define UMSEL10 6 2713 #define UMSEL11 7 2714 2715 /* USART1 Baud Rate Register Bytes */ 2716 #define UBRR1 _SFR_MEM16(0xCC) 2717 #define UBRR1L _SFR_MEM8(0xCC) 2718 #define UBRR1H _SFR_MEM8(0xCD) 2719 2720 /* USART1 I/O Data Register */ 2721 #define UDR1 _SFR_MEM8(0xCE) 2722 2723 /* UDR1 */ 2724 2725 #define UDR10 0 2726 #define UDR11 1 2727 #define UDR12 2 2728 #define UDR13 3 2729 #define UDR14 4 2730 #define UDR15 5 2731 #define UDR16 6 2732 #define UDR17 7 2733 2734 /* Symbol Counter Received Frame Timestamp Register LL-Byte */ 2735 #define SCRSTRLL _SFR_MEM8(0xD7) 2736 2737 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2738 2739 struct __reg_SCRSTRLL { 2740 unsigned int scrstrll : 8; /* Symbol Counter Received Frame Timestamp Register LL-Byte */ 2741 }; 2742 2743 #define SCRSTRLL_struct _SFR_MEM8_STRUCT(0xd7, struct __reg_SCRSTRLL) 2744 2745 #endif /* __ASSEMBLER__ */ 2746 2747 /* SCRSTRLL */ 2748 2749 #define SCRSTRLL0 0 2750 #define SCRSTRLL1 1 2751 #define SCRSTRLL2 2 2752 #define SCRSTRLL3 3 2753 #define SCRSTRLL4 4 2754 #define SCRSTRLL5 5 2755 #define SCRSTRLL6 6 2756 #define SCRSTRLL7 7 2757 2758 /* Symbol Counter Received Frame Timestamp Register LH-Byte */ 2759 #define SCRSTRLH _SFR_MEM8(0xD8) 2760 2761 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2762 2763 struct __reg_SCRSTRLH { 2764 unsigned int scrstrlh : 8; /* Symbol Counter Received Frame Timestamp Register LH-Byte */ 2765 }; 2766 2767 #define SCRSTRLH_struct _SFR_MEM8_STRUCT(0xd8, struct __reg_SCRSTRLH) 2768 2769 #endif /* __ASSEMBLER__ */ 2770 2771 /* SCRSTRLH */ 2772 2773 #define SCRSTRLH0 0 2774 #define SCRSTRLH1 1 2775 #define SCRSTRLH2 2 2776 #define SCRSTRLH3 3 2777 #define SCRSTRLH4 4 2778 #define SCRSTRLH5 5 2779 #define SCRSTRLH6 6 2780 #define SCRSTRLH7 7 2781 2782 /* Symbol Counter Received Frame Timestamp Register HL-Byte */ 2783 #define SCRSTRHL _SFR_MEM8(0xD9) 2784 2785 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2786 2787 struct __reg_SCRSTRHL { 2788 unsigned int scrstrhl : 8; /* Symbol Counter Received Frame Timestamp Register HL-Byte */ 2789 }; 2790 2791 #define SCRSTRHL_struct _SFR_MEM8_STRUCT(0xd9, struct __reg_SCRSTRHL) 2792 2793 #endif /* __ASSEMBLER__ */ 2794 2795 /* SCRSTRHL */ 2796 2797 #define SCRSTRHL0 0 2798 #define SCRSTRHL1 1 2799 #define SCRSTRHL2 2 2800 #define SCRSTRHL3 3 2801 #define SCRSTRHL4 4 2802 #define SCRSTRHL5 5 2803 #define SCRSTRHL6 6 2804 #define SCRSTRHL7 7 2805 2806 /* Symbol Counter Received Frame Timestamp Register HH-Byte */ 2807 #define SCRSTRHH _SFR_MEM8(0xDA) 2808 2809 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2810 2811 struct __reg_SCRSTRHH { 2812 unsigned int scrstrhh : 8; /* Symbol Counter Received Frame Timestamp Register HH-Byte */ 2813 }; 2814 2815 #define SCRSTRHH_struct _SFR_MEM8_STRUCT(0xda, struct __reg_SCRSTRHH) 2816 2817 #endif /* __ASSEMBLER__ */ 2818 2819 /* SCRSTRHH */ 2820 2821 #define SCRSTRHH0 0 2822 #define SCRSTRHH1 1 2823 #define SCRSTRHH2 2 2824 #define SCRSTRHH3 3 2825 #define SCRSTRHH4 4 2826 #define SCRSTRHH5 5 2827 #define SCRSTRHH6 6 2828 #define SCRSTRHH7 7 2829 2830 /* Symbol Counter Compare Source Register */ 2831 #define SCCSR _SFR_MEM8(0xDB) 2832 2833 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2834 2835 struct __reg_SCCSR { 2836 unsigned int sccs1 : 2; /* Symbol Counter Compare Source select register for Compare Units */ 2837 unsigned int sccs2 : 2; /* Symbol Counter Compare Source select register for Compare Unit 2 */ 2838 unsigned int sccs3 : 2; /* Symbol Counter Compare Source select register for Compare Unit 3 */ 2839 unsigned int : 2; 2840 }; 2841 2842 #define SCCSR_struct _SFR_MEM8_STRUCT(0xdb, struct __reg_SCCSR) 2843 2844 #endif /* __ASSEMBLER__ */ 2845 2846 /* SCCSR */ 2847 2848 #define SCCS10 0 2849 #define SCCS11 1 2850 #define SCCS20 2 2851 #define SCCS21 3 2852 #define SCCS30 4 2853 #define SCCS31 5 2854 2855 /* Symbol Counter Control Register 0 */ 2856 #define SCCR0 _SFR_MEM8(0xDC) 2857 2858 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2859 2860 struct __reg_SCCR0 { 2861 unsigned int sccmp : 3; /* Symbol Counter Compare Unit 3 Mode select */ 2862 unsigned int sctse : 1; /* Symbol Counter Automatic Timestamping enable */ 2863 unsigned int sccksel : 1; /* Symbol Counter Clock Source select */ 2864 unsigned int scen : 1; /* Symbol Counter enable */ 2865 unsigned int scmbts : 1; /* Manual Beacon Timestamp */ 2866 unsigned int scres : 1; /* Symbol Counter Synchronization */ 2867 }; 2868 2869 #define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0) 2870 2871 #endif /* __ASSEMBLER__ */ 2872 2873 /* SCCR0 */ 2874 2875 #define SCCMP1 0 2876 #define SCCMP2 1 2877 #define SCCMP3 2 2878 #define SCTSE 3 2879 #define SCCKSEL 4 2880 #define SCEN 5 2881 #define SCMBTS 6 2882 #define SCRES 7 2883 2884 /* Symbol Counter Control Register 1 */ 2885 #define SCCR1 _SFR_MEM8(0xDD) 2886 2887 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2888 2889 struct __reg_SCCR1 { 2890 unsigned int scenbo : 1; /* Backoff Slot Counter enable */ 2891 unsigned int sceeclk : 1; /* Enable External Clock Source on PG2 */ 2892 unsigned int scckdiv : 3; /* Clock divider for synchronous clock source (16MHz Transceiver Clock) */ 2893 unsigned int scbtsm : 1; /* Symbol Counter Beacon Timestamp Mask Register */ 2894 unsigned int : 2; 2895 }; 2896 2897 #define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1) 2898 2899 #endif /* __ASSEMBLER__ */ 2900 2901 /* SCCR1 */ 2902 2903 #define SCENBO 0 2904 #define SCEECLK 1 2905 #define SCCKDIV0 2 2906 #define SCCKDIV1 3 2907 #define SCCKDIV2 4 2908 #define SCBTSM 5 2909 2910 /* Symbol Counter Status Register */ 2911 #define SCSR _SFR_MEM8(0xDE) 2912 2913 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2914 2915 struct __reg_SCSR { 2916 unsigned int scbsy : 1; /* Symbol Counter busy */ 2917 unsigned int : 7; 2918 }; 2919 2920 #define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR) 2921 2922 #endif /* __ASSEMBLER__ */ 2923 2924 /* SCSR */ 2925 2926 #define SCBSY 0 2927 2928 /* Symbol Counter Interrupt Mask Register */ 2929 #define SCIRQM _SFR_MEM8(0xDF) 2930 2931 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2932 2933 struct __reg_SCIRQM { 2934 unsigned int irqmcp : 3; /* Symbol Counter Compare Match 3 IRQ enable */ 2935 unsigned int irqmof : 1; /* Symbol Counter Overflow IRQ enable */ 2936 unsigned int irqmbo : 1; /* Backoff Slot Counter IRQ enable */ 2937 unsigned int : 3; 2938 }; 2939 2940 #define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM) 2941 2942 #endif /* __ASSEMBLER__ */ 2943 2944 /* SCIRQM */ 2945 2946 #define IRQMCP1 0 2947 #define IRQMCP2 1 2948 #define IRQMCP3 2 2949 #define IRQMOF 3 2950 #define IRQMBO 4 2951 2952 /* Symbol Counter Interrupt Status Register */ 2953 #define SCIRQS _SFR_MEM8(0xE0) 2954 2955 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2956 2957 struct __reg_SCIRQS { 2958 unsigned int irqscp : 3; /* Compare Unit 3 Compare Match IRQ */ 2959 unsigned int irqsof : 1; /* Symbol Counter Overflow IRQ */ 2960 unsigned int irqsbo : 1; /* Backoff Slot Counter IRQ */ 2961 unsigned int : 3; 2962 }; 2963 2964 #define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS) 2965 2966 #endif /* __ASSEMBLER__ */ 2967 2968 /* SCIRQS */ 2969 2970 #define IRQSCP1 0 2971 #define IRQSCP2 1 2972 #define IRQSCP3 2 2973 #define IRQSOF 3 2974 #define IRQSBO 4 2975 2976 /* Symbol Counter Register LL-Byte */ 2977 #define SCCNTLL _SFR_MEM8(0xE1) 2978 2979 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2980 2981 struct __reg_SCCNTLL { 2982 unsigned int sccntll : 8; /* Symbol Counter Register LL-Byte */ 2983 }; 2984 2985 #define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL) 2986 2987 #endif /* __ASSEMBLER__ */ 2988 2989 /* SCCNTLL */ 2990 2991 #define SCCNTLL0 0 2992 #define SCCNTLL1 1 2993 #define SCCNTLL2 2 2994 #define SCCNTLL3 3 2995 #define SCCNTLL4 4 2996 #define SCCNTLL5 5 2997 #define SCCNTLL6 6 2998 #define SCCNTLL7 7 2999 3000 /* Symbol Counter Register LH-Byte */ 3001 #define SCCNTLH _SFR_MEM8(0xE2) 3002 3003 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3004 3005 struct __reg_SCCNTLH { 3006 unsigned int sccntlh : 8; /* Symbol Counter Register LH-Byte */ 3007 }; 3008 3009 #define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH) 3010 3011 #endif /* __ASSEMBLER__ */ 3012 3013 /* SCCNTLH */ 3014 3015 #define SCCNTLH0 0 3016 #define SCCNTLH1 1 3017 #define SCCNTLH2 2 3018 #define SCCNTLH3 3 3019 #define SCCNTLH4 4 3020 #define SCCNTLH5 5 3021 #define SCCNTLH6 6 3022 #define SCCNTLH7 7 3023 3024 /* Symbol Counter Register HL-Byte */ 3025 #define SCCNTHL _SFR_MEM8(0xE3) 3026 3027 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3028 3029 struct __reg_SCCNTHL { 3030 unsigned int sccnthl : 8; /* Symbol Counter Register HL-Byte */ 3031 }; 3032 3033 #define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL) 3034 3035 #endif /* __ASSEMBLER__ */ 3036 3037 /* SCCNTHL */ 3038 3039 #define SCCNTHL0 0 3040 #define SCCNTHL1 1 3041 #define SCCNTHL2 2 3042 #define SCCNTHL3 3 3043 #define SCCNTHL4 4 3044 #define SCCNTHL5 5 3045 #define SCCNTHL6 6 3046 #define SCCNTHL7 7 3047 3048 /* Symbol Counter Register HH-Byte */ 3049 #define SCCNTHH _SFR_MEM8(0xE4) 3050 3051 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3052 3053 struct __reg_SCCNTHH { 3054 unsigned int sccnthh : 8; /* Symbol Counter Register HH-Byte */ 3055 }; 3056 3057 #define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH) 3058 3059 #endif /* __ASSEMBLER__ */ 3060 3061 /* SCCNTHH */ 3062 3063 #define SCCNTHH0 0 3064 #define SCCNTHH1 1 3065 #define SCCNTHH2 2 3066 #define SCCNTHH3 3 3067 #define SCCNTHH4 4 3068 #define SCCNTHH5 5 3069 #define SCCNTHH6 6 3070 #define SCCNTHH7 7 3071 3072 /* Symbol Counter Beacon Timestamp Register LL-Byte */ 3073 #define SCBTSRLL _SFR_MEM8(0xE5) 3074 3075 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3076 3077 struct __reg_SCBTSRLL { 3078 unsigned int scbtsrll : 8; /* Symbol Counter Beacon Timestamp Register LL-Byte */ 3079 }; 3080 3081 #define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL) 3082 3083 #endif /* __ASSEMBLER__ */ 3084 3085 /* SCBTSRLL */ 3086 3087 #define SCBTSRLL0 0 3088 #define SCBTSRLL1 1 3089 #define SCBTSRLL2 2 3090 #define SCBTSRLL3 3 3091 #define SCBTSRLL4 4 3092 #define SCBTSRLL5 5 3093 #define SCBTSRLL6 6 3094 #define SCBTSRLL7 7 3095 3096 /* Symbol Counter Beacon Timestamp Register LH-Byte */ 3097 #define SCBTSRLH _SFR_MEM8(0xE6) 3098 3099 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3100 3101 struct __reg_SCBTSRLH { 3102 unsigned int scbtsrlh : 8; /* Symbol Counter Beacon Timestamp Register LH-Byte */ 3103 }; 3104 3105 #define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH) 3106 3107 #endif /* __ASSEMBLER__ */ 3108 3109 /* SCBTSRLH */ 3110 3111 #define SCBTSRLH0 0 3112 #define SCBTSRLH1 1 3113 #define SCBTSRLH2 2 3114 #define SCBTSRLH3 3 3115 #define SCBTSRLH4 4 3116 #define SCBTSRLH5 5 3117 #define SCBTSRLH6 6 3118 #define SCBTSRLH7 7 3119 3120 /* Symbol Counter Beacon Timestamp Register HL-Byte */ 3121 #define SCBTSRHL _SFR_MEM8(0xE7) 3122 3123 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3124 3125 struct __reg_SCBTSRHL { 3126 unsigned int scbtsrhl : 8; /* Symbol Counter Beacon Timestamp Register HL-Byte */ 3127 }; 3128 3129 #define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL) 3130 3131 #endif /* __ASSEMBLER__ */ 3132 3133 /* SCBTSRHL */ 3134 3135 #define SCBTSRHL0 0 3136 #define SCBTSRHL1 1 3137 #define SCBTSRHL2 2 3138 #define SCBTSRHL3 3 3139 #define SCBTSRHL4 4 3140 #define SCBTSRHL5 5 3141 #define SCBTSRHL6 6 3142 #define SCBTSRHL7 7 3143 3144 /* Symbol Counter Beacon Timestamp Register HH-Byte */ 3145 #define SCBTSRHH _SFR_MEM8(0xE8) 3146 3147 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3148 3149 struct __reg_SCBTSRHH { 3150 unsigned int scbtsrhh : 8; /* Symbol Counter Beacon Timestamp Register HH-Byte */ 3151 }; 3152 3153 #define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH) 3154 3155 #endif /* __ASSEMBLER__ */ 3156 3157 /* SCBTSRHH */ 3158 3159 #define SCBTSRHH0 0 3160 #define SCBTSRHH1 1 3161 #define SCBTSRHH2 2 3162 #define SCBTSRHH3 3 3163 #define SCBTSRHH4 4 3164 #define SCBTSRHH5 5 3165 #define SCBTSRHH6 6 3166 #define SCBTSRHH7 7 3167 3168 /* Symbol Counter Frame Timestamp Register LL-Byte */ 3169 #define SCTSRLL _SFR_MEM8(0xE9) 3170 3171 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3172 3173 struct __reg_SCTSRLL { 3174 unsigned int sctsrll : 8; /* Symbol Counter Frame Timestamp Register LL-Byte */ 3175 }; 3176 3177 #define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL) 3178 3179 #endif /* __ASSEMBLER__ */ 3180 3181 /* SCTSRLL */ 3182 3183 #define SCTSRLL0 0 3184 #define SCTSRLL1 1 3185 #define SCTSRLL2 2 3186 #define SCTSRLL3 3 3187 #define SCTSRLL4 4 3188 #define SCTSRLL5 5 3189 #define SCTSRLL6 6 3190 #define SCTSRLL7 7 3191 3192 /* Symbol Counter Frame Timestamp Register LH-Byte */ 3193 #define SCTSRLH _SFR_MEM8(0xEA) 3194 3195 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3196 3197 struct __reg_SCTSRLH { 3198 unsigned int sctsrlh : 8; /* Symbol Counter Frame Timestamp Register LH-Byte */ 3199 }; 3200 3201 #define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH) 3202 3203 #endif /* __ASSEMBLER__ */ 3204 3205 /* SCTSRLH */ 3206 3207 #define SCTSRLH0 0 3208 #define SCTSRLH1 1 3209 #define SCTSRLH2 2 3210 #define SCTSRLH3 3 3211 #define SCTSRLH4 4 3212 #define SCTSRLH5 5 3213 #define SCTSRLH6 6 3214 #define SCTSRLH7 7 3215 3216 /* Symbol Counter Frame Timestamp Register HL-Byte */ 3217 #define SCTSRHL _SFR_MEM8(0xEB) 3218 3219 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3220 3221 struct __reg_SCTSRHL { 3222 unsigned int sctsrhl : 8; /* Symbol Counter Frame Timestamp Register HL-Byte */ 3223 }; 3224 3225 #define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL) 3226 3227 #endif /* __ASSEMBLER__ */ 3228 3229 /* SCTSRHL */ 3230 3231 #define SCTSRHL0 0 3232 #define SCTSRHL1 1 3233 #define SCTSRHL2 2 3234 #define SCTSRHL3 3 3235 #define SCTSRHL4 4 3236 #define SCTSRHL5 5 3237 #define SCTSRHL6 6 3238 #define SCTSRHL7 7 3239 3240 /* Symbol Counter Frame Timestamp Register HH-Byte */ 3241 #define SCTSRHH _SFR_MEM8(0xEC) 3242 3243 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3244 3245 struct __reg_SCTSRHH { 3246 unsigned int sctsrhh : 8; /* Symbol Counter Frame Timestamp Register HH-Byte */ 3247 }; 3248 3249 #define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH) 3250 3251 #endif /* __ASSEMBLER__ */ 3252 3253 /* SCTSRHH */ 3254 3255 #define SCTSRHH0 0 3256 #define SCTSRHH1 1 3257 #define SCTSRHH2 2 3258 #define SCTSRHH3 3 3259 #define SCTSRHH4 4 3260 #define SCTSRHH5 5 3261 #define SCTSRHH6 6 3262 #define SCTSRHH7 7 3263 3264 /* Symbol Counter Output Compare Register 3 LL-Byte */ 3265 #define SCOCR3LL _SFR_MEM8(0xED) 3266 3267 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3268 3269 struct __reg_SCOCR3LL { 3270 unsigned int scocr3ll : 8; /* Symbol Counter Output Compare Register 3 LL-Byte */ 3271 }; 3272 3273 #define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL) 3274 3275 #endif /* __ASSEMBLER__ */ 3276 3277 /* SCOCR3LL */ 3278 3279 #define SCOCR3LL0 0 3280 #define SCOCR3LL1 1 3281 #define SCOCR3LL2 2 3282 #define SCOCR3LL3 3 3283 #define SCOCR3LL4 4 3284 #define SCOCR3LL5 5 3285 #define SCOCR3LL6 6 3286 #define SCOCR3LL7 7 3287 3288 /* Symbol Counter Output Compare Register 3 LH-Byte */ 3289 #define SCOCR3LH _SFR_MEM8(0xEE) 3290 3291 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3292 3293 struct __reg_SCOCR3LH { 3294 unsigned int scocr3lh : 8; /* Symbol Counter Output Compare Register 3 LH-Byte */ 3295 }; 3296 3297 #define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH) 3298 3299 #endif /* __ASSEMBLER__ */ 3300 3301 /* SCOCR3LH */ 3302 3303 #define SCOCR3LH0 0 3304 #define SCOCR3LH1 1 3305 #define SCOCR3LH2 2 3306 #define SCOCR3LH3 3 3307 #define SCOCR3LH4 4 3308 #define SCOCR3LH5 5 3309 #define SCOCR3LH6 6 3310 #define SCOCR3LH7 7 3311 3312 /* Symbol Counter Output Compare Register 3 HL-Byte */ 3313 #define SCOCR3HL _SFR_MEM8(0xEF) 3314 3315 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3316 3317 struct __reg_SCOCR3HL { 3318 unsigned int scocr3hl : 8; /* Symbol Counter Output Compare Register 3 HL-Byte */ 3319 }; 3320 3321 #define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL) 3322 3323 #endif /* __ASSEMBLER__ */ 3324 3325 /* SCOCR3HL */ 3326 3327 #define SCOCR3HL0 0 3328 #define SCOCR3HL1 1 3329 #define SCOCR3HL2 2 3330 #define SCOCR3HL3 3 3331 #define SCOCR3HL4 4 3332 #define SCOCR3HL5 5 3333 #define SCOCR3HL6 6 3334 #define SCOCR3HL7 7 3335 3336 /* Symbol Counter Output Compare Register 3 HH-Byte */ 3337 #define SCOCR3HH _SFR_MEM8(0xF0) 3338 3339 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3340 3341 struct __reg_SCOCR3HH { 3342 unsigned int scocr3hh : 8; /* Symbol Counter Output Compare Register 3 HH-Byte */ 3343 }; 3344 3345 #define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH) 3346 3347 #endif /* __ASSEMBLER__ */ 3348 3349 /* SCOCR3HH */ 3350 3351 #define SCOCR3HH0 0 3352 #define SCOCR3HH1 1 3353 #define SCOCR3HH2 2 3354 #define SCOCR3HH3 3 3355 #define SCOCR3HH4 4 3356 #define SCOCR3HH5 5 3357 #define SCOCR3HH6 6 3358 #define SCOCR3HH7 7 3359 3360 /* Symbol Counter Output Compare Register 2 LL-Byte */ 3361 #define SCOCR2LL _SFR_MEM8(0xF1) 3362 3363 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3364 3365 struct __reg_SCOCR2LL { 3366 unsigned int scocr2ll : 8; /* Symbol Counter Output Compare Register 2 LL-Byte */ 3367 }; 3368 3369 #define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL) 3370 3371 #endif /* __ASSEMBLER__ */ 3372 3373 /* SCOCR2LL */ 3374 3375 #define SCOCR2LL0 0 3376 #define SCOCR2LL1 1 3377 #define SCOCR2LL2 2 3378 #define SCOCR2LL3 3 3379 #define SCOCR2LL4 4 3380 #define SCOCR2LL5 5 3381 #define SCOCR2LL6 6 3382 #define SCOCR2LL7 7 3383 3384 /* Symbol Counter Output Compare Register 2 LH-Byte */ 3385 #define SCOCR2LH _SFR_MEM8(0xF2) 3386 3387 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3388 3389 struct __reg_SCOCR2LH { 3390 unsigned int scocr2lh : 8; /* Symbol Counter Output Compare Register 2 LH-Byte */ 3391 }; 3392 3393 #define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH) 3394 3395 #endif /* __ASSEMBLER__ */ 3396 3397 /* SCOCR2LH */ 3398 3399 #define SCOCR2LH0 0 3400 #define SCOCR2LH1 1 3401 #define SCOCR2LH2 2 3402 #define SCOCR2LH3 3 3403 #define SCOCR2LH4 4 3404 #define SCOCR2LH5 5 3405 #define SCOCR2LH6 6 3406 #define SCOCR2LH7 7 3407 3408 /* Symbol Counter Output Compare Register 2 HL-Byte */ 3409 #define SCOCR2HL _SFR_MEM8(0xF3) 3410 3411 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3412 3413 struct __reg_SCOCR2HL { 3414 unsigned int scocr2hl : 8; /* Symbol Counter Output Compare Register 2 HL-Byte */ 3415 }; 3416 3417 #define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL) 3418 3419 #endif /* __ASSEMBLER__ */ 3420 3421 /* SCOCR2HL */ 3422 3423 #define SCOCR2HL0 0 3424 #define SCOCR2HL1 1 3425 #define SCOCR2HL2 2 3426 #define SCOCR2HL3 3 3427 #define SCOCR2HL4 4 3428 #define SCOCR2HL5 5 3429 #define SCOCR2HL6 6 3430 #define SCOCR2HL7 7 3431 3432 /* Symbol Counter Output Compare Register 2 HH-Byte */ 3433 #define SCOCR2HH _SFR_MEM8(0xF4) 3434 3435 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3436 3437 struct __reg_SCOCR2HH { 3438 unsigned int scocr2hh : 8; /* Symbol Counter Output Compare Register 2 HH-Byte */ 3439 }; 3440 3441 #define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH) 3442 3443 #endif /* __ASSEMBLER__ */ 3444 3445 /* SCOCR2HH */ 3446 3447 #define SCOCR2HH0 0 3448 #define SCOCR2HH1 1 3449 #define SCOCR2HH2 2 3450 #define SCOCR2HH3 3 3451 #define SCOCR2HH4 4 3452 #define SCOCR2HH5 5 3453 #define SCOCR2HH6 6 3454 #define SCOCR2HH7 7 3455 3456 /* Symbol Counter Output Compare Register 1 LL-Byte */ 3457 #define SCOCR1LL _SFR_MEM8(0xF5) 3458 3459 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3460 3461 struct __reg_SCOCR1LL { 3462 unsigned int scocr1ll : 8; /* Symbol Counter Output Compare Register 1 LL-Byte */ 3463 }; 3464 3465 #define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL) 3466 3467 #endif /* __ASSEMBLER__ */ 3468 3469 /* SCOCR1LL */ 3470 3471 #define SCOCR1LL0 0 3472 #define SCOCR1LL1 1 3473 #define SCOCR1LL2 2 3474 #define SCOCR1LL3 3 3475 #define SCOCR1LL4 4 3476 #define SCOCR1LL5 5 3477 #define SCOCR1LL6 6 3478 #define SCOCR1LL7 7 3479 3480 /* Symbol Counter Output Compare Register 1 LH-Byte */ 3481 #define SCOCR1LH _SFR_MEM8(0xF6) 3482 3483 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3484 3485 struct __reg_SCOCR1LH { 3486 unsigned int scocr1lh : 8; /* Symbol Counter Output Compare Register 1 LH-Byte */ 3487 }; 3488 3489 #define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH) 3490 3491 #endif /* __ASSEMBLER__ */ 3492 3493 /* SCOCR1LH */ 3494 3495 #define SCOCR1LH0 0 3496 #define SCOCR1LH1 1 3497 #define SCOCR1LH2 2 3498 #define SCOCR1LH3 3 3499 #define SCOCR1LH4 4 3500 #define SCOCR1LH5 5 3501 #define SCOCR1LH6 6 3502 #define SCOCR1LH7 7 3503 3504 /* Symbol Counter Output Compare Register 1 HL-Byte */ 3505 #define SCOCR1HL _SFR_MEM8(0xF7) 3506 3507 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3508 3509 struct __reg_SCOCR1HL { 3510 unsigned int scocr1hl : 8; /* Symbol Counter Output Compare Register 1 HL-Byte */ 3511 }; 3512 3513 #define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL) 3514 3515 #endif /* __ASSEMBLER__ */ 3516 3517 /* SCOCR1HL */ 3518 3519 #define SCOCR1HL0 0 3520 #define SCOCR1HL1 1 3521 #define SCOCR1HL2 2 3522 #define SCOCR1HL3 3 3523 #define SCOCR1HL4 4 3524 #define SCOCR1HL5 5 3525 #define SCOCR1HL6 6 3526 #define SCOCR1HL7 7 3527 3528 /* Symbol Counter Output Compare Register 1 HH-Byte */ 3529 #define SCOCR1HH _SFR_MEM8(0xF8) 3530 3531 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3532 3533 struct __reg_SCOCR1HH { 3534 unsigned int scocr1hh : 8; /* Symbol Counter Output Compare Register 1 HH-Byte */ 3535 }; 3536 3537 #define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH) 3538 3539 #endif /* __ASSEMBLER__ */ 3540 3541 /* SCOCR1HH */ 3542 3543 #define SCOCR1HH0 0 3544 #define SCOCR1HH1 1 3545 #define SCOCR1HH2 2 3546 #define SCOCR1HH3 3 3547 #define SCOCR1HH4 4 3548 #define SCOCR1HH5 5 3549 #define SCOCR1HH6 6 3550 #define SCOCR1HH7 7 3551 3552 /* Symbol Counter Transmit Frame Timestamp Register LL-Byte */ 3553 #define SCTSTRLL _SFR_MEM8(0xF9) 3554 3555 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3556 3557 struct __reg_SCTSTRLL { 3558 unsigned int sctstrll : 8; /* Symbol Counter Transmit Frame Timestamp Register LL-Byte */ 3559 }; 3560 3561 #define SCTSTRLL_struct _SFR_MEM8_STRUCT(0xf9, struct __reg_SCTSTRLL) 3562 3563 #endif /* __ASSEMBLER__ */ 3564 3565 /* SCTSTRLL */ 3566 3567 #define SCTSTRLL0 0 3568 #define SCTSTRLL1 1 3569 #define SCTSTRLL2 2 3570 #define SCTSTRLL3 3 3571 #define SCTSTRLL4 4 3572 #define SCTSTRLL5 5 3573 #define SCTSTRLL6 6 3574 #define SCTSTRLL7 7 3575 3576 /* Symbol Counter Transmit Frame Timestamp Register LH-Byte */ 3577 #define SCTSTRLH _SFR_MEM8(0xFA) 3578 3579 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3580 3581 struct __reg_SCTSTRLH { 3582 unsigned int sctstrlh : 8; /* Symbol Counter Transmit Frame Timestamp Register LH-Byte */ 3583 }; 3584 3585 #define SCTSTRLH_struct _SFR_MEM8_STRUCT(0xfa, struct __reg_SCTSTRLH) 3586 3587 #endif /* __ASSEMBLER__ */ 3588 3589 /* SCTSTRLH */ 3590 3591 #define SCTSTRLH0 0 3592 #define SCTSTRLH1 1 3593 #define SCTSTRLH2 2 3594 #define SCTSTRLH3 3 3595 #define SCTSTRLH4 4 3596 #define SCTSTRLH5 5 3597 #define SCTSTRLH6 6 3598 #define SCTSTRLH7 7 3599 3600 /* Symbol Counter Transmit Frame Timestamp Register HL-Byte */ 3601 #define SCTSTRHL _SFR_MEM8(0xFB) 3602 3603 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3604 3605 struct __reg_SCTSTRHL { 3606 unsigned int sctstrhl : 8; /* Symbol Counter Transmit Frame Timestamp Register HL-Byte */ 3607 }; 3608 3609 #define SCTSTRHL_struct _SFR_MEM8_STRUCT(0xfb, struct __reg_SCTSTRHL) 3610 3611 #endif /* __ASSEMBLER__ */ 3612 3613 /* SCTSTRHL */ 3614 3615 #define SCTSTRHL0 0 3616 #define SCTSTRHL1 1 3617 #define SCTSTRHL2 2 3618 #define SCTSTRHL3 3 3619 #define SCTSTRHL4 4 3620 #define SCTSTRHL5 5 3621 #define SCTSTRHL6 6 3622 #define SCTSTRHL7 7 3623 3624 /* Symbol Counter Transmit Frame Timestamp Register HH-Byte */ 3625 #define SCTSTRHH _SFR_MEM8(0xFC) 3626 3627 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3628 3629 struct __reg_SCTSTRHH { 3630 unsigned int sctstrhh : 8; /* Symbol Counter Transmit Frame Timestamp Register HH-Byte */ 3631 }; 3632 3633 #define SCTSTRHH_struct _SFR_MEM8_STRUCT(0xfc, struct __reg_SCTSTRHH) 3634 3635 #endif /* __ASSEMBLER__ */ 3636 3637 /* SCTSTRHH */ 3638 3639 #define SCTSTRHH0 0 3640 #define SCTSTRHH1 1 3641 #define SCTSTRHH2 2 3642 #define SCTSTRHH3 3 3643 #define SCTSTRHH4 4 3644 #define SCTSTRHH5 5 3645 #define SCTSTRHH6 6 3646 #define SCTSTRHH7 7 3647 3648 /* Multiple Address Filter Configuration Register 0 */ 3649 #define MAFCR0 _SFR_MEM8(0x10C) 3650 3651 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3652 3653 struct __reg_MAFCR0 { 3654 unsigned int maf0en : 1; /* Multiple Address Filter 0 Enable */ 3655 unsigned int maf1en : 1; /* Multiple Address Filter 1 Enable */ 3656 unsigned int maf2en : 1; /* Multiple Address Filter 2 Enable */ 3657 unsigned int maf3en : 1; /* Multiple Address Filter 3 Enable */ 3658 unsigned int : 4; 3659 }; 3660 3661 #define MAFCR0_struct _SFR_MEM8_STRUCT(0x10c, struct __reg_MAFCR0) 3662 3663 #endif /* __ASSEMBLER__ */ 3664 3665 /* MAFCR0 */ 3666 3667 #define MAF0EN 0 3668 #define MAF1EN 1 3669 #define MAF2EN 2 3670 #define MAF3EN 3 3671 3672 /* Multiple Address Filter Configuration Register 1 */ 3673 #define MAFCR1 _SFR_MEM8(0x10D) 3674 3675 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3676 3677 struct __reg_MAFCR1 { 3678 unsigned int aack_0_i_am_coord : 1; /* Enable PAN Coordinator mode for address filter 0. */ 3679 unsigned int aack_0_set_pd : 1; /* Set Data Pending bit for address filter 0. */ 3680 unsigned int aack_1_i_am_coord : 1; /* Enable PAN Coordinator mode for address filter 1. */ 3681 unsigned int aack_1_set_pd : 1; /* Set Data Pending bit for address filter 1. */ 3682 unsigned int aack_2_i_am_coord : 1; /* Enable PAN Coordinator mode for address filter 2. */ 3683 unsigned int aack_2_set_pd : 1; /* Set Data Pending bit for address filter 2. */ 3684 unsigned int aack_3_i_am_coord : 1; /* Enable PAN Coordinator mode for address filter 3. */ 3685 unsigned int aack_3_set_pd : 1; /* Set Data Pending bit for address filter 3. */ 3686 }; 3687 3688 #define MAFCR1_struct _SFR_MEM8_STRUCT(0x10d, struct __reg_MAFCR1) 3689 3690 #endif /* __ASSEMBLER__ */ 3691 3692 /* MAFCR1 */ 3693 3694 #define AACK_0_I_AM_COORD 0 3695 #define AACK_0_SET_PD 1 3696 #define AACK_1_I_AM_COORD 2 3697 #define AACK_1_SET_PD 3 3698 #define AACK_2_I_AM_COORD 4 3699 #define AACK_2_SET_PD 5 3700 #define AACK_3_I_AM_COORD 6 3701 #define AACK_3_SET_PD 7 3702 3703 /* Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) */ 3704 #define MAFSA0L _SFR_MEM8(0x10E) 3705 3706 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3707 3708 struct __reg_MAFSA0L { 3709 unsigned int mafsa0l : 8; /* MAC Short Address low Byte for Frame Filter 0 */ 3710 }; 3711 3712 #define MAFSA0L_struct _SFR_MEM8_STRUCT(0x10e, struct __reg_MAFSA0L) 3713 3714 #endif /* __ASSEMBLER__ */ 3715 3716 /* MAFSA0L */ 3717 3718 #define MAFSA0L0 0 3719 #define MAFSA0L1 1 3720 #define MAFSA0L2 2 3721 #define MAFSA0L3 3 3722 #define MAFSA0L4 4 3723 #define MAFSA0L5 5 3724 #define MAFSA0L6 6 3725 #define MAFSA0L7 7 3726 3727 /* Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) */ 3728 #define MAFSA0H _SFR_MEM8(0x10F) 3729 3730 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3731 3732 struct __reg_MAFSA0H { 3733 unsigned int mafsa0h : 8; /* MAC Short Address high Byte for Frame Filter 0 */ 3734 }; 3735 3736 #define MAFSA0H_struct _SFR_MEM8_STRUCT(0x10f, struct __reg_MAFSA0H) 3737 3738 #endif /* __ASSEMBLER__ */ 3739 3740 /* MAFSA0H */ 3741 3742 #define MAFSA0H0 0 3743 #define MAFSA0H1 1 3744 #define MAFSA0H2 2 3745 #define MAFSA0H3 3 3746 #define MAFSA0H4 4 3747 #define MAFSA0H5 5 3748 #define MAFSA0H6 6 3749 #define MAFSA0H7 7 3750 3751 /* Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) */ 3752 #define MAFPA0L _SFR_MEM8(0x110) 3753 3754 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3755 3756 struct __reg_MAFPA0L { 3757 unsigned int mafpa0l : 8; /* MAC Personal Area Network ID low Byte for Frame Filter 0 */ 3758 }; 3759 3760 #define MAFPA0L_struct _SFR_MEM8_STRUCT(0x110, struct __reg_MAFPA0L) 3761 3762 #endif /* __ASSEMBLER__ */ 3763 3764 /* MAFPA0L */ 3765 3766 #define MAFPA0L0 0 3767 #define MAFPA0L1 1 3768 #define MAFPA0L2 2 3769 #define MAFPA0L3 3 3770 #define MAFPA0L4 4 3771 #define MAFPA0L5 5 3772 #define MAFPA0L6 6 3773 #define MAFPA0L7 7 3774 3775 /* Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) */ 3776 #define MAFPA0H _SFR_MEM8(0x111) 3777 3778 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3779 3780 struct __reg_MAFPA0H { 3781 unsigned int mafpa0h : 8; /* MAC Personal Area Network ID high Byte for Frame Filter 0 */ 3782 }; 3783 3784 #define MAFPA0H_struct _SFR_MEM8_STRUCT(0x111, struct __reg_MAFPA0H) 3785 3786 #endif /* __ASSEMBLER__ */ 3787 3788 /* MAFPA0H */ 3789 3790 #define MAFPA0H0 0 3791 #define MAFPA0H1 1 3792 #define MAFPA0H2 2 3793 #define MAFPA0H3 3 3794 #define MAFPA0H4 4 3795 #define MAFPA0H5 5 3796 #define MAFPA0H6 6 3797 #define MAFPA0H7 7 3798 3799 /* Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) */ 3800 #define MAFSA1L _SFR_MEM8(0x112) 3801 3802 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3803 3804 struct __reg_MAFSA1L { 3805 unsigned int mafsa1l : 8; /* MAC Short Address low Byte for Frame Filter 1 */ 3806 }; 3807 3808 #define MAFSA1L_struct _SFR_MEM8_STRUCT(0x112, struct __reg_MAFSA1L) 3809 3810 #endif /* __ASSEMBLER__ */ 3811 3812 /* MAFSA1L */ 3813 3814 #define MAFSA1L0 0 3815 #define MAFSA1L1 1 3816 #define MAFSA1L2 2 3817 #define MAFSA1L3 3 3818 #define MAFSA1L4 4 3819 #define MAFSA1L5 5 3820 #define MAFSA1L6 6 3821 #define MAFSA1L7 7 3822 3823 /* Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) */ 3824 #define MAFSA1H _SFR_MEM8(0x113) 3825 3826 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3827 3828 struct __reg_MAFSA1H { 3829 unsigned int mafsa1h : 8; /* MAC Short Address high Byte for Frame Filter 1 */ 3830 }; 3831 3832 #define MAFSA1H_struct _SFR_MEM8_STRUCT(0x113, struct __reg_MAFSA1H) 3833 3834 #endif /* __ASSEMBLER__ */ 3835 3836 /* MAFSA1H */ 3837 3838 #define MAFSA1H0 0 3839 #define MAFSA1H1 1 3840 #define MAFSA1H2 2 3841 #define MAFSA1H3 3 3842 #define MAFSA1H4 4 3843 #define MAFSA1H5 5 3844 #define MAFSA1H6 6 3845 #define MAFSA1H7 7 3846 3847 /* Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) */ 3848 #define MAFPA1L _SFR_MEM8(0x114) 3849 3850 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3851 3852 struct __reg_MAFPA1L { 3853 unsigned int mafpa1l : 8; /* MAC Personal Area Network ID low Byte for Frame Filter 1 */ 3854 }; 3855 3856 #define MAFPA1L_struct _SFR_MEM8_STRUCT(0x114, struct __reg_MAFPA1L) 3857 3858 #endif /* __ASSEMBLER__ */ 3859 3860 /* MAFPA1L */ 3861 3862 #define MAFPA1L0 0 3863 #define MAFPA1L1 1 3864 #define MAFPA1L2 2 3865 #define MAFPA1L3 3 3866 #define MAFPA1L4 4 3867 #define MAFPA1L5 5 3868 #define MAFPA1L6 6 3869 #define MAFPA1L7 7 3870 3871 /* Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) */ 3872 #define MAFPA1H _SFR_MEM8(0x115) 3873 3874 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3875 3876 struct __reg_MAFPA1H { 3877 unsigned int mafpa1h : 8; /* MAC Personal Area Network ID high Byte for Frame Filter 1 */ 3878 }; 3879 3880 #define MAFPA1H_struct _SFR_MEM8_STRUCT(0x115, struct __reg_MAFPA1H) 3881 3882 #endif /* __ASSEMBLER__ */ 3883 3884 /* MAFPA1H */ 3885 3886 #define MAFPA1H0 0 3887 #define MAFPA1H1 1 3888 #define MAFPA1H2 2 3889 #define MAFPA1H3 3 3890 #define MAFPA1H4 4 3891 #define MAFPA1H5 5 3892 #define MAFPA1H6 6 3893 #define MAFPA1H7 7 3894 3895 /* Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) */ 3896 #define MAFSA2L _SFR_MEM8(0x116) 3897 3898 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3899 3900 struct __reg_MAFSA2L { 3901 unsigned int mafsa2l : 8; /* MAC Short Address low Byte for Frame Filter 2 */ 3902 }; 3903 3904 #define MAFSA2L_struct _SFR_MEM8_STRUCT(0x116, struct __reg_MAFSA2L) 3905 3906 #endif /* __ASSEMBLER__ */ 3907 3908 /* MAFSA2L */ 3909 3910 #define MAFSA2L0 0 3911 #define MAFSA2L1 1 3912 #define MAFSA2L2 2 3913 #define MAFSA2L3 3 3914 #define MAFSA2L4 4 3915 #define MAFSA2L5 5 3916 #define MAFSA2L6 6 3917 #define MAFSA2L7 7 3918 3919 /* Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) */ 3920 #define MAFSA2H _SFR_MEM8(0x117) 3921 3922 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3923 3924 struct __reg_MAFSA2H { 3925 unsigned int mafsa2h : 8; /* MAC Short Address high Byte for Frame Filter 2 */ 3926 }; 3927 3928 #define MAFSA2H_struct _SFR_MEM8_STRUCT(0x117, struct __reg_MAFSA2H) 3929 3930 #endif /* __ASSEMBLER__ */ 3931 3932 /* MAFSA2H */ 3933 3934 #define MAFSA2H0 0 3935 #define MAFSA2H1 1 3936 #define MAFSA2H2 2 3937 #define MAFSA2H3 3 3938 #define MAFSA2H4 4 3939 #define MAFSA2H5 5 3940 #define MAFSA2H6 6 3941 #define MAFSA2H7 7 3942 3943 /* Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) */ 3944 #define MAFPA2L _SFR_MEM8(0x118) 3945 3946 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3947 3948 struct __reg_MAFPA2L { 3949 unsigned int mafpa2l : 8; /* MAC Personal Area Network ID low Byte for Frame Filter 2 */ 3950 }; 3951 3952 #define MAFPA2L_struct _SFR_MEM8_STRUCT(0x118, struct __reg_MAFPA2L) 3953 3954 #endif /* __ASSEMBLER__ */ 3955 3956 /* MAFPA2L */ 3957 3958 #define MAFPA2L0 0 3959 #define MAFPA2L1 1 3960 #define MAFPA2L2 2 3961 #define MAFPA2L3 3 3962 #define MAFPA2L4 4 3963 #define MAFPA2L5 5 3964 #define MAFPA2L6 6 3965 #define MAFPA2L7 7 3966 3967 /* Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) */ 3968 #define MAFPA2H _SFR_MEM8(0x119) 3969 3970 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3971 3972 struct __reg_MAFPA2H { 3973 unsigned int mafpa2h : 8; /* MAC Personal Area Network ID high Byte for Frame Filter 2 */ 3974 }; 3975 3976 #define MAFPA2H_struct _SFR_MEM8_STRUCT(0x119, struct __reg_MAFPA2H) 3977 3978 #endif /* __ASSEMBLER__ */ 3979 3980 /* MAFPA2H */ 3981 3982 #define MAFPA2H0 0 3983 #define MAFPA2H1 1 3984 #define MAFPA2H2 2 3985 #define MAFPA2H3 3 3986 #define MAFPA2H4 4 3987 #define MAFPA2H5 5 3988 #define MAFPA2H6 6 3989 #define MAFPA2H7 7 3990 3991 /* Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) */ 3992 #define MAFSA3L _SFR_MEM8(0x11A) 3993 3994 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3995 3996 struct __reg_MAFSA3L { 3997 unsigned int mafsa3l : 8; /* MAC Short Address low Byte for Frame Filter 3 */ 3998 }; 3999 4000 #define MAFSA3L_struct _SFR_MEM8_STRUCT(0x11a, struct __reg_MAFSA3L) 4001 4002 #endif /* __ASSEMBLER__ */ 4003 4004 /* MAFSA3L */ 4005 4006 #define MAFSA3L0 0 4007 #define MAFSA3L1 1 4008 #define MAFSA3L2 2 4009 #define MAFSA3L3 3 4010 #define MAFSA3L4 4 4011 #define MAFSA3L5 5 4012 #define MAFSA3L6 6 4013 #define MAFSA3L7 7 4014 4015 /* Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) */ 4016 #define MAFSA3H _SFR_MEM8(0x11B) 4017 4018 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4019 4020 struct __reg_MAFSA3H { 4021 unsigned int mafsa3h : 8; /* MAC Short Address high Byte for Frame Filter 3 */ 4022 }; 4023 4024 #define MAFSA3H_struct _SFR_MEM8_STRUCT(0x11b, struct __reg_MAFSA3H) 4025 4026 #endif /* __ASSEMBLER__ */ 4027 4028 /* MAFSA3H */ 4029 4030 #define MAFSA3H0 0 4031 #define MAFSA3H1 1 4032 #define MAFSA3H2 2 4033 #define MAFSA3H3 3 4034 #define MAFSA3H4 4 4035 #define MAFSA3H5 5 4036 #define MAFSA3H6 6 4037 #define MAFSA3H7 7 4038 4039 /* Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) */ 4040 #define MAFPA3L _SFR_MEM8(0x11C) 4041 4042 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4043 4044 struct __reg_MAFPA3L { 4045 unsigned int mafpa3l : 8; /* MAC Personal Area Network ID low Byte for Frame Filter 3 */ 4046 }; 4047 4048 #define MAFPA3L_struct _SFR_MEM8_STRUCT(0x11c, struct __reg_MAFPA3L) 4049 4050 #endif /* __ASSEMBLER__ */ 4051 4052 /* MAFPA3L */ 4053 4054 #define MAFPA3L0 0 4055 #define MAFPA3L1 1 4056 #define MAFPA3L2 2 4057 #define MAFPA3L3 3 4058 #define MAFPA3L4 4 4059 #define MAFPA3L5 5 4060 #define MAFPA3L6 6 4061 #define MAFPA3L7 7 4062 4063 /* Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) */ 4064 #define MAFPA3H _SFR_MEM8(0x11D) 4065 4066 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4067 4068 struct __reg_MAFPA3H { 4069 unsigned int mafpa3h : 8; /* MAC Personal Area Network ID high Byte for Frame Filter 3 */ 4070 }; 4071 4072 #define MAFPA3H_struct _SFR_MEM8_STRUCT(0x11d, struct __reg_MAFPA3H) 4073 4074 #endif /* __ASSEMBLER__ */ 4075 4076 /* MAFPA3H */ 4077 4078 #define MAFPA3H0 0 4079 #define MAFPA3H1 1 4080 #define MAFPA3H2 2 4081 #define MAFPA3H3 3 4082 #define MAFPA3H4 4 4083 #define MAFPA3H5 5 4084 #define MAFPA3H6 6 4085 #define MAFPA3H7 7 4086 4087 /* Timer/Counter5 Control Register A */ 4088 #define TCCR5A _SFR_MEM8(0x120) 4089 4090 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4091 4092 struct __reg_TCCR5A { 4093 unsigned int wgm5 : 2; /* Waveform Generation Mode */ 4094 unsigned int com5c : 2; /* Compare Output Mode for Channel C */ 4095 unsigned int com5b : 2; /* Compare Output Mode for Channel B */ 4096 unsigned int com5a : 2; /* Compare Output Mode for Channel A */ 4097 }; 4098 4099 #define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A) 4100 4101 #endif /* __ASSEMBLER__ */ 4102 4103 /* TCCR5A */ 4104 4105 #define WGM50 0 4106 #define WGM51 1 4107 #define COM5C0 2 4108 #define COM5C1 3 4109 #define COM5B0 4 4110 #define COM5B1 5 4111 #define COM5A0 6 4112 #define COM5A1 7 4113 4114 /* Timer/Counter5 Control Register B */ 4115 #define TCCR5B _SFR_MEM8(0x121) 4116 4117 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4118 4119 struct __reg_TCCR5B { 4120 unsigned int cs5 : 3; /* Clock Select */ 4121 unsigned int wgm5 : 2; /* Waveform Generation Mode */ 4122 unsigned int : 1; 4123 unsigned int ices5 : 1; /* Input Capture 5 Edge Select */ 4124 unsigned int icnc5 : 1; /* Input Capture 5 Noise Canceller */ 4125 }; 4126 4127 #define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B) 4128 4129 #endif /* __ASSEMBLER__ */ 4130 4131 /* TCCR5B */ 4132 4133 #define CS50 0 4134 #define CS51 1 4135 #define CS52 2 4136 #define WGM52 3 4137 #define WGM53 4 4138 #define ICES5 6 4139 #define ICNC5 7 4140 4141 /* Timer/Counter5 Control Register C */ 4142 #define TCCR5C _SFR_MEM8(0x122) 4143 4144 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4145 4146 struct __reg_TCCR5C { 4147 unsigned int : 5; 4148 unsigned int foc5c : 1; /* Force Output Compare for Channel C */ 4149 unsigned int foc5b : 1; /* Force Output Compare for Channel B */ 4150 unsigned int foc5a : 1; /* Force Output Compare for Channel A */ 4151 }; 4152 4153 #define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C) 4154 4155 #endif /* __ASSEMBLER__ */ 4156 4157 /* TCCR5C */ 4158 4159 #define FOC5C 5 4160 #define FOC5B 6 4161 #define FOC5A 7 4162 4163 /* Timer/Counter5 Bytes */ 4164 #define TCNT5 _SFR_MEM16(0x124) 4165 #define TCNT5L _SFR_MEM8(0x124) 4166 #define TCNT5H _SFR_MEM8(0x125) 4167 4168 /* Timer/Counter5 Input Capture Register Bytes */ 4169 #define ICR5 _SFR_MEM16(0x126) 4170 #define ICR5L _SFR_MEM8(0x126) 4171 #define ICR5H _SFR_MEM8(0x127) 4172 4173 /* Timer/Counter5 Output Compare Register A Bytes */ 4174 #define OCR5A _SFR_MEM16(0x128) 4175 #define OCR5AL _SFR_MEM8(0x128) 4176 #define OCR5AH _SFR_MEM8(0x129) 4177 4178 /* Timer/Counter5 Output Compare Register B Bytes */ 4179 #define OCR5B _SFR_MEM16(0x12A) 4180 #define OCR5BL _SFR_MEM8(0x12A) 4181 #define OCR5BH _SFR_MEM8(0x12B) 4182 4183 /* Timer/Counter5 Output Compare Register C Bytes */ 4184 #define OCR5C _SFR_MEM16(0x12C) 4185 #define OCR5CL _SFR_MEM8(0x12C) 4186 #define OCR5CH _SFR_MEM8(0x12D) 4187 4188 /* Low Leakage Voltage Regulator Control Register */ 4189 #define LLCR _SFR_MEM8(0x12F) 4190 4191 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4192 4193 struct __reg_LLCR { 4194 unsigned int llencal : 1; /* Enable Automatic Calibration */ 4195 unsigned int llshort : 1; /* Short Lower Calibration Circuit */ 4196 unsigned int lltco : 1; /* Temperature Coefficient of Current Source */ 4197 unsigned int llcal : 1; /* Calibration Active */ 4198 unsigned int llcomp : 1; /* Comparator Output */ 4199 unsigned int lldone : 1; /* Calibration Done */ 4200 unsigned int : 2; 4201 }; 4202 4203 #define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR) 4204 4205 #endif /* __ASSEMBLER__ */ 4206 4207 /* LLCR */ 4208 4209 #define LLENCAL 0 4210 #define LLSHORT 1 4211 #define LLTCO 2 4212 #define LLCAL 3 4213 #define LLCOMP 4 4214 #define LLDONE 5 4215 4216 /* Low Leakage Voltage Regulator Data Register (Low-Byte) */ 4217 #define LLDRL _SFR_MEM8(0x130) 4218 4219 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4220 4221 struct __reg_LLDRL { 4222 unsigned int lldrl : 4; /* Low-Byte Data Register Bits */ 4223 unsigned int : 4; 4224 }; 4225 4226 #define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL) 4227 4228 #endif /* __ASSEMBLER__ */ 4229 4230 /* LLDRL */ 4231 4232 #define LLDRL0 0 4233 #define LLDRL1 1 4234 #define LLDRL2 2 4235 #define LLDRL3 3 4236 4237 /* Low Leakage Voltage Regulator Data Register (High-Byte) */ 4238 #define LLDRH _SFR_MEM8(0x131) 4239 4240 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4241 4242 struct __reg_LLDRH { 4243 unsigned int lldrh : 5; /* High-Byte Data Register Bits */ 4244 unsigned int : 3; 4245 }; 4246 4247 #define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH) 4248 4249 #endif /* __ASSEMBLER__ */ 4250 4251 /* LLDRH */ 4252 4253 #define LLDRH0 0 4254 #define LLDRH1 1 4255 #define LLDRH2 2 4256 #define LLDRH3 3 4257 #define LLDRH4 4 4258 4259 /* Data Retention Configuration Register #3 */ 4260 #define DRTRAM3 _SFR_MEM8(0x132) 4261 4262 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4263 4264 struct __reg_DRTRAM3 { 4265 unsigned int : 4; 4266 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 4267 unsigned int drtswok : 1; /* DRT Switch OK */ 4268 unsigned int : 2; 4269 }; 4270 4271 #define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3) 4272 4273 #endif /* __ASSEMBLER__ */ 4274 4275 /* DRTRAM3 */ 4276 4277 #define ENDRT 4 4278 #define DRTSWOK 5 4279 4280 /* Data Retention Configuration Register #2 */ 4281 #define DRTRAM2 _SFR_MEM8(0x133) 4282 4283 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4284 4285 struct __reg_DRTRAM2 { 4286 unsigned int : 4; 4287 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 4288 unsigned int drtswok : 1; /* DRT Switch OK */ 4289 unsigned int : 2; 4290 }; 4291 4292 #define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2) 4293 4294 #endif /* __ASSEMBLER__ */ 4295 4296 /* DRTRAM2 */ 4297 4298 #define ENDRT 4 4299 #define DRTSWOK 5 4300 4301 /* Data Retention Configuration Register #1 */ 4302 #define DRTRAM1 _SFR_MEM8(0x134) 4303 4304 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4305 4306 struct __reg_DRTRAM1 { 4307 unsigned int : 4; 4308 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 4309 unsigned int drtswok : 1; /* DRT Switch OK */ 4310 unsigned int : 2; 4311 }; 4312 4313 #define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1) 4314 4315 #endif /* __ASSEMBLER__ */ 4316 4317 /* DRTRAM1 */ 4318 4319 #define ENDRT 4 4320 #define DRTSWOK 5 4321 4322 /* Data Retention Configuration Register #0 */ 4323 #define DRTRAM0 _SFR_MEM8(0x135) 4324 4325 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4326 4327 struct __reg_DRTRAM0 { 4328 unsigned int : 4; 4329 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 4330 unsigned int drtswok : 1; /* DRT Switch OK */ 4331 unsigned int : 2; 4332 }; 4333 4334 #define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0) 4335 4336 #endif /* __ASSEMBLER__ */ 4337 4338 /* DRTRAM0 */ 4339 4340 #define ENDRT 4 4341 #define DRTSWOK 5 4342 4343 /* Port Driver Strength Register 0 */ 4344 #define DPDS0 _SFR_MEM8(0x136) 4345 4346 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4347 4348 struct __reg_DPDS0 { 4349 unsigned int pbdrv : 2; /* Driver Strength Port B */ 4350 unsigned int pddrv : 2; /* Driver Strength Port D */ 4351 unsigned int pedrv : 2; /* Driver Strength Port E */ 4352 unsigned int pfdrv : 2; /* Driver Strength Port F */ 4353 }; 4354 4355 #define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0) 4356 4357 #endif /* __ASSEMBLER__ */ 4358 4359 /* DPDS0 */ 4360 4361 #define PBDRV0 0 4362 #define PBDRV1 1 4363 #define PDDRV0 2 4364 #define PDDRV1 3 4365 #define PEDRV0 4 4366 #define PEDRV1 5 4367 #define PFDRV0 6 4368 #define PFDRV1 7 4369 4370 /* Port Driver Strength Register 1 */ 4371 #define DPDS1 _SFR_MEM8(0x137) 4372 4373 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4374 4375 struct __reg_DPDS1 { 4376 unsigned int pgdrv : 2; /* Driver Strength Port G */ 4377 unsigned int : 6; 4378 }; 4379 4380 #define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1) 4381 4382 #endif /* __ASSEMBLER__ */ 4383 4384 /* DPDS1 */ 4385 4386 #define PGDRV0 0 4387 #define PGDRV1 1 4388 4389 /* Power Amplifier Ramp up/down Control Register */ 4390 #define PARCR _SFR_MEM8(0x138) 4391 4392 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4393 4394 struct __reg_PARCR { 4395 unsigned int parufi : 1; /* Power Amplifier Ramp Up Frequency Inversion */ 4396 unsigned int pardfi : 1; /* Power Amplifier Ramp Down Frequency Inversion */ 4397 unsigned int paltu : 3; /* ext. PA Ramp Up Lead Time */ 4398 unsigned int paltd : 3; /* ext. PA Ramp Down Lead Time */ 4399 }; 4400 4401 #define PARCR_struct _SFR_MEM8_STRUCT(0x138, struct __reg_PARCR) 4402 4403 /* symbolic names */ 4404 4405 #define PALTU_MINUS_3US 0 4406 #define PALTU_MINUS_2US 1 4407 #define PALTU_MINUS_1US 2 4408 #define PALTU_0US 3 4409 #define PALTU_1US 4 4410 #define PALTU_2US 5 4411 #define PALTU_3US 6 4412 #define PALTU_4US 7 4413 #define PALTD_MINUS_3US 0 4414 #define PALTD_MINUS_2US 1 4415 #define PALTD_MINUS_1US 2 4416 #define PALTD_0US 3 4417 #define PALTD_1US 4 4418 #define PALTD_2US 5 4419 #define PALTD_3US 6 4420 #define PALTD_4US 7 4421 4422 #endif /* __ASSEMBLER__ */ 4423 4424 /* PARCR */ 4425 4426 #define PARUFI 0 4427 #define PARDFI 1 4428 #define PALTU0 2 4429 #define PALTU1 3 4430 #define PALTU2 4 4431 #define PALTD0 5 4432 #define PALTD1 6 4433 #define PALTD2 7 4434 4435 /* Transceiver Pin Register */ 4436 #define TRXPR _SFR_MEM8(0x139) 4437 4438 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4439 4440 struct __reg_TRXPR { 4441 unsigned int trxrst : 1; /* Force Transceiver Reset */ 4442 unsigned int slptr : 1; /* Multi-purpose Transceiver Control Bit */ 4443 unsigned int : 6; 4444 }; 4445 4446 #define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR) 4447 4448 #endif /* __ASSEMBLER__ */ 4449 4450 /* TRXPR */ 4451 4452 #define TRXRST 0 4453 #define SLPTR 1 4454 4455 /* AES Control Register */ 4456 #define AES_CTRL _SFR_MEM8(0x13C) 4457 4458 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4459 4460 struct __reg_AES_CTRL { 4461 unsigned int : 2; 4462 unsigned int aes_im : 1; /* AES Interrupt Enable */ 4463 unsigned int aes_dir : 1; /* Set AES Operation Direction */ 4464 unsigned int : 1; 4465 unsigned int aes_mode : 1; /* Set AES Operation Mode */ 4466 unsigned int : 1; 4467 unsigned int aes_request : 1; /* Request AES Operation. */ 4468 }; 4469 4470 #define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL) 4471 4472 /* symbolic names */ 4473 4474 #define AES_DIR_ENC 0 4475 #define AES_DIR_DEC 1 4476 #define AES_MODE_ECB 0 4477 #define AES_MODE_CBC 1 4478 4479 #endif /* __ASSEMBLER__ */ 4480 4481 /* AES_CTRL */ 4482 4483 #define AES_IM 2 4484 #define AES_DIR 3 4485 #define AES_MODE 5 4486 #define AES_REQUEST 7 4487 4488 /* AES Status Register */ 4489 #define AES_STATUS _SFR_MEM8(0x13D) 4490 4491 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4492 4493 struct __reg_AES_STATUS { 4494 unsigned int aes_done : 1; /* AES Operation Finished with Success */ 4495 unsigned int : 6; 4496 unsigned int aes_er : 1; /* AES Operation Finished with Error */ 4497 }; 4498 4499 #define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS) 4500 4501 #endif /* __ASSEMBLER__ */ 4502 4503 /* AES_STATUS */ 4504 4505 #define AES_DONE 0 4506 #define AES_ER 7 4507 4508 /* AES Plain and Cipher Text Buffer Register */ 4509 #define AES_STATE _SFR_MEM8(0x13E) 4510 4511 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4512 4513 struct __reg_AES_STATE { 4514 unsigned int aes_state : 8; /* AES Plain and Cipher Text Buffer */ 4515 }; 4516 4517 #define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE) 4518 4519 #endif /* __ASSEMBLER__ */ 4520 4521 /* AES_STATE */ 4522 4523 #define AES_STATE0 0 4524 #define AES_STATE1 1 4525 #define AES_STATE2 2 4526 #define AES_STATE3 3 4527 #define AES_STATE4 4 4528 #define AES_STATE5 5 4529 #define AES_STATE6 6 4530 #define AES_STATE7 7 4531 4532 /* AES Encryption and Decryption Key Buffer Register */ 4533 #define AES_KEY _SFR_MEM8(0x13F) 4534 4535 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4536 4537 struct __reg_AES_KEY { 4538 unsigned int aes_key : 8; /* AES Encryption/Decryption Key Buffer */ 4539 }; 4540 4541 #define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY) 4542 4543 #endif /* __ASSEMBLER__ */ 4544 4545 /* AES_KEY */ 4546 4547 #define AES_KEY0 0 4548 #define AES_KEY1 1 4549 #define AES_KEY2 2 4550 #define AES_KEY3 3 4551 #define AES_KEY4 4 4552 #define AES_KEY5 5 4553 #define AES_KEY6 6 4554 #define AES_KEY7 7 4555 4556 /* Transceiver Status Register */ 4557 #define TRX_STATUS _SFR_MEM8(0x141) 4558 4559 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4560 4561 struct __reg_TRX_STATUS { 4562 unsigned int trx_status : 5; /* Transceiver Main Status */ 4563 unsigned int tst_status : 1; /* Test mode status */ 4564 unsigned int cca_status : 1; /* CCA Status Result */ 4565 unsigned int cca_done : 1; /* CCA Algorithm Status */ 4566 }; 4567 4568 #define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS) 4569 4570 /* symbolic names */ 4571 4572 #define BUSY_RX 1 4573 #define BUSY_TX 2 4574 #define RX_ON 6 4575 #define TRX_OFF 8 4576 #define PLL_ON 9 4577 #define SLEEP 15 4578 #define BUSY_RX_AACK 17 4579 #define BUSY_TX_ARET 18 4580 #define RX_AACK_ON 22 4581 #define TX_ARET_ON 25 4582 #define STATE_TRANSITION_IN_PROGRESS 31 4583 #define TST_DISABLED 0 4584 #define TST_ENABLED 1 4585 #define CCA_BUSY 0 4586 #define CCA_IDLE 1 4587 #define CCA_NOT_FIN 0 4588 #define CCA_FIN 1 4589 4590 #endif /* __ASSEMBLER__ */ 4591 4592 /* TRX_STATUS */ 4593 4594 #define TRX_STATUS0 0 4595 #define TRX_STATUS1 1 4596 #define TRX_STATUS2 2 4597 #define TRX_STATUS3 3 4598 #define TRX_STATUS4 4 4599 #define TST_STATUS 5 4600 #define CCA_STATUS 6 4601 #define CCA_DONE 7 4602 4603 /* Transceiver State Control Register */ 4604 #define TRX_STATE _SFR_MEM8(0x142) 4605 4606 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4607 4608 struct __reg_TRX_STATE { 4609 unsigned int trx_cmd : 5; /* State Control Command */ 4610 unsigned int trac_status : 3; /* Transaction Status */ 4611 }; 4612 4613 #define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE) 4614 4615 /* symbolic names */ 4616 4617 #define CMD_NOP 0 4618 #define CMD_TX_START 2 4619 #define CMD_FORCE_TRX_OFF 3 4620 #define CMD_FORCE_PLL_ON 4 4621 #define CMD_RX_ON 6 4622 #define CMD_TRX_OFF 8 4623 #define CMD_PLL_ON 9 4624 #define CMD_RX_AACK_ON 22 4625 #define CMD_TX_ARET_ON 25 4626 #define TRAC_SUCCESS 0 4627 #define TRAC_SUCCESS_DATA_PENDING 1 4628 #define TRAC_SUCCESS_WAIT_FOR_ACK 2 4629 #define TRAC_CHANNEL_ACCESS_FAILURE 3 4630 #define TRAC_NO_ACK 5 4631 #define TRAC_INVALID 7 4632 4633 #endif /* __ASSEMBLER__ */ 4634 4635 /* TRX_STATE */ 4636 4637 #define TRX_CMD0 0 4638 #define TRX_CMD1 1 4639 #define TRX_CMD2 2 4640 #define TRX_CMD3 3 4641 #define TRX_CMD4 4 4642 #define TRAC_STATUS0 5 4643 #define TRAC_STATUS1 6 4644 #define TRAC_STATUS2 7 4645 4646 /* Reserved */ 4647 #define TRX_CTRL_0 _SFR_MEM8(0x143) 4648 4649 /* Transceiver Control Register 1 */ 4650 #define TRX_CTRL_1 _SFR_MEM8(0x144) 4651 4652 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4653 4654 struct __reg_TRX_CTRL_1 { 4655 unsigned int : 4; 4656 unsigned int pll_tx_flt : 1; /* Enable PLL TX Filter */ 4657 unsigned int tx_auto_crc_on : 1; /* Enable Automatic CRC Calculation */ 4658 unsigned int irq_2_ext_en : 1; /* Connect Frame Start IRQ to TC1 */ 4659 unsigned int pa_ext_en : 1; /* External PA support enable */ 4660 }; 4661 4662 #define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1) 4663 4664 #endif /* __ASSEMBLER__ */ 4665 4666 /* TRX_CTRL_1 */ 4667 4668 #define PLL_TX_FLT 4 4669 #define TX_AUTO_CRC_ON 5 4670 #define IRQ_2_EXT_EN 6 4671 #define PA_EXT_EN 7 4672 4673 /* Transceiver Transmit Power Control Register */ 4674 #define PHY_TX_PWR _SFR_MEM8(0x145) 4675 4676 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4677 4678 struct __reg_PHY_TX_PWR { 4679 unsigned int tx_pwr : 4; /* Transmit Power Setting */ 4680 unsigned int : 4; 4681 }; 4682 4683 #define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR) 4684 4685 #endif /* __ASSEMBLER__ */ 4686 4687 /* PHY_TX_PWR */ 4688 4689 #define TX_PWR0 0 4690 #define TX_PWR1 1 4691 #define TX_PWR2 2 4692 #define TX_PWR3 3 4693 4694 /* Receiver Signal Strength Indicator Register */ 4695 #define PHY_RSSI _SFR_MEM8(0x146) 4696 4697 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4698 4699 struct __reg_PHY_RSSI { 4700 unsigned int rssi : 5; /* Receiver Signal Strength Indicator */ 4701 unsigned int rnd_value : 2; /* Random Value */ 4702 unsigned int rx_crc_valid : 1; /* Received Frame CRC Status */ 4703 }; 4704 4705 #define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI) 4706 4707 /* symbolic names */ 4708 4709 #define RSSI_MIN 0 4710 #define RSSI_MIN_PLUS_3dB 1 4711 #define RSSI_MAX 28 4712 #define CRC_INVALID 0 4713 #define CRC_VALID 1 4714 4715 #endif /* __ASSEMBLER__ */ 4716 4717 /* PHY_RSSI */ 4718 4719 #define RSSI0 0 4720 #define RSSI1 1 4721 #define RSSI2 2 4722 #define RSSI3 3 4723 #define RSSI4 4 4724 #define RND_VALUE0 5 4725 #define RND_VALUE1 6 4726 #define RX_CRC_VALID 7 4727 4728 /* Transceiver Energy Detection Level Register */ 4729 #define PHY_ED_LEVEL _SFR_MEM8(0x147) 4730 4731 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4732 4733 struct __reg_PHY_ED_LEVEL { 4734 unsigned int ed_level : 8; /* Energy Detection Level */ 4735 }; 4736 4737 #define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL) 4738 4739 /* symbolic names */ 4740 4741 #define ED_MIN 0 4742 #define ED_MIN_PLUS_1dB 1 4743 #define ED_MAX 83 4744 #define ED_RESET 255 4745 4746 #endif /* __ASSEMBLER__ */ 4747 4748 /* PHY_ED_LEVEL */ 4749 4750 #define ED_LEVEL0 0 4751 #define ED_LEVEL1 1 4752 #define ED_LEVEL2 2 4753 #define ED_LEVEL3 3 4754 #define ED_LEVEL4 4 4755 #define ED_LEVEL5 5 4756 #define ED_LEVEL6 6 4757 #define ED_LEVEL7 7 4758 4759 /* Transceiver Clear Channel Assessment (CCA) Control Register */ 4760 #define PHY_CC_CCA _SFR_MEM8(0x148) 4761 4762 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4763 4764 struct __reg_PHY_CC_CCA { 4765 unsigned int channel : 5; /* RX/TX Channel Selection */ 4766 unsigned int cca_mode : 2; /* Select CCA Measurement Mode */ 4767 unsigned int cca_request : 1; /* Manual CCA Measurement Request */ 4768 }; 4769 4770 #define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA) 4771 4772 /* symbolic names */ 4773 4774 #define F_2405MHZ 11 4775 #define F_2410MHZ 12 4776 #define F_2415MHZ 13 4777 #define F_2420MHZ 14 4778 #define F_2425MHZ 15 4779 #define F_2430MHZ 16 4780 #define F_2435MHZ 17 4781 #define F_2440MHZ 18 4782 #define F_2445MHZ 19 4783 #define F_2450MHZ 20 4784 #define F_2455MHZ 21 4785 #define F_2460MHZ 22 4786 #define F_2465MHZ 23 4787 #define F_2470MHZ 24 4788 #define F_2475MHZ 25 4789 #define F_2480MHZ 26 4790 #define CCA_CS_OR_ED 0 4791 #define CCA_ED 1 4792 #define CCA_CS 2 4793 #define CCA_CS_AND_ED 3 4794 4795 #endif /* __ASSEMBLER__ */ 4796 4797 /* PHY_CC_CCA */ 4798 4799 #define CHANNEL0 0 4800 #define CHANNEL1 1 4801 #define CHANNEL2 2 4802 #define CHANNEL3 3 4803 #define CHANNEL4 4 4804 #define CCA_MODE0 5 4805 #define CCA_MODE1 6 4806 #define CCA_REQUEST 7 4807 4808 /* Transceiver CCA Threshold Setting Register */ 4809 #define CCA_THRES _SFR_MEM8(0x149) 4810 4811 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4812 4813 struct __reg_CCA_THRES { 4814 unsigned int cca_ed_thres : 4; /* ED Threshold Level for CCA Measurement */ 4815 unsigned int cca_cs_thres : 4; /* CS Threshold Level for CCA Measurement */ 4816 }; 4817 4818 #define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES) 4819 4820 #endif /* __ASSEMBLER__ */ 4821 4822 /* CCA_THRES */ 4823 4824 #define CCA_ED_THRES0 0 4825 #define CCA_ED_THRES1 1 4826 #define CCA_ED_THRES2 2 4827 #define CCA_ED_THRES3 3 4828 #define CCA_CS_THRES0 4 4829 #define CCA_CS_THRES1 5 4830 #define CCA_CS_THRES2 6 4831 #define CCA_CS_THRES3 7 4832 4833 /* Transceiver Receive Control Register */ 4834 #define RX_CTRL _SFR_MEM8(0x14A) 4835 4836 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4837 4838 struct __reg_RX_CTRL { 4839 unsigned int pdt_thres : 4; /* Receiver Sensitivity Control */ 4840 unsigned int : 4; 4841 }; 4842 4843 #define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL) 4844 4845 /* symbolic names */ 4846 4847 #define PDT_THRES_ANT_DIV_OFF 7 4848 #define PDT_THRES_ANT_DIV_ON 3 4849 4850 #endif /* __ASSEMBLER__ */ 4851 4852 /* RX_CTRL */ 4853 4854 #define PDT_THRES0 0 4855 #define PDT_THRES1 1 4856 #define PDT_THRES2 2 4857 #define PDT_THRES3 3 4858 4859 /* Start of Frame Delimiter Value Register */ 4860 #define SFD_VALUE _SFR_MEM8(0x14B) 4861 4862 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4863 4864 struct __reg_SFD_VALUE { 4865 unsigned int sfd_value : 8; /* Start of Frame Delimiter Value */ 4866 }; 4867 4868 #define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE) 4869 4870 /* symbolic names */ 4871 4872 #define IEEE_SFD 167 4873 4874 #endif /* __ASSEMBLER__ */ 4875 4876 /* SFD_VALUE */ 4877 4878 #define SFD_VALUE0 0 4879 #define SFD_VALUE1 1 4880 #define SFD_VALUE2 2 4881 #define SFD_VALUE3 3 4882 #define SFD_VALUE4 4 4883 #define SFD_VALUE5 5 4884 #define SFD_VALUE6 6 4885 #define SFD_VALUE7 7 4886 4887 /* Transceiver Control Register 2 */ 4888 #define TRX_CTRL_2 _SFR_MEM8(0x14C) 4889 4890 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4891 4892 struct __reg_TRX_CTRL_2 { 4893 unsigned int oqpsk_data_rate : 2; /* Data Rate Selection */ 4894 unsigned int : 5; 4895 unsigned int rx_safe_mode : 1; /* RX Safe Mode */ 4896 }; 4897 4898 #define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2) 4899 4900 /* symbolic names */ 4901 4902 #define RATE_250KB 0 4903 #define RATE_500KB 1 4904 #define RATE_1000KB 2 4905 #define RATE_2000KB 3 4906 4907 #endif /* __ASSEMBLER__ */ 4908 4909 /* TRX_CTRL_2 */ 4910 4911 #define OQPSK_DATA_RATE0 0 4912 #define OQPSK_DATA_RATE1 1 4913 #define RX_SAFE_MODE 7 4914 4915 /* Antenna Diversity Control Register */ 4916 #define ANT_DIV _SFR_MEM8(0x14D) 4917 4918 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4919 4920 struct __reg_ANT_DIV { 4921 unsigned int ant_ctrl : 2; /* Static Antenna Diversity Switch Control */ 4922 unsigned int ant_ext_sw_en : 1; /* Enable External Antenna Switch Control */ 4923 unsigned int ant_div_en : 1; /* Enable Antenna Diversity */ 4924 unsigned int : 3; 4925 unsigned int ant_sel : 1; /* Antenna Diversity Antenna Status */ 4926 }; 4927 4928 #define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV) 4929 4930 /* symbolic names */ 4931 4932 #define ANT_1 1 4933 #define ANT_0 2 4934 #define ANT_RESET 3 4935 #define ANT_DIV_EXT_SW_DIS 0 4936 #define ANT_DIV_EXT_SW_EN 1 4937 #define ANTENNA_0 0 4938 #define ANTENNA_1 1 4939 4940 #endif /* __ASSEMBLER__ */ 4941 4942 /* ANT_DIV */ 4943 4944 #define ANT_CTRL0 0 4945 #define ANT_CTRL1 1 4946 #define ANT_EXT_SW_EN 2 4947 #define ANT_DIV_EN 3 4948 #define ANT_SEL 7 4949 4950 /* Transceiver Interrupt Enable Register */ 4951 #define IRQ_MASK _SFR_MEM8(0x14E) 4952 4953 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4954 4955 struct __reg_IRQ_MASK { 4956 unsigned int pll_lock_en : 1; /* PLL Lock Interrupt Enable */ 4957 unsigned int pll_unlock_en : 1; /* PLL Unlock Interrupt Enable */ 4958 unsigned int rx_start_en : 1; /* RX_START Interrupt Enable */ 4959 unsigned int rx_end_en : 1; /* RX_END Interrupt Enable */ 4960 unsigned int cca_ed_done_en : 1; /* End of ED Measurement Interrupt Enable */ 4961 unsigned int ami_en : 1; /* Address Match Interrupt Enable */ 4962 unsigned int tx_end_en : 1; /* TX_END Interrupt Enable */ 4963 unsigned int awake_en : 1; /* Awake Interrupt Enable */ 4964 }; 4965 4966 #define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK) 4967 4968 #endif /* __ASSEMBLER__ */ 4969 4970 /* IRQ_MASK */ 4971 4972 #define PLL_LOCK_EN 0 4973 #define PLL_UNLOCK_EN 1 4974 #define RX_START_EN 2 4975 #define RX_END_EN 3 4976 #define CCA_ED_DONE_EN 4 4977 #define AMI_EN 5 4978 #define TX_END_EN 6 4979 #define AWAKE_EN 7 4980 4981 /* Transceiver Interrupt Status Register */ 4982 #define IRQ_STATUS _SFR_MEM8(0x14F) 4983 4984 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4985 4986 struct __reg_IRQ_STATUS { 4987 unsigned int pll_lock : 1; /* PLL Lock Interrupt Status */ 4988 unsigned int pll_unlock : 1; /* PLL Unlock Interrupt Status */ 4989 unsigned int rx_start : 1; /* RX_START Interrupt Status */ 4990 unsigned int rx_end : 1; /* RX_END Interrupt Status */ 4991 unsigned int cca_ed_done : 1; /* End of ED Measurement Interrupt Status */ 4992 unsigned int ami : 1; /* Address Match Interrupt Status */ 4993 unsigned int tx_end : 1; /* TX_END Interrupt Status */ 4994 unsigned int awake : 1; /* Awake Interrupt Status */ 4995 }; 4996 4997 #define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS) 4998 4999 #endif /* __ASSEMBLER__ */ 5000 5001 /* IRQ_STATUS */ 5002 5003 #define PLL_LOCK 0 5004 #define PLL_UNLOCK 1 5005 #define RX_START 2 5006 #define RX_END 3 5007 #define CCA_ED_DONE 4 5008 #define AMI 5 5009 #define TX_END 6 5010 #define AWAKE 7 5011 5012 /* Voltage Regulator Control and Status Register */ 5013 #define VREG_CTRL _SFR_MEM8(0x150) 5014 5015 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5016 5017 struct __reg_VREG_CTRL { 5018 unsigned int : 2; 5019 unsigned int dvdd_ok : 1; /* DVDD Supply Voltage Valid */ 5020 unsigned int dvreg_ext : 1; /* Use External DVDD Regulator */ 5021 unsigned int : 2; 5022 unsigned int avdd_ok : 1; /* AVDD Supply Voltage Valid */ 5023 unsigned int avreg_ext : 1; /* Use External AVDD Regulator */ 5024 }; 5025 5026 #define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL) 5027 5028 /* symbolic names */ 5029 5030 #define DVDD_INT 0 5031 #define DVDD_EXT 1 5032 #define AVDD_INT 0 5033 #define AVDD_EXT 1 5034 5035 #endif /* __ASSEMBLER__ */ 5036 5037 /* VREG_CTRL */ 5038 5039 #define DVDD_OK 2 5040 #define DVREG_EXT 3 5041 #define AVDD_OK 6 5042 #define AVREG_EXT 7 5043 5044 /* Battery Monitor Control and Status Register */ 5045 #define BATMON _SFR_MEM8(0x151) 5046 5047 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5048 5049 struct __reg_BATMON { 5050 unsigned int batmon_vth : 4; /* Battery Monitor Threshold Voltage */ 5051 unsigned int batmon_hr : 1; /* Battery Monitor Voltage Range */ 5052 unsigned int batmon_ok : 1; /* Battery Monitor Status */ 5053 unsigned int bat_low_en : 1; /* Battery Monitor Interrupt Enable */ 5054 unsigned int bat_low : 1; /* Battery Monitor Interrupt Status */ 5055 }; 5056 5057 #define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON) 5058 5059 /* symbolic names */ 5060 5061 #define BATMON_HR_DIS 0 5062 #define BATMON_HR_EN 1 5063 5064 #endif /* __ASSEMBLER__ */ 5065 5066 /* BATMON */ 5067 5068 #define BATMON_VTH0 0 5069 #define BATMON_VTH1 1 5070 #define BATMON_VTH2 2 5071 #define BATMON_VTH3 3 5072 #define BATMON_HR 4 5073 #define BATMON_OK 5 5074 #define BAT_LOW_EN 6 5075 #define BAT_LOW 7 5076 5077 /* Crystal Oscillator Control Register */ 5078 #define XOSC_CTRL _SFR_MEM8(0x152) 5079 5080 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5081 5082 struct __reg_XOSC_CTRL { 5083 unsigned int xtal_trim : 4; /* Crystal Oscillator Load Capacitance Trimming */ 5084 unsigned int xtal_mode : 4; /* Crystal Oscillator Operating Mode */ 5085 }; 5086 5087 #define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL) 5088 5089 /* symbolic names */ 5090 5091 #define XTAL_TRIM_MIN 0 5092 #define XTAL_TRIM_MAX 15 5093 5094 #endif /* __ASSEMBLER__ */ 5095 5096 /* XOSC_CTRL */ 5097 5098 #define XTAL_TRIM0 0 5099 #define XTAL_TRIM1 1 5100 #define XTAL_TRIM2 2 5101 #define XTAL_TRIM3 3 5102 #define XTAL_MODE0 4 5103 #define XTAL_MODE1 5 5104 #define XTAL_MODE2 6 5105 #define XTAL_MODE3 7 5106 5107 /* Channel Control Register 0 */ 5108 #define CC_CTRL_0 _SFR_MEM8(0x153) 5109 5110 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5111 5112 struct __reg_CC_CTRL_0 { 5113 unsigned int cc_number : 8; /* Channel Number */ 5114 }; 5115 5116 #define CC_CTRL_0_struct _SFR_MEM8_STRUCT(0x153, struct __reg_CC_CTRL_0) 5117 5118 #endif /* __ASSEMBLER__ */ 5119 5120 /* CC_CTRL_0 */ 5121 5122 #define CC_NUMBER0 0 5123 #define CC_NUMBER1 1 5124 #define CC_NUMBER2 2 5125 #define CC_NUMBER3 3 5126 #define CC_NUMBER4 4 5127 #define CC_NUMBER5 5 5128 #define CC_NUMBER6 6 5129 #define CC_NUMBER7 7 5130 5131 /* Channel Control Register 1 */ 5132 #define CC_CTRL_1 _SFR_MEM8(0x154) 5133 5134 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5135 5136 struct __reg_CC_CTRL_1 { 5137 unsigned int cc_band : 4; /* Channel Band */ 5138 unsigned int : 4; 5139 }; 5140 5141 #define CC_CTRL_1_struct _SFR_MEM8_STRUCT(0x154, struct __reg_CC_CTRL_1) 5142 5143 #endif /* __ASSEMBLER__ */ 5144 5145 /* CC_CTRL_1 */ 5146 5147 #define CC_BAND0 0 5148 #define CC_BAND1 1 5149 #define CC_BAND2 2 5150 #define CC_BAND3 3 5151 5152 /* Transceiver Receiver Sensitivity Control Register */ 5153 #define RX_SYN _SFR_MEM8(0x155) 5154 5155 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5156 5157 struct __reg_RX_SYN { 5158 unsigned int rx_pdt_level : 4; /* Reduce Receiver Sensitivity */ 5159 unsigned int : 2; 5160 unsigned int rx_override : 1; /* Receiver Override Function */ 5161 unsigned int rx_pdt_dis : 1; /* Prevent Frame Reception */ 5162 }; 5163 5164 #define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN) 5165 5166 /* symbolic names */ 5167 5168 #define RX_PDT_LEVEL_MIN 0 5169 #define RX_PDT_LEVEL_MAX 15 5170 5171 #endif /* __ASSEMBLER__ */ 5172 5173 /* RX_SYN */ 5174 5175 #define RX_PDT_LEVEL0 0 5176 #define RX_PDT_LEVEL1 1 5177 #define RX_PDT_LEVEL2 2 5178 #define RX_PDT_LEVEL3 3 5179 #define RX_OVERRIDE 6 5180 #define RX_PDT_DIS 7 5181 5182 /* Transceiver Reduced Power Consumption Control */ 5183 #define TRX_RPC _SFR_MEM8(0x156) 5184 5185 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5186 5187 struct __reg_TRX_RPC { 5188 unsigned int : 1; 5189 unsigned int ipan_rpc_en : 1; /* Smart Receiving Mode IPAN Handling Enable */ 5190 unsigned int res0 : 1; /* Reserved */ 5191 unsigned int pll_rpc_en : 1; /* PLL Smart Receiving Mode Enable */ 5192 unsigned int pdt_rpc_en : 1; /* Smart Receiving Mode Reduced Sensitivity Enable */ 5193 unsigned int rx_rpc_en : 1; /* Receiver Smart Receiving Mode Enable */ 5194 unsigned int rx_rpc_ctrl : 2; /* Smart Receiving Mode Timing */ 5195 }; 5196 5197 #define TRX_RPC_struct _SFR_MEM8_STRUCT(0x156, struct __reg_TRX_RPC) 5198 5199 #endif /* __ASSEMBLER__ */ 5200 5201 /* TRX_RPC */ 5202 5203 #define IPAN_RPC_EN 1 5204 #define PLL_RPC_EN 3 5205 #define PDT_RPC_EN 4 5206 #define RX_RPC_EN 5 5207 #define RX_RPC_CTRL0 6 5208 #define RX_RPC_CTRL1 7 5209 5210 /* Transceiver Acknowledgment Frame Control Register 1 */ 5211 #define XAH_CTRL_1 _SFR_MEM8(0x157) 5212 5213 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5214 5215 struct __reg_XAH_CTRL_1 { 5216 unsigned int : 1; 5217 unsigned int aack_prom_mode : 1; /* Enable Promiscuous Mode */ 5218 unsigned int aack_ack_time : 1; /* Reduce Acknowledgment Time */ 5219 unsigned int : 1; 5220 unsigned int aack_upld_res_ft : 1; /* Process Reserved Frames */ 5221 unsigned int aack_fltr_res_ft : 1; /* Filter Reserved Frames */ 5222 unsigned int : 2; 5223 }; 5224 5225 #define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1) 5226 5227 /* symbolic names */ 5228 5229 #define AACK_ACK_TIME_12_SYM 0 5230 #define AACK_ACK_TIME_2_SYM 1 5231 5232 #endif /* __ASSEMBLER__ */ 5233 5234 /* XAH_CTRL_1 */ 5235 5236 #define AACK_PROM_MODE 1 5237 #define AACK_ACK_TIME 2 5238 #define AACK_UPLD_RES_FT 4 5239 #define AACK_FLTR_RES_FT 5 5240 5241 /* Transceiver Filter Tuning Control Register */ 5242 #define FTN_CTRL _SFR_MEM8(0x158) 5243 5244 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5245 5246 struct __reg_FTN_CTRL { 5247 unsigned int : 7; 5248 unsigned int ftn_start : 1; /* Start Calibration Loop of Filter Tuning Network */ 5249 }; 5250 5251 #define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL) 5252 5253 #endif /* __ASSEMBLER__ */ 5254 5255 /* FTN_CTRL */ 5256 5257 #define FTN_START 7 5258 5259 /* Transceiver Center Frequency Calibration Control Register */ 5260 #define PLL_CF _SFR_MEM8(0x15A) 5261 5262 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5263 5264 struct __reg_PLL_CF { 5265 unsigned int : 7; 5266 unsigned int pll_cf_start : 1; /* Start Center Frequency Calibration */ 5267 }; 5268 5269 #define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF) 5270 5271 #endif /* __ASSEMBLER__ */ 5272 5273 /* PLL_CF */ 5274 5275 #define PLL_CF_START 7 5276 5277 /* Transceiver Delay Cell Calibration Control Register */ 5278 #define PLL_DCU _SFR_MEM8(0x15B) 5279 5280 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5281 5282 struct __reg_PLL_DCU { 5283 unsigned int : 7; 5284 unsigned int pll_dcu_start : 1; /* Start Delay Cell Calibration */ 5285 }; 5286 5287 #define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU) 5288 5289 #endif /* __ASSEMBLER__ */ 5290 5291 /* PLL_DCU */ 5292 5293 #define PLL_DCU_START 7 5294 5295 /* Device Identification Register (Part Number) */ 5296 #define PART_NUM _SFR_MEM8(0x15C) 5297 5298 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5299 5300 struct __reg_PART_NUM { 5301 unsigned int part_num : 8; /* Part Number */ 5302 }; 5303 5304 #define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM) 5305 5306 /* symbolic names */ 5307 5308 #define P_RFR2 148 5309 5310 #endif /* __ASSEMBLER__ */ 5311 5312 /* PART_NUM */ 5313 5314 #define PART_NUM0 0 5315 #define PART_NUM1 1 5316 #define PART_NUM2 2 5317 #define PART_NUM3 3 5318 #define PART_NUM4 4 5319 #define PART_NUM5 5 5320 #define PART_NUM6 6 5321 #define PART_NUM7 7 5322 5323 /* Device Identification Register (Version Number) */ 5324 #define VERSION_NUM _SFR_MEM8(0x15D) 5325 5326 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5327 5328 struct __reg_VERSION_NUM { 5329 unsigned int version_num : 8; /* Version Number */ 5330 }; 5331 5332 #define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM) 5333 5334 /* symbolic names */ 5335 5336 #define REV_A 12 5337 #define REV_B 1 5338 #define REV_C 3 5339 #define REV_D 4 5340 5341 #endif /* __ASSEMBLER__ */ 5342 5343 /* VERSION_NUM */ 5344 5345 #define VERSION_NUM0 0 5346 #define VERSION_NUM1 1 5347 #define VERSION_NUM2 2 5348 #define VERSION_NUM3 3 5349 #define VERSION_NUM4 4 5350 #define VERSION_NUM5 5 5351 #define VERSION_NUM6 6 5352 #define VERSION_NUM7 7 5353 5354 /* Device Identification Register (Manufacture ID Low Byte) */ 5355 #define MAN_ID_0 _SFR_MEM8(0x15E) 5356 5357 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5358 5359 struct __reg_MAN_ID_0 { 5360 unsigned int man_id_00 : 1; /* Manufacturer ID (Low Byte) */ 5361 unsigned int man_id_01 : 1; /* Manufacturer ID (Low Byte) */ 5362 unsigned int man_id_02 : 1; /* Manufacturer ID (Low Byte) */ 5363 unsigned int man_id_03 : 1; /* Manufacturer ID (Low Byte) */ 5364 unsigned int man_id_04 : 1; /* Manufacturer ID (Low Byte) */ 5365 unsigned int man_id_05 : 1; /* Manufacturer ID (Low Byte) */ 5366 unsigned int man_id_06 : 1; /* Manufacturer ID (Low Byte) */ 5367 unsigned int man_id_07 : 1; /* Manufacturer ID (Low Byte) */ 5368 }; 5369 5370 #define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0) 5371 5372 /* symbolic names */ 5373 5374 #define ATMEL_BYTE_0 31 5375 5376 #endif /* __ASSEMBLER__ */ 5377 5378 /* MAN_ID_0 */ 5379 5380 #define MAN_ID_00 0 5381 #define MAN_ID_01 1 5382 #define MAN_ID_02 2 5383 #define MAN_ID_03 3 5384 #define MAN_ID_04 4 5385 #define MAN_ID_05 5 5386 #define MAN_ID_06 6 5387 #define MAN_ID_07 7 5388 5389 /* Device Identification Register (Manufacture ID High Byte) */ 5390 #define MAN_ID_1 _SFR_MEM8(0x15F) 5391 5392 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5393 5394 struct __reg_MAN_ID_1 { 5395 unsigned int man_id_ : 8; /* Manufacturer ID (High Byte) */ 5396 }; 5397 5398 #define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1) 5399 5400 /* symbolic names */ 5401 5402 #define ATMEL_BYTE_1 0 5403 5404 #endif /* __ASSEMBLER__ */ 5405 5406 /* MAN_ID_1 */ 5407 5408 #define MAN_ID_10 0 5409 #define MAN_ID_11 1 5410 #define MAN_ID_12 2 5411 #define MAN_ID_13 3 5412 #define MAN_ID_14 4 5413 #define MAN_ID_15 5 5414 #define MAN_ID_16 6 5415 #define MAN_ID_17 7 5416 5417 /* Transceiver MAC Short Address Register (Low Byte) */ 5418 #define SHORT_ADDR_0 _SFR_MEM8(0x160) 5419 5420 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5421 5422 struct __reg_SHORT_ADDR_0 { 5423 unsigned int short_addr_00 : 1; /* MAC Short Address */ 5424 unsigned int short_addr_01 : 1; /* MAC Short Address */ 5425 unsigned int short_addr_02 : 1; /* MAC Short Address */ 5426 unsigned int short_addr_03 : 1; /* MAC Short Address */ 5427 unsigned int short_addr_04 : 1; /* MAC Short Address */ 5428 unsigned int short_addr_05 : 1; /* MAC Short Address */ 5429 unsigned int short_addr_06 : 1; /* MAC Short Address */ 5430 unsigned int short_addr_07 : 1; /* MAC Short Address */ 5431 }; 5432 5433 #define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0) 5434 5435 #endif /* __ASSEMBLER__ */ 5436 5437 /* SHORT_ADDR_0 */ 5438 5439 #define SHORT_ADDR_00 0 5440 #define SHORT_ADDR_01 1 5441 #define SHORT_ADDR_02 2 5442 #define SHORT_ADDR_03 3 5443 #define SHORT_ADDR_04 4 5444 #define SHORT_ADDR_05 5 5445 #define SHORT_ADDR_06 6 5446 #define SHORT_ADDR_07 7 5447 5448 /* Transceiver MAC Short Address Register (High Byte) */ 5449 #define SHORT_ADDR_1 _SFR_MEM8(0x161) 5450 5451 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5452 5453 struct __reg_SHORT_ADDR_1 { 5454 unsigned int short_addr_ : 8; /* MAC Short Address */ 5455 }; 5456 5457 #define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1) 5458 5459 #endif /* __ASSEMBLER__ */ 5460 5461 /* SHORT_ADDR_1 */ 5462 5463 #define SHORT_ADDR_10 0 5464 #define SHORT_ADDR_11 1 5465 #define SHORT_ADDR_12 2 5466 #define SHORT_ADDR_13 3 5467 #define SHORT_ADDR_14 4 5468 #define SHORT_ADDR_15 5 5469 #define SHORT_ADDR_16 6 5470 #define SHORT_ADDR_17 7 5471 5472 /* Transceiver Personal Area Network ID Register (Low Byte) */ 5473 #define PAN_ID_0 _SFR_MEM8(0x162) 5474 5475 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5476 5477 struct __reg_PAN_ID_0 { 5478 unsigned int pan_id_00 : 1; /* MAC Personal Area Network ID */ 5479 unsigned int pan_id_01 : 1; /* MAC Personal Area Network ID */ 5480 unsigned int pan_id_02 : 1; /* MAC Personal Area Network ID */ 5481 unsigned int pan_id_03 : 1; /* MAC Personal Area Network ID */ 5482 unsigned int pan_id_04 : 1; /* MAC Personal Area Network ID */ 5483 unsigned int pan_id_05 : 1; /* MAC Personal Area Network ID */ 5484 unsigned int pan_id_06 : 1; /* MAC Personal Area Network ID */ 5485 unsigned int pan_id_07 : 1; /* MAC Personal Area Network ID */ 5486 }; 5487 5488 #define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0) 5489 5490 #endif /* __ASSEMBLER__ */ 5491 5492 /* PAN_ID_0 */ 5493 5494 #define PAN_ID_00 0 5495 #define PAN_ID_01 1 5496 #define PAN_ID_02 2 5497 #define PAN_ID_03 3 5498 #define PAN_ID_04 4 5499 #define PAN_ID_05 5 5500 #define PAN_ID_06 6 5501 #define PAN_ID_07 7 5502 5503 /* Transceiver Personal Area Network ID Register (High Byte) */ 5504 #define PAN_ID_1 _SFR_MEM8(0x163) 5505 5506 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5507 5508 struct __reg_PAN_ID_1 { 5509 unsigned int pan_id_ : 8; /* MAC Personal Area Network ID */ 5510 }; 5511 5512 #define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1) 5513 5514 #endif /* __ASSEMBLER__ */ 5515 5516 /* PAN_ID_1 */ 5517 5518 #define PAN_ID_10 0 5519 #define PAN_ID_11 1 5520 #define PAN_ID_12 2 5521 #define PAN_ID_13 3 5522 #define PAN_ID_14 4 5523 #define PAN_ID_15 5 5524 #define PAN_ID_16 6 5525 #define PAN_ID_17 7 5526 5527 /* Transceiver MAC IEEE Address Register 0 */ 5528 #define IEEE_ADDR_0 _SFR_MEM8(0x164) 5529 5530 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5531 5532 struct __reg_IEEE_ADDR_0 { 5533 unsigned int ieee_addr_00 : 1; /* MAC IEEE Address */ 5534 unsigned int ieee_addr_01 : 1; /* MAC IEEE Address */ 5535 unsigned int ieee_addr_02 : 1; /* MAC IEEE Address */ 5536 unsigned int ieee_addr_03 : 1; /* MAC IEEE Address */ 5537 unsigned int ieee_addr_04 : 1; /* MAC IEEE Address */ 5538 unsigned int ieee_addr_05 : 1; /* MAC IEEE Address */ 5539 unsigned int ieee_addr_06 : 1; /* MAC IEEE Address */ 5540 unsigned int ieee_addr_07 : 1; /* MAC IEEE Address */ 5541 }; 5542 5543 #define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0) 5544 5545 #endif /* __ASSEMBLER__ */ 5546 5547 /* IEEE_ADDR_0 */ 5548 5549 #define IEEE_ADDR_00 0 5550 #define IEEE_ADDR_01 1 5551 #define IEEE_ADDR_02 2 5552 #define IEEE_ADDR_03 3 5553 #define IEEE_ADDR_04 4 5554 #define IEEE_ADDR_05 5 5555 #define IEEE_ADDR_06 6 5556 #define IEEE_ADDR_07 7 5557 5558 /* Transceiver MAC IEEE Address Register 1 */ 5559 #define IEEE_ADDR_1 _SFR_MEM8(0x165) 5560 5561 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5562 5563 struct __reg_IEEE_ADDR_1 { 5564 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5565 }; 5566 5567 #define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1) 5568 5569 #endif /* __ASSEMBLER__ */ 5570 5571 /* IEEE_ADDR_1 */ 5572 5573 #define IEEE_ADDR_10 0 5574 #define IEEE_ADDR_11 1 5575 #define IEEE_ADDR_12 2 5576 #define IEEE_ADDR_13 3 5577 #define IEEE_ADDR_14 4 5578 #define IEEE_ADDR_15 5 5579 #define IEEE_ADDR_16 6 5580 #define IEEE_ADDR_17 7 5581 5582 /* Transceiver MAC IEEE Address Register 2 */ 5583 #define IEEE_ADDR_2 _SFR_MEM8(0x166) 5584 5585 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5586 5587 struct __reg_IEEE_ADDR_2 { 5588 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5589 }; 5590 5591 #define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2) 5592 5593 #endif /* __ASSEMBLER__ */ 5594 5595 /* IEEE_ADDR_2 */ 5596 5597 #define IEEE_ADDR_20 0 5598 #define IEEE_ADDR_21 1 5599 #define IEEE_ADDR_22 2 5600 #define IEEE_ADDR_23 3 5601 #define IEEE_ADDR_24 4 5602 #define IEEE_ADDR_25 5 5603 #define IEEE_ADDR_26 6 5604 #define IEEE_ADDR_27 7 5605 5606 /* Transceiver MAC IEEE Address Register 3 */ 5607 #define IEEE_ADDR_3 _SFR_MEM8(0x167) 5608 5609 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5610 5611 struct __reg_IEEE_ADDR_3 { 5612 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5613 }; 5614 5615 #define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3) 5616 5617 #endif /* __ASSEMBLER__ */ 5618 5619 /* IEEE_ADDR_3 */ 5620 5621 #define IEEE_ADDR_30 0 5622 #define IEEE_ADDR_31 1 5623 #define IEEE_ADDR_32 2 5624 #define IEEE_ADDR_33 3 5625 #define IEEE_ADDR_34 4 5626 #define IEEE_ADDR_35 5 5627 #define IEEE_ADDR_36 6 5628 #define IEEE_ADDR_37 7 5629 5630 /* Transceiver MAC IEEE Address Register 4 */ 5631 #define IEEE_ADDR_4 _SFR_MEM8(0x168) 5632 5633 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5634 5635 struct __reg_IEEE_ADDR_4 { 5636 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5637 }; 5638 5639 #define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4) 5640 5641 #endif /* __ASSEMBLER__ */ 5642 5643 /* IEEE_ADDR_4 */ 5644 5645 #define IEEE_ADDR_40 0 5646 #define IEEE_ADDR_41 1 5647 #define IEEE_ADDR_42 2 5648 #define IEEE_ADDR_43 3 5649 #define IEEE_ADDR_44 4 5650 #define IEEE_ADDR_45 5 5651 #define IEEE_ADDR_46 6 5652 #define IEEE_ADDR_47 7 5653 5654 /* Transceiver MAC IEEE Address Register 5 */ 5655 #define IEEE_ADDR_5 _SFR_MEM8(0x169) 5656 5657 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5658 5659 struct __reg_IEEE_ADDR_5 { 5660 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5661 }; 5662 5663 #define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5) 5664 5665 #endif /* __ASSEMBLER__ */ 5666 5667 /* IEEE_ADDR_5 */ 5668 5669 #define IEEE_ADDR_50 0 5670 #define IEEE_ADDR_51 1 5671 #define IEEE_ADDR_52 2 5672 #define IEEE_ADDR_53 3 5673 #define IEEE_ADDR_54 4 5674 #define IEEE_ADDR_55 5 5675 #define IEEE_ADDR_56 6 5676 #define IEEE_ADDR_57 7 5677 5678 /* Transceiver MAC IEEE Address Register 6 */ 5679 #define IEEE_ADDR_6 _SFR_MEM8(0x16A) 5680 5681 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5682 5683 struct __reg_IEEE_ADDR_6 { 5684 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5685 }; 5686 5687 #define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6) 5688 5689 #endif /* __ASSEMBLER__ */ 5690 5691 /* IEEE_ADDR_6 */ 5692 5693 #define IEEE_ADDR_60 0 5694 #define IEEE_ADDR_61 1 5695 #define IEEE_ADDR_62 2 5696 #define IEEE_ADDR_63 3 5697 #define IEEE_ADDR_64 4 5698 #define IEEE_ADDR_65 5 5699 #define IEEE_ADDR_66 6 5700 #define IEEE_ADDR_67 7 5701 5702 /* Transceiver MAC IEEE Address Register 7 */ 5703 #define IEEE_ADDR_7 _SFR_MEM8(0x16B) 5704 5705 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5706 5707 struct __reg_IEEE_ADDR_7 { 5708 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5709 }; 5710 5711 #define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7) 5712 5713 #endif /* __ASSEMBLER__ */ 5714 5715 /* IEEE_ADDR_7 */ 5716 5717 #define IEEE_ADDR_70 0 5718 #define IEEE_ADDR_71 1 5719 #define IEEE_ADDR_72 2 5720 #define IEEE_ADDR_73 3 5721 #define IEEE_ADDR_74 4 5722 #define IEEE_ADDR_75 5 5723 #define IEEE_ADDR_76 6 5724 #define IEEE_ADDR_77 7 5725 5726 /* Transceiver Extended Operating Mode Control Register */ 5727 #define XAH_CTRL_0 _SFR_MEM8(0x16C) 5728 5729 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5730 5731 struct __reg_XAH_CTRL_0 { 5732 unsigned int slotted_operation : 1; /* Set Slotted Acknowledgment */ 5733 unsigned int max_csma_retries : 3; /* Maximum Number of CSMA-CA Procedure Repetition Attempts */ 5734 unsigned int max_frame_retries : 4; /* Maximum Number of Frame Re-transmission Attempts */ 5735 }; 5736 5737 #define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0) 5738 5739 /* symbolic names */ 5740 5741 #define SLOTTED_OP_DIS 0 5742 #define SLOTTED_OP_EN 1 5743 5744 #endif /* __ASSEMBLER__ */ 5745 5746 /* XAH_CTRL_0 */ 5747 5748 #define SLOTTED_OPERATION 0 5749 #define MAX_CSMA_RETRIES0 1 5750 #define MAX_CSMA_RETRIES1 2 5751 #define MAX_CSMA_RETRIES2 3 5752 #define MAX_FRAME_RETRIES0 4 5753 #define MAX_FRAME_RETRIES1 5 5754 #define MAX_FRAME_RETRIES2 6 5755 #define MAX_FRAME_RETRIES3 7 5756 5757 /* Transceiver CSMA-CA Random Number Generator Seed Register */ 5758 #define CSMA_SEED_0 _SFR_MEM8(0x16D) 5759 5760 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5761 5762 struct __reg_CSMA_SEED_0 { 5763 unsigned int csma_seed_00 : 1; /* Seed Value for CSMA Random Number Generator */ 5764 unsigned int csma_seed_01 : 1; /* Seed Value for CSMA Random Number Generator */ 5765 unsigned int csma_seed_02 : 1; /* Seed Value for CSMA Random Number Generator */ 5766 unsigned int csma_seed_03 : 1; /* Seed Value for CSMA Random Number Generator */ 5767 unsigned int csma_seed_04 : 1; /* Seed Value for CSMA Random Number Generator */ 5768 unsigned int csma_seed_05 : 1; /* Seed Value for CSMA Random Number Generator */ 5769 unsigned int csma_seed_06 : 1; /* Seed Value for CSMA Random Number Generator */ 5770 unsigned int csma_seed_07 : 1; /* Seed Value for CSMA Random Number Generator */ 5771 }; 5772 5773 #define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0) 5774 5775 #endif /* __ASSEMBLER__ */ 5776 5777 /* CSMA_SEED_0 */ 5778 5779 #define CSMA_SEED_00 0 5780 #define CSMA_SEED_01 1 5781 #define CSMA_SEED_02 2 5782 #define CSMA_SEED_03 3 5783 #define CSMA_SEED_04 4 5784 #define CSMA_SEED_05 5 5785 #define CSMA_SEED_06 6 5786 #define CSMA_SEED_07 7 5787 5788 /* Transceiver Acknowledgment Frame Control Register 2 */ 5789 #define CSMA_SEED_1 _SFR_MEM8(0x16E) 5790 5791 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5792 5793 struct __reg_CSMA_SEED_1 { 5794 unsigned int csma_seed_1 : 3; /* Seed Value for CSMA Random Number Generator */ 5795 unsigned int aack_i_am_coord : 1; /* Set Personal Area Network Coordinator */ 5796 unsigned int aack_dis_ack : 1; /* Disable Acknowledgment Frame Transmission */ 5797 unsigned int aack_set_pd : 1; /* Set Frame Pending Sub-field */ 5798 unsigned int aack_fvn_mode : 2; /* Acknowledgment Frame Filter Mode */ 5799 }; 5800 5801 #define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1) 5802 5803 #endif /* __ASSEMBLER__ */ 5804 5805 /* CSMA_SEED_1 */ 5806 5807 #define CSMA_SEED_10 0 5808 #define CSMA_SEED_11 1 5809 #define CSMA_SEED_12 2 5810 #define AACK_I_AM_COORD 3 5811 #define AACK_DIS_ACK 4 5812 #define AACK_SET_PD 5 5813 #define AACK_FVN_MODE0 6 5814 #define AACK_FVN_MODE1 7 5815 5816 /* Transceiver CSMA-CA Back-off Exponent Control Register */ 5817 #define CSMA_BE _SFR_MEM8(0x16F) 5818 5819 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5820 5821 struct __reg_CSMA_BE { 5822 unsigned int min_be : 4; /* Minimum Back-off Exponent */ 5823 unsigned int max_be : 4; /* Maximum Back-off Exponent */ 5824 }; 5825 5826 #define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE) 5827 5828 #endif /* __ASSEMBLER__ */ 5829 5830 /* CSMA_BE */ 5831 5832 #define MIN_BE0 0 5833 #define MIN_BE1 1 5834 #define MIN_BE2 2 5835 #define MIN_BE3 3 5836 #define MAX_BE0 4 5837 #define MAX_BE1 5 5838 #define MAX_BE2 6 5839 #define MAX_BE3 7 5840 5841 /* Transceiver Digital Test Control Register */ 5842 #define TST_CTRL_DIGI _SFR_MEM8(0x176) 5843 5844 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5845 5846 struct __reg_TST_CTRL_DIGI { 5847 unsigned int tst_ctrl_dig : 4; /* Digital Test Controller Register */ 5848 unsigned int : 4; 5849 }; 5850 5851 #define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI) 5852 5853 #endif /* __ASSEMBLER__ */ 5854 5855 /* TST_CTRL_DIGI */ 5856 5857 #define TST_CTRL_DIG0 0 5858 #define TST_CTRL_DIG1 1 5859 #define TST_CTRL_DIG2 2 5860 #define TST_CTRL_DIG3 3 5861 5862 /* Transceiver Received Frame Length Register */ 5863 #define TST_RX_LENGTH _SFR_MEM8(0x17B) 5864 5865 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5866 5867 struct __reg_TST_RX_LENGTH { 5868 unsigned int rx_length : 8; /* Received Frame Length */ 5869 }; 5870 5871 #define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH) 5872 5873 #endif /* __ASSEMBLER__ */ 5874 5875 /* TST_RX_LENGTH */ 5876 5877 #define RX_LENGTH0 0 5878 #define RX_LENGTH1 1 5879 #define RX_LENGTH2 2 5880 #define RX_LENGTH3 3 5881 #define RX_LENGTH4 4 5882 #define RX_LENGTH5 5 5883 #define RX_LENGTH6 6 5884 #define RX_LENGTH7 7 5885 5886 /* Start of frame buffer */ 5887 #define TRXFBST _SFR_MEM8(0x180) 5888 5889 /* TRXFBST */ 5890 5891 #define TRXFBST0 0 5892 #define TRXFBST1 1 5893 #define TRXFBST2 2 5894 #define TRXFBST3 3 5895 #define TRXFBST4 4 5896 #define TRXFBST5 5 5897 #define TRXFBST6 6 5898 #define TRXFBST7 7 5899 5900 /* End of frame buffer */ 5901 #define TRXFBEND _SFR_MEM8(0x1FF) 5902 5903 /* TRXFBEND */ 5904 5905 #define TRXFBEND0 0 5906 #define TRXFBEND1 1 5907 #define TRXFBEND2 2 5908 #define TRXFBEND3 3 5909 #define TRXFBEND4 4 5910 #define TRXFBEND5 5 5911 #define TRXFBEND6 6 5912 #define TRXFBEND7 7 5913 5914 5915 /* Interrupt vectors */ 5916 /* Vector 0 is the reset vector */ 5917 5918 #define _VECTORS_SIZE 308 5919 5920 /* External Interrupt Request 0 */ 5921 #define INT0_vect _VECTOR(1) 5922 #define INT0_vect_num 1 5923 5924 /* External Interrupt Request 1 */ 5925 #define INT1_vect _VECTOR(2) 5926 #define INT1_vect_num 2 5927 5928 /* External Interrupt Request 2 */ 5929 #define INT2_vect _VECTOR(3) 5930 #define INT2_vect_num 3 5931 5932 /* External Interrupt Request 3 */ 5933 #define INT3_vect _VECTOR(4) 5934 #define INT3_vect_num 4 5935 5936 /* External Interrupt Request 4 */ 5937 #define INT4_vect _VECTOR(5) 5938 #define INT4_vect_num 5 5939 5940 /* External Interrupt Request 5 */ 5941 #define INT5_vect _VECTOR(6) 5942 #define INT5_vect_num 6 5943 5944 /* External Interrupt Request 6 */ 5945 #define INT6_vect _VECTOR(7) 5946 #define INT6_vect_num 7 5947 5948 /* External Interrupt Request 7 */ 5949 #define INT7_vect _VECTOR(8) 5950 #define INT7_vect_num 8 5951 5952 /* Pin Change Interrupt Request 0 */ 5953 #define PCINT0_vect _VECTOR(9) 5954 #define PCINT0_vect_num 9 5955 5956 /* Pin Change Interrupt Request 1 */ 5957 #define PCINT1_vect _VECTOR(10) 5958 #define PCINT1_vect_num 10 5959 5960 /* Pin Change Interrupt Request 2 */ 5961 #define PCINT2_vect _VECTOR(11) 5962 #define PCINT2_vect_num 11 5963 5964 /* Watchdog Time-out Interrupt */ 5965 #define WDT_vect _VECTOR(12) 5966 #define WDT_vect_num 12 5967 5968 /* Timer/Counter2 Compare Match A */ 5969 #define TIMER2_COMPA_vect _VECTOR(13) 5970 #define TIMER2_COMPA_vect_num 13 5971 5972 /* Timer/Counter2 Compare Match B */ 5973 #define TIMER2_COMPB_vect _VECTOR(14) 5974 #define TIMER2_COMPB_vect_num 14 5975 5976 /* Timer/Counter2 Overflow */ 5977 #define TIMER2_OVF_vect _VECTOR(15) 5978 #define TIMER2_OVF_vect_num 15 5979 5980 /* Timer/Counter1 Capture Event */ 5981 #define TIMER1_CAPT_vect _VECTOR(16) 5982 #define TIMER1_CAPT_vect_num 16 5983 5984 /* Timer/Counter1 Compare Match A */ 5985 #define TIMER1_COMPA_vect _VECTOR(17) 5986 #define TIMER1_COMPA_vect_num 17 5987 5988 /* Timer/Counter1 Compare Match B */ 5989 #define TIMER1_COMPB_vect _VECTOR(18) 5990 #define TIMER1_COMPB_vect_num 18 5991 5992 /* Timer/Counter1 Compare Match C */ 5993 #define TIMER1_COMPC_vect _VECTOR(19) 5994 #define TIMER1_COMPC_vect_num 19 5995 5996 /* Timer/Counter1 Overflow */ 5997 #define TIMER1_OVF_vect _VECTOR(20) 5998 #define TIMER1_OVF_vect_num 20 5999 6000 /* Timer/Counter0 Compare Match A */ 6001 #define TIMER0_COMPA_vect _VECTOR(21) 6002 #define TIMER0_COMPA_vect_num 21 6003 6004 /* Timer/Counter0 Compare Match B */ 6005 #define TIMER0_COMPB_vect _VECTOR(22) 6006 #define TIMER0_COMPB_vect_num 22 6007 6008 /* Timer/Counter0 Overflow */ 6009 #define TIMER0_OVF_vect _VECTOR(23) 6010 #define TIMER0_OVF_vect_num 23 6011 6012 /* SPI Serial Transfer Complete */ 6013 #define SPI_STC_vect _VECTOR(24) 6014 #define SPI_STC_vect_num 24 6015 6016 /* USART0, Rx Complete */ 6017 #define USART0_RX_vect _VECTOR(25) 6018 #define USART0_RX_vect_num 25 6019 6020 /* USART0 Data register Empty */ 6021 #define USART0_UDRE_vect _VECTOR(26) 6022 #define USART0_UDRE_vect_num 26 6023 6024 /* USART0, Tx Complete */ 6025 #define USART0_TX_vect _VECTOR(27) 6026 #define USART0_TX_vect_num 27 6027 6028 /* Analog Comparator */ 6029 #define ANALOG_COMP_vect _VECTOR(28) 6030 #define ANALOG_COMP_vect_num 28 6031 6032 /* ADC Conversion Complete */ 6033 #define ADC_vect _VECTOR(29) 6034 #define ADC_vect_num 29 6035 6036 /* EEPROM Ready */ 6037 #define EE_READY_vect _VECTOR(30) 6038 #define EE_READY_vect_num 30 6039 6040 /* Timer/Counter3 Capture Event */ 6041 #define TIMER3_CAPT_vect _VECTOR(31) 6042 #define TIMER3_CAPT_vect_num 31 6043 6044 /* Timer/Counter3 Compare Match A */ 6045 #define TIMER3_COMPA_vect _VECTOR(32) 6046 #define TIMER3_COMPA_vect_num 32 6047 6048 /* Timer/Counter3 Compare Match B */ 6049 #define TIMER3_COMPB_vect _VECTOR(33) 6050 #define TIMER3_COMPB_vect_num 33 6051 6052 /* Timer/Counter3 Compare Match C */ 6053 #define TIMER3_COMPC_vect _VECTOR(34) 6054 #define TIMER3_COMPC_vect_num 34 6055 6056 /* Timer/Counter3 Overflow */ 6057 #define TIMER3_OVF_vect _VECTOR(35) 6058 #define TIMER3_OVF_vect_num 35 6059 6060 /* USART1, Rx Complete */ 6061 #define USART1_RX_vect _VECTOR(36) 6062 #define USART1_RX_vect_num 36 6063 6064 /* USART1 Data register Empty */ 6065 #define USART1_UDRE_vect _VECTOR(37) 6066 #define USART1_UDRE_vect_num 37 6067 6068 /* USART1, Tx Complete */ 6069 #define USART1_TX_vect _VECTOR(38) 6070 #define USART1_TX_vect_num 38 6071 6072 /* 2-wire Serial Interface */ 6073 #define TWI_vect _VECTOR(39) 6074 #define TWI_vect_num 39 6075 6076 /* Store Program Memory Read */ 6077 #define SPM_READY_vect _VECTOR(40) 6078 #define SPM_READY_vect_num 40 6079 6080 /* Timer/Counter4 Capture Event */ 6081 #define TIMER4_CAPT_vect _VECTOR(41) 6082 #define TIMER4_CAPT_vect_num 41 6083 6084 /* Timer/Counter4 Compare Match A */ 6085 #define TIMER4_COMPA_vect _VECTOR(42) 6086 #define TIMER4_COMPA_vect_num 42 6087 6088 /* Timer/Counter4 Compare Match B */ 6089 #define TIMER4_COMPB_vect _VECTOR(43) 6090 #define TIMER4_COMPB_vect_num 43 6091 6092 /* Timer/Counter4 Compare Match C */ 6093 #define TIMER4_COMPC_vect _VECTOR(44) 6094 #define TIMER4_COMPC_vect_num 44 6095 6096 /* Timer/Counter4 Overflow */ 6097 #define TIMER4_OVF_vect _VECTOR(45) 6098 #define TIMER4_OVF_vect_num 45 6099 6100 /* Timer/Counter5 Capture Event */ 6101 #define TIMER5_CAPT_vect _VECTOR(46) 6102 #define TIMER5_CAPT_vect_num 46 6103 6104 /* Timer/Counter5 Compare Match A */ 6105 #define TIMER5_COMPA_vect _VECTOR(47) 6106 #define TIMER5_COMPA_vect_num 47 6107 6108 /* Timer/Counter5 Compare Match B */ 6109 #define TIMER5_COMPB_vect _VECTOR(48) 6110 #define TIMER5_COMPB_vect_num 48 6111 6112 /* Timer/Counter5 Compare Match C */ 6113 #define TIMER5_COMPC_vect _VECTOR(49) 6114 #define TIMER5_COMPC_vect_num 49 6115 6116 /* Timer/Counter5 Overflow */ 6117 #define TIMER5_OVF_vect _VECTOR(50) 6118 #define TIMER5_OVF_vect_num 50 6119 6120 /* Reserved, vector numbers above has to be kept unchanged */ 6121 #define RESERVED_51_vect _VECTOR(51) 6122 #define RESERVED_51_vect_num 51 6123 6124 /* Reserved, vector numbers above has to be kept unchanged */ 6125 #define RESERVED_52_vect _VECTOR(52) 6126 #define RESERVED_52_vect_num 52 6127 6128 /* Reserved, vector numbers above has to be kept unchanged */ 6129 #define RESERVED_53_vect _VECTOR(53) 6130 #define RESERVED_53_vect_num 53 6131 6132 /* Reserved, vector numbers above has to be kept unchanged */ 6133 #define RESERVED_54_vect _VECTOR(54) 6134 #define RESERVED_54_vect_num 54 6135 6136 /* Reserved, vector numbers above has to be kept unchanged */ 6137 #define RESERVED_55_vect _VECTOR(55) 6138 #define RESERVED_55_vect_num 55 6139 6140 /* Reserved, vector numbers above has to be kept unchanged */ 6141 #define RESERVED_56_vect _VECTOR(56) 6142 #define RESERVED_56_vect_num 56 6143 6144 /* TRX24 - PLL lock interrupt */ 6145 #define TRX24_PLL_LOCK_vect _VECTOR(57) 6146 #define TRX24_PLL_LOCK_vect_num 57 6147 6148 /* TRX24 - PLL unlock interrupt */ 6149 #define TRX24_PLL_UNLOCK_vect _VECTOR(58) 6150 #define TRX24_PLL_UNLOCK_vect_num 58 6151 6152 /* TRX24 - Receive start interrupt */ 6153 #define TRX24_RX_START_vect _VECTOR(59) 6154 #define TRX24_RX_START_vect_num 59 6155 6156 /* TRX24 - RX_END interrupt */ 6157 #define TRX24_RX_END_vect _VECTOR(60) 6158 #define TRX24_RX_END_vect_num 60 6159 6160 /* TRX24 - CCA/ED done interrupt */ 6161 #define TRX24_CCA_ED_DONE_vect _VECTOR(61) 6162 #define TRX24_CCA_ED_DONE_vect_num 61 6163 6164 /* TRX24 - XAH - AMI */ 6165 #define TRX24_XAH_AMI_vect _VECTOR(62) 6166 #define TRX24_XAH_AMI_vect_num 62 6167 6168 /* TRX24 - TX_END interrupt */ 6169 #define TRX24_TX_END_vect _VECTOR(63) 6170 #define TRX24_TX_END_vect_num 63 6171 6172 /* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ 6173 #define TRX24_AWAKE_vect _VECTOR(64) 6174 #define TRX24_AWAKE_vect_num 64 6175 6176 /* Symbol counter - compare match 1 interrupt */ 6177 #define SCNT_CMP1_vect _VECTOR(65) 6178 #define SCNT_CMP1_vect_num 65 6179 6180 /* Symbol counter - compare match 2 interrupt */ 6181 #define SCNT_CMP2_vect _VECTOR(66) 6182 #define SCNT_CMP2_vect_num 66 6183 6184 /* Symbol counter - compare match 3 interrupt */ 6185 #define SCNT_CMP3_vect _VECTOR(67) 6186 #define SCNT_CMP3_vect_num 67 6187 6188 /* Symbol counter - overflow interrupt */ 6189 #define SCNT_OVFL_vect _VECTOR(68) 6190 #define SCNT_OVFL_vect_num 68 6191 6192 /* Symbol counter - backoff interrupt */ 6193 #define SCNT_BACKOFF_vect _VECTOR(69) 6194 #define SCNT_BACKOFF_vect_num 69 6195 6196 /* AES engine ready interrupt */ 6197 #define AES_READY_vect _VECTOR(70) 6198 #define AES_READY_vect_num 70 6199 6200 /* Battery monitor indicates supply voltage below threshold */ 6201 #define BAT_LOW_vect _VECTOR(71) 6202 #define BAT_LOW_vect_num 71 6203 6204 /* TRX24 TX start interrupt */ 6205 #define TRX24_TX_START_vect _VECTOR(72) 6206 #define TRX24_TX_START_vect_num 72 6207 6208 /* Address match interrupt of address filter 0 */ 6209 #define TRX24_AMI0_vect _VECTOR(73) 6210 #define TRX24_AMI0_vect_num 73 6211 6212 /* Address match interrupt of address filter 1 */ 6213 #define TRX24_AMI1_vect _VECTOR(74) 6214 #define TRX24_AMI1_vect_num 74 6215 6216 /* Address match interrupt of address filter 2 */ 6217 #define TRX24_AMI2_vect _VECTOR(75) 6218 #define TRX24_AMI2_vect_num 75 6219 6220 /* Address match interrupt of address filter 3 */ 6221 #define TRX24_AMI3_vect _VECTOR(76) 6222 #define TRX24_AMI3_vect_num 76 6223 6224 6225 /* memory parameters */ 6226 6227 #define SPM_PAGESIZE (256) 6228 #define RAMSTART (0x200) 6229 #define RAMSIZE (0x8000) 6230 #define RAMEND (0x81FF) 6231 #define XRAMSTART (0x0000) 6232 #define XRAMSIZE (0x0000) 6233 #define XRAMEND RAMEND 6234 #define E2END (0x1FFF) 6235 #define E2PAGESIZE (0x08) 6236 #define FLASHEND (0x3ffff) 6237 6238 6239 /* Fuses */ 6240 6241 #define FUSE_MEMORY_SIZE 3 6242 6243 /* LFUSE Byte */ 6244 #define FUSE_CKSEL0 ~_BV(0) /* Select Clock Source */ 6245 #define FUSE_CKSEL1 ~_BV(1) /* Select Clock Source */ 6246 #define FUSE_CKSEL2 ~_BV(2) /* Select Clock Source */ 6247 #define FUSE_CKSEL3 ~_BV(3) /* Select Clock Source */ 6248 #define FUSE_SUT0 ~_BV(4) /* Select start-up time */ 6249 #define FUSE_SUT1 ~_BV(5) /* Select start-up time */ 6250 #define FUSE_CKOUT ~_BV(6) /* Clock output */ 6251 #define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */ 6252 #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) 6253 6254 /* HFUSE Byte */ 6255 #define FUSE_BOOTRST ~_BV(0) /* Select Reset Vector */ 6256 #define FUSE_BOOTSZ0 ~_BV(1) /* Select Boot Size */ 6257 #define FUSE_BOOTSZ1 ~_BV(2) /* Select Boot Size */ 6258 #define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */ 6259 #define FUSE_WDTON ~_BV(4) /* Watchdog timer always on */ 6260 #define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */ 6261 #define FUSE_JTAGEN ~_BV(6) /* Enable JTAG */ 6262 #define FUSE_OCDEN ~_BV(7) /* Enable OCD */ 6263 #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) 6264 6265 /* EFUSE Byte */ 6266 #define FUSE_BODLEVEL0 ~_BV(0) /* Brown-out Detector trigger level */ 6267 #define FUSE_BODLEVEL1 ~_BV(1) /* Brown-out Detector trigger level */ 6268 #define FUSE_BODLEVEL2 ~_BV(2) /* Brown-out Detector trigger level */ 6269 #define EFUSE_DEFAULT (0xFF) 6270 6271 6272 6273 /* Lock Bits */ 6274 6275 #define __BOOT_LOCK_BITS_0_EXIST 6276 #define __BOOT_LOCK_BITS_1_EXIST 6277 #define __LOCK_BITS_EXIST 6278 6279 6280 /* Signature */ 6281 6282 #define SIGNATURE_0 0x1E 6283 #define SIGNATURE_1 0xA8 6284 #define SIGNATURE_2 0x03 6285 6286 #define SLEEP_MODE_IDLE (0x00<<1) 6287 #define SLEEP_MODE_ADC (0x01<<1) 6288 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 6289 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 6290 #define SLEEP_MODE_STANDBY (0x06<<1) 6291 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 6292 6293 6294 #endif /* _AVR_IOM2564RFR2_H_ */ 6295