1 /* Copyright (c) 2004, 2005, 2006, 2007 Eric B. Weddington 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: iom325.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 32 33 /* avr/iom325.h - definitions for ATmega325 and ATmega325P. */ 34 35 #ifndef _AVR_IOM325_H_ 36 #define _AVR_IOM325_H_ 1 37 38 /* This file should only be included from <avr/io.h>, never directly. */ 39 40 #ifndef _AVR_IO_H_ 41 # error "Include <avr/io.h> instead of this file." 42 #endif 43 44 #ifndef _AVR_IOXXX_H_ 45 # define _AVR_IOXXX_H_ "iom325.h" 46 #else 47 # error "Attempt to include more than one <avr/ioXXX.h> file." 48 #endif 49 50 /* Registers and associated bit numbers */ 51 52 #define PINA _SFR_IO8(0x00) 53 #define PINA7 7 54 #define PINA6 6 55 #define PINA5 5 56 #define PINA4 4 57 #define PINA3 3 58 #define PINA2 2 59 #define PINA1 1 60 #define PINA0 0 61 62 #define DDRA _SFR_IO8(0x01) 63 #define DDA7 7 64 #define DDA6 6 65 #define DDA5 5 66 #define DDA4 4 67 #define DDA3 3 68 #define DDA2 2 69 #define DDA1 1 70 #define DDA0 0 71 72 #define PORTA _SFR_IO8(0x02) 73 #define PA7 7 74 #define PA6 6 75 #define PA5 5 76 #define PA4 4 77 #define PA3 3 78 #define PA2 2 79 #define PA1 1 80 #define PA0 0 81 82 #define PINB _SFR_IO8(0x03) 83 #define PINB7 7 84 #define PINB6 6 85 #define PINB5 5 86 #define PINB4 4 87 #define PINB3 3 88 #define PINB2 2 89 #define PINB1 1 90 #define PINB0 0 91 92 #define DDRB _SFR_IO8(0x04) 93 #define DDB7 7 94 #define DDB6 6 95 #define DDB5 5 96 #define DDB4 4 97 #define DDB3 3 98 #define DDB2 2 99 #define DDB1 1 100 #define DDB0 0 101 102 #define PORTB _SFR_IO8(0x05) 103 #define PB7 7 104 #define PB6 6 105 #define PB5 5 106 #define PB4 4 107 #define PB3 3 108 #define PB2 2 109 #define PB1 1 110 #define PB0 0 111 112 #define PINC _SFR_IO8(0x06) 113 #define PINC7 7 114 #define PINC6 6 115 #define PINC5 5 116 #define PINC4 4 117 #define PINC3 3 118 #define PINC2 2 119 #define PINC1 1 120 #define PINC0 0 121 122 #define DDRC _SFR_IO8(0x07) 123 #define DDC7 7 124 #define DDC6 6 125 #define DDC5 5 126 #define DDC4 4 127 #define DDC3 3 128 #define DDC2 2 129 #define DDC1 1 130 #define DDC0 0 131 132 #define PORTC _SFR_IO8(0x08) 133 #define PC7 7 134 #define PC6 6 135 #define PC5 5 136 #define PC4 4 137 #define PC3 3 138 #define PC2 2 139 #define PC1 1 140 #define PC0 0 141 142 #define PIND _SFR_IO8(0x09) 143 #define PIND7 7 144 #define PIND6 6 145 #define PIND5 5 146 #define PIND4 4 147 #define PIND3 3 148 #define PIND2 2 149 #define PIND1 1 150 #define PIND0 0 151 152 #define DDRD _SFR_IO8(0x0A) 153 #define DDD7 7 154 #define DDD6 6 155 #define DDD5 5 156 #define DDD4 4 157 #define DDD3 3 158 #define DDD2 2 159 #define DDD1 1 160 #define DDD0 0 161 162 #define PORTD _SFR_IO8(0x0B) 163 #define PD7 7 164 #define PD6 6 165 #define PD5 5 166 #define PD4 4 167 #define PD3 3 168 #define PD2 2 169 #define PD1 1 170 #define PD0 0 171 172 #define PINE _SFR_IO8(0x0C) 173 #define PINE7 7 174 #define PINE6 6 175 #define PINE5 5 176 #define PINE4 4 177 #define PINE3 3 178 #define PINE2 2 179 #define PINE1 1 180 #define PINE0 0 181 182 #define DDRE _SFR_IO8(0x0D) 183 #define DDE7 7 184 #define DDE6 6 185 #define DDE5 5 186 #define DDE4 4 187 #define DDE3 3 188 #define DDE2 2 189 #define DDE1 1 190 #define DDE0 0 191 192 #define PORTE _SFR_IO8(0x0E) 193 #define PE7 7 194 #define PE6 6 195 #define PE5 5 196 #define PE4 4 197 #define PE3 3 198 #define PE2 2 199 #define PE1 1 200 #define PE0 0 201 202 #define PINF _SFR_IO8(0x0F) 203 #define PINF7 7 204 #define PINF6 6 205 #define PINF5 5 206 #define PINF4 4 207 #define PINF3 3 208 #define PINF2 2 209 #define PINF1 1 210 #define PINF0 0 211 212 #define DDRF _SFR_IO8(0x10) 213 #define DDF7 7 214 #define DDF6 6 215 #define DDF5 5 216 #define DDF4 4 217 #define DDF3 3 218 #define DDF2 2 219 #define DDF1 1 220 #define DDF0 0 221 222 #define PORTF _SFR_IO8(0x11) 223 #define PF7 7 224 #define PF6 6 225 #define PF5 5 226 #define PF4 4 227 #define PF3 3 228 #define PF2 2 229 #define PF1 1 230 #define PF0 0 231 232 #define PING _SFR_IO8(0x12) 233 #define PING5 5 234 #define PING4 4 235 #define PING3 3 236 #define PING2 2 237 #define PING1 1 238 #define PING0 0 239 240 #define DDRG _SFR_IO8(0x13) 241 #define DDG4 4 242 #define DDG3 3 243 #define DDG2 2 244 #define DDG1 1 245 #define DDG0 0 246 247 #define PORTG _SFR_IO8(0x14) 248 #define PG4 4 249 #define PG3 3 250 #define PG2 2 251 #define PG1 1 252 #define PG0 0 253 254 #define TIFR0 _SFR_IO8(0x15) 255 #define TOV0 0 256 #define OCF0A 1 257 258 #define TIFR1 _SFR_IO8(0x16) 259 #define TOV1 0 260 #define OCF1A 1 261 #define OCF1B 2 262 #define ICF1 5 263 264 #define TIFR2 _SFR_IO8(0x17) 265 #define TOV2 0 266 #define OCF2A 1 267 268 /* Reserved [0x18..0x1B] */ 269 270 #define EIFR _SFR_IO8(0x1C) 271 #define INTF0 0 272 #define PCIF0 4 273 #define PCIF1 5 274 275 #define EIMSK _SFR_IO8(0x1D) 276 #define INT0 0 277 #define PCIE0 4 278 #define PCIE1 5 279 280 #define GPIOR0 _SFR_IO8(0x1E) 281 282 #define EECR _SFR_IO8(0x1F) 283 #define EERE 0 284 #define EEWE 1 285 #define EEMWE 2 286 #define EERIE 3 287 288 #define EEDR _SFR_IO8(0X20) 289 290 /* Combine EEARL and EEARH */ 291 #define EEAR _SFR_IO16(0x21) 292 #define EEARL _SFR_IO8(0x21) 293 #define EEARH _SFR_IO8(0X22) 294 295 /* 6-char sequence denoting where to find the EEPROM registers in memory space. 296 Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM 297 subroutines. 298 First two letters: EECR address. 299 Second two letters: EEDR address. 300 Last two letters: EEAR address. */ 301 #define __EEPROM_REG_LOCATIONS__ 1F2021 302 303 304 #define GTCCR _SFR_IO8(0x23) 305 #define PSR10 0 306 #define PSR2 1 307 #define TSM 7 308 309 #define TCCR0A _SFR_IO8(0x24) 310 #define CS00 0 311 #define CS01 1 312 #define CS02 2 313 #define WGM01 3 314 #define COM0A0 4 315 #define COM0A1 5 316 #define WGM00 6 317 #define FOC0A 7 318 319 /* Reserved [0x25] */ 320 321 #define TCNT0 _SFR_IO8(0X26) 322 323 #define OCR0A _SFR_IO8(0X27) 324 325 /* Reserved [0x28..0x29] */ 326 327 #define GPIOR1 _SFR_IO8(0x2A) 328 329 #define GPIOR2 _SFR_IO8(0x2B) 330 331 #define SPCR _SFR_IO8(0x2C) 332 #define SPR0 0 333 #define SPR1 1 334 #define CPHA 2 335 #define CPOL 3 336 #define MSTR 4 337 #define DORD 5 338 #define SPE 6 339 #define SPIE 7 340 341 #define SPSR _SFR_IO8(0x2D) 342 #define SPI2X 0 343 #define WCOL 6 344 #define SPIF 7 345 346 #define SPDR _SFR_IO8(0X2E) 347 348 /* Reserved [0x2F] */ 349 350 #define ACSR _SFR_IO8(0x30) 351 #define ACIS0 0 352 #define ACIS1 1 353 #define ACIC 2 354 #define ACIE 3 355 #define ACI 4 356 #define ACO 5 357 #define ACBG 6 358 #define ACD 7 359 360 #define OCDR _SFR_IO8(0x31) 361 #define OCDR0 0 362 #define OCDR1 1 363 #define OCDR2 2 364 #define OCDR3 3 365 #define OCDR4 4 366 #define OCDR5 5 367 #define OCDR6 6 368 #define OCDR7 7 369 #define IDRD 7 370 371 /* Reserved [0x32] */ 372 373 #define SMCR _SFR_IO8(0x33) 374 #define SE 0 375 #define SM0 1 376 #define SM1 2 377 #define SM2 3 378 379 #define MCUSR _SFR_IO8(0x34) 380 #define PORF 0 381 #define EXTRF 1 382 #define BORF 2 383 #define WDRF 3 384 #define JTRF 4 385 386 #define MCUCR _SFR_IO8(0X35) 387 #define IVCE 0 388 #define IVSEL 1 389 #define PUD 4 390 #if defined(__AVR_ATmega325P__) 391 #define BODSE 5 392 #define BODS 6 393 #endif 394 #define JTD 7 395 396 /* Reserved [0x36] */ 397 398 #define SPMCSR _SFR_IO8(0x37) 399 #define SPMEN 0 400 #define PGERS 1 401 #define PGWRT 2 402 #define BLBSET 3 403 #define RWWSRE 4 404 #define RWWSB 6 405 #define SPMIE 7 406 407 /* Reserved [0x38..0x3C] */ 408 409 /* SP [0x3D..0x3E] */ 410 /* SREG [0x3F] */ 411 412 #define WDTCR _SFR_MEM8(0x60) 413 #define WDP0 0 414 #define WDP1 1 415 #define WDP2 2 416 #define WDE 3 417 #define WDCE 4 418 419 #define CLKPR _SFR_MEM8(0x61) 420 #define CLKPS0 0 421 #define CLKPS1 1 422 #define CLKPS2 2 423 #define CLKPS3 3 424 #define CLKPCE 7 425 426 /* Reserved [0x62..0x63] */ 427 428 #define PRR _SFR_MEM8(0x64) 429 #define PRADC 0 430 #define PRUSART0 1 431 #define PRSPI 2 432 #define PRTIM1 3 433 434 #define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)) 435 #define __AVR_HAVE_PRR_PRADC 436 #define __AVR_HAVE_PRR_PRUSART0 437 #define __AVR_HAVE_PRR_PRSPI 438 #define __AVR_HAVE_PRR_PRTIM1 439 440 /* Reserved [0x65] */ 441 442 #define OSCCAL _SFR_MEM8(0x66) 443 444 /* Reserved [0x67..0x68] */ 445 446 #define EICRA _SFR_MEM8(0x69) 447 #define ISC00 0 448 #define ISC01 1 449 450 /* Reserved [0x6A] */ 451 452 #define PCMSK0 _SFR_MEM8(0x6B) 453 #define PCINT0 0 454 #define PCINT1 1 455 #define PCINT2 2 456 #define PCINT3 3 457 #define PCINT4 4 458 #define PCINT5 5 459 #define PCINT6 6 460 #define PCINT7 7 461 462 #define PCMSK1 _SFR_MEM8(0x6C) 463 #define PCINT8 0 464 #define PCINT9 1 465 #define PCINT10 2 466 #define PCINT11 3 467 #define PCINT12 4 468 #define PCINT13 5 469 #define PCINT14 6 470 #define PCINT15 7 471 472 /* Reserved [0x6D] */ 473 474 #define TIMSK0 _SFR_MEM8(0x6E) 475 #define TOIE0 0 476 #define OCIE0A 1 477 478 #define TIMSK1 _SFR_MEM8(0x6F) 479 #define TOIE1 0 480 #define OCIE1A 1 481 #define OCIE1B 2 482 #define ICIE1 5 483 484 #define TIMSK2 _SFR_MEM8(0x70) 485 #define TOIE2 0 486 #define OCIE2A 1 487 488 /* Reserved [0x71..0x77] */ 489 490 /* Combine ADCL and ADCH */ 491 #ifndef __ASSEMBLER__ 492 #define ADC _SFR_MEM16(0x78) 493 #endif 494 #define ADCW _SFR_MEM16(0x78) 495 #define ADCL _SFR_MEM8(0x78) 496 #define ADCH _SFR_MEM8(0x79) 497 498 #define ADCSRA _SFR_MEM8(0x7A) 499 #define ADPS0 0 500 #define ADPS1 1 501 #define ADPS2 2 502 #define ADIE 3 503 #define ADIF 4 504 #define ADATE 5 505 #define ADSC 6 506 #define ADEN 7 507 508 #define ADCSRB _SFR_MEM8(0x7B) 509 #define ADTS0 0 510 #define ADTS1 1 511 #define ADTS2 2 512 #define ACME 6 513 514 #define ADMUX _SFR_MEM8(0x7C) 515 #define MUX0 0 516 #define MUX1 1 517 #define MUX2 2 518 #define MUX3 3 519 #define MUX4 4 520 #define ADLAR 5 521 #define REFS0 6 522 #define REFS1 7 523 524 /* Reserved [0x7D] */ 525 526 #define DIDR0 _SFR_MEM8(0x7E) 527 #define ADC0D 0 528 #define ADC1D 1 529 #define ADC2D 2 530 #define ADC3D 3 531 #define ADC4D 4 532 #define ADC5D 5 533 #define ADC6D 6 534 #define ADC7D 7 535 536 #define DIDR1 _SFR_MEM8(0x7F) 537 #define AIN0D 0 538 #define AIN1D 1 539 540 #define TCCR1A _SFR_MEM8(0X80) 541 #define WGM10 0 542 #define WGM11 1 543 #define COM1B0 4 544 #define COM1B1 5 545 #define COM1A0 6 546 #define COM1A1 7 547 548 #define TCCR1B _SFR_MEM8(0X81) 549 #define CS10 0 550 #define CS11 1 551 #define CS12 2 552 #define WGM12 3 553 #define WGM13 4 554 #define ICES1 6 555 #define ICNC1 7 556 557 #define TCCR1C _SFR_MEM8(0x82) 558 #define FOC1B 6 559 #define FOC1A 7 560 561 /* Reserved [0x83] */ 562 563 /* Combine TCNT1L and TCNT1H */ 564 #define TCNT1 _SFR_MEM16(0x84) 565 566 #define TCNT1L _SFR_MEM8(0x84) 567 #define TCNT1H _SFR_MEM8(0x85) 568 569 /* Combine ICR1L and ICR1H */ 570 #define ICR1 _SFR_MEM16(0x86) 571 572 #define ICR1L _SFR_MEM8(0x86) 573 #define ICR1H _SFR_MEM8(0x87) 574 575 /* Combine OCR1AL and OCR1AH */ 576 #define OCR1A _SFR_MEM16(0x88) 577 578 #define OCR1AL _SFR_MEM8(0x88) 579 #define OCR1AH _SFR_MEM8(0x89) 580 581 /* Combine OCR1BL and OCR1BH */ 582 #define OCR1B _SFR_MEM16(0x8A) 583 584 #define OCR1BL _SFR_MEM8(0x8A) 585 #define OCR1BH _SFR_MEM8(0x8B) 586 587 /* Reserved [0x8C..0xAF] */ 588 589 #define TCCR2A _SFR_MEM8(0xB0) 590 #define CS20 0 591 #define CS21 1 592 #define CS22 2 593 #define WGM21 3 594 #define COM2A0 4 595 #define COM2A1 5 596 #define WGM20 6 597 #define FOC2A 7 598 599 /* Reserved [0xB1] */ 600 601 #define TCNT2 _SFR_MEM8(0xB2) 602 603 #define OCR2A _SFR_MEM8(0xB3) 604 605 /* Reserved [0xB4..0xB5] */ 606 607 #define ASSR _SFR_MEM8(0xB6) 608 #define TCR2UB 0 609 #define OCR2UB 1 610 #define TCN2UB 2 611 #define AS2 3 612 #define EXCLK 4 613 614 /* Reserved [0xB7] */ 615 616 #define USICR _SFR_MEM8(0xB8) 617 #define USITC 0 618 #define USICLK 1 619 #define USICS0 2 620 #define USICS1 3 621 #define USIWM0 4 622 #define USIWM1 5 623 #define USIOIE 6 624 #define USISIE 7 625 626 #define USISR _SFR_MEM8(0xB9) 627 #define USICNT0 0 628 #define USICNT1 1 629 #define USICNT2 2 630 #define USICNT3 3 631 #define USIDC 4 632 #define USIPF 5 633 #define USIOIF 6 634 #define USISIF 7 635 636 #define USIDR _SFR_MEM8(0xBA) 637 638 /* Reserved [0xBB..0xBF] */ 639 640 #define UCSR0A _SFR_MEM8(0xC0) 641 #define MPCM0 0 642 #define U2X0 1 643 #define UPE0 2 644 #define DOR0 3 645 #define FE0 4 646 #define UDRE0 5 647 #define TXC0 6 648 #define RXC0 7 649 650 #define UCSR0B _SFR_MEM8(0XC1) 651 #define TXB80 0 652 #define RXB80 1 653 #define UCSZ02 2 654 #define TXEN0 3 655 #define RXEN0 4 656 #define UDRIE0 5 657 #define TXCIE0 6 658 #define RXCIE0 7 659 660 #define UCSR0C _SFR_MEM8(0xC2) 661 #define UCPOL0 0 662 #define UCSZ00 1 663 #define UCSZ01 2 664 #define USBS0 3 665 #define UPM00 4 666 #define UPM01 5 667 #define UMSEL0 6 668 669 /* Reserved [0xC3] */ 670 671 /* Combine UBRR0L and UBRR0H */ 672 #define UBRR0 _SFR_MEM16(0xC4) 673 674 #define UBRR0L _SFR_MEM8(0xC4) 675 #define UBRR0H _SFR_MEM8(0xC5) 676 677 #define UDR0 _SFR_MEM8(0XC6) 678 679 /* Reserved [0xC7..0xFF] */ 680 681 682 /* Interrupt vectors */ 683 /* Vector 0 is the reset vector */ 684 685 /* External Interrupt Request 0 */ 686 #define INT0_vect_num 1 687 #define INT0_vect _VECTOR(1) 688 #define SIG_INTERRUPT0 _VECTOR(1) 689 690 /* Pin Change Interrupt Request 0 */ 691 #define PCINT0_vect_num 2 692 #define PCINT0_vect _VECTOR(2) 693 #define SIG_PIN_CHANGE0 _VECTOR(2) 694 695 /* Pin Change Interrupt Request 1 */ 696 #define PCINT1_vect_num 3 697 #define PCINT1_vect _VECTOR(3) 698 #define SIG_PIN_CHANGE1 _VECTOR(3) 699 700 /* Timer/Counter2 Compare Match */ 701 #define TIMER2_COMP_vect_num 4 702 #define TIMER2_COMP_vect _VECTOR(4) 703 #define SIG_OUTPUT_COMPARE2 _VECTOR(4) 704 705 /* Timer/Counter2 Overflow */ 706 #define TIMER2_OVF_vect_num 5 707 #define TIMER2_OVF_vect _VECTOR(5) 708 #define SIG_OVERFLOW2 _VECTOR(5) 709 710 /* Timer/Counter1 Capture Event */ 711 #define TIMER1_CAPT_vect_num 6 712 #define TIMER1_CAPT_vect _VECTOR(6) 713 #define SIG_INPUT_CAPTURE1 _VECTOR(6) 714 715 /* Timer/Counter1 Compare Match A */ 716 #define TIMER1_COMPA_vect_num 7 717 #define TIMER1_COMPA_vect _VECTOR(7) 718 #define SIG_OUTPUT_COMPARE1A _VECTOR(7) 719 720 /* Timer/Counter Compare Match B */ 721 #define TIMER1_COMPB_vect_num 8 722 #define TIMER1_COMPB_vect _VECTOR(8) 723 #define SIG_OUTPUT_COMPARE1B _VECTOR(8) 724 725 /* Timer/Counter1 Overflow */ 726 #define TIMER1_OVF_vect_num 9 727 #define TIMER1_OVF_vect _VECTOR(9) 728 #define SIG_OVERFLOW1 _VECTOR(9) 729 730 /* Timer/Counter0 Compare Match */ 731 #define TIMER0_COMP_vect_num 10 732 #define TIMER0_COMP_vect _VECTOR(10) 733 #define SIG_OUTPUT_COMPARE0 _VECTOR(10) 734 735 /* Timer/Counter0 Overflow */ 736 #define TIMER0_OVF_vect_num 11 737 #define TIMER0_OVF_vect _VECTOR(11) 738 #define SIG_OVERFLOW0 _VECTOR(11) 739 740 /* SPI Serial Transfer Complete */ 741 #define SPI_STC_vect_num 12 742 #define SPI_STC_vect _VECTOR(12) 743 #define SIG_SPI _VECTOR(12) 744 745 /* USART0, Rx Complete */ 746 #define USART0_RX_vect_num 13 747 #define USART0_RX_vect _VECTOR(13) 748 #define SIG_UART_RECV _VECTOR(13) 749 750 /* USART0 Data register Empty */ 751 #define USART0_UDRE_vect_num 14 752 #define USART0_UDRE_vect _VECTOR(14) 753 #define SIG_UART_DATA _VECTOR(14) 754 755 /* USART0, Tx Complete */ 756 #define USART0_TX_vect_num 15 757 #define USART0_TX_vect _VECTOR(15) 758 #define SIG_UART_TRANS _VECTOR(15) 759 760 /* USI Start Condition */ 761 #define USI_START_vect_num 16 762 #define USI_START_vect _VECTOR(16) 763 #define SIG_USI_START _VECTOR(16) 764 765 /* USI Overflow */ 766 #define USI_OVERFLOW_vect_num 17 767 #define USI_OVERFLOW_vect _VECTOR(17) 768 #define SIG_USI_OVERFLOW _VECTOR(17) 769 770 /* Analog Comparator */ 771 #define ANALOG_COMP_vect_num 18 772 #define ANALOG_COMP_vect _VECTOR(18) 773 #define SIG_COMPARATOR _VECTOR(18) 774 775 /* ADC Conversion Complete */ 776 #define ADC_vect_num 19 777 #define ADC_vect _VECTOR(19) 778 #define SIG_ADC _VECTOR(19) 779 780 /* EEPROM Ready */ 781 #define EE_READY_vect_num 20 782 #define EE_READY_vect _VECTOR(20) 783 #define SIG_EEPROM_READY _VECTOR(20) 784 785 /* Store Program Memory Read */ 786 #define SPM_READY_vect_num 21 787 #define SPM_READY_vect _VECTOR(21) 788 #define SIG_SPM_READY _VECTOR(21) 789 790 /* Vector 22 is Reserved */ 791 792 #define _VECTORS_SIZE 92 793 794 795 /* Constants */ 796 #define SPM_PAGESIZE 128 797 #define RAMSTART (0x100) 798 #define RAMEND 0x8FF 799 #define XRAMEND RAMEND 800 #define E2END 0x3FF 801 #define E2PAGESIZE 4 802 #define FLASHEND 0x7FFF 803 804 805 /* Fuses */ 806 807 #define FUSE_MEMORY_SIZE 3 808 809 /* Low Fuse Byte */ 810 #define FUSE_CKSEL0 (unsigned char)~_BV(0) 811 #define FUSE_CKSEL1 (unsigned char)~_BV(1) 812 #define FUSE_CKSEL2 (unsigned char)~_BV(2) 813 #define FUSE_CKSEL3 (unsigned char)~_BV(3) 814 #define FUSE_SUT0 (unsigned char)~_BV(4) 815 #define FUSE_SUT1 (unsigned char)~_BV(5) 816 #define FUSE_CKOUT (unsigned char)~_BV(6) 817 #define FUSE_CKDIV8 (unsigned char)~_BV(7) 818 #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) 819 820 /* High Fuse Byte */ 821 #define FUSE_BOOTRST (unsigned char)~_BV(0) 822 #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) 823 #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) 824 #define FUSE_EESAVE (unsigned char)~_BV(3) 825 #define FUSE_WDTON (unsigned char)~_BV(4) 826 #define FUSE_SPIEN (unsigned char)~_BV(5) 827 #define FUSE_JTAGEN (unsigned char)~_BV(6) 828 #define FUSE_OCDEN (unsigned char)~_BV(7) 829 #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) 830 831 /* Extended Fuse Byte */ 832 #define FUSE_RSTDISBL (unsigned char)~_BV(0) 833 #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) 834 #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) 835 #define EFUSE_DEFAULT (0xFF) 836 837 838 /* Lock Bits */ 839 #define __LOCK_BITS_EXIST 840 #define __BOOT_LOCK_BITS_0_EXIST 841 #define __BOOT_LOCK_BITS_1_EXIST 842 843 844 /* Signature */ 845 #define SIGNATURE_0 0x1E 846 #define SIGNATURE_1 0x95 847 #define SIGNATURE_2 0x05 848 849 850 /* Deprecated items */ 851 #if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) 852 853 #pragma GCC system_header 854 855 #pragma GCC poison SIG_INTERRUPT0 856 #pragma GCC poison SIG_PIN_CHANGE0 857 #pragma GCC poison SIG_PIN_CHANGE1 858 #pragma GCC poison SIG_OUTPUT_COMPARE2 859 #pragma GCC poison SIG_OVERFLOW2 860 #pragma GCC poison SIG_INPUT_CAPTURE1 861 #pragma GCC poison SIG_OUTPUT_COMPARE1A 862 #pragma GCC poison SIG_OUTPUT_COMPARE1B 863 #pragma GCC poison SIG_OVERFLOW1 864 #pragma GCC poison SIG_OUTPUT_COMPARE0 865 #pragma GCC poison SIG_OVERFLOW0 866 #pragma GCC poison SIG_SPI 867 #pragma GCC poison SIG_UART_RECV 868 #pragma GCC poison SIG_UART_DATA 869 #pragma GCC poison SIG_UART_TRANS 870 #pragma GCC poison SIG_USI_START 871 #pragma GCC poison SIG_USI_OVERFLOW 872 #pragma GCC poison SIG_COMPARATOR 873 #pragma GCC poison SIG_ADC 874 #pragma GCC poison SIG_EEPROM_READY 875 #pragma GCC poison SIG_SPM_READY 876 877 #endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ 878 879 880 881 #define SLEEP_MODE_IDLE (0x00<<1) 882 #define SLEEP_MODE_ADC (0x01<<1) 883 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 884 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 885 #define SLEEP_MODE_STANDBY (0x06<<1) 886 887 888 #endif /* _AVR_IOM325_H_ */ 889