1 /* Copyright (c) 2009 Atmel Corporation 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: iotn4313.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 32 33 /* avr/iotn4313.h - definitions for ATtiny4313 */ 34 35 /* This file should only be included from <avr/io.h>, never directly. */ 36 37 #ifndef _AVR_IO_H_ 38 # error "Include <avr/io.h> instead of this file." 39 #endif 40 41 #ifndef _AVR_IOXXX_H_ 42 # define _AVR_IOXXX_H_ "iotn4313.h" 43 #else 44 # error "Attempt to include more than one <avr/ioXXX.h> file." 45 #endif 46 47 48 #ifndef _AVR_ATtiny4313_H_ 49 #define _AVR_ATtiny4313_H_ 1 50 51 52 /* Registers and associated bit numbers. */ 53 54 #define USIBR _SFR_IO8(0x000) 55 #define USIBR0 0 56 #define USIBR1 1 57 #define USIBR2 2 58 #define USIBR3 3 59 #define USIBR4 4 60 #define USIBR5 5 61 #define USIBR6 6 62 #define USIBR7 7 63 64 #define DIDR _SFR_IO8(0x001) 65 #define AIN0D 0 66 #define AIN1D 1 67 68 #define UBRRH _SFR_IO8(0x002) 69 #define UBRR8 0 70 #define UBRR9 1 71 #define UBRR10 2 72 #define UBRR11 3 73 74 #define UCSRC _SFR_IO8(0x003) 75 #define UCPOL 0 76 #define UCSZ0 1 77 #define UCSZ1 2 78 #define USBS 3 79 #define UPM0 4 80 #define UPM1 5 81 #define UMSEL0 6 82 #define UMSEL1 7 83 84 /* When in MSPIM mode */ 85 #define UCPHA 1 86 #define UDORD 2 87 88 #define PCMSK1 _SFR_IO8(0x004) 89 #define PCINT8 0 90 #define PCINT9 1 91 #define PCINT10 2 92 93 #define PCMSK2 _SFR_IO8(0x005) 94 #define PCINT11 0 95 #define PCINT12 1 96 #define PCINT13 2 97 #define PCINT14 3 98 #define PCINT15 4 99 #define PCINT16 5 100 #define PCINT17 6 101 102 #define PRR _SFR_IO8(0x006) 103 #define PRUSART 0 104 #define PRUSI 1 105 #define PRTIM0 2 106 #define PRTIM1 3 107 108 #define __AVR_HAVE_PRR ((1<<PRUSART)|(1<<PRUSI)|(1<<PRTIM0)|(1<<PRTIM1)) 109 #define __AVR_HAVE_PRR_PRUSART 110 #define __AVR_HAVE_PRR_PRUSI 111 #define __AVR_HAVE_PRR_PRTIM0 112 #define __AVR_HAVE_PRR_PRTIM1 113 114 #define BODCR _SFR_IO8(0x007) 115 #define BPDSE 0 116 #define BPDS 1 117 118 #define ACSR _SFR_IO8(0x008) 119 #define ACIS0 0 120 #define ACIS1 1 121 #define ACIC 2 122 #define ACIE 3 123 #define ACI 4 124 #define ACO 5 125 #define ACBG 6 126 #define ACD 7 127 128 #define UBRRL _SFR_IO8(0x009) 129 #define UBRR0 0 130 #define UBRR1 1 131 #define UBRR2 2 132 #define UBRR3 3 133 #define UBRR4 4 134 #define UBRR5 5 135 #define UBRR6 6 136 #define UBRR7 7 137 138 #define UCSRB _SFR_IO8(0x00A) 139 #define TXB8 0 140 #define RXB8 1 141 #define UCSZ2 2 142 #define TXEN 3 143 #define RXEN 4 144 #define UDRIE 5 145 #define TXCIE 6 146 #define RXCIE 7 147 148 #define UCSRA _SFR_IO8(0x00B) 149 #define MPCM 0 150 #define U2X 1 151 #define UPE 2 152 #define DOR 3 153 #define FE 4 154 #define UDRE 5 155 #define TXC 6 156 #define RXC 7 157 158 #define UDR _SFR_IO8(0x00C) 159 #define UDR0 0 160 #define UDR1 1 161 #define UDR2 2 162 #define UDR3 3 163 #define UDR4 4 164 #define UDR5 5 165 #define UDR6 6 166 #define UDR7 7 167 168 #define USICR _SFR_IO8(0x00D) 169 #define USITC 0 170 #define USICLK 1 171 #define USICS0 2 172 #define USICS1 3 173 #define USIWM0 4 174 #define USIWM1 5 175 #define USIOIE 6 176 #define USISIE 7 177 178 #define USISR _SFR_IO8(0x00E) 179 #define USICNT0 0 180 #define USICNT1 1 181 #define USICNT2 2 182 #define USICNT3 3 183 #define USIDC 4 184 #define USIPF 5 185 #define USIOIF 6 186 #define USISIF 7 187 188 #define USIDR _SFR_IO8(0x00F) 189 #define USIDR0 0 190 #define USIDR1 1 191 #define USIDR2 2 192 #define USIDR3 3 193 #define USIDR4 4 194 #define USIDR5 5 195 #define USIDR6 6 196 #define USIDR7 7 197 198 #define PIND _SFR_IO8(0x010) 199 #define PIND0 0 200 #define PIND1 1 201 #define PIND2 2 202 #define PIND3 3 203 #define PIND4 4 204 #define PIND5 5 205 #define PIND6 6 206 207 #define DDRD _SFR_IO8(0x011) 208 #define DDD0 0 209 #define DDD1 1 210 #define DDD2 2 211 #define DDD3 3 212 #define DDD4 4 213 #define DDD5 5 214 #define DDD6 6 215 216 #define PORTD _SFR_IO8(0x012) 217 #define PORTD0 0 218 #define PORTD1 1 219 #define PORTD2 2 220 #define PORTD3 3 221 #define PORTD4 4 222 #define PORTD5 5 223 #define PORTD6 6 224 225 #define GPIOR0 _SFR_IO8(0x013) 226 #define GPIOR00 0 227 #define GPIOR01 1 228 #define GPIOR02 2 229 #define GPIOR03 3 230 #define GPIOR04 4 231 #define GPIOR05 5 232 #define GPIOR06 6 233 #define GPIOR07 7 234 235 #define GPIOR1 _SFR_IO8(0x014) 236 #define GPIOR10 0 237 #define GPIOR11 1 238 #define GPIOR12 2 239 #define GPIOR13 3 240 #define GPIOR14 4 241 #define GPIOR15 5 242 #define GPIOR16 6 243 #define GPIOR17 7 244 245 #define GPIOR2 _SFR_IO8(0x015) 246 #define GPIOR20 0 247 #define GPIOR21 1 248 #define GPIOR22 2 249 #define GPIOR23 3 250 #define GPIOR24 4 251 #define GPIOR25 5 252 #define GPIOR26 6 253 #define GPIOR27 7 254 255 #define PINB _SFR_IO8(0x016) 256 #define PINB0 0 257 #define PINB1 1 258 #define PINB2 2 259 #define PINB3 3 260 #define PINB4 4 261 #define PINB5 5 262 #define PINB6 6 263 #define PINB7 7 264 265 #define DDRB _SFR_IO8(0x017) 266 #define DDB0 0 267 #define DDB1 1 268 #define DDB2 2 269 #define DDB3 3 270 #define DDB4 4 271 #define DDB5 5 272 #define DDB6 6 273 #define DDB7 7 274 275 #define PORTB _SFR_IO8(0x018) 276 #define PORTB0 0 277 #define PORTB1 1 278 #define PORTB2 2 279 #define PORTB3 3 280 #define PORTB4 4 281 #define PORTB5 5 282 #define PORTB6 6 283 #define PORTB7 7 284 285 #define PINA _SFR_IO8(0x019) 286 #define PINA0 0 287 #define PINA1 1 288 #define PINA2 2 289 290 #define DDRA _SFR_IO8(0x01A) 291 #define DDA0 0 292 #define DDA1 1 293 #define DDA2 2 294 295 #define PORTA _SFR_IO8(0x01B) 296 #define PORTA0 0 297 #define PORTA1 1 298 #define PORTA2 2 299 300 #define EECR _SFR_IO8(0x01C) 301 #define EERE 0 302 #define EEPE 1 303 #define EEMPE 2 304 #define EERIE 3 305 #define EEPM0 4 306 #define EEPM1 5 307 308 #define EEDR _SFR_IO8(0x01D) 309 #define EEDR0 0 310 #define EEDR1 1 311 #define EEDR2 2 312 #define EEDR3 3 313 #define EEDR4 4 314 #define EEDR5 5 315 #define EEDR6 6 316 #define EEDR7 7 317 318 #define EEAR _SFR_IO8(0x01E) 319 #define EEAR0 0 320 #define EEAR1 1 321 #define EEAR2 2 322 #define EEAR3 3 323 #define EEAR4 4 324 #define EEAR5 5 325 #define EEAR6 6 326 327 #define PCMSK _SFR_IO8(0x020) 328 #define PCINT0 0 329 #define PCINT1 1 330 #define PCINT2 2 331 #define PCINT3 3 332 #define PCINT4 4 333 #define PCINT5 5 334 #define PCINT6 6 335 #define PCINT7 7 336 337 #define WDTCR _SFR_IO8(0x021) 338 #define WDP0 0 339 #define WDP1 1 340 #define WDP2 2 341 #define WDE 3 342 #define WDCE 4 343 #define WDP3 5 344 #define WDIE 6 345 #define WDIF 7 346 347 #define TCCR1C _SFR_IO8(0x022) 348 #define FOC1B 6 349 #define FOC1A 7 350 351 #define GTCCR _SFR_IO8(0x023) 352 #define PSR10 0 353 354 #define ICR1 _SFR_IO16(0x024) 355 356 #define ICR1L _SFR_IO8(0x024) 357 #define ICR1L0 0 358 #define ICR1L1 1 359 #define ICR1L2 2 360 #define ICR1L3 3 361 #define ICR1L4 4 362 #define ICR1L5 5 363 #define ICR1L6 6 364 #define ICR1L7 7 365 366 #define ICR1H _SFR_IO8(0x025) 367 #define ICR1H0 0 368 #define ICR1H1 1 369 #define ICR1H2 2 370 #define ICR1H3 3 371 #define ICR1H4 4 372 #define ICR1H5 5 373 #define ICR1H6 6 374 #define ICR1H7 7 375 376 #define CLKPR _SFR_IO8(0x026) 377 #define CLKPS0 0 378 #define CLKPS1 1 379 #define CLKPS2 2 380 #define CLKPS3 3 381 #define CLKPCE 7 382 383 #define OCR1B _SFR_IO16(0x028) 384 385 #define OCR1BL _SFR_IO8(0x028) 386 #define OCR1BL0 0 387 #define OCR1BL1 1 388 #define OCR1BL2 2 389 #define OCR1BL3 3 390 #define OCR1BL4 4 391 #define OCR1BL5 5 392 #define OCR1BL6 6 393 #define OCR1BL7 7 394 395 #define OCR1BH _SFR_IO8(0x029) 396 #define OCR1BH0 0 397 #define OCR1BH1 1 398 #define OCR1BH2 2 399 #define OCR1BH3 3 400 #define OCR1BH4 4 401 #define OCR1BH5 5 402 #define OCR1BH6 6 403 #define OCR1BH7 7 404 405 #define OCR1A _SFR_IO16(0x02A) 406 407 #define OCR1AL _SFR_IO8(0x02A) 408 #define OCR1AL0 0 409 #define OCR1AL1 1 410 #define OCR1AL2 2 411 #define OCR1AL3 3 412 #define OCR1AL4 4 413 #define OCR1AL5 5 414 #define OCR1AL6 6 415 #define OCR1AL7 7 416 417 #define OCR1AH _SFR_IO8(0x02B) 418 #define OCR1AH0 0 419 #define OCR1AH1 1 420 #define OCR1AH2 2 421 #define OCR1AH3 3 422 #define OCR1AH4 4 423 #define OCR1AH5 5 424 #define OCR1AH6 6 425 #define OCR1AH7 7 426 427 #define TCNT1 _SFR_IO16(0x02C) 428 429 #define TCNT1L _SFR_IO8(0x02C) 430 #define TCNT1L0 0 431 #define TCNT1L1 1 432 #define TCNT1L2 2 433 #define TCNT1L3 3 434 #define TCNT1L4 4 435 #define TCNT1L5 5 436 #define TCNT1L6 6 437 #define TCNT1L7 7 438 439 #define TCNT1H _SFR_IO8(0x02D) 440 #define TCNT1H0 0 441 #define TCNT1H1 1 442 #define TCNT1H2 2 443 #define TCNT1H3 3 444 #define TCNT1H4 4 445 #define TCNT1H5 5 446 #define TCNT1H6 6 447 #define TCNT1H7 7 448 449 #define TCCR1B _SFR_IO8(0x02E) 450 #define CS10 0 451 #define CS11 1 452 #define CS12 2 453 #define WGM12 3 454 #define WGM13 4 455 #define ICES1 6 456 #define ICNC1 7 457 458 #define TCCR1A _SFR_IO8(0x02F) 459 #define WGM10 0 460 #define WGM11 1 461 #define COM1B0 4 462 #define COM1B1 5 463 #define COM1A0 6 464 #define COM1A1 7 465 466 #define TCCR0A _SFR_IO8(0x030) 467 #define WGM00 0 468 #define WGM01 1 469 #define COM0B0 4 470 #define COM0B1 5 471 #define COM0A0 6 472 #define COM0A1 7 473 474 #define OSCCAL _SFR_IO8(0x031) 475 #define CAL0 0 476 #define CAL1 1 477 #define CAL2 2 478 #define CAL3 3 479 #define CAL4 4 480 #define CAL5 5 481 #define CAL6 6 482 483 #define TCNT0 _SFR_IO8(0x032) 484 #define TCNT0_0 0 485 #define TCNT0_1 1 486 #define TCNT0_2 2 487 #define TCNT0_3 3 488 #define TCNT0_4 4 489 #define TCNT0_5 5 490 #define TCNT0_6 6 491 #define TCNT0_7 7 492 493 #define TCCR0B _SFR_IO8(0x033) 494 #define CS00 0 495 #define CS01 1 496 #define CS02 2 497 #define WGM02 3 498 #define FOC0B 6 499 #define FOC0A 7 500 501 #define MCUSR _SFR_IO8(0x034) 502 #define PORF 0 503 #define EXTRF 1 504 #define BORF 2 505 #define WDRF 3 506 507 #define MCUCR _SFR_IO8(0x035) 508 #define ISC00 0 509 #define ISC01 1 510 #define ISC10 2 511 #define ISC11 3 512 #define SM0 4 513 #define SE 5 514 #define SM1 6 515 #define PUD 7 516 517 #define OCR0A _SFR_IO8(0x036) 518 #define OCR0A_0 0 519 #define OCR0A_1 1 520 #define OCR0A_2 2 521 #define OCR0A_3 3 522 #define OCR0A_4 4 523 #define OCR0A_5 5 524 #define OCR0A_6 6 525 #define OCR0A_7 7 526 527 #define SPMCSR _SFR_IO8(0x037) 528 #define SPMEN 0 529 #define PGERS 1 530 #define PGWRT 2 531 #define RFLB 3 532 #define CTPB 4 533 #define RSIG 5 534 535 #define TIFR _SFR_IO8(0x038) 536 #define OCF0A 0 537 #define TOV0 1 538 #define OCF0B 2 539 #define ICF1 3 540 #define OCF1B 5 541 #define OCF1A 6 542 #define TOV1 7 543 544 #define TIMSK _SFR_IO8(0x039) 545 #define OCIE0A 0 546 #define TOIE0 1 547 #define OCIE0B 2 548 #define ICIE1 3 549 #define OCIE1B 5 550 #define OCIE1A 6 551 #define TOIE1 7 552 553 #define EIFR _SFR_IO8(0x03A) 554 #define GIFR _SFR_IO8(0x03A) 555 #define PCIF1 3 556 #define PCIF2 4 557 #define PCIF0 5 558 #define INTF0 6 559 #define INTF1 7 560 561 #define GIMSK _SFR_IO8(0x03B) 562 #define PCIE1 3 563 #define PCIE2 4 564 #define PCIE0 5 565 #define INT0 6 566 #define INT1 7 567 568 #define OCR0B _SFR_IO8(0x03C) 569 #define OCR0_0 0 570 #define OCR0_1 1 571 #define OCR0_2 2 572 #define OCR0_3 3 573 #define OCR0_4 4 574 #define OCR0_5 5 575 #define OCR0_6 6 576 #define OCR0_7 7 577 578 579 /* Interrupt vectors */ 580 /* Vector 0 is the reset vector */ 581 #define INT0_vect_num 1 582 #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ 583 #define INT1_vect_num 2 584 #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ 585 #define TIMER1_CAPT_vect_num 3 586 #define TIMER1_CAPT_vect _VECTOR(3) /* Timer/Counter1 Capture Event */ 587 #define TIMER1_COMPA_vect_num 4 588 #define TIMER1_COMPA_vect _VECTOR(4) /* Timer/Counter1 Compare Match A */ 589 #define TIMER1_OVF_vect_num 5 590 #define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ 591 #define TIMER0_OVF_vect_num 6 592 #define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ 593 #define USART0_RX_vect_num 7 594 #define USART0_RX_vect _VECTOR(7) /* USART, Rx Complete */ 595 #define USART_RX_vect_num 7 596 #define USART_RX_vect _VECTOR(7) /* alias */ 597 #define USART0_UDRE_vect_num 8 598 #define USART0_UDRE_vect _VECTOR(8) /* USART Data Register Empty */ 599 #define USART_UDRE_vect_num 8 600 #define USART_UDRE_vect _VECTOR(8) /* alias */ 601 #define USART0_TX_vect_num 9 602 #define USART0_TX_vect _VECTOR(9) /* USART, Tx Complete */ 603 #define USART_TX_vect_num 9 604 #define USART_TX_vect _VECTOR(9) /* alias */ 605 #define ANA_COMP_vect_num 10 606 #define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ 607 #define PCINT0_vect_num 11 608 #define PCINT0_vect _VECTOR(11) /* Pin Change Interrupt Request 0 */ 609 #define PCINT_B_vect_num 11 610 #define PCINT_B_vect _VECTOR(11) /* alias */ 611 #define TIMER1_COMPB_vect_num 12 612 #define TIMER1_COMPB_vect _VECTOR(12) /* */ 613 #define TIMER0_COMPA_vect_num 13 614 #define TIMER0_COMPA_vect _VECTOR(13) /* */ 615 #define TIMER0_COMPB_vect_num 14 616 #define TIMER0_COMPB_vect _VECTOR(14) /* */ 617 #define USI_START_vect_num 15 618 #define USI_START_vect _VECTOR(15) /* USI Start Condition */ 619 #define USI_OVERFLOW_vect_num 16 620 #define USI_OVERFLOW_vect _VECTOR(16) /* USI Overflow */ 621 #define EEPROM_Ready_vect_num 17 622 #define EEPROM_Ready_vect _VECTOR(17) /* EEPROM Ready */ 623 #define WDT_OVERFLOW_vect_num 18 624 #define WDT_OVERFLOW_vect _VECTOR(18) /* Watchdog Timer Overflow */ 625 #define PCINT1_vect_num 19 626 #define PCINT1_vect _VECTOR(19) /* Pin Change Interrupt Request 1 */ 627 #define PCINT_A_vect_num 19 628 #define PCINT_A_vect _VECTOR(19) /* alias */ 629 #define PCINT2_vect_num 20 630 #define PCINT2_vect _VECTOR(20) /* Pin Change Interrupt Request 2 */ 631 #define PCINT_D_vect_num 20 632 #define PCINT_D_vect _VECTOR(20) /* alias */ 633 634 #define _VECTOR_SIZE 2 /* Size of individual vector. */ 635 #define _VECTORS_SIZE (21 * _VECTOR_SIZE) 636 637 638 /* Constants */ 639 #define SPM_PAGESIZE (64) 640 #define RAMSTART (0x60) 641 #define RAMSIZE (256) 642 #define RAMEND (RAMSTART + RAMSIZE - 1) 643 #define XRAMSTART (NA) 644 #define XRAMSIZE (0) 645 #define XRAMEND (RAMEND) 646 #define E2END (0xFF) 647 #define E2PAGESIZE (4) 648 #define FLASHEND (0xFFF) 649 650 651 /* Fuses */ 652 #define FUSE_MEMORY_SIZE 3 653 654 /* Low Fuse Byte */ 655 #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ 656 #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ 657 #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ 658 #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ 659 #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ 660 #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ 661 #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ 662 #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ 663 #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) 664 665 /* High Fuse Byte */ 666 #define FUSE_RSTDISBL (unsigned char)~_BV(0) /* External reset disable */ 667 #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ 668 #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ 669 #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) /* Brown-out Detector trigger level */ 670 #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ 671 #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ 672 #define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ 673 #define FUSE_DWEN (unsigned char)~_BV(7) /* debugWIRE Enable */ 674 #define HFUSE_DEFAULT (FUSE_SPIEN) 675 676 /* Extended Fuse Byte */ 677 #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ 678 #define EFUSE_DEFAULT (0xFF) 679 680 681 /* Lock Bits */ 682 #define __LOCK_BITS_EXIST 683 684 685 /* Signature */ 686 #define SIGNATURE_0 0x1E 687 #define SIGNATURE_1 0x92 688 #define SIGNATURE_2 0x0D 689 690 691 /* Device Pin Definitions */ 692 #define RXD_DDR DDRD 693 #define RXD_PORT PORTD 694 #define RXD_PIN PIND 695 #define RXD_BIT 0 696 697 #define TXD_DDR DDRD 698 #define TXD_PORT PORTD 699 #define TXD_PIN PIND 700 #define TXD_BIT 1 701 702 #define PA1_DDR DDRXTAL 703 #define PA1_PORT PORTXTAL 704 #define PA1_PIN PINXTAL 705 #define PA1_BIT XTAL2 706 707 #define PA0_DDR DDRXTAL 708 #define PA0_PORT PORTXTAL 709 #define PA0_PIN PINXTAL 710 #define PA0_BIT XTAL1 711 712 #define INT0_DDR DDRD 713 #define INT0_PORT PORTD 714 #define INT0_PIN PIND 715 #define INT0_BIT 2 716 717 #define XCK_DDR DDRD 718 #define XCK_PORT PORTD 719 #define XCK_PIN PIND 720 #define XCK_BIT 2 721 722 #define CKOUT_DDR DDRD 723 #define CKOUT_PORT PORTD 724 #define CKOUT_PIN PIND 725 #define CKOUT_BIT 2 726 727 #define INT1_DDR DDRD 728 #define INT1_PORT PORTD 729 #define INT1_PIN PIND 730 #define INT1_BIT 3 731 732 #define T0_DDR DDRD 733 #define T0_PORT PORTD 734 #define T0_PIN PIND 735 #define T0_BIT 4 736 737 #define T1_DDR DDRD 738 #define T1_PORT PORTD 739 #define T1_PIN PIND 740 #define T1_BIT 5 741 742 #define OC0B_DDR DDRD 743 #define OC0B_PORT PORTD 744 #define OC0B_PIN PIND 745 #define OC0B_BIT 5 746 747 #define ICP_DDR DDRD 748 #define ICP_PORT PORTD 749 #define ICP_PIN PIND 750 #define ICP_BIT 6 751 752 #define AIN0_DDR DDRB 753 #define AIN0_PORT PORTB 754 #define AIN0_PIN PINB 755 #define AIN0_BIT 0 756 757 #define AIN1_DDR DDRB 758 #define AIN1_PORT PORTB 759 #define AIN1_PIN PINB 760 #define AIN1_BIT 1 761 762 #define OC0A_DDR DDRB 763 #define OC0A_PORT PORTB 764 #define OC0A_PIN PINB 765 #define OC0A_BIT 2 766 767 #define OC1A_DDR DDRB 768 #define OC1A_PORT PORTB 769 #define OC1A_PIN PINB 770 #define OC1A_BIT 3 771 772 #define OC1B_DDR DDRB 773 #define OC1B_PORT PORTB 774 #define OC1B_PIN PINB 775 #define OC1B_BIT 4 776 777 #define MOSI_DDR DDRB 778 #define MOSI_PORT PORTB 779 #define MOSI_PIN PINB 780 #define MOSI_BIT 5 781 782 #define DI_DDR DDRB 783 #define DI_PORT PORTB 784 #define DI_PIN PINB 785 #define DI_BIT 5 786 787 #define MISO_DDR DDRB 788 #define MISO_PORT PORTB 789 #define MISO_PIN PINB 790 #define MISO_BIT 6 791 792 #define DO_DDR DDRB 793 #define DO_PORT PORTB 794 #define DO_PIN PINB 795 #define DO_BIT 6 796 797 #define SCK_DDR DDRB 798 #define SCK_PORT PORTB 799 #define SCK_PIN PINB 800 #define SCK_BIT 7 801 802 #define SCL_DDR DDRB 803 #define SCL_PORT PORTB 804 #define SCL_PIN PINB 805 #define SCL_BIT 7 806 807 808 #define SLEEP_MODE_IDLE (0x00<<4) 809 #define SLEEP_MODE_STANDBY (0x04<<4) 810 #define SLEEP_MODE_PWR_DOWN (0x05<<4) 811 812 #endif /* _AVR_ATtiny4313_H_ */ 813 814