1 /***************************************************************************** 2 * 3 * Copyright (C) 2014 Atmel Corporation 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * * Neither the name of the copyright holders nor the names of 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 ****************************************************************************/ 33 34 35 /* $Id: iox128c3.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 36 37 #ifndef _AVR_IO_H_ 38 # error "Include <avr/io.h> instead of this file." 39 #endif 40 41 #ifndef _AVR_IOXXX_H_ 42 # define _AVR_IOXXX_H_ "iox128c3.h" 43 #else 44 # error "Attempt to include more than one <avr/ioXXX.h> file." 45 #endif 46 47 #ifndef _AVR_ATXMEGA128C3_H_INCLUDED 48 #define _AVR_ATXMEGA128C3_H_INCLUDED 49 50 /* Ungrouped common registers */ 51 #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ 52 #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ 53 #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ 54 #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ 55 56 /* Deprecated */ 57 #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ 58 #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ 59 #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ 60 #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ 61 62 #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ 63 #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ 64 #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ 65 #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ 66 #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ 67 #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ 68 #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ 69 #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ 70 #define SREG _SFR_MEM8(0x003F) /* Status Register */ 71 72 /* C Language Only */ 73 #if !defined (__ASSEMBLER__) 74 75 #include <stdint.h> 76 77 typedef volatile uint8_t register8_t; 78 typedef volatile uint16_t register16_t; 79 typedef volatile uint32_t register32_t; 80 81 82 #ifdef _WORDREGISTER 83 #undef _WORDREGISTER 84 #endif 85 #define _WORDREGISTER(regname) \ 86 __extension__ union \ 87 { \ 88 register16_t regname; \ 89 struct \ 90 { \ 91 register8_t regname ## L; \ 92 register8_t regname ## H; \ 93 }; \ 94 } 95 96 #ifdef _DWORDREGISTER 97 #undef _DWORDREGISTER 98 #endif 99 #define _DWORDREGISTER(regname) \ 100 __extension__ union \ 101 { \ 102 register32_t regname; \ 103 struct \ 104 { \ 105 register8_t regname ## 0; \ 106 register8_t regname ## 1; \ 107 register8_t regname ## 2; \ 108 register8_t regname ## 3; \ 109 }; \ 110 } 111 112 113 /* 114 ========================================================================== 115 IO Module Structures 116 ========================================================================== 117 */ 118 119 120 /* 121 -------------------------------------------------------------------------- 122 VPORT - Virtual Ports 123 -------------------------------------------------------------------------- 124 */ 125 126 /* Virtual Port */ 127 typedef struct VPORT_struct 128 { 129 register8_t DIR; /* I/O Port Data Direction */ 130 register8_t OUT; /* I/O Port Output */ 131 register8_t IN; /* I/O Port Input */ 132 register8_t INTFLAGS; /* Interrupt Flag Register */ 133 } VPORT_t; 134 135 136 /* 137 -------------------------------------------------------------------------- 138 XOCD - On-Chip Debug System 139 -------------------------------------------------------------------------- 140 */ 141 142 /* On-Chip Debug System */ 143 typedef struct OCD_struct 144 { 145 register8_t OCDR0; /* OCD Register 0 */ 146 register8_t OCDR1; /* OCD Register 1 */ 147 } OCD_t; 148 149 150 /* 151 -------------------------------------------------------------------------- 152 CPU - CPU 153 -------------------------------------------------------------------------- 154 */ 155 156 /* CCP signatures */ 157 typedef enum CCP_enum 158 { 159 CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ 160 CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ 161 } CCP_t; 162 163 164 /* 165 -------------------------------------------------------------------------- 166 CLK - Clock System 167 -------------------------------------------------------------------------- 168 */ 169 170 /* Clock System */ 171 typedef struct CLK_struct 172 { 173 register8_t CTRL; /* Control Register */ 174 register8_t PSCTRL; /* Prescaler Control Register */ 175 register8_t LOCK; /* Lock register */ 176 register8_t RTCCTRL; /* RTC Control Register */ 177 register8_t USBCTRL; /* USB Control Register */ 178 } CLK_t; 179 180 181 /* Power Reduction */ 182 typedef struct PR_struct 183 { 184 register8_t PRGEN; /* General Power Reduction */ 185 register8_t PRPA; /* Power Reduction Port A */ 186 register8_t reserved_0x02; 187 register8_t PRPC; /* Power Reduction Port C */ 188 register8_t PRPD; /* Power Reduction Port D */ 189 register8_t PRPE; /* Power Reduction Port E */ 190 register8_t PRPF; /* Power Reduction Port F */ 191 } PR_t; 192 193 /* System Clock Selection */ 194 typedef enum CLK_SCLKSEL_enum 195 { 196 CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ 197 CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ 198 CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ 199 CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ 200 CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ 201 } CLK_SCLKSEL_t; 202 203 /* Prescaler A Division Factor */ 204 typedef enum CLK_PSADIV_enum 205 { 206 CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ 207 CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ 208 CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ 209 CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ 210 CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ 211 CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ 212 CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ 213 CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ 214 CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ 215 CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ 216 } CLK_PSADIV_t; 217 218 /* Prescaler B and C Division Factor */ 219 typedef enum CLK_PSBCDIV_enum 220 { 221 CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ 222 CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ 223 CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ 224 CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ 225 } CLK_PSBCDIV_t; 226 227 /* RTC Clock Source */ 228 typedef enum CLK_RTCSRC_enum 229 { 230 CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ 231 CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ 232 CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ 233 CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ 234 CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ 235 CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ 236 } CLK_RTCSRC_t; 237 238 /* USB Prescaler Division Factor */ 239 typedef enum CLK_USBPSDIV_enum 240 { 241 CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ 242 CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ 243 CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ 244 CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ 245 CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ 246 CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ 247 } CLK_USBPSDIV_t; 248 249 /* USB Clock Source */ 250 typedef enum CLK_USBSRC_enum 251 { 252 CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ 253 CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ 254 } CLK_USBSRC_t; 255 256 257 /* 258 -------------------------------------------------------------------------- 259 SLEEP - Sleep Controller 260 -------------------------------------------------------------------------- 261 */ 262 263 /* Sleep Controller */ 264 typedef struct SLEEP_struct 265 { 266 register8_t CTRL; /* Control Register */ 267 } SLEEP_t; 268 269 /* Sleep Mode */ 270 typedef enum SLEEP_SMODE_enum 271 { 272 SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ 273 SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ 274 SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ 275 SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ 276 SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ 277 } SLEEP_SMODE_t; 278 279 280 #define SLEEP_MODE_IDLE (0x00<<1) 281 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 282 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 283 #define SLEEP_MODE_STANDBY (0x06<<1) 284 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 285 286 287 /* 288 -------------------------------------------------------------------------- 289 OSC - Oscillator 290 -------------------------------------------------------------------------- 291 */ 292 293 /* Oscillator */ 294 typedef struct OSC_struct 295 { 296 register8_t CTRL; /* Control Register */ 297 register8_t STATUS; /* Status Register */ 298 register8_t XOSCCTRL; /* External Oscillator Control Register */ 299 register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ 300 register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ 301 register8_t PLLCTRL; /* PLL Control Register */ 302 register8_t DFLLCTRL; /* DFLL Control Register */ 303 } OSC_t; 304 305 /* Oscillator Frequency Range */ 306 typedef enum OSC_FRQRANGE_enum 307 { 308 OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ 309 OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ 310 OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ 311 OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ 312 } OSC_FRQRANGE_t; 313 314 /* External Oscillator Selection and Startup Time */ 315 typedef enum OSC_XOSCSEL_enum 316 { 317 OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ 318 OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ 319 OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ 320 OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ 321 OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ 322 } OSC_XOSCSEL_t; 323 324 /* PLL Clock Source */ 325 typedef enum OSC_PLLSRC_enum 326 { 327 OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ 328 OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ 329 OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ 330 } OSC_PLLSRC_t; 331 332 /* 2 MHz DFLL Calibration Reference */ 333 typedef enum OSC_RC2MCREF_enum 334 { 335 OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ 336 OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ 337 } OSC_RC2MCREF_t; 338 339 /* 32 MHz DFLL Calibration Reference */ 340 typedef enum OSC_RC32MCREF_enum 341 { 342 OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ 343 OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ 344 OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ 345 } OSC_RC32MCREF_t; 346 347 348 /* 349 -------------------------------------------------------------------------- 350 DFLL - DFLL 351 -------------------------------------------------------------------------- 352 */ 353 354 /* DFLL */ 355 typedef struct DFLL_struct 356 { 357 register8_t CTRL; /* Control Register */ 358 register8_t reserved_0x01; 359 register8_t CALA; /* Calibration Register A */ 360 register8_t CALB; /* Calibration Register B */ 361 register8_t COMP0; /* Oscillator Compare Register 0 */ 362 register8_t COMP1; /* Oscillator Compare Register 1 */ 363 register8_t COMP2; /* Oscillator Compare Register 2 */ 364 register8_t reserved_0x07; 365 } DFLL_t; 366 367 368 /* 369 -------------------------------------------------------------------------- 370 RST - Reset 371 -------------------------------------------------------------------------- 372 */ 373 374 /* Reset */ 375 typedef struct RST_struct 376 { 377 register8_t STATUS; /* Status Register */ 378 register8_t CTRL; /* Control Register */ 379 } RST_t; 380 381 382 /* 383 -------------------------------------------------------------------------- 384 WDT - Watch-Dog Timer 385 -------------------------------------------------------------------------- 386 */ 387 388 /* Watch-Dog Timer */ 389 typedef struct WDT_struct 390 { 391 register8_t CTRL; /* Control */ 392 register8_t WINCTRL; /* Windowed Mode Control */ 393 register8_t STATUS; /* Status */ 394 } WDT_t; 395 396 /* Period setting */ 397 typedef enum WDT_PER_enum 398 { 399 WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ 400 WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ 401 WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ 402 WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ 403 WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ 404 WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ 405 WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ 406 WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ 407 WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ 408 WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ 409 WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ 410 } WDT_PER_t; 411 412 /* Closed window period */ 413 typedef enum WDT_WPER_enum 414 { 415 WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ 416 WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ 417 WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ 418 WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ 419 WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ 420 WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ 421 WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ 422 WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ 423 WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ 424 WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ 425 WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ 426 } WDT_WPER_t; 427 428 429 /* 430 -------------------------------------------------------------------------- 431 MCU - MCU Control 432 -------------------------------------------------------------------------- 433 */ 434 435 /* MCU Control */ 436 typedef struct MCU_struct 437 { 438 register8_t DEVID0; /* Device ID byte 0 */ 439 register8_t DEVID1; /* Device ID byte 1 */ 440 register8_t DEVID2; /* Device ID byte 2 */ 441 register8_t REVID; /* Revision ID */ 442 register8_t reserved_0x04; 443 register8_t reserved_0x05; 444 register8_t reserved_0x06; 445 register8_t ANAINIT; /* Analog Startup Delay */ 446 register8_t EVSYSLOCK; /* Event System Lock */ 447 register8_t AWEXLOCK; /* AWEX Lock */ 448 register8_t reserved_0x0A; 449 register8_t reserved_0x0B; 450 } MCU_t; 451 452 453 /* 454 -------------------------------------------------------------------------- 455 PMIC - Programmable Multi-level Interrupt Controller 456 -------------------------------------------------------------------------- 457 */ 458 459 /* Programmable Multi-level Interrupt Controller */ 460 typedef struct PMIC_struct 461 { 462 register8_t STATUS; /* Status Register */ 463 register8_t INTPRI; /* Interrupt Priority */ 464 register8_t CTRL; /* Control Register */ 465 register8_t reserved_0x03; 466 register8_t reserved_0x04; 467 register8_t reserved_0x05; 468 register8_t reserved_0x06; 469 register8_t reserved_0x07; 470 register8_t reserved_0x08; 471 register8_t reserved_0x09; 472 register8_t reserved_0x0A; 473 register8_t reserved_0x0B; 474 register8_t reserved_0x0C; 475 register8_t reserved_0x0D; 476 register8_t reserved_0x0E; 477 register8_t reserved_0x0F; 478 } PMIC_t; 479 480 481 /* 482 -------------------------------------------------------------------------- 483 PORTCFG - Port Configuration 484 -------------------------------------------------------------------------- 485 */ 486 487 /* I/O port Configuration */ 488 typedef struct PORTCFG_struct 489 { 490 register8_t MPCMASK; /* Multi-pin Configuration Mask */ 491 register8_t reserved_0x01; 492 register8_t VPCTRLA; /* Virtual Port Control Register A */ 493 register8_t VPCTRLB; /* Virtual Port Control Register B */ 494 register8_t CLKEVOUT; /* Clock and Event Out Register */ 495 register8_t reserved_0x05; 496 register8_t EVOUTSEL; /* Event Output Select */ 497 } PORTCFG_t; 498 499 /* Virtual Port Mapping */ 500 typedef enum PORTCFG_VP02MAP_enum 501 { 502 PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ 503 PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ 504 PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ 505 PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ 506 PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ 507 PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ 508 PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ 509 PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ 510 PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ 511 PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ 512 PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ 513 PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ 514 PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ 515 PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ 516 PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ 517 PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ 518 } PORTCFG_VP02MAP_t; 519 520 /* Virtual Port Mapping */ 521 typedef enum PORTCFG_VP13MAP_enum 522 { 523 PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ 524 PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ 525 PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ 526 PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ 527 PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ 528 PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ 529 PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ 530 PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ 531 PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ 532 PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ 533 PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ 534 PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ 535 PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ 536 PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ 537 PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ 538 PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ 539 } PORTCFG_VP13MAP_t; 540 541 /* System Clock Output Port */ 542 typedef enum PORTCFG_CLKOUT_enum 543 { 544 PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ 545 PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ 546 PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ 547 PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ 548 } PORTCFG_CLKOUT_t; 549 550 /* Peripheral Clock Output Select */ 551 typedef enum PORTCFG_CLKOUTSEL_enum 552 { 553 PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ 554 PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ 555 PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ 556 } PORTCFG_CLKOUTSEL_t; 557 558 /* Event Output Port */ 559 typedef enum PORTCFG_EVOUT_enum 560 { 561 PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ 562 PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ 563 PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ 564 PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ 565 } PORTCFG_EVOUT_t; 566 567 /* Event Output Select */ 568 typedef enum PORTCFG_EVOUTSEL_enum 569 { 570 PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ 571 PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ 572 PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ 573 PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ 574 } PORTCFG_EVOUTSEL_t; 575 576 577 /* 578 -------------------------------------------------------------------------- 579 CRC - Cyclic Redundancy Checker 580 -------------------------------------------------------------------------- 581 */ 582 583 /* Cyclic Redundancy Checker */ 584 typedef struct CRC_struct 585 { 586 register8_t CTRL; /* Control Register */ 587 register8_t STATUS; /* Status Register */ 588 register8_t reserved_0x02; 589 register8_t DATAIN; /* Data Input */ 590 register8_t CHECKSUM0; /* Checksum byte 0 */ 591 register8_t CHECKSUM1; /* Checksum byte 1 */ 592 register8_t CHECKSUM2; /* Checksum byte 2 */ 593 register8_t CHECKSUM3; /* Checksum byte 3 */ 594 } CRC_t; 595 596 /* Reset */ 597 typedef enum CRC_RESET_enum 598 { 599 CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ 600 CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ 601 CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ 602 } CRC_RESET_t; 603 604 /* Input Source */ 605 typedef enum CRC_SOURCE_enum 606 { 607 CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ 608 CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ 609 CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ 610 } CRC_SOURCE_t; 611 612 613 /* 614 -------------------------------------------------------------------------- 615 EVSYS - Event System 616 -------------------------------------------------------------------------- 617 */ 618 619 /* Event System */ 620 typedef struct EVSYS_struct 621 { 622 register8_t CH0MUX; /* Event Channel 0 Multiplexer */ 623 register8_t CH1MUX; /* Event Channel 1 Multiplexer */ 624 register8_t CH2MUX; /* Event Channel 2 Multiplexer */ 625 register8_t CH3MUX; /* Event Channel 3 Multiplexer */ 626 register8_t reserved_0x04; 627 register8_t reserved_0x05; 628 register8_t reserved_0x06; 629 register8_t reserved_0x07; 630 register8_t CH0CTRL; /* Channel 0 Control Register */ 631 register8_t CH1CTRL; /* Channel 1 Control Register */ 632 register8_t CH2CTRL; /* Channel 2 Control Register */ 633 register8_t CH3CTRL; /* Channel 3 Control Register */ 634 register8_t reserved_0x0C; 635 register8_t reserved_0x0D; 636 register8_t reserved_0x0E; 637 register8_t reserved_0x0F; 638 register8_t STROBE; /* Event Strobe */ 639 register8_t DATA; /* Event Data */ 640 } EVSYS_t; 641 642 /* Quadrature Decoder Index Recognition Mode */ 643 typedef enum EVSYS_QDIRM_enum 644 { 645 EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ 646 EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ 647 EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ 648 EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ 649 } EVSYS_QDIRM_t; 650 651 /* Digital filter coefficient */ 652 typedef enum EVSYS_DIGFILT_enum 653 { 654 EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ 655 EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ 656 EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ 657 EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ 658 EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ 659 EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ 660 EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ 661 EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ 662 } EVSYS_DIGFILT_t; 663 664 /* Event Channel multiplexer input selection */ 665 typedef enum EVSYS_CHMUX_enum 666 { 667 EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ 668 EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ 669 EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ 670 EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ 671 EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ 672 EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ 673 EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ 674 EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ 675 EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ 676 EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ 677 EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ 678 EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ 679 EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ 680 EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ 681 EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ 682 EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ 683 EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ 684 EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ 685 EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ 686 EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ 687 EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ 688 EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ 689 EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ 690 EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ 691 EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ 692 EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ 693 EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ 694 EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ 695 EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ 696 EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ 697 EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ 698 EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ 699 EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ 700 EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ 701 EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ 702 EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ 703 EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ 704 EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ 705 EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ 706 EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ 707 EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ 708 EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ 709 EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ 710 EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ 711 EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ 712 EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ 713 EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ 714 EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ 715 EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ 716 EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ 717 EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ 718 EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ 719 EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ 720 EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ 721 EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ 722 EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ 723 EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ 724 EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ 725 EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ 726 EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ 727 EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ 728 EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ 729 EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ 730 EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ 731 EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ 732 EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ 733 EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ 734 EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ 735 EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ 736 EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ 737 EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ 738 EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ 739 EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ 740 EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ 741 EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ 742 EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ 743 EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ 744 EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ 745 EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ 746 EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ 747 EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ 748 EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ 749 EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ 750 EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ 751 EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ 752 EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ 753 EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ 754 EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ 755 EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ 756 EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ 757 EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ 758 EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ 759 EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ 760 EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ 761 EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ 762 EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ 763 EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ 764 EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ 765 EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ 766 EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ 767 } EVSYS_CHMUX_t; 768 769 770 /* 771 -------------------------------------------------------------------------- 772 NVM - Non Volatile Memory Controller 773 -------------------------------------------------------------------------- 774 */ 775 776 /* Non-volatile Memory Controller */ 777 typedef struct NVM_struct 778 { 779 register8_t ADDR0; /* Address Register 0 */ 780 register8_t ADDR1; /* Address Register 1 */ 781 register8_t ADDR2; /* Address Register 2 */ 782 register8_t reserved_0x03; 783 register8_t DATA0; /* Data Register 0 */ 784 register8_t DATA1; /* Data Register 1 */ 785 register8_t DATA2; /* Data Register 2 */ 786 register8_t reserved_0x07; 787 register8_t reserved_0x08; 788 register8_t reserved_0x09; 789 register8_t CMD; /* Command */ 790 register8_t CTRLA; /* Control Register A */ 791 register8_t CTRLB; /* Control Register B */ 792 register8_t INTCTRL; /* Interrupt Control */ 793 register8_t reserved_0x0E; 794 register8_t STATUS; /* Status */ 795 register8_t LOCKBITS; /* Lock Bits */ 796 } NVM_t; 797 798 /* NVM Command */ 799 typedef enum NVM_CMD_enum 800 { 801 NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ 802 NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ 803 NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ 804 NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ 805 NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ 806 NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ 807 NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ 808 NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ 809 NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ 810 NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ 811 NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ 812 NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ 813 NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ 814 NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ 815 NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ 816 NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ 817 NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ 818 NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ 819 NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ 820 NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ 821 NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ 822 NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ 823 NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ 824 NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ 825 NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ 826 NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ 827 NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ 828 NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ 829 NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ 830 NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ 831 NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ 832 NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ 833 NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ 834 NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ 835 } NVM_CMD_t; 836 837 /* SPM ready interrupt level */ 838 typedef enum NVM_SPMLVL_enum 839 { 840 NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ 841 NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ 842 NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ 843 NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ 844 } NVM_SPMLVL_t; 845 846 /* EEPROM ready interrupt level */ 847 typedef enum NVM_EELVL_enum 848 { 849 NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 850 NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ 851 NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ 852 NVM_EELVL_HI_gc = (0x03<<0), /* High level */ 853 } NVM_EELVL_t; 854 855 /* Boot lock bits - boot setcion */ 856 typedef enum NVM_BLBB_enum 857 { 858 NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ 859 NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ 860 NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ 861 NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ 862 } NVM_BLBB_t; 863 864 /* Boot lock bits - application section */ 865 typedef enum NVM_BLBA_enum 866 { 867 NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ 868 NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ 869 NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ 870 NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ 871 } NVM_BLBA_t; 872 873 /* Boot lock bits - application table section */ 874 typedef enum NVM_BLBAT_enum 875 { 876 NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ 877 NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ 878 NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ 879 NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ 880 } NVM_BLBAT_t; 881 882 /* Lock bits */ 883 typedef enum NVM_LB_enum 884 { 885 NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ 886 NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ 887 NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ 888 } NVM_LB_t; 889 890 891 /* 892 -------------------------------------------------------------------------- 893 ADC - Analog/Digital Converter 894 -------------------------------------------------------------------------- 895 */ 896 897 /* ADC Channel */ 898 typedef struct ADC_CH_struct 899 { 900 register8_t CTRL; /* Control Register */ 901 register8_t MUXCTRL; /* MUX Control */ 902 register8_t INTCTRL; /* Channel Interrupt Control Register */ 903 register8_t INTFLAGS; /* Interrupt Flags */ 904 _WORDREGISTER(RES); /* Channel Result */ 905 register8_t SCAN; /* Input Channel Scan */ 906 register8_t reserved_0x07; 907 } ADC_CH_t; 908 909 910 /* Analog-to-Digital Converter */ 911 typedef struct ADC_struct 912 { 913 register8_t CTRLA; /* Control Register A */ 914 register8_t CTRLB; /* Control Register B */ 915 register8_t REFCTRL; /* Reference Control */ 916 register8_t EVCTRL; /* Event Control */ 917 register8_t PRESCALER; /* Clock Prescaler */ 918 register8_t reserved_0x05; 919 register8_t INTFLAGS; /* Interrupt Flags */ 920 register8_t TEMP; /* Temporary Register */ 921 register8_t reserved_0x08; 922 register8_t reserved_0x09; 923 register8_t reserved_0x0A; 924 register8_t reserved_0x0B; 925 _WORDREGISTER(CAL); /* Calibration Value */ 926 register8_t reserved_0x0E; 927 register8_t reserved_0x0F; 928 _WORDREGISTER(CH0RES); /* Channel 0 Result */ 929 register8_t reserved_0x12; 930 register8_t reserved_0x13; 931 register8_t reserved_0x14; 932 register8_t reserved_0x15; 933 register8_t reserved_0x16; 934 register8_t reserved_0x17; 935 _WORDREGISTER(CMP); /* Compare Value */ 936 register8_t reserved_0x1A; 937 register8_t reserved_0x1B; 938 register8_t reserved_0x1C; 939 register8_t reserved_0x1D; 940 register8_t reserved_0x1E; 941 register8_t reserved_0x1F; 942 ADC_CH_t CH0; /* ADC Channel 0 */ 943 } ADC_t; 944 945 /* Current Limitation */ 946 typedef enum ADC_CURRLIMIT_enum 947 { 948 ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ 949 ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ 950 ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ 951 ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ 952 } ADC_CURRLIMIT_t; 953 954 /* Positive input multiplexer selection */ 955 typedef enum ADC_CH_MUXPOS_enum 956 { 957 ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ 958 ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ 959 ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ 960 ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ 961 ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ 962 ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ 963 ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ 964 ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ 965 ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ 966 ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ 967 ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ 968 ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ 969 ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ 970 ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ 971 ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ 972 ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ 973 } ADC_CH_MUXPOS_t; 974 975 /* Internal input multiplexer selections */ 976 typedef enum ADC_CH_MUXINT_enum 977 { 978 ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ 979 ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ 980 ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ 981 } ADC_CH_MUXINT_t; 982 983 /* Negative input multiplexer selection */ 984 typedef enum ADC_CH_MUXNEG_enum 985 { 986 ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ 987 ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ 988 ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ 989 ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ 990 ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ 991 ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ 992 ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ 993 ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ 994 } ADC_CH_MUXNEG_t; 995 996 /* Input mode */ 997 typedef enum ADC_CH_INPUTMODE_enum 998 { 999 ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ 1000 ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ 1001 ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ 1002 ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ 1003 } ADC_CH_INPUTMODE_t; 1004 1005 /* Gain factor */ 1006 typedef enum ADC_CH_GAIN_enum 1007 { 1008 ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ 1009 ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ 1010 ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ 1011 ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ 1012 ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ 1013 ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ 1014 ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ 1015 ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ 1016 } ADC_CH_GAIN_t; 1017 1018 /* Conversion result resolution */ 1019 typedef enum ADC_RESOLUTION_enum 1020 { 1021 ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ 1022 ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ 1023 ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ 1024 } ADC_RESOLUTION_t; 1025 1026 /* Voltage reference selection */ 1027 typedef enum ADC_REFSEL_enum 1028 { 1029 ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ 1030 ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ 1031 ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ 1032 ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ 1033 ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ 1034 } ADC_REFSEL_t; 1035 1036 /* Event channel input selection */ 1037 typedef enum ADC_EVSEL_enum 1038 { 1039 ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ 1040 ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ 1041 ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ 1042 ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ 1043 } ADC_EVSEL_t; 1044 1045 /* Event action selection */ 1046 typedef enum ADC_EVACT_enum 1047 { 1048 ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ 1049 ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ 1050 ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ 1051 } ADC_EVACT_t; 1052 1053 /* Interupt mode */ 1054 typedef enum ADC_CH_INTMODE_enum 1055 { 1056 ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ 1057 ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ 1058 ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ 1059 } ADC_CH_INTMODE_t; 1060 1061 /* Interrupt level */ 1062 typedef enum ADC_CH_INTLVL_enum 1063 { 1064 ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1065 ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ 1066 ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ 1067 ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ 1068 } ADC_CH_INTLVL_t; 1069 1070 /* Clock prescaler */ 1071 typedef enum ADC_PRESCALER_enum 1072 { 1073 ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ 1074 ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ 1075 ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ 1076 ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ 1077 ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ 1078 ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ 1079 ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ 1080 ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ 1081 } ADC_PRESCALER_t; 1082 1083 1084 /* 1085 -------------------------------------------------------------------------- 1086 AC - Analog Comparator 1087 -------------------------------------------------------------------------- 1088 */ 1089 1090 /* Analog Comparator */ 1091 typedef struct AC_struct 1092 { 1093 register8_t AC0CTRL; /* Analog Comparator 0 Control */ 1094 register8_t AC1CTRL; /* Analog Comparator 1 Control */ 1095 register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ 1096 register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ 1097 register8_t CTRLA; /* Control Register A */ 1098 register8_t CTRLB; /* Control Register B */ 1099 register8_t WINCTRL; /* Window Mode Control */ 1100 register8_t STATUS; /* Status */ 1101 } AC_t; 1102 1103 /* Interrupt mode */ 1104 typedef enum AC_INTMODE_enum 1105 { 1106 AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ 1107 AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ 1108 AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ 1109 } AC_INTMODE_t; 1110 1111 /* Interrupt level */ 1112 typedef enum AC_INTLVL_enum 1113 { 1114 AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ 1115 AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ 1116 AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ 1117 AC_INTLVL_HI_gc = (0x03<<4), /* High level */ 1118 } AC_INTLVL_t; 1119 1120 /* Hysteresis mode selection */ 1121 typedef enum AC_HYSMODE_enum 1122 { 1123 AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ 1124 AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ 1125 AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ 1126 } AC_HYSMODE_t; 1127 1128 /* Positive input multiplexer selection */ 1129 typedef enum AC_MUXPOS_enum 1130 { 1131 AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ 1132 AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ 1133 AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ 1134 AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ 1135 AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ 1136 AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ 1137 AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ 1138 } AC_MUXPOS_t; 1139 1140 /* Negative input multiplexer selection */ 1141 typedef enum AC_MUXNEG_enum 1142 { 1143 AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ 1144 AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ 1145 AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ 1146 AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ 1147 AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ 1148 AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ 1149 AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ 1150 } AC_MUXNEG_t; 1151 1152 /* Windows interrupt mode */ 1153 typedef enum AC_WINTMODE_enum 1154 { 1155 AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ 1156 AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ 1157 AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ 1158 AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ 1159 } AC_WINTMODE_t; 1160 1161 /* Window interrupt level */ 1162 typedef enum AC_WINTLVL_enum 1163 { 1164 AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1165 AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ 1166 AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ 1167 AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ 1168 } AC_WINTLVL_t; 1169 1170 /* Window mode state */ 1171 typedef enum AC_WSTATE_enum 1172 { 1173 AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ 1174 AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ 1175 AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ 1176 } AC_WSTATE_t; 1177 1178 1179 /* 1180 -------------------------------------------------------------------------- 1181 RTC - Real-Time Counter 1182 -------------------------------------------------------------------------- 1183 */ 1184 1185 /* Real-Time Counter */ 1186 typedef struct RTC_struct 1187 { 1188 register8_t CTRL; /* Control Register */ 1189 register8_t STATUS; /* Status Register */ 1190 register8_t INTCTRL; /* Interrupt Control Register */ 1191 register8_t INTFLAGS; /* Interrupt Flags */ 1192 register8_t TEMP; /* Temporary register */ 1193 register8_t reserved_0x05; 1194 register8_t reserved_0x06; 1195 register8_t reserved_0x07; 1196 _WORDREGISTER(CNT); /* Count Register */ 1197 _WORDREGISTER(PER); /* Period Register */ 1198 _WORDREGISTER(COMP); /* Compare Register */ 1199 } RTC_t; 1200 1201 /* Prescaler Factor */ 1202 typedef enum RTC_PRESCALER_enum 1203 { 1204 RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ 1205 RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ 1206 RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ 1207 RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ 1208 RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ 1209 RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ 1210 RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ 1211 RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ 1212 } RTC_PRESCALER_t; 1213 1214 /* Compare Interrupt level */ 1215 typedef enum RTC_COMPINTLVL_enum 1216 { 1217 RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1218 RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1219 RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1220 RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ 1221 } RTC_COMPINTLVL_t; 1222 1223 /* Overflow Interrupt level */ 1224 typedef enum RTC_OVFINTLVL_enum 1225 { 1226 RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1227 RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1228 RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1229 RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ 1230 } RTC_OVFINTLVL_t; 1231 1232 1233 /* 1234 -------------------------------------------------------------------------- 1235 TWI - Two-Wire Interface 1236 -------------------------------------------------------------------------- 1237 */ 1238 1239 /* */ 1240 typedef struct TWI_MASTER_struct 1241 { 1242 register8_t CTRLA; /* Control Register A */ 1243 register8_t CTRLB; /* Control Register B */ 1244 register8_t CTRLC; /* Control Register C */ 1245 register8_t STATUS; /* Status Register */ 1246 register8_t BAUD; /* Baurd Rate Control Register */ 1247 register8_t ADDR; /* Address Register */ 1248 register8_t DATA; /* Data Register */ 1249 } TWI_MASTER_t; 1250 1251 1252 /* */ 1253 typedef struct TWI_SLAVE_struct 1254 { 1255 register8_t CTRLA; /* Control Register A */ 1256 register8_t CTRLB; /* Control Register B */ 1257 register8_t STATUS; /* Status Register */ 1258 register8_t ADDR; /* Address Register */ 1259 register8_t DATA; /* Data Register */ 1260 register8_t ADDRMASK; /* Address Mask Register */ 1261 } TWI_SLAVE_t; 1262 1263 1264 /* Two-Wire Interface */ 1265 typedef struct TWI_struct 1266 { 1267 register8_t CTRL; /* TWI Common Control Register */ 1268 TWI_MASTER_t MASTER; /* TWI master module */ 1269 TWI_SLAVE_t SLAVE; /* TWI slave module */ 1270 } TWI_t; 1271 1272 /* SDA Hold Time */ 1273 typedef enum TWI_SDAHOLD_enum 1274 { 1275 TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ 1276 TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ 1277 TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ 1278 TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ 1279 } TWI_SDAHOLD_t; 1280 1281 /* Master Interrupt Level */ 1282 typedef enum TWI_MASTER_INTLVL_enum 1283 { 1284 TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1285 TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ 1286 TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1287 TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ 1288 } TWI_MASTER_INTLVL_t; 1289 1290 /* Inactive Timeout */ 1291 typedef enum TWI_MASTER_TIMEOUT_enum 1292 { 1293 TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ 1294 TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ 1295 TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ 1296 TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ 1297 } TWI_MASTER_TIMEOUT_t; 1298 1299 /* Master Command */ 1300 typedef enum TWI_MASTER_CMD_enum 1301 { 1302 TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ 1303 TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ 1304 TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ 1305 TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ 1306 } TWI_MASTER_CMD_t; 1307 1308 /* Master Bus State */ 1309 typedef enum TWI_MASTER_BUSSTATE_enum 1310 { 1311 TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ 1312 TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ 1313 TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ 1314 TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ 1315 } TWI_MASTER_BUSSTATE_t; 1316 1317 /* Slave Interrupt Level */ 1318 typedef enum TWI_SLAVE_INTLVL_enum 1319 { 1320 TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1321 TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ 1322 TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1323 TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ 1324 } TWI_SLAVE_INTLVL_t; 1325 1326 /* Slave Command */ 1327 typedef enum TWI_SLAVE_CMD_enum 1328 { 1329 TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ 1330 TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ 1331 TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ 1332 } TWI_SLAVE_CMD_t; 1333 1334 1335 /* 1336 -------------------------------------------------------------------------- 1337 USB - USB 1338 -------------------------------------------------------------------------- 1339 */ 1340 1341 /* USB Endpoint */ 1342 typedef struct USB_EP_struct 1343 { 1344 register8_t STATUS; /* Endpoint Status */ 1345 register8_t CTRL; /* Endpoint Control */ 1346 _WORDREGISTER(CNT); /* USB Endpoint Counter */ 1347 _WORDREGISTER(DATAPTR); /* Data Pointer */ 1348 _WORDREGISTER(AUXDATA); /* Auxiliary Data */ 1349 } USB_EP_t; 1350 1351 1352 /* Universal Serial Bus */ 1353 typedef struct USB_struct 1354 { 1355 register8_t CTRLA; /* Control Register A */ 1356 register8_t CTRLB; /* Control Register B */ 1357 register8_t STATUS; /* Status Register */ 1358 register8_t ADDR; /* Address Register */ 1359 register8_t FIFOWP; /* FIFO Write Pointer Register */ 1360 register8_t FIFORP; /* FIFO Read Pointer Register */ 1361 _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ 1362 register8_t INTCTRLA; /* Interrupt Control Register A */ 1363 register8_t INTCTRLB; /* Interrupt Control Register B */ 1364 register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ 1365 register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ 1366 register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ 1367 register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ 1368 register8_t reserved_0x0E; 1369 register8_t reserved_0x0F; 1370 register8_t reserved_0x10; 1371 register8_t reserved_0x11; 1372 register8_t reserved_0x12; 1373 register8_t reserved_0x13; 1374 register8_t reserved_0x14; 1375 register8_t reserved_0x15; 1376 register8_t reserved_0x16; 1377 register8_t reserved_0x17; 1378 register8_t reserved_0x18; 1379 register8_t reserved_0x19; 1380 register8_t reserved_0x1A; 1381 register8_t reserved_0x1B; 1382 register8_t reserved_0x1C; 1383 register8_t reserved_0x1D; 1384 register8_t reserved_0x1E; 1385 register8_t reserved_0x1F; 1386 register8_t reserved_0x20; 1387 register8_t reserved_0x21; 1388 register8_t reserved_0x22; 1389 register8_t reserved_0x23; 1390 register8_t reserved_0x24; 1391 register8_t reserved_0x25; 1392 register8_t reserved_0x26; 1393 register8_t reserved_0x27; 1394 register8_t reserved_0x28; 1395 register8_t reserved_0x29; 1396 register8_t reserved_0x2A; 1397 register8_t reserved_0x2B; 1398 register8_t reserved_0x2C; 1399 register8_t reserved_0x2D; 1400 register8_t reserved_0x2E; 1401 register8_t reserved_0x2F; 1402 register8_t reserved_0x30; 1403 register8_t reserved_0x31; 1404 register8_t reserved_0x32; 1405 register8_t reserved_0x33; 1406 register8_t reserved_0x34; 1407 register8_t reserved_0x35; 1408 register8_t reserved_0x36; 1409 register8_t reserved_0x37; 1410 register8_t reserved_0x38; 1411 register8_t reserved_0x39; 1412 register8_t CAL0; /* Calibration Byte 0 */ 1413 register8_t CAL1; /* Calibration Byte 1 */ 1414 } USB_t; 1415 1416 1417 /* USB Endpoint Table */ 1418 typedef struct USB_EP_TABLE_struct 1419 { 1420 USB_EP_t EP0OUT; /* Endpoint 0 */ 1421 USB_EP_t EP0IN; /* Endpoint 0 */ 1422 USB_EP_t EP1OUT; /* Endpoint 1 */ 1423 USB_EP_t EP1IN; /* Endpoint 1 */ 1424 USB_EP_t EP2OUT; /* Endpoint 2 */ 1425 USB_EP_t EP2IN; /* Endpoint 2 */ 1426 USB_EP_t EP3OUT; /* Endpoint 3 */ 1427 USB_EP_t EP3IN; /* Endpoint 3 */ 1428 USB_EP_t EP4OUT; /* Endpoint 4 */ 1429 USB_EP_t EP4IN; /* Endpoint 4 */ 1430 USB_EP_t EP5OUT; /* Endpoint 5 */ 1431 USB_EP_t EP5IN; /* Endpoint 5 */ 1432 USB_EP_t EP6OUT; /* Endpoint 6 */ 1433 USB_EP_t EP6IN; /* Endpoint 6 */ 1434 USB_EP_t EP7OUT; /* Endpoint 7 */ 1435 USB_EP_t EP7IN; /* Endpoint 7 */ 1436 USB_EP_t EP8OUT; /* Endpoint 8 */ 1437 USB_EP_t EP8IN; /* Endpoint 8 */ 1438 USB_EP_t EP9OUT; /* Endpoint 9 */ 1439 USB_EP_t EP9IN; /* Endpoint 9 */ 1440 USB_EP_t EP10OUT; /* Endpoint 10 */ 1441 USB_EP_t EP10IN; /* Endpoint 10 */ 1442 USB_EP_t EP11OUT; /* Endpoint 11 */ 1443 USB_EP_t EP11IN; /* Endpoint 11 */ 1444 USB_EP_t EP12OUT; /* Endpoint 12 */ 1445 USB_EP_t EP12IN; /* Endpoint 12 */ 1446 USB_EP_t EP13OUT; /* Endpoint 13 */ 1447 USB_EP_t EP13IN; /* Endpoint 13 */ 1448 USB_EP_t EP14OUT; /* Endpoint 14 */ 1449 USB_EP_t EP14IN; /* Endpoint 14 */ 1450 USB_EP_t EP15OUT; /* Endpoint 15 */ 1451 USB_EP_t EP15IN; /* Endpoint 15 */ 1452 register8_t reserved_0x100; 1453 register8_t reserved_0x101; 1454 register8_t reserved_0x102; 1455 register8_t reserved_0x103; 1456 register8_t reserved_0x104; 1457 register8_t reserved_0x105; 1458 register8_t reserved_0x106; 1459 register8_t reserved_0x107; 1460 register8_t reserved_0x108; 1461 register8_t reserved_0x109; 1462 register8_t reserved_0x10A; 1463 register8_t reserved_0x10B; 1464 register8_t reserved_0x10C; 1465 register8_t reserved_0x10D; 1466 register8_t reserved_0x10E; 1467 register8_t reserved_0x10F; 1468 register8_t FRAMENUML; /* Frame Number Low Byte */ 1469 register8_t FRAMENUMH; /* Frame Number High Byte */ 1470 } USB_EP_TABLE_t; 1471 1472 /* Interrupt level */ 1473 typedef enum USB_INTLVL_enum 1474 { 1475 USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1476 USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ 1477 USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ 1478 USB_INTLVL_HI_gc = (0x03<<0), /* High level */ 1479 } USB_INTLVL_t; 1480 1481 /* USB Endpoint Type */ 1482 typedef enum USB_EP_TYPE_enum 1483 { 1484 USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ 1485 USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ 1486 USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ 1487 USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ 1488 } USB_EP_TYPE_t; 1489 1490 /* USB Endpoint Buffersize */ 1491 typedef enum USB_EP_BUFSIZE_enum 1492 { 1493 USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ 1494 USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ 1495 USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ 1496 USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ 1497 USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ 1498 USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ 1499 USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ 1500 USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ 1501 } USB_EP_BUFSIZE_t; 1502 1503 1504 /* 1505 -------------------------------------------------------------------------- 1506 PORT - I/O Port Configuration 1507 -------------------------------------------------------------------------- 1508 */ 1509 1510 /* I/O Ports */ 1511 typedef struct PORT_struct 1512 { 1513 register8_t DIR; /* I/O Port Data Direction */ 1514 register8_t DIRSET; /* I/O Port Data Direction Set */ 1515 register8_t DIRCLR; /* I/O Port Data Direction Clear */ 1516 register8_t DIRTGL; /* I/O Port Data Direction Toggle */ 1517 register8_t OUT; /* I/O Port Output */ 1518 register8_t OUTSET; /* I/O Port Output Set */ 1519 register8_t OUTCLR; /* I/O Port Output Clear */ 1520 register8_t OUTTGL; /* I/O Port Output Toggle */ 1521 register8_t IN; /* I/O port Input */ 1522 register8_t INTCTRL; /* Interrupt Control Register */ 1523 register8_t INT0MASK; /* Port Interrupt 0 Mask */ 1524 register8_t INT1MASK; /* Port Interrupt 1 Mask */ 1525 register8_t INTFLAGS; /* Interrupt Flag Register */ 1526 register8_t reserved_0x0D; 1527 register8_t REMAP; /* I/O Port Pin Remap Register */ 1528 register8_t reserved_0x0F; 1529 register8_t PIN0CTRL; /* Pin 0 Control Register */ 1530 register8_t PIN1CTRL; /* Pin 1 Control Register */ 1531 register8_t PIN2CTRL; /* Pin 2 Control Register */ 1532 register8_t PIN3CTRL; /* Pin 3 Control Register */ 1533 register8_t PIN4CTRL; /* Pin 4 Control Register */ 1534 register8_t PIN5CTRL; /* Pin 5 Control Register */ 1535 register8_t PIN6CTRL; /* Pin 6 Control Register */ 1536 register8_t PIN7CTRL; /* Pin 7 Control Register */ 1537 } PORT_t; 1538 1539 /* Port Interrupt 0 Level */ 1540 typedef enum PORT_INT0LVL_enum 1541 { 1542 PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1543 PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ 1544 PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ 1545 PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ 1546 } PORT_INT0LVL_t; 1547 1548 /* Port Interrupt 1 Level */ 1549 typedef enum PORT_INT1LVL_enum 1550 { 1551 PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1552 PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ 1553 PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ 1554 PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ 1555 } PORT_INT1LVL_t; 1556 1557 /* Output/Pull Configuration */ 1558 typedef enum PORT_OPC_enum 1559 { 1560 PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ 1561 PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ 1562 PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ 1563 PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ 1564 PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ 1565 PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ 1566 PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ 1567 PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ 1568 } PORT_OPC_t; 1569 1570 /* Input/Sense Configuration */ 1571 typedef enum PORT_ISC_enum 1572 { 1573 PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ 1574 PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ 1575 PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ 1576 PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ 1577 PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ 1578 } PORT_ISC_t; 1579 1580 1581 /* 1582 -------------------------------------------------------------------------- 1583 TC - 16-bit Timer/Counter With PWM 1584 -------------------------------------------------------------------------- 1585 */ 1586 1587 /* 16-bit Timer/Counter 0 */ 1588 typedef struct TC0_struct 1589 { 1590 register8_t CTRLA; /* Control Register A */ 1591 register8_t CTRLB; /* Control Register B */ 1592 register8_t CTRLC; /* Control register C */ 1593 register8_t CTRLD; /* Control Register D */ 1594 register8_t CTRLE; /* Control Register E */ 1595 register8_t reserved_0x05; 1596 register8_t INTCTRLA; /* Interrupt Control Register A */ 1597 register8_t INTCTRLB; /* Interrupt Control Register B */ 1598 register8_t CTRLFCLR; /* Control Register F Clear */ 1599 register8_t CTRLFSET; /* Control Register F Set */ 1600 register8_t CTRLGCLR; /* Control Register G Clear */ 1601 register8_t CTRLGSET; /* Control Register G Set */ 1602 register8_t INTFLAGS; /* Interrupt Flag Register */ 1603 register8_t reserved_0x0D; 1604 register8_t reserved_0x0E; 1605 register8_t TEMP; /* Temporary Register For 16-bit Access */ 1606 register8_t reserved_0x10; 1607 register8_t reserved_0x11; 1608 register8_t reserved_0x12; 1609 register8_t reserved_0x13; 1610 register8_t reserved_0x14; 1611 register8_t reserved_0x15; 1612 register8_t reserved_0x16; 1613 register8_t reserved_0x17; 1614 register8_t reserved_0x18; 1615 register8_t reserved_0x19; 1616 register8_t reserved_0x1A; 1617 register8_t reserved_0x1B; 1618 register8_t reserved_0x1C; 1619 register8_t reserved_0x1D; 1620 register8_t reserved_0x1E; 1621 register8_t reserved_0x1F; 1622 _WORDREGISTER(CNT); /* Count */ 1623 register8_t reserved_0x22; 1624 register8_t reserved_0x23; 1625 register8_t reserved_0x24; 1626 register8_t reserved_0x25; 1627 _WORDREGISTER(PER); /* Period */ 1628 _WORDREGISTER(CCA); /* Compare or Capture A */ 1629 _WORDREGISTER(CCB); /* Compare or Capture B */ 1630 _WORDREGISTER(CCC); /* Compare or Capture C */ 1631 _WORDREGISTER(CCD); /* Compare or Capture D */ 1632 register8_t reserved_0x30; 1633 register8_t reserved_0x31; 1634 register8_t reserved_0x32; 1635 register8_t reserved_0x33; 1636 register8_t reserved_0x34; 1637 register8_t reserved_0x35; 1638 _WORDREGISTER(PERBUF); /* Period Buffer */ 1639 _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ 1640 _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ 1641 _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ 1642 _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ 1643 } TC0_t; 1644 1645 1646 /* 16-bit Timer/Counter 1 */ 1647 typedef struct TC1_struct 1648 { 1649 register8_t CTRLA; /* Control Register A */ 1650 register8_t CTRLB; /* Control Register B */ 1651 register8_t CTRLC; /* Control register C */ 1652 register8_t CTRLD; /* Control Register D */ 1653 register8_t CTRLE; /* Control Register E */ 1654 register8_t reserved_0x05; 1655 register8_t INTCTRLA; /* Interrupt Control Register A */ 1656 register8_t INTCTRLB; /* Interrupt Control Register B */ 1657 register8_t CTRLFCLR; /* Control Register F Clear */ 1658 register8_t CTRLFSET; /* Control Register F Set */ 1659 register8_t CTRLGCLR; /* Control Register G Clear */ 1660 register8_t CTRLGSET; /* Control Register G Set */ 1661 register8_t INTFLAGS; /* Interrupt Flag Register */ 1662 register8_t reserved_0x0D; 1663 register8_t reserved_0x0E; 1664 register8_t TEMP; /* Temporary Register For 16-bit Access */ 1665 register8_t reserved_0x10; 1666 register8_t reserved_0x11; 1667 register8_t reserved_0x12; 1668 register8_t reserved_0x13; 1669 register8_t reserved_0x14; 1670 register8_t reserved_0x15; 1671 register8_t reserved_0x16; 1672 register8_t reserved_0x17; 1673 register8_t reserved_0x18; 1674 register8_t reserved_0x19; 1675 register8_t reserved_0x1A; 1676 register8_t reserved_0x1B; 1677 register8_t reserved_0x1C; 1678 register8_t reserved_0x1D; 1679 register8_t reserved_0x1E; 1680 register8_t reserved_0x1F; 1681 _WORDREGISTER(CNT); /* Count */ 1682 register8_t reserved_0x22; 1683 register8_t reserved_0x23; 1684 register8_t reserved_0x24; 1685 register8_t reserved_0x25; 1686 _WORDREGISTER(PER); /* Period */ 1687 _WORDREGISTER(CCA); /* Compare or Capture A */ 1688 _WORDREGISTER(CCB); /* Compare or Capture B */ 1689 register8_t reserved_0x2C; 1690 register8_t reserved_0x2D; 1691 register8_t reserved_0x2E; 1692 register8_t reserved_0x2F; 1693 register8_t reserved_0x30; 1694 register8_t reserved_0x31; 1695 register8_t reserved_0x32; 1696 register8_t reserved_0x33; 1697 register8_t reserved_0x34; 1698 register8_t reserved_0x35; 1699 _WORDREGISTER(PERBUF); /* Period Buffer */ 1700 _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ 1701 _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ 1702 } TC1_t; 1703 1704 /* Clock Selection */ 1705 typedef enum TC_CLKSEL_enum 1706 { 1707 TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ 1708 TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ 1709 TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ 1710 TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ 1711 TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ 1712 TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ 1713 TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ 1714 TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ 1715 TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ 1716 TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ 1717 TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ 1718 TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ 1719 } TC_CLKSEL_t; 1720 1721 /* Waveform Generation Mode */ 1722 typedef enum TC_WGMODE_enum 1723 { 1724 TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ 1725 TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ 1726 TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ 1727 TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ 1728 TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ 1729 TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ 1730 TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ 1731 TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ 1732 TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ 1733 TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ 1734 } TC_WGMODE_t; 1735 1736 /* Byte Mode */ 1737 typedef enum TC_BYTEM_enum 1738 { 1739 TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ 1740 TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ 1741 TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ 1742 } TC_BYTEM_t; 1743 1744 /* Event Action */ 1745 typedef enum TC_EVACT_enum 1746 { 1747 TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ 1748 TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ 1749 TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ 1750 TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ 1751 TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ 1752 TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ 1753 TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ 1754 } TC_EVACT_t; 1755 1756 /* Event Selection */ 1757 typedef enum TC_EVSEL_enum 1758 { 1759 TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ 1760 TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ 1761 TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ 1762 TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ 1763 TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ 1764 } TC_EVSEL_t; 1765 1766 /* Error Interrupt Level */ 1767 typedef enum TC_ERRINTLVL_enum 1768 { 1769 TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1770 TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1771 TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1772 TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ 1773 } TC_ERRINTLVL_t; 1774 1775 /* Overflow Interrupt Level */ 1776 typedef enum TC_OVFINTLVL_enum 1777 { 1778 TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1779 TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1780 TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1781 TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ 1782 } TC_OVFINTLVL_t; 1783 1784 /* Compare or Capture D Interrupt Level */ 1785 typedef enum TC_CCDINTLVL_enum 1786 { 1787 TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1788 TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ 1789 TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1790 TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ 1791 } TC_CCDINTLVL_t; 1792 1793 /* Compare or Capture C Interrupt Level */ 1794 typedef enum TC_CCCINTLVL_enum 1795 { 1796 TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 1797 TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 1798 TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 1799 TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ 1800 } TC_CCCINTLVL_t; 1801 1802 /* Compare or Capture B Interrupt Level */ 1803 typedef enum TC_CCBINTLVL_enum 1804 { 1805 TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1806 TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1807 TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1808 TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ 1809 } TC_CCBINTLVL_t; 1810 1811 /* Compare or Capture A Interrupt Level */ 1812 typedef enum TC_CCAINTLVL_enum 1813 { 1814 TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1815 TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1816 TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1817 TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ 1818 } TC_CCAINTLVL_t; 1819 1820 /* Timer/Counter Command */ 1821 typedef enum TC_CMD_enum 1822 { 1823 TC_CMD_NONE_gc = (0x00<<2), /* No Command */ 1824 TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ 1825 TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ 1826 TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ 1827 } TC_CMD_t; 1828 1829 1830 /* 1831 -------------------------------------------------------------------------- 1832 TC2 - 16-bit Timer/Counter type 2 1833 -------------------------------------------------------------------------- 1834 */ 1835 1836 /* 16-bit Timer/Counter type 2 */ 1837 typedef struct TC2_struct 1838 { 1839 register8_t CTRLA; /* Control Register A */ 1840 register8_t CTRLB; /* Control Register B */ 1841 register8_t CTRLC; /* Control register C */ 1842 register8_t reserved_0x03; 1843 register8_t CTRLE; /* Control Register E */ 1844 register8_t reserved_0x05; 1845 register8_t INTCTRLA; /* Interrupt Control Register A */ 1846 register8_t INTCTRLB; /* Interrupt Control Register B */ 1847 register8_t reserved_0x08; 1848 register8_t CTRLF; /* Control Register F */ 1849 register8_t reserved_0x0A; 1850 register8_t reserved_0x0B; 1851 register8_t INTFLAGS; /* Interrupt Flag Register */ 1852 register8_t reserved_0x0D; 1853 register8_t reserved_0x0E; 1854 register8_t reserved_0x0F; 1855 register8_t reserved_0x10; 1856 register8_t reserved_0x11; 1857 register8_t reserved_0x12; 1858 register8_t reserved_0x13; 1859 register8_t reserved_0x14; 1860 register8_t reserved_0x15; 1861 register8_t reserved_0x16; 1862 register8_t reserved_0x17; 1863 register8_t reserved_0x18; 1864 register8_t reserved_0x19; 1865 register8_t reserved_0x1A; 1866 register8_t reserved_0x1B; 1867 register8_t reserved_0x1C; 1868 register8_t reserved_0x1D; 1869 register8_t reserved_0x1E; 1870 register8_t reserved_0x1F; 1871 register8_t LCNT; /* Low Byte Count */ 1872 register8_t HCNT; /* High Byte Count */ 1873 register8_t reserved_0x22; 1874 register8_t reserved_0x23; 1875 register8_t reserved_0x24; 1876 register8_t reserved_0x25; 1877 register8_t LPER; /* Low Byte Period */ 1878 register8_t HPER; /* High Byte Period */ 1879 register8_t LCMPA; /* Low Byte Compare A */ 1880 register8_t HCMPA; /* High Byte Compare A */ 1881 register8_t LCMPB; /* Low Byte Compare B */ 1882 register8_t HCMPB; /* High Byte Compare B */ 1883 register8_t LCMPC; /* Low Byte Compare C */ 1884 register8_t HCMPC; /* High Byte Compare C */ 1885 register8_t LCMPD; /* Low Byte Compare D */ 1886 register8_t HCMPD; /* High Byte Compare D */ 1887 } TC2_t; 1888 1889 /* Clock Selection */ 1890 typedef enum TC2_CLKSEL_enum 1891 { 1892 TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ 1893 TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ 1894 TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ 1895 TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ 1896 TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ 1897 TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ 1898 TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ 1899 TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ 1900 TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ 1901 TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ 1902 TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ 1903 TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ 1904 } TC2_CLKSEL_t; 1905 1906 /* Byte Mode */ 1907 typedef enum TC2_BYTEM_enum 1908 { 1909 TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ 1910 TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ 1911 TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ 1912 } TC2_BYTEM_t; 1913 1914 /* High Byte Underflow Interrupt Level */ 1915 typedef enum TC2_HUNFINTLVL_enum 1916 { 1917 TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1918 TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1919 TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1920 TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ 1921 } TC2_HUNFINTLVL_t; 1922 1923 /* Low Byte Underflow Interrupt Level */ 1924 typedef enum TC2_LUNFINTLVL_enum 1925 { 1926 TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1927 TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1928 TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1929 TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ 1930 } TC2_LUNFINTLVL_t; 1931 1932 /* Low Byte Compare D Interrupt Level */ 1933 typedef enum TC2_LCMPDINTLVL_enum 1934 { 1935 TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1936 TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ 1937 TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1938 TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ 1939 } TC2_LCMPDINTLVL_t; 1940 1941 /* Low Byte Compare C Interrupt Level */ 1942 typedef enum TC2_LCMPCINTLVL_enum 1943 { 1944 TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 1945 TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 1946 TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 1947 TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ 1948 } TC2_LCMPCINTLVL_t; 1949 1950 /* Low Byte Compare B Interrupt Level */ 1951 typedef enum TC2_LCMPBINTLVL_enum 1952 { 1953 TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1954 TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1955 TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1956 TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ 1957 } TC2_LCMPBINTLVL_t; 1958 1959 /* Low Byte Compare A Interrupt Level */ 1960 typedef enum TC2_LCMPAINTLVL_enum 1961 { 1962 TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1963 TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1964 TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1965 TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ 1966 } TC2_LCMPAINTLVL_t; 1967 1968 /* Timer/Counter Command */ 1969 typedef enum TC2_CMD_enum 1970 { 1971 TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ 1972 TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ 1973 TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ 1974 } TC2_CMD_t; 1975 1976 /* Timer/Counter Command */ 1977 typedef enum TC2_CMDEN_enum 1978 { 1979 TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ 1980 TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ 1981 TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ 1982 } TC2_CMDEN_t; 1983 1984 1985 /* 1986 -------------------------------------------------------------------------- 1987 AWEX - Timer/Counter Advanced Waveform Extension 1988 -------------------------------------------------------------------------- 1989 */ 1990 1991 /* Advanced Waveform Extension */ 1992 typedef struct AWEX_struct 1993 { 1994 register8_t CTRL; /* Control Register */ 1995 register8_t reserved_0x01; 1996 register8_t FDEMASK; /* Fault Detection Event Mask */ 1997 register8_t FDCTRL; /* Fault Detection Control Register */ 1998 register8_t STATUS; /* Status Register */ 1999 register8_t STATUSSET; /* Status Set Register */ 2000 register8_t DTBOTH; /* Dead Time Both Sides */ 2001 register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ 2002 register8_t DTLS; /* Dead Time Low Side */ 2003 register8_t DTHS; /* Dead Time High Side */ 2004 register8_t DTLSBUF; /* Dead Time Low Side Buffer */ 2005 register8_t DTHSBUF; /* Dead Time High Side Buffer */ 2006 register8_t OUTOVEN; /* Output Override Enable */ 2007 } AWEX_t; 2008 2009 /* Fault Detect Action */ 2010 typedef enum AWEX_FDACT_enum 2011 { 2012 AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ 2013 AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ 2014 AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ 2015 } AWEX_FDACT_t; 2016 2017 2018 /* 2019 -------------------------------------------------------------------------- 2020 HIRES - Timer/Counter High-Resolution Extension 2021 -------------------------------------------------------------------------- 2022 */ 2023 2024 /* High-Resolution Extension */ 2025 typedef struct HIRES_struct 2026 { 2027 register8_t CTRLA; /* Control Register */ 2028 } HIRES_t; 2029 2030 /* High Resolution Enable */ 2031 typedef enum HIRES_HREN_enum 2032 { 2033 HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ 2034 HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ 2035 HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ 2036 HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ 2037 } HIRES_HREN_t; 2038 2039 2040 /* 2041 -------------------------------------------------------------------------- 2042 USART - Universal Asynchronous Receiver-Transmitter 2043 -------------------------------------------------------------------------- 2044 */ 2045 2046 /* Universal Synchronous/Asynchronous Receiver/Transmitter */ 2047 typedef struct USART_struct 2048 { 2049 register8_t DATA; /* Data Register */ 2050 register8_t STATUS; /* Status Register */ 2051 register8_t reserved_0x02; 2052 register8_t CTRLA; /* Control Register A */ 2053 register8_t CTRLB; /* Control Register B */ 2054 register8_t CTRLC; /* Control Register C */ 2055 register8_t BAUDCTRLA; /* Baud Rate Control Register A */ 2056 register8_t BAUDCTRLB; /* Baud Rate Control Register B */ 2057 } USART_t; 2058 2059 /* Receive Complete Interrupt level */ 2060 typedef enum USART_RXCINTLVL_enum 2061 { 2062 USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 2063 USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 2064 USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 2065 USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ 2066 } USART_RXCINTLVL_t; 2067 2068 /* Transmit Complete Interrupt level */ 2069 typedef enum USART_TXCINTLVL_enum 2070 { 2071 USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 2072 USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ 2073 USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 2074 USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ 2075 } USART_TXCINTLVL_t; 2076 2077 /* Data Register Empty Interrupt level */ 2078 typedef enum USART_DREINTLVL_enum 2079 { 2080 USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2081 USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ 2082 USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2083 USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ 2084 } USART_DREINTLVL_t; 2085 2086 /* Character Size */ 2087 typedef enum USART_CHSIZE_enum 2088 { 2089 USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ 2090 USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ 2091 USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ 2092 USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ 2093 USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ 2094 } USART_CHSIZE_t; 2095 2096 /* Communication Mode */ 2097 typedef enum USART_CMODE_enum 2098 { 2099 USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ 2100 USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ 2101 USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ 2102 USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ 2103 } USART_CMODE_t; 2104 2105 /* Parity Mode */ 2106 typedef enum USART_PMODE_enum 2107 { 2108 USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ 2109 USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ 2110 USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ 2111 } USART_PMODE_t; 2112 2113 2114 /* 2115 -------------------------------------------------------------------------- 2116 SPI - Serial Peripheral Interface 2117 -------------------------------------------------------------------------- 2118 */ 2119 2120 /* Serial Peripheral Interface */ 2121 typedef struct SPI_struct 2122 { 2123 register8_t CTRL; /* Control Register */ 2124 register8_t INTCTRL; /* Interrupt Control Register */ 2125 register8_t STATUS; /* Status Register */ 2126 register8_t DATA; /* Data Register */ 2127 } SPI_t; 2128 2129 /* SPI Mode */ 2130 typedef enum SPI_MODE_enum 2131 { 2132 SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ 2133 SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ 2134 SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ 2135 SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ 2136 } SPI_MODE_t; 2137 2138 /* Prescaler setting */ 2139 typedef enum SPI_PRESCALER_enum 2140 { 2141 SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ 2142 SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ 2143 SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ 2144 SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ 2145 } SPI_PRESCALER_t; 2146 2147 /* Interrupt level */ 2148 typedef enum SPI_INTLVL_enum 2149 { 2150 SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2151 SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ 2152 SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2153 SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ 2154 } SPI_INTLVL_t; 2155 2156 2157 /* 2158 -------------------------------------------------------------------------- 2159 IRCOM - IR Communication Module 2160 -------------------------------------------------------------------------- 2161 */ 2162 2163 /* IR Communication Module */ 2164 typedef struct IRCOM_struct 2165 { 2166 register8_t CTRL; /* Control Register */ 2167 register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ 2168 register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ 2169 } IRCOM_t; 2170 2171 /* Event channel selection */ 2172 typedef enum IRDA_EVSEL_enum 2173 { 2174 IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ 2175 IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ 2176 IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ 2177 IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ 2178 IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ 2179 } IRDA_EVSEL_t; 2180 2181 2182 /* 2183 -------------------------------------------------------------------------- 2184 FUSE - Fuses and Lockbits 2185 -------------------------------------------------------------------------- 2186 */ 2187 2188 /* Fuses */ 2189 typedef struct NVM_FUSES_struct 2190 { 2191 register8_t reserved_0x00; 2192 register8_t FUSEBYTE1; /* Watchdog Configuration */ 2193 register8_t FUSEBYTE2; /* Reset Configuration */ 2194 register8_t reserved_0x03; 2195 register8_t FUSEBYTE4; /* Start-up Configuration */ 2196 register8_t FUSEBYTE5; /* EESAVE and BOD Level */ 2197 } NVM_FUSES_t; 2198 2199 /* Boot Loader Section Reset Vector */ 2200 typedef enum BOOTRST_enum 2201 { 2202 BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ 2203 BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ 2204 } BOOTRST_t; 2205 2206 /* Timer Oscillator pin location */ 2207 typedef enum TOSCSEL_enum 2208 { 2209 TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ 2210 TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ 2211 } TOSCSEL_t; 2212 2213 /* BOD operation */ 2214 typedef enum BOD_enum 2215 { 2216 BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ 2217 BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ 2218 BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ 2219 } BOD_t; 2220 2221 /* BOD operation */ 2222 typedef enum BODACT_enum 2223 { 2224 BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ 2225 BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ 2226 BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ 2227 } BODACT_t; 2228 2229 /* Watchdog (Window) Timeout Period */ 2230 typedef enum WD_enum 2231 { 2232 WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ 2233 WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ 2234 WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ 2235 WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ 2236 WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ 2237 WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ 2238 WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ 2239 WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ 2240 WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ 2241 WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ 2242 WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ 2243 } WD_t; 2244 2245 /* Watchdog (Window) Timeout Period */ 2246 typedef enum WDP_enum 2247 { 2248 WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ 2249 WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ 2250 WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ 2251 WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ 2252 WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ 2253 WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ 2254 WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ 2255 WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ 2256 WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ 2257 WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ 2258 WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ 2259 } WDP_t; 2260 2261 /* Start-up Time */ 2262 typedef enum SUT_enum 2263 { 2264 SUT_0MS_gc = (0x03<<2), /* 0 ms */ 2265 SUT_4MS_gc = (0x01<<2), /* 4 ms */ 2266 SUT_64MS_gc = (0x00<<2), /* 64 ms */ 2267 } SUT_t; 2268 2269 /* Brown Out Detection Voltage Level */ 2270 typedef enum BODLVL_enum 2271 { 2272 BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ 2273 BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ 2274 BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ 2275 BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ 2276 BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ 2277 BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ 2278 BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ 2279 BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ 2280 } BODLVL_t; 2281 2282 2283 /* 2284 -------------------------------------------------------------------------- 2285 LOCKBIT - Fuses and Lockbits 2286 -------------------------------------------------------------------------- 2287 */ 2288 2289 /* Lock Bits */ 2290 typedef struct NVM_LOCKBITS_struct 2291 { 2292 register8_t LOCKBITS; /* Lock Bits */ 2293 } NVM_LOCKBITS_t; 2294 2295 /* Boot lock bits - boot setcion */ 2296 typedef enum FUSE_BLBB_enum 2297 { 2298 FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ 2299 FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ 2300 FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ 2301 FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ 2302 } FUSE_BLBB_t; 2303 2304 /* Boot lock bits - application section */ 2305 typedef enum FUSE_BLBA_enum 2306 { 2307 FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ 2308 FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ 2309 FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ 2310 FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ 2311 } FUSE_BLBA_t; 2312 2313 /* Boot lock bits - application table section */ 2314 typedef enum FUSE_BLBAT_enum 2315 { 2316 FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ 2317 FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ 2318 FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ 2319 FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ 2320 } FUSE_BLBAT_t; 2321 2322 /* Lock bits */ 2323 typedef enum FUSE_LB_enum 2324 { 2325 FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ 2326 FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ 2327 FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ 2328 } FUSE_LB_t; 2329 2330 2331 /* 2332 -------------------------------------------------------------------------- 2333 SIGROW - Signature Row 2334 -------------------------------------------------------------------------- 2335 */ 2336 2337 /* Production Signatures */ 2338 typedef struct NVM_PROD_SIGNATURES_struct 2339 { 2340 register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ 2341 register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ 2342 register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ 2343 register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ 2344 register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ 2345 register8_t reserved_0x05; 2346 register8_t reserved_0x06; 2347 register8_t reserved_0x07; 2348 register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ 2349 register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ 2350 register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ 2351 register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ 2352 register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ 2353 register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ 2354 register8_t reserved_0x0E; 2355 register8_t reserved_0x0F; 2356 register8_t WAFNUM; /* Wafer Number */ 2357 register8_t reserved_0x11; 2358 register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ 2359 register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ 2360 register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ 2361 register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ 2362 register8_t reserved_0x16; 2363 register8_t reserved_0x17; 2364 register8_t reserved_0x18; 2365 register8_t reserved_0x19; 2366 register8_t USBCAL0; /* USB Calibration Byte 0 */ 2367 register8_t USBCAL1; /* USB Calibration Byte 1 */ 2368 register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ 2369 register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ 2370 register8_t reserved_0x1E; 2371 register8_t reserved_0x1F; 2372 register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ 2373 register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ 2374 register8_t reserved_0x22; 2375 register8_t reserved_0x23; 2376 register8_t reserved_0x24; 2377 register8_t reserved_0x25; 2378 register8_t reserved_0x26; 2379 register8_t reserved_0x27; 2380 register8_t reserved_0x28; 2381 register8_t reserved_0x29; 2382 register8_t reserved_0x2A; 2383 register8_t reserved_0x2B; 2384 register8_t reserved_0x2C; 2385 register8_t reserved_0x2D; 2386 register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ 2387 register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ 2388 register8_t reserved_0x30; 2389 register8_t reserved_0x31; 2390 register8_t reserved_0x32; 2391 register8_t reserved_0x33; 2392 register8_t reserved_0x34; 2393 register8_t reserved_0x35; 2394 register8_t reserved_0x36; 2395 register8_t reserved_0x37; 2396 register8_t reserved_0x38; 2397 register8_t reserved_0x39; 2398 register8_t reserved_0x3A; 2399 register8_t reserved_0x3B; 2400 register8_t reserved_0x3C; 2401 register8_t reserved_0x3D; 2402 register8_t reserved_0x3E; 2403 register8_t reserved_0x3F; 2404 } NVM_PROD_SIGNATURES_t; 2405 2406 /* 2407 ========================================================================== 2408 IO Module Instances. Mapped to memory. 2409 ========================================================================== 2410 */ 2411 2412 #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ 2413 #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ 2414 #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ 2415 #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ 2416 #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ 2417 #define CLK (*(CLK_t *) 0x0040) /* Clock System */ 2418 #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ 2419 #define OSC (*(OSC_t *) 0x0050) /* Oscillator */ 2420 #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ 2421 #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ 2422 #define PR (*(PR_t *) 0x0070) /* Power Reduction */ 2423 #define RST (*(RST_t *) 0x0078) /* Reset */ 2424 #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ 2425 #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ 2426 #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ 2427 #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ 2428 #define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ 2429 #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ 2430 #define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ 2431 #define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ 2432 #define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ 2433 #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ 2434 #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ 2435 #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ 2436 #define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ 2437 #define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ 2438 #define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ 2439 #define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ 2440 #define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ 2441 #define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ 2442 #define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ 2443 #define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ 2444 #define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ 2445 #define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ 2446 #define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ 2447 #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ 2448 #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ 2449 #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ 2450 #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ 2451 #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ 2452 #define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ 2453 #define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ 2454 #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ 2455 #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ 2456 #define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ 2457 #define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ 2458 #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ 2459 #define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ 2460 #define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ 2461 2462 2463 #endif /* !defined (__ASSEMBLER__) */ 2464 2465 2466 /* ========== Flattened fully qualified IO register names ========== */ 2467 2468 /* GPIO - General Purpose IO Registers */ 2469 #define GPIO_GPIOR0 _SFR_MEM8(0x0000) 2470 #define GPIO_GPIOR1 _SFR_MEM8(0x0001) 2471 #define GPIO_GPIOR2 _SFR_MEM8(0x0002) 2472 #define GPIO_GPIOR3 _SFR_MEM8(0x0003) 2473 2474 /* Deprecated */ 2475 #define GPIO_GPIO0 _SFR_MEM8(0x0000) 2476 #define GPIO_GPIO1 _SFR_MEM8(0x0001) 2477 #define GPIO_GPIO2 _SFR_MEM8(0x0002) 2478 #define GPIO_GPIO3 _SFR_MEM8(0x0003) 2479 2480 /* NVM_FUSES - Fuses */ 2481 #define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) 2482 #define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) 2483 #define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) 2484 #define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) 2485 2486 /* NVM_LOCKBITS - Lock Bits */ 2487 #define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) 2488 2489 /* NVM_PROD_SIGNATURES - Production Signatures */ 2490 #define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) 2491 #define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) 2492 #define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) 2493 #define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) 2494 #define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) 2495 #define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) 2496 #define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) 2497 #define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) 2498 #define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) 2499 #define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) 2500 #define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) 2501 #define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) 2502 #define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) 2503 #define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) 2504 #define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) 2505 #define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) 2506 #define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) 2507 #define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) 2508 #define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) 2509 #define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) 2510 #define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) 2511 #define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) 2512 #define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) 2513 #define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) 2514 2515 /* VPORT - Virtual Port */ 2516 #define VPORT0_DIR _SFR_MEM8(0x0010) 2517 #define VPORT0_OUT _SFR_MEM8(0x0011) 2518 #define VPORT0_IN _SFR_MEM8(0x0012) 2519 #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) 2520 2521 /* VPORT - Virtual Port */ 2522 #define VPORT1_DIR _SFR_MEM8(0x0014) 2523 #define VPORT1_OUT _SFR_MEM8(0x0015) 2524 #define VPORT1_IN _SFR_MEM8(0x0016) 2525 #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) 2526 2527 /* VPORT - Virtual Port */ 2528 #define VPORT2_DIR _SFR_MEM8(0x0018) 2529 #define VPORT2_OUT _SFR_MEM8(0x0019) 2530 #define VPORT2_IN _SFR_MEM8(0x001A) 2531 #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) 2532 2533 /* VPORT - Virtual Port */ 2534 #define VPORT3_DIR _SFR_MEM8(0x001C) 2535 #define VPORT3_OUT _SFR_MEM8(0x001D) 2536 #define VPORT3_IN _SFR_MEM8(0x001E) 2537 #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) 2538 2539 /* OCD - On-Chip Debug System */ 2540 #define OCD_OCDR0 _SFR_MEM8(0x002E) 2541 #define OCD_OCDR1 _SFR_MEM8(0x002F) 2542 2543 /* CPU - CPU registers */ 2544 #define CPU_CCP _SFR_MEM8(0x0034) 2545 #define CPU_RAMPD _SFR_MEM8(0x0038) 2546 #define CPU_RAMPX _SFR_MEM8(0x0039) 2547 #define CPU_RAMPY _SFR_MEM8(0x003A) 2548 #define CPU_RAMPZ _SFR_MEM8(0x003B) 2549 #define CPU_EIND _SFR_MEM8(0x003C) 2550 #define CPU_SPL _SFR_MEM8(0x003D) 2551 #define CPU_SPH _SFR_MEM8(0x003E) 2552 #define CPU_SREG _SFR_MEM8(0x003F) 2553 2554 /* CLK - Clock System */ 2555 #define CLK_CTRL _SFR_MEM8(0x0040) 2556 #define CLK_PSCTRL _SFR_MEM8(0x0041) 2557 #define CLK_LOCK _SFR_MEM8(0x0042) 2558 #define CLK_RTCCTRL _SFR_MEM8(0x0043) 2559 #define CLK_USBCTRL _SFR_MEM8(0x0044) 2560 2561 /* SLEEP - Sleep Controller */ 2562 #define SLEEP_CTRL _SFR_MEM8(0x0048) 2563 2564 /* OSC - Oscillator */ 2565 #define OSC_CTRL _SFR_MEM8(0x0050) 2566 #define OSC_STATUS _SFR_MEM8(0x0051) 2567 #define OSC_XOSCCTRL _SFR_MEM8(0x0052) 2568 #define OSC_XOSCFAIL _SFR_MEM8(0x0053) 2569 #define OSC_RC32KCAL _SFR_MEM8(0x0054) 2570 #define OSC_PLLCTRL _SFR_MEM8(0x0055) 2571 #define OSC_DFLLCTRL _SFR_MEM8(0x0056) 2572 2573 /* DFLL - DFLL */ 2574 #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) 2575 #define DFLLRC32M_CALA _SFR_MEM8(0x0062) 2576 #define DFLLRC32M_CALB _SFR_MEM8(0x0063) 2577 #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) 2578 #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) 2579 #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) 2580 2581 /* DFLL - DFLL */ 2582 #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) 2583 #define DFLLRC2M_CALA _SFR_MEM8(0x006A) 2584 #define DFLLRC2M_CALB _SFR_MEM8(0x006B) 2585 #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) 2586 #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) 2587 #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) 2588 2589 /* PR - Power Reduction */ 2590 #define PR_PRGEN _SFR_MEM8(0x0070) 2591 #define PR_PRPA _SFR_MEM8(0x0071) 2592 #define PR_PRPC _SFR_MEM8(0x0073) 2593 #define PR_PRPD _SFR_MEM8(0x0074) 2594 #define PR_PRPE _SFR_MEM8(0x0075) 2595 #define PR_PRPF _SFR_MEM8(0x0076) 2596 2597 /* RST - Reset */ 2598 #define RST_STATUS _SFR_MEM8(0x0078) 2599 #define RST_CTRL _SFR_MEM8(0x0079) 2600 2601 /* WDT - Watch-Dog Timer */ 2602 #define WDT_CTRL _SFR_MEM8(0x0080) 2603 #define WDT_WINCTRL _SFR_MEM8(0x0081) 2604 #define WDT_STATUS _SFR_MEM8(0x0082) 2605 2606 /* MCU - MCU Control */ 2607 #define MCU_DEVID0 _SFR_MEM8(0x0090) 2608 #define MCU_DEVID1 _SFR_MEM8(0x0091) 2609 #define MCU_DEVID2 _SFR_MEM8(0x0092) 2610 #define MCU_REVID _SFR_MEM8(0x0093) 2611 #define MCU_ANAINIT _SFR_MEM8(0x0097) 2612 #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) 2613 #define MCU_AWEXLOCK _SFR_MEM8(0x0099) 2614 2615 /* PMIC - Programmable Multi-level Interrupt Controller */ 2616 #define PMIC_STATUS _SFR_MEM8(0x00A0) 2617 #define PMIC_INTPRI _SFR_MEM8(0x00A1) 2618 #define PMIC_CTRL _SFR_MEM8(0x00A2) 2619 2620 /* PORTCFG - I/O port Configuration */ 2621 #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) 2622 #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) 2623 #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) 2624 #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) 2625 #define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) 2626 2627 /* CRC - Cyclic Redundancy Checker */ 2628 #define CRC_CTRL _SFR_MEM8(0x00D0) 2629 #define CRC_STATUS _SFR_MEM8(0x00D1) 2630 #define CRC_DATAIN _SFR_MEM8(0x00D3) 2631 #define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) 2632 #define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) 2633 #define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) 2634 #define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) 2635 2636 /* EVSYS - Event System */ 2637 #define EVSYS_CH0MUX _SFR_MEM8(0x0180) 2638 #define EVSYS_CH1MUX _SFR_MEM8(0x0181) 2639 #define EVSYS_CH2MUX _SFR_MEM8(0x0182) 2640 #define EVSYS_CH3MUX _SFR_MEM8(0x0183) 2641 #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) 2642 #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) 2643 #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) 2644 #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) 2645 #define EVSYS_STROBE _SFR_MEM8(0x0190) 2646 #define EVSYS_DATA _SFR_MEM8(0x0191) 2647 2648 /* NVM - Non-volatile Memory Controller */ 2649 #define NVM_ADDR0 _SFR_MEM8(0x01C0) 2650 #define NVM_ADDR1 _SFR_MEM8(0x01C1) 2651 #define NVM_ADDR2 _SFR_MEM8(0x01C2) 2652 #define NVM_DATA0 _SFR_MEM8(0x01C4) 2653 #define NVM_DATA1 _SFR_MEM8(0x01C5) 2654 #define NVM_DATA2 _SFR_MEM8(0x01C6) 2655 #define NVM_CMD _SFR_MEM8(0x01CA) 2656 #define NVM_CTRLA _SFR_MEM8(0x01CB) 2657 #define NVM_CTRLB _SFR_MEM8(0x01CC) 2658 #define NVM_INTCTRL _SFR_MEM8(0x01CD) 2659 #define NVM_STATUS _SFR_MEM8(0x01CF) 2660 #define NVM_LOCKBITS _SFR_MEM8(0x01D0) 2661 2662 /* ADC - Analog-to-Digital Converter */ 2663 #define ADCA_CTRLA _SFR_MEM8(0x0200) 2664 #define ADCA_CTRLB _SFR_MEM8(0x0201) 2665 #define ADCA_REFCTRL _SFR_MEM8(0x0202) 2666 #define ADCA_EVCTRL _SFR_MEM8(0x0203) 2667 #define ADCA_PRESCALER _SFR_MEM8(0x0204) 2668 #define ADCA_INTFLAGS _SFR_MEM8(0x0206) 2669 #define ADCA_TEMP _SFR_MEM8(0x0207) 2670 #define ADCA_CAL _SFR_MEM16(0x020C) 2671 #define ADCA_CH0RES _SFR_MEM16(0x0210) 2672 #define ADCA_CMP _SFR_MEM16(0x0218) 2673 #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) 2674 #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) 2675 #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) 2676 #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) 2677 #define ADCA_CH0_RES _SFR_MEM16(0x0224) 2678 #define ADCA_CH0_SCAN _SFR_MEM8(0x0226) 2679 2680 /* AC - Analog Comparator */ 2681 #define ACA_AC0CTRL _SFR_MEM8(0x0380) 2682 #define ACA_AC1CTRL _SFR_MEM8(0x0381) 2683 #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) 2684 #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) 2685 #define ACA_CTRLA _SFR_MEM8(0x0384) 2686 #define ACA_CTRLB _SFR_MEM8(0x0385) 2687 #define ACA_WINCTRL _SFR_MEM8(0x0386) 2688 #define ACA_STATUS _SFR_MEM8(0x0387) 2689 2690 /* RTC - Real-Time Counter */ 2691 #define RTC_CTRL _SFR_MEM8(0x0400) 2692 #define RTC_STATUS _SFR_MEM8(0x0401) 2693 #define RTC_INTCTRL _SFR_MEM8(0x0402) 2694 #define RTC_INTFLAGS _SFR_MEM8(0x0403) 2695 #define RTC_TEMP _SFR_MEM8(0x0404) 2696 #define RTC_CNT _SFR_MEM16(0x0408) 2697 #define RTC_PER _SFR_MEM16(0x040A) 2698 #define RTC_COMP _SFR_MEM16(0x040C) 2699 2700 /* TWI - Two-Wire Interface */ 2701 #define TWIC_CTRL _SFR_MEM8(0x0480) 2702 #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) 2703 #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) 2704 #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) 2705 #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) 2706 #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) 2707 #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) 2708 #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) 2709 #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) 2710 #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) 2711 #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) 2712 #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) 2713 #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) 2714 #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) 2715 2716 /* TWI - Two-Wire Interface */ 2717 #define TWIE_CTRL _SFR_MEM8(0x04A0) 2718 #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) 2719 #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) 2720 #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) 2721 #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) 2722 #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) 2723 #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) 2724 #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) 2725 #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) 2726 #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) 2727 #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) 2728 #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) 2729 #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) 2730 #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) 2731 2732 /* USB - Universal Serial Bus */ 2733 #define USB_CTRLA _SFR_MEM8(0x04C0) 2734 #define USB_CTRLB _SFR_MEM8(0x04C1) 2735 #define USB_STATUS _SFR_MEM8(0x04C2) 2736 #define USB_ADDR _SFR_MEM8(0x04C3) 2737 #define USB_FIFOWP _SFR_MEM8(0x04C4) 2738 #define USB_FIFORP _SFR_MEM8(0x04C5) 2739 #define USB_EPPTR _SFR_MEM16(0x04C6) 2740 #define USB_INTCTRLA _SFR_MEM8(0x04C8) 2741 #define USB_INTCTRLB _SFR_MEM8(0x04C9) 2742 #define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) 2743 #define USB_INTFLAGSASET _SFR_MEM8(0x04CB) 2744 #define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) 2745 #define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) 2746 #define USB_CAL0 _SFR_MEM8(0x04FA) 2747 #define USB_CAL1 _SFR_MEM8(0x04FB) 2748 2749 /* PORT - I/O Ports */ 2750 #define PORTA_DIR _SFR_MEM8(0x0600) 2751 #define PORTA_DIRSET _SFR_MEM8(0x0601) 2752 #define PORTA_DIRCLR _SFR_MEM8(0x0602) 2753 #define PORTA_DIRTGL _SFR_MEM8(0x0603) 2754 #define PORTA_OUT _SFR_MEM8(0x0604) 2755 #define PORTA_OUTSET _SFR_MEM8(0x0605) 2756 #define PORTA_OUTCLR _SFR_MEM8(0x0606) 2757 #define PORTA_OUTTGL _SFR_MEM8(0x0607) 2758 #define PORTA_IN _SFR_MEM8(0x0608) 2759 #define PORTA_INTCTRL _SFR_MEM8(0x0609) 2760 #define PORTA_INT0MASK _SFR_MEM8(0x060A) 2761 #define PORTA_INT1MASK _SFR_MEM8(0x060B) 2762 #define PORTA_INTFLAGS _SFR_MEM8(0x060C) 2763 #define PORTA_REMAP _SFR_MEM8(0x060E) 2764 #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) 2765 #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) 2766 #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) 2767 #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) 2768 #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) 2769 #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) 2770 #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) 2771 #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) 2772 2773 /* PORT - I/O Ports */ 2774 #define PORTB_DIR _SFR_MEM8(0x0620) 2775 #define PORTB_DIRSET _SFR_MEM8(0x0621) 2776 #define PORTB_DIRCLR _SFR_MEM8(0x0622) 2777 #define PORTB_DIRTGL _SFR_MEM8(0x0623) 2778 #define PORTB_OUT _SFR_MEM8(0x0624) 2779 #define PORTB_OUTSET _SFR_MEM8(0x0625) 2780 #define PORTB_OUTCLR _SFR_MEM8(0x0626) 2781 #define PORTB_OUTTGL _SFR_MEM8(0x0627) 2782 #define PORTB_IN _SFR_MEM8(0x0628) 2783 #define PORTB_INTCTRL _SFR_MEM8(0x0629) 2784 #define PORTB_INT0MASK _SFR_MEM8(0x062A) 2785 #define PORTB_INT1MASK _SFR_MEM8(0x062B) 2786 #define PORTB_INTFLAGS _SFR_MEM8(0x062C) 2787 #define PORTB_REMAP _SFR_MEM8(0x062E) 2788 #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) 2789 #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) 2790 #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) 2791 #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) 2792 #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) 2793 #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) 2794 #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) 2795 #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) 2796 2797 /* PORT - I/O Ports */ 2798 #define PORTC_DIR _SFR_MEM8(0x0640) 2799 #define PORTC_DIRSET _SFR_MEM8(0x0641) 2800 #define PORTC_DIRCLR _SFR_MEM8(0x0642) 2801 #define PORTC_DIRTGL _SFR_MEM8(0x0643) 2802 #define PORTC_OUT _SFR_MEM8(0x0644) 2803 #define PORTC_OUTSET _SFR_MEM8(0x0645) 2804 #define PORTC_OUTCLR _SFR_MEM8(0x0646) 2805 #define PORTC_OUTTGL _SFR_MEM8(0x0647) 2806 #define PORTC_IN _SFR_MEM8(0x0648) 2807 #define PORTC_INTCTRL _SFR_MEM8(0x0649) 2808 #define PORTC_INT0MASK _SFR_MEM8(0x064A) 2809 #define PORTC_INT1MASK _SFR_MEM8(0x064B) 2810 #define PORTC_INTFLAGS _SFR_MEM8(0x064C) 2811 #define PORTC_REMAP _SFR_MEM8(0x064E) 2812 #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) 2813 #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) 2814 #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) 2815 #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) 2816 #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) 2817 #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) 2818 #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) 2819 #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) 2820 2821 /* PORT - I/O Ports */ 2822 #define PORTD_DIR _SFR_MEM8(0x0660) 2823 #define PORTD_DIRSET _SFR_MEM8(0x0661) 2824 #define PORTD_DIRCLR _SFR_MEM8(0x0662) 2825 #define PORTD_DIRTGL _SFR_MEM8(0x0663) 2826 #define PORTD_OUT _SFR_MEM8(0x0664) 2827 #define PORTD_OUTSET _SFR_MEM8(0x0665) 2828 #define PORTD_OUTCLR _SFR_MEM8(0x0666) 2829 #define PORTD_OUTTGL _SFR_MEM8(0x0667) 2830 #define PORTD_IN _SFR_MEM8(0x0668) 2831 #define PORTD_INTCTRL _SFR_MEM8(0x0669) 2832 #define PORTD_INT0MASK _SFR_MEM8(0x066A) 2833 #define PORTD_INT1MASK _SFR_MEM8(0x066B) 2834 #define PORTD_INTFLAGS _SFR_MEM8(0x066C) 2835 #define PORTD_REMAP _SFR_MEM8(0x066E) 2836 #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) 2837 #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) 2838 #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) 2839 #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) 2840 #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) 2841 #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) 2842 #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) 2843 #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) 2844 2845 /* PORT - I/O Ports */ 2846 #define PORTE_DIR _SFR_MEM8(0x0680) 2847 #define PORTE_DIRSET _SFR_MEM8(0x0681) 2848 #define PORTE_DIRCLR _SFR_MEM8(0x0682) 2849 #define PORTE_DIRTGL _SFR_MEM8(0x0683) 2850 #define PORTE_OUT _SFR_MEM8(0x0684) 2851 #define PORTE_OUTSET _SFR_MEM8(0x0685) 2852 #define PORTE_OUTCLR _SFR_MEM8(0x0686) 2853 #define PORTE_OUTTGL _SFR_MEM8(0x0687) 2854 #define PORTE_IN _SFR_MEM8(0x0688) 2855 #define PORTE_INTCTRL _SFR_MEM8(0x0689) 2856 #define PORTE_INT0MASK _SFR_MEM8(0x068A) 2857 #define PORTE_INT1MASK _SFR_MEM8(0x068B) 2858 #define PORTE_INTFLAGS _SFR_MEM8(0x068C) 2859 #define PORTE_REMAP _SFR_MEM8(0x068E) 2860 #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) 2861 #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) 2862 #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) 2863 #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) 2864 #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) 2865 #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) 2866 #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) 2867 #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) 2868 2869 /* PORT - I/O Ports */ 2870 #define PORTF_DIR _SFR_MEM8(0x06A0) 2871 #define PORTF_DIRSET _SFR_MEM8(0x06A1) 2872 #define PORTF_DIRCLR _SFR_MEM8(0x06A2) 2873 #define PORTF_DIRTGL _SFR_MEM8(0x06A3) 2874 #define PORTF_OUT _SFR_MEM8(0x06A4) 2875 #define PORTF_OUTSET _SFR_MEM8(0x06A5) 2876 #define PORTF_OUTCLR _SFR_MEM8(0x06A6) 2877 #define PORTF_OUTTGL _SFR_MEM8(0x06A7) 2878 #define PORTF_IN _SFR_MEM8(0x06A8) 2879 #define PORTF_INTCTRL _SFR_MEM8(0x06A9) 2880 #define PORTF_INT0MASK _SFR_MEM8(0x06AA) 2881 #define PORTF_INT1MASK _SFR_MEM8(0x06AB) 2882 #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) 2883 #define PORTF_REMAP _SFR_MEM8(0x06AE) 2884 #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) 2885 #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) 2886 #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) 2887 #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) 2888 #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) 2889 #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) 2890 #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) 2891 #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) 2892 2893 /* PORT - I/O Ports */ 2894 #define PORTR_DIR _SFR_MEM8(0x07E0) 2895 #define PORTR_DIRSET _SFR_MEM8(0x07E1) 2896 #define PORTR_DIRCLR _SFR_MEM8(0x07E2) 2897 #define PORTR_DIRTGL _SFR_MEM8(0x07E3) 2898 #define PORTR_OUT _SFR_MEM8(0x07E4) 2899 #define PORTR_OUTSET _SFR_MEM8(0x07E5) 2900 #define PORTR_OUTCLR _SFR_MEM8(0x07E6) 2901 #define PORTR_OUTTGL _SFR_MEM8(0x07E7) 2902 #define PORTR_IN _SFR_MEM8(0x07E8) 2903 #define PORTR_INTCTRL _SFR_MEM8(0x07E9) 2904 #define PORTR_INT0MASK _SFR_MEM8(0x07EA) 2905 #define PORTR_INT1MASK _SFR_MEM8(0x07EB) 2906 #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) 2907 #define PORTR_REMAP _SFR_MEM8(0x07EE) 2908 #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) 2909 #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) 2910 #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) 2911 #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) 2912 #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) 2913 #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) 2914 #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) 2915 #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) 2916 2917 /* TC0 - 16-bit Timer/Counter 0 */ 2918 #define TCC0_CTRLA _SFR_MEM8(0x0800) 2919 #define TCC0_CTRLB _SFR_MEM8(0x0801) 2920 #define TCC0_CTRLC _SFR_MEM8(0x0802) 2921 #define TCC0_CTRLD _SFR_MEM8(0x0803) 2922 #define TCC0_CTRLE _SFR_MEM8(0x0804) 2923 #define TCC0_INTCTRLA _SFR_MEM8(0x0806) 2924 #define TCC0_INTCTRLB _SFR_MEM8(0x0807) 2925 #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) 2926 #define TCC0_CTRLFSET _SFR_MEM8(0x0809) 2927 #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) 2928 #define TCC0_CTRLGSET _SFR_MEM8(0x080B) 2929 #define TCC0_INTFLAGS _SFR_MEM8(0x080C) 2930 #define TCC0_TEMP _SFR_MEM8(0x080F) 2931 #define TCC0_CNT _SFR_MEM16(0x0820) 2932 #define TCC0_PER _SFR_MEM16(0x0826) 2933 #define TCC0_CCA _SFR_MEM16(0x0828) 2934 #define TCC0_CCB _SFR_MEM16(0x082A) 2935 #define TCC0_CCC _SFR_MEM16(0x082C) 2936 #define TCC0_CCD _SFR_MEM16(0x082E) 2937 #define TCC0_PERBUF _SFR_MEM16(0x0836) 2938 #define TCC0_CCABUF _SFR_MEM16(0x0838) 2939 #define TCC0_CCBBUF _SFR_MEM16(0x083A) 2940 #define TCC0_CCCBUF _SFR_MEM16(0x083C) 2941 #define TCC0_CCDBUF _SFR_MEM16(0x083E) 2942 2943 /* TC2 - 16-bit Timer/Counter type 2 */ 2944 #define TCC2_CTRLA _SFR_MEM8(0x0800) 2945 #define TCC2_CTRLB _SFR_MEM8(0x0801) 2946 #define TCC2_CTRLC _SFR_MEM8(0x0802) 2947 #define TCC2_CTRLE _SFR_MEM8(0x0804) 2948 #define TCC2_INTCTRLA _SFR_MEM8(0x0806) 2949 #define TCC2_INTCTRLB _SFR_MEM8(0x0807) 2950 #define TCC2_CTRLF _SFR_MEM8(0x0809) 2951 #define TCC2_INTFLAGS _SFR_MEM8(0x080C) 2952 #define TCC2_LCNT _SFR_MEM8(0x0820) 2953 #define TCC2_HCNT _SFR_MEM8(0x0821) 2954 #define TCC2_LPER _SFR_MEM8(0x0826) 2955 #define TCC2_HPER _SFR_MEM8(0x0827) 2956 #define TCC2_LCMPA _SFR_MEM8(0x0828) 2957 #define TCC2_HCMPA _SFR_MEM8(0x0829) 2958 #define TCC2_LCMPB _SFR_MEM8(0x082A) 2959 #define TCC2_HCMPB _SFR_MEM8(0x082B) 2960 #define TCC2_LCMPC _SFR_MEM8(0x082C) 2961 #define TCC2_HCMPC _SFR_MEM8(0x082D) 2962 #define TCC2_LCMPD _SFR_MEM8(0x082E) 2963 #define TCC2_HCMPD _SFR_MEM8(0x082F) 2964 2965 /* TC1 - 16-bit Timer/Counter 1 */ 2966 #define TCC1_CTRLA _SFR_MEM8(0x0840) 2967 #define TCC1_CTRLB _SFR_MEM8(0x0841) 2968 #define TCC1_CTRLC _SFR_MEM8(0x0842) 2969 #define TCC1_CTRLD _SFR_MEM8(0x0843) 2970 #define TCC1_CTRLE _SFR_MEM8(0x0844) 2971 #define TCC1_INTCTRLA _SFR_MEM8(0x0846) 2972 #define TCC1_INTCTRLB _SFR_MEM8(0x0847) 2973 #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) 2974 #define TCC1_CTRLFSET _SFR_MEM8(0x0849) 2975 #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) 2976 #define TCC1_CTRLGSET _SFR_MEM8(0x084B) 2977 #define TCC1_INTFLAGS _SFR_MEM8(0x084C) 2978 #define TCC1_TEMP _SFR_MEM8(0x084F) 2979 #define TCC1_CNT _SFR_MEM16(0x0860) 2980 #define TCC1_PER _SFR_MEM16(0x0866) 2981 #define TCC1_CCA _SFR_MEM16(0x0868) 2982 #define TCC1_CCB _SFR_MEM16(0x086A) 2983 #define TCC1_PERBUF _SFR_MEM16(0x0876) 2984 #define TCC1_CCABUF _SFR_MEM16(0x0878) 2985 #define TCC1_CCBBUF _SFR_MEM16(0x087A) 2986 2987 /* AWEX - Advanced Waveform Extension */ 2988 #define AWEXC_CTRL _SFR_MEM8(0x0880) 2989 #define AWEXC_FDEMASK _SFR_MEM8(0x0882) 2990 #define AWEXC_FDCTRL _SFR_MEM8(0x0883) 2991 #define AWEXC_STATUS _SFR_MEM8(0x0884) 2992 #define AWEXC_STATUSSET _SFR_MEM8(0x0885) 2993 #define AWEXC_DTBOTH _SFR_MEM8(0x0886) 2994 #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) 2995 #define AWEXC_DTLS _SFR_MEM8(0x0888) 2996 #define AWEXC_DTHS _SFR_MEM8(0x0889) 2997 #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) 2998 #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) 2999 #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) 3000 3001 /* HIRES - High-Resolution Extension */ 3002 #define HIRESC_CTRLA _SFR_MEM8(0x0890) 3003 3004 /* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ 3005 #define USARTC0_DATA _SFR_MEM8(0x08A0) 3006 #define USARTC0_STATUS _SFR_MEM8(0x08A1) 3007 #define USARTC0_CTRLA _SFR_MEM8(0x08A3) 3008 #define USARTC0_CTRLB _SFR_MEM8(0x08A4) 3009 #define USARTC0_CTRLC _SFR_MEM8(0x08A5) 3010 #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) 3011 #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) 3012 3013 /* SPI - Serial Peripheral Interface */ 3014 #define SPIC_CTRL _SFR_MEM8(0x08C0) 3015 #define SPIC_INTCTRL _SFR_MEM8(0x08C1) 3016 #define SPIC_STATUS _SFR_MEM8(0x08C2) 3017 #define SPIC_DATA _SFR_MEM8(0x08C3) 3018 3019 /* IRCOM - IR Communication Module */ 3020 #define IRCOM_CTRL _SFR_MEM8(0x08F8) 3021 #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) 3022 #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) 3023 3024 /* TC0 - 16-bit Timer/Counter 0 */ 3025 #define TCD0_CTRLA _SFR_MEM8(0x0900) 3026 #define TCD0_CTRLB _SFR_MEM8(0x0901) 3027 #define TCD0_CTRLC _SFR_MEM8(0x0902) 3028 #define TCD0_CTRLD _SFR_MEM8(0x0903) 3029 #define TCD0_CTRLE _SFR_MEM8(0x0904) 3030 #define TCD0_INTCTRLA _SFR_MEM8(0x0906) 3031 #define TCD0_INTCTRLB _SFR_MEM8(0x0907) 3032 #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) 3033 #define TCD0_CTRLFSET _SFR_MEM8(0x0909) 3034 #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) 3035 #define TCD0_CTRLGSET _SFR_MEM8(0x090B) 3036 #define TCD0_INTFLAGS _SFR_MEM8(0x090C) 3037 #define TCD0_TEMP _SFR_MEM8(0x090F) 3038 #define TCD0_CNT _SFR_MEM16(0x0920) 3039 #define TCD0_PER _SFR_MEM16(0x0926) 3040 #define TCD0_CCA _SFR_MEM16(0x0928) 3041 #define TCD0_CCB _SFR_MEM16(0x092A) 3042 #define TCD0_CCC _SFR_MEM16(0x092C) 3043 #define TCD0_CCD _SFR_MEM16(0x092E) 3044 #define TCD0_PERBUF _SFR_MEM16(0x0936) 3045 #define TCD0_CCABUF _SFR_MEM16(0x0938) 3046 #define TCD0_CCBBUF _SFR_MEM16(0x093A) 3047 #define TCD0_CCCBUF _SFR_MEM16(0x093C) 3048 #define TCD0_CCDBUF _SFR_MEM16(0x093E) 3049 3050 /* TC2 - 16-bit Timer/Counter type 2 */ 3051 #define TCD2_CTRLA _SFR_MEM8(0x0900) 3052 #define TCD2_CTRLB _SFR_MEM8(0x0901) 3053 #define TCD2_CTRLC _SFR_MEM8(0x0902) 3054 #define TCD2_CTRLE _SFR_MEM8(0x0904) 3055 #define TCD2_INTCTRLA _SFR_MEM8(0x0906) 3056 #define TCD2_INTCTRLB _SFR_MEM8(0x0907) 3057 #define TCD2_CTRLF _SFR_MEM8(0x0909) 3058 #define TCD2_INTFLAGS _SFR_MEM8(0x090C) 3059 #define TCD2_LCNT _SFR_MEM8(0x0920) 3060 #define TCD2_HCNT _SFR_MEM8(0x0921) 3061 #define TCD2_LPER _SFR_MEM8(0x0926) 3062 #define TCD2_HPER _SFR_MEM8(0x0927) 3063 #define TCD2_LCMPA _SFR_MEM8(0x0928) 3064 #define TCD2_HCMPA _SFR_MEM8(0x0929) 3065 #define TCD2_LCMPB _SFR_MEM8(0x092A) 3066 #define TCD2_HCMPB _SFR_MEM8(0x092B) 3067 #define TCD2_LCMPC _SFR_MEM8(0x092C) 3068 #define TCD2_HCMPC _SFR_MEM8(0x092D) 3069 #define TCD2_LCMPD _SFR_MEM8(0x092E) 3070 #define TCD2_HCMPD _SFR_MEM8(0x092F) 3071 3072 /* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ 3073 #define USARTD0_DATA _SFR_MEM8(0x09A0) 3074 #define USARTD0_STATUS _SFR_MEM8(0x09A1) 3075 #define USARTD0_CTRLA _SFR_MEM8(0x09A3) 3076 #define USARTD0_CTRLB _SFR_MEM8(0x09A4) 3077 #define USARTD0_CTRLC _SFR_MEM8(0x09A5) 3078 #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) 3079 #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) 3080 3081 /* SPI - Serial Peripheral Interface */ 3082 #define SPID_CTRL _SFR_MEM8(0x09C0) 3083 #define SPID_INTCTRL _SFR_MEM8(0x09C1) 3084 #define SPID_STATUS _SFR_MEM8(0x09C2) 3085 #define SPID_DATA _SFR_MEM8(0x09C3) 3086 3087 /* TC0 - 16-bit Timer/Counter 0 */ 3088 #define TCE0_CTRLA _SFR_MEM8(0x0A00) 3089 #define TCE0_CTRLB _SFR_MEM8(0x0A01) 3090 #define TCE0_CTRLC _SFR_MEM8(0x0A02) 3091 #define TCE0_CTRLD _SFR_MEM8(0x0A03) 3092 #define TCE0_CTRLE _SFR_MEM8(0x0A04) 3093 #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) 3094 #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) 3095 #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) 3096 #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) 3097 #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) 3098 #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) 3099 #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) 3100 #define TCE0_TEMP _SFR_MEM8(0x0A0F) 3101 #define TCE0_CNT _SFR_MEM16(0x0A20) 3102 #define TCE0_PER _SFR_MEM16(0x0A26) 3103 #define TCE0_CCA _SFR_MEM16(0x0A28) 3104 #define TCE0_CCB _SFR_MEM16(0x0A2A) 3105 #define TCE0_CCC _SFR_MEM16(0x0A2C) 3106 #define TCE0_CCD _SFR_MEM16(0x0A2E) 3107 #define TCE0_PERBUF _SFR_MEM16(0x0A36) 3108 #define TCE0_CCABUF _SFR_MEM16(0x0A38) 3109 #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) 3110 #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) 3111 #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) 3112 3113 /* TC2 - 16-bit Timer/Counter type 2 */ 3114 #define TCE2_CTRLA _SFR_MEM8(0x0A00) 3115 #define TCE2_CTRLB _SFR_MEM8(0x0A01) 3116 #define TCE2_CTRLC _SFR_MEM8(0x0A02) 3117 #define TCE2_CTRLE _SFR_MEM8(0x0A04) 3118 #define TCE2_INTCTRLA _SFR_MEM8(0x0A06) 3119 #define TCE2_INTCTRLB _SFR_MEM8(0x0A07) 3120 #define TCE2_CTRLF _SFR_MEM8(0x0A09) 3121 #define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) 3122 #define TCE2_LCNT _SFR_MEM8(0x0A20) 3123 #define TCE2_HCNT _SFR_MEM8(0x0A21) 3124 #define TCE2_LPER _SFR_MEM8(0x0A26) 3125 #define TCE2_HPER _SFR_MEM8(0x0A27) 3126 #define TCE2_LCMPA _SFR_MEM8(0x0A28) 3127 #define TCE2_HCMPA _SFR_MEM8(0x0A29) 3128 #define TCE2_LCMPB _SFR_MEM8(0x0A2A) 3129 #define TCE2_HCMPB _SFR_MEM8(0x0A2B) 3130 #define TCE2_LCMPC _SFR_MEM8(0x0A2C) 3131 #define TCE2_HCMPC _SFR_MEM8(0x0A2D) 3132 #define TCE2_LCMPD _SFR_MEM8(0x0A2E) 3133 #define TCE2_HCMPD _SFR_MEM8(0x0A2F) 3134 3135 /* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ 3136 #define USARTE0_DATA _SFR_MEM8(0x0AA0) 3137 #define USARTE0_STATUS _SFR_MEM8(0x0AA1) 3138 #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) 3139 #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) 3140 #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) 3141 #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) 3142 #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) 3143 3144 /* TC0 - 16-bit Timer/Counter 0 */ 3145 #define TCF0_CTRLA _SFR_MEM8(0x0B00) 3146 #define TCF0_CTRLB _SFR_MEM8(0x0B01) 3147 #define TCF0_CTRLC _SFR_MEM8(0x0B02) 3148 #define TCF0_CTRLD _SFR_MEM8(0x0B03) 3149 #define TCF0_CTRLE _SFR_MEM8(0x0B04) 3150 #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) 3151 #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) 3152 #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) 3153 #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) 3154 #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) 3155 #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) 3156 #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) 3157 #define TCF0_TEMP _SFR_MEM8(0x0B0F) 3158 #define TCF0_CNT _SFR_MEM16(0x0B20) 3159 #define TCF0_PER _SFR_MEM16(0x0B26) 3160 #define TCF0_CCA _SFR_MEM16(0x0B28) 3161 #define TCF0_CCB _SFR_MEM16(0x0B2A) 3162 #define TCF0_CCC _SFR_MEM16(0x0B2C) 3163 #define TCF0_CCD _SFR_MEM16(0x0B2E) 3164 #define TCF0_PERBUF _SFR_MEM16(0x0B36) 3165 #define TCF0_CCABUF _SFR_MEM16(0x0B38) 3166 #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) 3167 #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) 3168 #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) 3169 3170 /* TC2 - 16-bit Timer/Counter type 2 */ 3171 #define TCF2_CTRLA _SFR_MEM8(0x0B00) 3172 #define TCF2_CTRLB _SFR_MEM8(0x0B01) 3173 #define TCF2_CTRLC _SFR_MEM8(0x0B02) 3174 #define TCF2_CTRLE _SFR_MEM8(0x0B04) 3175 #define TCF2_INTCTRLA _SFR_MEM8(0x0B06) 3176 #define TCF2_INTCTRLB _SFR_MEM8(0x0B07) 3177 #define TCF2_CTRLF _SFR_MEM8(0x0B09) 3178 #define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) 3179 #define TCF2_LCNT _SFR_MEM8(0x0B20) 3180 #define TCF2_HCNT _SFR_MEM8(0x0B21) 3181 #define TCF2_LPER _SFR_MEM8(0x0B26) 3182 #define TCF2_HPER _SFR_MEM8(0x0B27) 3183 #define TCF2_LCMPA _SFR_MEM8(0x0B28) 3184 #define TCF2_HCMPA _SFR_MEM8(0x0B29) 3185 #define TCF2_LCMPB _SFR_MEM8(0x0B2A) 3186 #define TCF2_HCMPB _SFR_MEM8(0x0B2B) 3187 #define TCF2_LCMPC _SFR_MEM8(0x0B2C) 3188 #define TCF2_HCMPC _SFR_MEM8(0x0B2D) 3189 #define TCF2_LCMPD _SFR_MEM8(0x0B2E) 3190 #define TCF2_HCMPD _SFR_MEM8(0x0B2F) 3191 3192 3193 3194 /*================== Bitfield Definitions ================== */ 3195 3196 /* VPORT - Virtual Ports */ 3197 /* VPORT.INTFLAGS bit masks and bit positions */ 3198 #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ 3199 #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ 3200 3201 #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ 3202 #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ 3203 3204 /* XOCD - On-Chip Debug System */ 3205 /* OCD.OCDR0 bit masks and bit positions */ 3206 #define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ 3207 #define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ 3208 #define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ 3209 #define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ 3210 #define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ 3211 #define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ 3212 #define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ 3213 #define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ 3214 #define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ 3215 #define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ 3216 #define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ 3217 #define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ 3218 #define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ 3219 #define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ 3220 #define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ 3221 #define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ 3222 #define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ 3223 #define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ 3224 3225 /* OCD.OCDR1 bit masks and bit positions */ 3226 /* OCD_OCDRD Predefined. */ 3227 /* OCD_OCDRD Predefined. */ 3228 3229 /* CPU - CPU */ 3230 /* CPU.CCP bit masks and bit positions */ 3231 #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ 3232 #define CPU_CCP_gp 0 /* CCP signature group position. */ 3233 #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ 3234 #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ 3235 #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ 3236 #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ 3237 #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ 3238 #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ 3239 #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ 3240 #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ 3241 #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ 3242 #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ 3243 #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ 3244 #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ 3245 #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ 3246 #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ 3247 #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ 3248 #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ 3249 3250 /* CPU.SREG bit masks and bit positions */ 3251 #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ 3252 #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ 3253 3254 #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ 3255 #define CPU_T_bp 6 /* Transfer Bit bit position. */ 3256 3257 #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ 3258 #define CPU_H_bp 5 /* Half Carry Flag bit position. */ 3259 3260 #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ 3261 #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ 3262 3263 #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ 3264 #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ 3265 3266 #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ 3267 #define CPU_N_bp 2 /* Negative Flag bit position. */ 3268 3269 #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ 3270 #define CPU_Z_bp 1 /* Zero Flag bit position. */ 3271 3272 #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ 3273 #define CPU_C_bp 0 /* Carry Flag bit position. */ 3274 3275 /* CLK - Clock System */ 3276 /* CLK.CTRL bit masks and bit positions */ 3277 #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ 3278 #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ 3279 #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ 3280 #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ 3281 #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ 3282 #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ 3283 #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ 3284 #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ 3285 3286 /* CLK.PSCTRL bit masks and bit positions */ 3287 #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ 3288 #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ 3289 #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ 3290 #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ 3291 #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ 3292 #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ 3293 #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ 3294 #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ 3295 #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ 3296 #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ 3297 #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ 3298 #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ 3299 3300 #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ 3301 #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ 3302 #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ 3303 #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ 3304 #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ 3305 #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ 3306 3307 /* CLK.LOCK bit masks and bit positions */ 3308 #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ 3309 #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ 3310 3311 /* CLK.RTCCTRL bit masks and bit positions */ 3312 #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ 3313 #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ 3314 #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ 3315 #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ 3316 #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ 3317 #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ 3318 #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ 3319 #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ 3320 3321 #define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ 3322 #define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ 3323 3324 /* CLK.USBCTRL bit masks and bit positions */ 3325 #define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ 3326 #define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ 3327 #define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ 3328 #define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ 3329 #define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ 3330 #define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ 3331 #define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ 3332 #define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ 3333 3334 #define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ 3335 #define CLK_USBSRC_gp 1 /* Clock Source group position. */ 3336 #define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ 3337 #define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ 3338 #define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ 3339 #define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ 3340 3341 #define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ 3342 #define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ 3343 3344 /* PR.PRGEN bit masks and bit positions */ 3345 #define PR_USB_bm 0x40 /* USB bit mask. */ 3346 #define PR_USB_bp 6 /* USB bit position. */ 3347 3348 #define PR_AES_bm 0x10 /* AES bit mask. */ 3349 #define PR_AES_bp 4 /* AES bit position. */ 3350 3351 #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ 3352 #define PR_RTC_bp 2 /* Real-time Counter bit position. */ 3353 3354 #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ 3355 #define PR_EVSYS_bp 1 /* Event System bit position. */ 3356 3357 #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ 3358 #define PR_DMA_bp 0 /* DMA-Controller bit position. */ 3359 3360 /* PR.PRPA bit masks and bit positions */ 3361 #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ 3362 #define PR_ADC_bp 1 /* Port A ADC bit position. */ 3363 3364 #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ 3365 #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ 3366 3367 /* PR.PRPC bit masks and bit positions */ 3368 #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ 3369 #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ 3370 3371 #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ 3372 #define PR_USART1_bp 5 /* Port C USART1 bit position. */ 3373 3374 #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ 3375 #define PR_USART0_bp 4 /* Port C USART0 bit position. */ 3376 3377 #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ 3378 #define PR_SPI_bp 3 /* Port C SPI bit position. */ 3379 3380 #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ 3381 #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ 3382 3383 #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ 3384 #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ 3385 3386 #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ 3387 #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ 3388 3389 /* PR.PRPD bit masks and bit positions */ 3390 /* PR_USART0 Predefined. */ 3391 /* PR_USART0 Predefined. */ 3392 3393 /* PR_SPI Predefined. */ 3394 /* PR_SPI Predefined. */ 3395 3396 /* PR_TC0 Predefined. */ 3397 /* PR_TC0 Predefined. */ 3398 3399 /* PR.PRPE bit masks and bit positions */ 3400 /* PR_TWI Predefined. */ 3401 /* PR_TWI Predefined. */ 3402 3403 /* PR_USART0 Predefined. */ 3404 /* PR_USART0 Predefined. */ 3405 3406 /* PR_TC0 Predefined. */ 3407 /* PR_TC0 Predefined. */ 3408 3409 /* PR.PRPF bit masks and bit positions */ 3410 /* PR_USART0 Predefined. */ 3411 /* PR_USART0 Predefined. */ 3412 3413 /* PR_TC0 Predefined. */ 3414 /* PR_TC0 Predefined. */ 3415 3416 /* SLEEP - Sleep Controller */ 3417 /* SLEEP.CTRL bit masks and bit positions */ 3418 #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ 3419 #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ 3420 #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ 3421 #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ 3422 #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ 3423 #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ 3424 #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ 3425 #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ 3426 3427 #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ 3428 #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ 3429 3430 /* OSC - Oscillator */ 3431 /* OSC.CTRL bit masks and bit positions */ 3432 #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ 3433 #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ 3434 3435 #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ 3436 #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ 3437 3438 #define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ 3439 #define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ 3440 3441 #define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ 3442 #define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ 3443 3444 #define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ 3445 #define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ 3446 3447 /* OSC.STATUS bit masks and bit positions */ 3448 #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ 3449 #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ 3450 3451 #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ 3452 #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ 3453 3454 #define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ 3455 #define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ 3456 3457 #define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ 3458 #define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ 3459 3460 #define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ 3461 #define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ 3462 3463 /* OSC.XOSCCTRL bit masks and bit positions */ 3464 #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ 3465 #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ 3466 #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ 3467 #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ 3468 #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ 3469 #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ 3470 3471 #define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ 3472 #define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ 3473 3474 #define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ 3475 #define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ 3476 3477 #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ 3478 #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ 3479 #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ 3480 #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ 3481 #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ 3482 #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ 3483 #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ 3484 #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ 3485 #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ 3486 #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ 3487 3488 /* OSC.XOSCFAIL bit masks and bit positions */ 3489 #define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ 3490 #define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ 3491 3492 #define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ 3493 #define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ 3494 3495 #define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ 3496 #define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ 3497 3498 #define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ 3499 #define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ 3500 3501 /* OSC.PLLCTRL bit masks and bit positions */ 3502 #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ 3503 #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ 3504 #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ 3505 #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ 3506 #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ 3507 #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ 3508 3509 #define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ 3510 #define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ 3511 3512 #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ 3513 #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ 3514 #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ 3515 #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ 3516 #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ 3517 #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ 3518 #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ 3519 #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ 3520 #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ 3521 #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ 3522 #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ 3523 #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ 3524 3525 /* OSC.DFLLCTRL bit masks and bit positions */ 3526 #define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ 3527 #define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ 3528 #define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ 3529 #define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ 3530 #define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ 3531 #define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ 3532 3533 #define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ 3534 #define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ 3535 3536 /* DFLL - DFLL */ 3537 /* DFLL.CTRL bit masks and bit positions */ 3538 #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ 3539 #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ 3540 3541 /* DFLL.CALA bit masks and bit positions */ 3542 #define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ 3543 #define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ 3544 #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ 3545 #define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ 3546 #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ 3547 #define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ 3548 #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ 3549 #define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ 3550 #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ 3551 #define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ 3552 #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ 3553 #define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ 3554 #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ 3555 #define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ 3556 #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ 3557 #define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ 3558 3559 /* DFLL.CALB bit masks and bit positions */ 3560 #define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ 3561 #define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ 3562 #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ 3563 #define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ 3564 #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ 3565 #define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ 3566 #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ 3567 #define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ 3568 #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ 3569 #define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ 3570 #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ 3571 #define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ 3572 #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ 3573 #define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ 3574 3575 /* RST - Reset */ 3576 /* RST.STATUS bit masks and bit positions */ 3577 #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ 3578 #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ 3579 3580 #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ 3581 #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ 3582 3583 #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ 3584 #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ 3585 3586 #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ 3587 #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ 3588 3589 #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ 3590 #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ 3591 3592 #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ 3593 #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ 3594 3595 #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ 3596 #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ 3597 3598 /* RST.CTRL bit masks and bit positions */ 3599 #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ 3600 #define RST_SWRST_bp 0 /* Software Reset bit position. */ 3601 3602 /* WDT - Watch-Dog Timer */ 3603 /* WDT.CTRL bit masks and bit positions */ 3604 #define WDT_PER_gm 0x3C /* Period group mask. */ 3605 #define WDT_PER_gp 2 /* Period group position. */ 3606 #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ 3607 #define WDT_PER0_bp 2 /* Period bit 0 position. */ 3608 #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ 3609 #define WDT_PER1_bp 3 /* Period bit 1 position. */ 3610 #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ 3611 #define WDT_PER2_bp 4 /* Period bit 2 position. */ 3612 #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ 3613 #define WDT_PER3_bp 5 /* Period bit 3 position. */ 3614 3615 #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ 3616 #define WDT_ENABLE_bp 1 /* Enable bit position. */ 3617 3618 #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ 3619 #define WDT_CEN_bp 0 /* Change Enable bit position. */ 3620 3621 /* WDT.WINCTRL bit masks and bit positions */ 3622 #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ 3623 #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ 3624 #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ 3625 #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ 3626 #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ 3627 #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ 3628 #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ 3629 #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ 3630 #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ 3631 #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ 3632 3633 #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ 3634 #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ 3635 3636 #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ 3637 #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ 3638 3639 /* WDT.STATUS bit masks and bit positions */ 3640 #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ 3641 #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ 3642 3643 /* MCU - MCU Control */ 3644 /* MCU.ANAINIT bit masks and bit positions */ 3645 #define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ 3646 #define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ 3647 #define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ 3648 #define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ 3649 #define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ 3650 #define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ 3651 3652 /* MCU.EVSYSLOCK bit masks and bit positions */ 3653 #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ 3654 #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ 3655 3656 /* MCU.AWEXLOCK bit masks and bit positions */ 3657 #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ 3658 #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ 3659 3660 /* PMIC - Programmable Multi-level Interrupt Controller */ 3661 /* PMIC.STATUS bit masks and bit positions */ 3662 #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ 3663 #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ 3664 3665 #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ 3666 #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ 3667 3668 #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ 3669 #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ 3670 3671 #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ 3672 #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ 3673 3674 /* PMIC.INTPRI bit masks and bit positions */ 3675 #define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ 3676 #define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ 3677 #define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ 3678 #define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ 3679 #define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ 3680 #define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ 3681 #define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ 3682 #define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ 3683 #define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ 3684 #define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ 3685 #define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ 3686 #define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ 3687 #define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ 3688 #define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ 3689 #define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ 3690 #define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ 3691 #define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ 3692 #define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ 3693 3694 /* PMIC.CTRL bit masks and bit positions */ 3695 #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ 3696 #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ 3697 3698 #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ 3699 #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ 3700 3701 #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ 3702 #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ 3703 3704 #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ 3705 #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ 3706 3707 #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ 3708 #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ 3709 3710 /* PORTCFG - Port Configuration */ 3711 /* PORTCFG.VPCTRLA bit masks and bit positions */ 3712 #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ 3713 #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ 3714 #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ 3715 #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ 3716 #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ 3717 #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ 3718 #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ 3719 #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ 3720 #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ 3721 #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ 3722 3723 #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ 3724 #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ 3725 #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ 3726 #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ 3727 #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ 3728 #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ 3729 #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ 3730 #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ 3731 #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ 3732 #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ 3733 3734 /* PORTCFG.VPCTRLB bit masks and bit positions */ 3735 #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ 3736 #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ 3737 #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ 3738 #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ 3739 #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ 3740 #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ 3741 #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ 3742 #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ 3743 #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ 3744 #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ 3745 3746 #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ 3747 #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ 3748 #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ 3749 #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ 3750 #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ 3751 #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ 3752 #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ 3753 #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ 3754 #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ 3755 #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ 3756 3757 /* PORTCFG.CLKEVOUT bit masks and bit positions */ 3758 #define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ 3759 #define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ 3760 #define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ 3761 #define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ 3762 #define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ 3763 #define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ 3764 3765 #define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ 3766 #define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ 3767 #define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ 3768 #define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ 3769 #define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ 3770 #define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ 3771 3772 #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ 3773 #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ 3774 #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ 3775 #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ 3776 #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ 3777 #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ 3778 3779 #define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ 3780 #define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ 3781 3782 #define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ 3783 #define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ 3784 3785 /* PORTCFG.EVOUTSEL bit masks and bit positions */ 3786 #define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ 3787 #define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ 3788 #define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ 3789 #define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ 3790 #define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ 3791 #define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ 3792 #define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ 3793 #define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ 3794 3795 /* CRC - Cyclic Redundancy Checker */ 3796 /* CRC.CTRL bit masks and bit positions */ 3797 #define CRC_RESET_gm 0xC0 /* Reset group mask. */ 3798 #define CRC_RESET_gp 6 /* Reset group position. */ 3799 #define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ 3800 #define CRC_RESET0_bp 6 /* Reset bit 0 position. */ 3801 #define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ 3802 #define CRC_RESET1_bp 7 /* Reset bit 1 position. */ 3803 3804 #define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ 3805 #define CRC_CRC32_bp 5 /* CRC Mode bit position. */ 3806 3807 #define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ 3808 #define CRC_SOURCE_gp 0 /* Input Source group position. */ 3809 #define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ 3810 #define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ 3811 #define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ 3812 #define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ 3813 #define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ 3814 #define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ 3815 #define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ 3816 #define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ 3817 3818 /* CRC.STATUS bit masks and bit positions */ 3819 #define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ 3820 #define CRC_ZERO_bp 1 /* Zero detection bit position. */ 3821 3822 #define CRC_BUSY_bm 0x01 /* Busy bit mask. */ 3823 #define CRC_BUSY_bp 0 /* Busy bit position. */ 3824 3825 /* EVSYS - Event System */ 3826 /* EVSYS.CH0MUX bit masks and bit positions */ 3827 #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ 3828 #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ 3829 #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ 3830 #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ 3831 #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ 3832 #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ 3833 #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ 3834 #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ 3835 #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ 3836 #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ 3837 #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ 3838 #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ 3839 #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ 3840 #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ 3841 #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ 3842 #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ 3843 #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ 3844 #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ 3845 3846 /* EVSYS.CH1MUX bit masks and bit positions */ 3847 /* EVSYS_CHMUX Predefined. */ 3848 /* EVSYS_CHMUX Predefined. */ 3849 3850 /* EVSYS.CH2MUX bit masks and bit positions */ 3851 /* EVSYS_CHMUX Predefined. */ 3852 /* EVSYS_CHMUX Predefined. */ 3853 3854 /* EVSYS.CH3MUX bit masks and bit positions */ 3855 /* EVSYS_CHMUX Predefined. */ 3856 /* EVSYS_CHMUX Predefined. */ 3857 3858 /* EVSYS.CH0CTRL bit masks and bit positions */ 3859 #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ 3860 #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ 3861 #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ 3862 #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ 3863 #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ 3864 #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ 3865 3866 #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ 3867 #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ 3868 3869 #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ 3870 #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ 3871 3872 #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ 3873 #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ 3874 #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ 3875 #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ 3876 #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ 3877 #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ 3878 #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ 3879 #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ 3880 3881 /* EVSYS.CH1CTRL bit masks and bit positions */ 3882 /* EVSYS_DIGFILT Predefined. */ 3883 /* EVSYS_DIGFILT Predefined. */ 3884 3885 /* EVSYS.CH2CTRL bit masks and bit positions */ 3886 /* EVSYS_DIGFILT Predefined. */ 3887 /* EVSYS_DIGFILT Predefined. */ 3888 3889 /* EVSYS.CH3CTRL bit masks and bit positions */ 3890 /* EVSYS_DIGFILT Predefined. */ 3891 /* EVSYS_DIGFILT Predefined. */ 3892 3893 /* NVM - Non Volatile Memory Controller */ 3894 /* NVM.CMD bit masks and bit positions */ 3895 #define NVM_CMD_gm 0x7F /* Command group mask. */ 3896 #define NVM_CMD_gp 0 /* Command group position. */ 3897 #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ 3898 #define NVM_CMD0_bp 0 /* Command bit 0 position. */ 3899 #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ 3900 #define NVM_CMD1_bp 1 /* Command bit 1 position. */ 3901 #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ 3902 #define NVM_CMD2_bp 2 /* Command bit 2 position. */ 3903 #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ 3904 #define NVM_CMD3_bp 3 /* Command bit 3 position. */ 3905 #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ 3906 #define NVM_CMD4_bp 4 /* Command bit 4 position. */ 3907 #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ 3908 #define NVM_CMD5_bp 5 /* Command bit 5 position. */ 3909 #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ 3910 #define NVM_CMD6_bp 6 /* Command bit 6 position. */ 3911 3912 /* NVM.CTRLA bit masks and bit positions */ 3913 #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ 3914 #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ 3915 3916 /* NVM.CTRLB bit masks and bit positions */ 3917 #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ 3918 #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ 3919 3920 #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ 3921 #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ 3922 3923 #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ 3924 #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ 3925 3926 #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ 3927 #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ 3928 3929 /* NVM.INTCTRL bit masks and bit positions */ 3930 #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ 3931 #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ 3932 #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ 3933 #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ 3934 #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ 3935 #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ 3936 3937 #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ 3938 #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ 3939 #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ 3940 #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ 3941 #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ 3942 #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ 3943 3944 /* NVM.STATUS bit masks and bit positions */ 3945 #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ 3946 #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ 3947 3948 #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ 3949 #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ 3950 3951 #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ 3952 #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ 3953 3954 #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ 3955 #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ 3956 3957 /* NVM.LOCKBITS bit masks and bit positions */ 3958 #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ 3959 #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ 3960 #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ 3961 #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ 3962 #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ 3963 #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ 3964 3965 #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ 3966 #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ 3967 #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ 3968 #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ 3969 #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ 3970 #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ 3971 3972 #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ 3973 #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ 3974 #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ 3975 #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ 3976 #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ 3977 #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ 3978 3979 #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ 3980 #define NVM_LB_gp 0 /* Lock Bits group position. */ 3981 #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ 3982 #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ 3983 #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ 3984 #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ 3985 3986 /* ADC - Analog/Digital Converter */ 3987 /* ADC_CH.CTRL bit masks and bit positions */ 3988 #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ 3989 #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ 3990 3991 #define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ 3992 #define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ 3993 #define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ 3994 #define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ 3995 #define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ 3996 #define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ 3997 #define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ 3998 #define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ 3999 4000 #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ 4001 #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ 4002 #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ 4003 #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ 4004 #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ 4005 #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ 4006 4007 /* ADC_CH.MUXCTRL bit masks and bit positions */ 4008 #define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ 4009 #define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ 4010 #define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ 4011 #define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ 4012 #define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ 4013 #define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ 4014 #define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ 4015 #define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ 4016 #define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ 4017 #define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ 4018 4019 #define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ 4020 #define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ 4021 #define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ 4022 #define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ 4023 #define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ 4024 #define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ 4025 #define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ 4026 #define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ 4027 #define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ 4028 #define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ 4029 4030 #define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ 4031 #define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ 4032 #define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ 4033 #define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ 4034 #define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ 4035 #define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ 4036 4037 /* ADC_CH.INTCTRL bit masks and bit positions */ 4038 #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ 4039 #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ 4040 #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ 4041 #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ 4042 #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ 4043 #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ 4044 4045 #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ 4046 #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ 4047 #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ 4048 #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ 4049 #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ 4050 #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ 4051 4052 /* ADC_CH.INTFLAGS bit masks and bit positions */ 4053 #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ 4054 #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ 4055 4056 /* ADC_CH.SCAN bit masks and bit positions */ 4057 #define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ 4058 #define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ 4059 #define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ 4060 #define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ 4061 #define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ 4062 #define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ 4063 #define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ 4064 #define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ 4065 #define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ 4066 #define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ 4067 4068 #define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ 4069 #define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ 4070 #define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ 4071 #define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ 4072 #define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ 4073 #define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ 4074 #define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ 4075 #define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ 4076 #define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ 4077 #define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ 4078 4079 /* ADC.CTRLA bit masks and bit positions */ 4080 #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ 4081 #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ 4082 4083 #define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ 4084 #define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ 4085 4086 #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ 4087 #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ 4088 4089 /* ADC.CTRLB bit masks and bit positions */ 4090 #define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ 4091 #define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ 4092 #define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ 4093 #define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ 4094 #define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ 4095 #define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ 4096 4097 #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ 4098 #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ 4099 4100 #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ 4101 #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ 4102 4103 #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ 4104 #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ 4105 #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ 4106 #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ 4107 #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ 4108 #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ 4109 4110 /* ADC.REFCTRL bit masks and bit positions */ 4111 #define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ 4112 #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ 4113 #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ 4114 #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ 4115 #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ 4116 #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ 4117 #define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ 4118 #define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ 4119 4120 #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ 4121 #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ 4122 4123 #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ 4124 #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ 4125 4126 /* ADC.EVCTRL bit masks and bit positions */ 4127 #define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ 4128 #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ 4129 #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ 4130 #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ 4131 #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ 4132 #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ 4133 4134 #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ 4135 #define ADC_EVACT_gp 0 /* Event Action Select group position. */ 4136 #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ 4137 #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ 4138 #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ 4139 #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ 4140 #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ 4141 #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ 4142 4143 /* ADC.PRESCALER bit masks and bit positions */ 4144 #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ 4145 #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ 4146 #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ 4147 #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ 4148 #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ 4149 #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ 4150 #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ 4151 #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ 4152 4153 /* ADC.INTFLAGS bit masks and bit positions */ 4154 #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ 4155 #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ 4156 4157 /* AC - Analog Comparator */ 4158 /* AC.AC0CTRL bit masks and bit positions */ 4159 #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ 4160 #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ 4161 #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ 4162 #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ 4163 #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ 4164 #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ 4165 4166 #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ 4167 #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ 4168 #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ 4169 #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ 4170 #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ 4171 #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ 4172 4173 #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ 4174 #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ 4175 #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ 4176 #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ 4177 #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ 4178 #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ 4179 4180 #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ 4181 #define AC_ENABLE_bp 0 /* Enable bit position. */ 4182 4183 /* AC.AC1CTRL bit masks and bit positions */ 4184 /* AC_INTMODE Predefined. */ 4185 /* AC_INTMODE Predefined. */ 4186 4187 /* AC_INTLVL Predefined. */ 4188 /* AC_INTLVL Predefined. */ 4189 4190 /* AC_HYSMODE Predefined. */ 4191 /* AC_HYSMODE Predefined. */ 4192 4193 /* AC_ENABLE Predefined. */ 4194 /* AC_ENABLE Predefined. */ 4195 4196 /* AC.AC0MUXCTRL bit masks and bit positions */ 4197 #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ 4198 #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ 4199 #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ 4200 #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ 4201 #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ 4202 #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ 4203 #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ 4204 #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ 4205 4206 #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ 4207 #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ 4208 #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ 4209 #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ 4210 #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ 4211 #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ 4212 #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ 4213 #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ 4214 4215 /* AC.AC1MUXCTRL bit masks and bit positions */ 4216 /* AC_MUXPOS Predefined. */ 4217 /* AC_MUXPOS Predefined. */ 4218 4219 /* AC_MUXNEG Predefined. */ 4220 /* AC_MUXNEG Predefined. */ 4221 4222 /* AC.CTRLA bit masks and bit positions */ 4223 #define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ 4224 #define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ 4225 4226 #define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ 4227 #define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ 4228 4229 /* AC.CTRLB bit masks and bit positions */ 4230 #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ 4231 #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ 4232 #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ 4233 #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ 4234 #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ 4235 #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ 4236 #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ 4237 #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ 4238 #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ 4239 #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ 4240 #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ 4241 #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ 4242 #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ 4243 #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ 4244 4245 /* AC.WINCTRL bit masks and bit positions */ 4246 #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ 4247 #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ 4248 4249 #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ 4250 #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ 4251 #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ 4252 #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ 4253 #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ 4254 #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ 4255 4256 #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ 4257 #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ 4258 #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ 4259 #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ 4260 #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ 4261 #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ 4262 4263 /* AC.STATUS bit masks and bit positions */ 4264 #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ 4265 #define AC_WSTATE_gp 6 /* Window Mode State group position. */ 4266 #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ 4267 #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ 4268 #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ 4269 #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ 4270 4271 #define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ 4272 #define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ 4273 4274 #define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ 4275 #define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ 4276 4277 #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ 4278 #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ 4279 4280 #define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ 4281 #define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ 4282 4283 #define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ 4284 #define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ 4285 4286 /* RTC - Real-Time Counter */ 4287 /* RTC.CTRL bit masks and bit positions */ 4288 #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ 4289 #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ 4290 #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ 4291 #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ 4292 #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ 4293 #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ 4294 #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ 4295 #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ 4296 4297 /* RTC.STATUS bit masks and bit positions */ 4298 #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ 4299 #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ 4300 4301 /* RTC.INTCTRL bit masks and bit positions */ 4302 #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ 4303 #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ 4304 #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ 4305 #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ 4306 #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ 4307 #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ 4308 4309 #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ 4310 #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ 4311 #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ 4312 #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ 4313 #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ 4314 #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ 4315 4316 /* RTC.INTFLAGS bit masks and bit positions */ 4317 #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ 4318 #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ 4319 4320 #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 4321 #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 4322 4323 /* TWI - Two-Wire Interface */ 4324 /* TWI_MASTER.CTRLA bit masks and bit positions */ 4325 #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ 4326 #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ 4327 #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ 4328 #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ 4329 #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ 4330 #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ 4331 4332 #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ 4333 #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ 4334 4335 #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ 4336 #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ 4337 4338 #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ 4339 #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ 4340 4341 /* TWI_MASTER.CTRLB bit masks and bit positions */ 4342 #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ 4343 #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ 4344 #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ 4345 #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ 4346 #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ 4347 #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ 4348 4349 #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ 4350 #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ 4351 4352 #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ 4353 #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ 4354 4355 /* TWI_MASTER.CTRLC bit masks and bit positions */ 4356 #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ 4357 #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ 4358 4359 #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ 4360 #define TWI_MASTER_CMD_gp 0 /* Command group position. */ 4361 #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ 4362 #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ 4363 #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ 4364 #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ 4365 4366 /* TWI_MASTER.STATUS bit masks and bit positions */ 4367 #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ 4368 #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ 4369 4370 #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ 4371 #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ 4372 4373 #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ 4374 #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ 4375 4376 #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ 4377 #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ 4378 4379 #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ 4380 #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ 4381 4382 #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ 4383 #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ 4384 4385 #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ 4386 #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ 4387 #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ 4388 #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ 4389 #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ 4390 #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ 4391 4392 /* TWI_SLAVE.CTRLA bit masks and bit positions */ 4393 #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ 4394 #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ 4395 #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ 4396 #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ 4397 #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ 4398 #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ 4399 4400 #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ 4401 #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ 4402 4403 #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ 4404 #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ 4405 4406 #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ 4407 #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ 4408 4409 #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ 4410 #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ 4411 4412 #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ 4413 #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ 4414 4415 #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ 4416 #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ 4417 4418 /* TWI_SLAVE.CTRLB bit masks and bit positions */ 4419 #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ 4420 #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ 4421 4422 #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ 4423 #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ 4424 #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ 4425 #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ 4426 #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ 4427 #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ 4428 4429 /* TWI_SLAVE.STATUS bit masks and bit positions */ 4430 #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ 4431 #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ 4432 4433 #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ 4434 #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ 4435 4436 #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ 4437 #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ 4438 4439 #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ 4440 #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ 4441 4442 #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ 4443 #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ 4444 4445 #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ 4446 #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ 4447 4448 #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ 4449 #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ 4450 4451 #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ 4452 #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ 4453 4454 /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ 4455 #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ 4456 #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ 4457 #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ 4458 #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ 4459 #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ 4460 #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ 4461 #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ 4462 #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ 4463 #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ 4464 #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ 4465 #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ 4466 #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ 4467 #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ 4468 #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ 4469 #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ 4470 #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ 4471 4472 #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ 4473 #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ 4474 4475 /* TWI.CTRL bit masks and bit positions */ 4476 #define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ 4477 #define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ 4478 #define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ 4479 #define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ 4480 #define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ 4481 #define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ 4482 4483 #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ 4484 #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ 4485 4486 /* USB - USB */ 4487 /* USB_EP.STATUS bit masks and bit positions */ 4488 #define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ 4489 #define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ 4490 4491 #define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ 4492 #define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ 4493 4494 #define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ 4495 #define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ 4496 4497 #define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ 4498 #define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ 4499 4500 #define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ 4501 #define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ 4502 4503 #define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ 4504 #define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ 4505 4506 #define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ 4507 #define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ 4508 4509 #define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ 4510 #define USB_EP_BANK_bp 3 /* Bank Select bit position. */ 4511 4512 #define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ 4513 #define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ 4514 4515 #define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ 4516 #define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ 4517 4518 #define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ 4519 #define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ 4520 4521 /* USB_EP.CTRL bit masks and bit positions */ 4522 #define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ 4523 #define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ 4524 #define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ 4525 #define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ 4526 #define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ 4527 #define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ 4528 4529 #define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ 4530 #define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ 4531 4532 #define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ 4533 #define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ 4534 4535 #define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ 4536 #define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ 4537 4538 #define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ 4539 #define USB_EP_STALL_bp 2 /* Data Stall bit position. */ 4540 4541 #define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ 4542 #define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ 4543 #define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ 4544 #define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ 4545 #define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ 4546 #define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ 4547 #define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ 4548 #define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ 4549 4550 /* USB_EP.CNT bit masks and bit positions */ 4551 #define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ 4552 #define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ 4553 4554 /* USB.CTRLA bit masks and bit positions */ 4555 #define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ 4556 #define USB_ENABLE_bp 7 /* USB Enable bit position. */ 4557 4558 #define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ 4559 #define USB_SPEED_bp 6 /* Speed Select bit position. */ 4560 4561 #define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ 4562 #define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ 4563 4564 #define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ 4565 #define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ 4566 4567 #define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ 4568 #define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ 4569 #define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ 4570 #define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ 4571 #define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ 4572 #define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ 4573 #define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ 4574 #define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ 4575 #define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ 4576 #define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ 4577 4578 /* USB.CTRLB bit masks and bit positions */ 4579 #define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ 4580 #define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ 4581 4582 #define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ 4583 #define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ 4584 4585 #define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ 4586 #define USB_GNACK_bp 1 /* Global NACK bit position. */ 4587 4588 #define USB_ATTACH_bm 0x01 /* Attach bit mask. */ 4589 #define USB_ATTACH_bp 0 /* Attach bit position. */ 4590 4591 /* USB.STATUS bit masks and bit positions */ 4592 #define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ 4593 #define USB_URESUME_bp 3 /* Upstream Resume bit position. */ 4594 4595 #define USB_RESUME_bm 0x04 /* Resume bit mask. */ 4596 #define USB_RESUME_bp 2 /* Resume bit position. */ 4597 4598 #define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ 4599 #define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ 4600 4601 #define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ 4602 #define USB_BUSRST_bp 0 /* Bus Reset bit position. */ 4603 4604 /* USB.ADDR bit masks and bit positions */ 4605 #define USB_ADDR_gm 0x7F /* Device Address group mask. */ 4606 #define USB_ADDR_gp 0 /* Device Address group position. */ 4607 #define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ 4608 #define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ 4609 #define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ 4610 #define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ 4611 #define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ 4612 #define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ 4613 #define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ 4614 #define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ 4615 #define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ 4616 #define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ 4617 #define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ 4618 #define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ 4619 #define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ 4620 #define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ 4621 4622 /* USB.FIFOWP bit masks and bit positions */ 4623 #define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ 4624 #define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ 4625 #define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ 4626 #define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ 4627 #define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ 4628 #define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ 4629 #define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ 4630 #define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ 4631 #define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ 4632 #define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ 4633 #define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ 4634 #define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ 4635 4636 /* USB.FIFORP bit masks and bit positions */ 4637 #define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ 4638 #define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ 4639 #define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ 4640 #define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ 4641 #define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ 4642 #define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ 4643 #define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ 4644 #define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ 4645 #define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ 4646 #define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ 4647 #define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ 4648 #define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ 4649 4650 /* USB.INTCTRLA bit masks and bit positions */ 4651 #define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ 4652 #define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ 4653 4654 #define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ 4655 #define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ 4656 4657 #define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ 4658 #define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ 4659 4660 #define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ 4661 #define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ 4662 4663 #define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ 4664 #define USB_INTLVL_gp 0 /* Interrupt Level group position. */ 4665 #define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ 4666 #define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ 4667 #define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ 4668 #define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ 4669 4670 /* USB.INTCTRLB bit masks and bit positions */ 4671 #define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ 4672 #define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ 4673 4674 #define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ 4675 #define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ 4676 4677 /* USB.INTFLAGSACLR bit masks and bit positions */ 4678 #define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ 4679 #define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ 4680 4681 #define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ 4682 #define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ 4683 4684 #define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ 4685 #define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ 4686 4687 #define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ 4688 #define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ 4689 4690 #define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ 4691 #define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ 4692 4693 #define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ 4694 #define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ 4695 4696 #define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ 4697 #define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ 4698 4699 #define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ 4700 #define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ 4701 4702 /* USB.INTFLAGSASET bit masks and bit positions */ 4703 /* USB_SOFIF Predefined. */ 4704 /* USB_SOFIF Predefined. */ 4705 4706 /* USB_SUSPENDIF Predefined. */ 4707 /* USB_SUSPENDIF Predefined. */ 4708 4709 /* USB_RESUMEIF Predefined. */ 4710 /* USB_RESUMEIF Predefined. */ 4711 4712 /* USB_RSTIF Predefined. */ 4713 /* USB_RSTIF Predefined. */ 4714 4715 /* USB_CRCIF Predefined. */ 4716 /* USB_CRCIF Predefined. */ 4717 4718 /* USB_UNFIF Predefined. */ 4719 /* USB_UNFIF Predefined. */ 4720 4721 /* USB_OVFIF Predefined. */ 4722 /* USB_OVFIF Predefined. */ 4723 4724 /* USB_STALLIF Predefined. */ 4725 /* USB_STALLIF Predefined. */ 4726 4727 /* USB.INTFLAGSBCLR bit masks and bit positions */ 4728 #define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ 4729 #define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ 4730 4731 #define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ 4732 #define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ 4733 4734 /* USB.INTFLAGSBSET bit masks and bit positions */ 4735 /* USB_TRNIF Predefined. */ 4736 /* USB_TRNIF Predefined. */ 4737 4738 /* USB_SETUPIF Predefined. */ 4739 /* USB_SETUPIF Predefined. */ 4740 4741 /* PORT - I/O Port Configuration */ 4742 /* PORT.INTCTRL bit masks and bit positions */ 4743 #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ 4744 #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ 4745 #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ 4746 #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ 4747 #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ 4748 #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ 4749 4750 #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ 4751 #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ 4752 #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ 4753 #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ 4754 #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ 4755 #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ 4756 4757 /* PORT.INTFLAGS bit masks and bit positions */ 4758 #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ 4759 #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ 4760 4761 #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ 4762 #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ 4763 4764 /* PORT.REMAP bit masks and bit positions */ 4765 #define PORT_SPI_bm 0x20 /* SPI bit mask. */ 4766 #define PORT_SPI_bp 5 /* SPI bit position. */ 4767 4768 #define PORT_USART0_bm 0x10 /* USART0 bit mask. */ 4769 #define PORT_USART0_bp 4 /* USART0 bit position. */ 4770 4771 #define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ 4772 #define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ 4773 4774 #define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ 4775 #define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ 4776 4777 #define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ 4778 #define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ 4779 4780 #define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ 4781 #define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ 4782 4783 /* PORT.PIN0CTRL bit masks and bit positions */ 4784 #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ 4785 #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ 4786 4787 #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ 4788 #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ 4789 4790 #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ 4791 #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ 4792 #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ 4793 #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ 4794 #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ 4795 #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ 4796 #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ 4797 #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ 4798 4799 #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ 4800 #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ 4801 #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ 4802 #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ 4803 #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ 4804 #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ 4805 #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ 4806 #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ 4807 4808 /* PORT.PIN1CTRL bit masks and bit positions */ 4809 /* PORT_SRLEN Predefined. */ 4810 /* PORT_SRLEN Predefined. */ 4811 4812 /* PORT_INVEN Predefined. */ 4813 /* PORT_INVEN Predefined. */ 4814 4815 /* PORT_OPC Predefined. */ 4816 /* PORT_OPC Predefined. */ 4817 4818 /* PORT_ISC Predefined. */ 4819 /* PORT_ISC Predefined. */ 4820 4821 /* PORT.PIN2CTRL bit masks and bit positions */ 4822 /* PORT_SRLEN Predefined. */ 4823 /* PORT_SRLEN Predefined. */ 4824 4825 /* PORT_INVEN Predefined. */ 4826 /* PORT_INVEN Predefined. */ 4827 4828 /* PORT_OPC Predefined. */ 4829 /* PORT_OPC Predefined. */ 4830 4831 /* PORT_ISC Predefined. */ 4832 /* PORT_ISC Predefined. */ 4833 4834 /* PORT.PIN3CTRL bit masks and bit positions */ 4835 /* PORT_SRLEN Predefined. */ 4836 /* PORT_SRLEN Predefined. */ 4837 4838 /* PORT_INVEN Predefined. */ 4839 /* PORT_INVEN Predefined. */ 4840 4841 /* PORT_OPC Predefined. */ 4842 /* PORT_OPC Predefined. */ 4843 4844 /* PORT_ISC Predefined. */ 4845 /* PORT_ISC Predefined. */ 4846 4847 /* PORT.PIN4CTRL bit masks and bit positions */ 4848 /* PORT_SRLEN Predefined. */ 4849 /* PORT_SRLEN Predefined. */ 4850 4851 /* PORT_INVEN Predefined. */ 4852 /* PORT_INVEN Predefined. */ 4853 4854 /* PORT_OPC Predefined. */ 4855 /* PORT_OPC Predefined. */ 4856 4857 /* PORT_ISC Predefined. */ 4858 /* PORT_ISC Predefined. */ 4859 4860 /* PORT.PIN5CTRL bit masks and bit positions */ 4861 /* PORT_SRLEN Predefined. */ 4862 /* PORT_SRLEN Predefined. */ 4863 4864 /* PORT_INVEN Predefined. */ 4865 /* PORT_INVEN Predefined. */ 4866 4867 /* PORT_OPC Predefined. */ 4868 /* PORT_OPC Predefined. */ 4869 4870 /* PORT_ISC Predefined. */ 4871 /* PORT_ISC Predefined. */ 4872 4873 /* PORT.PIN6CTRL bit masks and bit positions */ 4874 /* PORT_SRLEN Predefined. */ 4875 /* PORT_SRLEN Predefined. */ 4876 4877 /* PORT_INVEN Predefined. */ 4878 /* PORT_INVEN Predefined. */ 4879 4880 /* PORT_OPC Predefined. */ 4881 /* PORT_OPC Predefined. */ 4882 4883 /* PORT_ISC Predefined. */ 4884 /* PORT_ISC Predefined. */ 4885 4886 /* PORT.PIN7CTRL bit masks and bit positions */ 4887 /* PORT_SRLEN Predefined. */ 4888 /* PORT_SRLEN Predefined. */ 4889 4890 /* PORT_INVEN Predefined. */ 4891 /* PORT_INVEN Predefined. */ 4892 4893 /* PORT_OPC Predefined. */ 4894 /* PORT_OPC Predefined. */ 4895 4896 /* PORT_ISC Predefined. */ 4897 /* PORT_ISC Predefined. */ 4898 4899 /* TC - 16-bit Timer/Counter With PWM */ 4900 /* TC0.CTRLA bit masks and bit positions */ 4901 #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 4902 #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ 4903 #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 4904 #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 4905 #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 4906 #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 4907 #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 4908 #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 4909 #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 4910 #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 4911 4912 /* TC0.CTRLB bit masks and bit positions */ 4913 #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ 4914 #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ 4915 4916 #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ 4917 #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ 4918 4919 #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ 4920 #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ 4921 4922 #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ 4923 #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ 4924 4925 #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ 4926 #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ 4927 #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ 4928 #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ 4929 #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ 4930 #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ 4931 #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ 4932 #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ 4933 4934 /* TC0.CTRLC bit masks and bit positions */ 4935 #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ 4936 #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ 4937 4938 #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ 4939 #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ 4940 4941 #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ 4942 #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ 4943 4944 #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ 4945 #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ 4946 4947 /* TC0.CTRLD bit masks and bit positions */ 4948 #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ 4949 #define TC0_EVACT_gp 5 /* Event Action group position. */ 4950 #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ 4951 #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ 4952 #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ 4953 #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ 4954 #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ 4955 #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ 4956 4957 #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ 4958 #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ 4959 4960 #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ 4961 #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ 4962 #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ 4963 #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ 4964 #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ 4965 #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ 4966 #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ 4967 #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ 4968 #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ 4969 #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ 4970 4971 /* TC0.CTRLE bit masks and bit positions */ 4972 #define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ 4973 #define TC0_BYTEM_gp 0 /* Byte Mode group position. */ 4974 #define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ 4975 #define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ 4976 #define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ 4977 #define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ 4978 4979 /* TC0.INTCTRLA bit masks and bit positions */ 4980 #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ 4981 #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ 4982 #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ 4983 #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ 4984 #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ 4985 #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ 4986 4987 #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ 4988 #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ 4989 #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ 4990 #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ 4991 #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ 4992 #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ 4993 4994 /* TC0.INTCTRLB bit masks and bit positions */ 4995 #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ 4996 #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ 4997 #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ 4998 #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ 4999 #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ 5000 #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ 5001 5002 #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ 5003 #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ 5004 #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ 5005 #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ 5006 #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ 5007 #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ 5008 5009 #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ 5010 #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ 5011 #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ 5012 #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ 5013 #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ 5014 #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ 5015 5016 #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ 5017 #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ 5018 #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ 5019 #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ 5020 #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ 5021 #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ 5022 5023 /* TC0.CTRLFCLR bit masks and bit positions */ 5024 #define TC0_CMD_gm 0x0C /* Command group mask. */ 5025 #define TC0_CMD_gp 2 /* Command group position. */ 5026 #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ 5027 #define TC0_CMD0_bp 2 /* Command bit 0 position. */ 5028 #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ 5029 #define TC0_CMD1_bp 3 /* Command bit 1 position. */ 5030 5031 #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ 5032 #define TC0_LUPD_bp 1 /* Lock Update bit position. */ 5033 5034 #define TC0_DIR_bm 0x01 /* Direction bit mask. */ 5035 #define TC0_DIR_bp 0 /* Direction bit position. */ 5036 5037 /* TC0.CTRLFSET bit masks and bit positions */ 5038 /* TC0_CMD Predefined. */ 5039 /* TC0_CMD Predefined. */ 5040 5041 /* TC0_LUPD Predefined. */ 5042 /* TC0_LUPD Predefined. */ 5043 5044 /* TC0_DIR Predefined. */ 5045 /* TC0_DIR Predefined. */ 5046 5047 /* TC0.CTRLGCLR bit masks and bit positions */ 5048 #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ 5049 #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ 5050 5051 #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ 5052 #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ 5053 5054 #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ 5055 #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ 5056 5057 #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ 5058 #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ 5059 5060 #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ 5061 #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ 5062 5063 /* TC0.CTRLGSET bit masks and bit positions */ 5064 /* TC0_CCDBV Predefined. */ 5065 /* TC0_CCDBV Predefined. */ 5066 5067 /* TC0_CCCBV Predefined. */ 5068 /* TC0_CCCBV Predefined. */ 5069 5070 /* TC0_CCBBV Predefined. */ 5071 /* TC0_CCBBV Predefined. */ 5072 5073 /* TC0_CCABV Predefined. */ 5074 /* TC0_CCABV Predefined. */ 5075 5076 /* TC0_PERBV Predefined. */ 5077 /* TC0_PERBV Predefined. */ 5078 5079 /* TC0.INTFLAGS bit masks and bit positions */ 5080 #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ 5081 #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ 5082 5083 #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ 5084 #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ 5085 5086 #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ 5087 #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ 5088 5089 #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ 5090 #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ 5091 5092 #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ 5093 #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ 5094 5095 #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 5096 #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 5097 5098 /* TC1.CTRLA bit masks and bit positions */ 5099 #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 5100 #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ 5101 #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 5102 #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 5103 #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 5104 #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 5105 #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 5106 #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 5107 #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 5108 #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 5109 5110 /* TC1.CTRLB bit masks and bit positions */ 5111 #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ 5112 #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ 5113 5114 #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ 5115 #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ 5116 5117 #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ 5118 #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ 5119 #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ 5120 #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ 5121 #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ 5122 #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ 5123 #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ 5124 #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ 5125 5126 /* TC1.CTRLC bit masks and bit positions */ 5127 #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ 5128 #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ 5129 5130 #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ 5131 #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ 5132 5133 /* TC1.CTRLD bit masks and bit positions */ 5134 #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ 5135 #define TC1_EVACT_gp 5 /* Event Action group position. */ 5136 #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ 5137 #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ 5138 #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ 5139 #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ 5140 #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ 5141 #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ 5142 5143 #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ 5144 #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ 5145 5146 #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ 5147 #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ 5148 #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ 5149 #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ 5150 #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ 5151 #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ 5152 #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ 5153 #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ 5154 #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ 5155 #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ 5156 5157 /* TC1.CTRLE bit masks and bit positions */ 5158 #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ 5159 #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ 5160 5161 /* TC1.INTCTRLA bit masks and bit positions */ 5162 #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ 5163 #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ 5164 #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ 5165 #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ 5166 #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ 5167 #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ 5168 5169 #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ 5170 #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ 5171 #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ 5172 #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ 5173 #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ 5174 #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ 5175 5176 /* TC1.INTCTRLB bit masks and bit positions */ 5177 #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ 5178 #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ 5179 #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ 5180 #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ 5181 #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ 5182 #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ 5183 5184 #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ 5185 #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ 5186 #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ 5187 #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ 5188 #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ 5189 #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ 5190 5191 /* TC1.CTRLFCLR bit masks and bit positions */ 5192 #define TC1_CMD_gm 0x0C /* Command group mask. */ 5193 #define TC1_CMD_gp 2 /* Command group position. */ 5194 #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ 5195 #define TC1_CMD0_bp 2 /* Command bit 0 position. */ 5196 #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ 5197 #define TC1_CMD1_bp 3 /* Command bit 1 position. */ 5198 5199 #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ 5200 #define TC1_LUPD_bp 1 /* Lock Update bit position. */ 5201 5202 #define TC1_DIR_bm 0x01 /* Direction bit mask. */ 5203 #define TC1_DIR_bp 0 /* Direction bit position. */ 5204 5205 /* TC1.CTRLFSET bit masks and bit positions */ 5206 /* TC1_CMD Predefined. */ 5207 /* TC1_CMD Predefined. */ 5208 5209 /* TC1_LUPD Predefined. */ 5210 /* TC1_LUPD Predefined. */ 5211 5212 /* TC1_DIR Predefined. */ 5213 /* TC1_DIR Predefined. */ 5214 5215 /* TC1.CTRLGCLR bit masks and bit positions */ 5216 #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ 5217 #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ 5218 5219 #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ 5220 #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ 5221 5222 #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ 5223 #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ 5224 5225 /* TC1.CTRLGSET bit masks and bit positions */ 5226 /* TC1_CCBBV Predefined. */ 5227 /* TC1_CCBBV Predefined. */ 5228 5229 /* TC1_CCABV Predefined. */ 5230 /* TC1_CCABV Predefined. */ 5231 5232 /* TC1_PERBV Predefined. */ 5233 /* TC1_PERBV Predefined. */ 5234 5235 /* TC1.INTFLAGS bit masks and bit positions */ 5236 #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ 5237 #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ 5238 5239 #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ 5240 #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ 5241 5242 #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ 5243 #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ 5244 5245 #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 5246 #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 5247 5248 /* TC2 - 16-bit Timer/Counter type 2 */ 5249 /* TC2.CTRLA bit masks and bit positions */ 5250 #define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 5251 #define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ 5252 #define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 5253 #define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 5254 #define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 5255 #define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 5256 #define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 5257 #define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 5258 #define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 5259 #define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 5260 5261 /* TC2.CTRLB bit masks and bit positions */ 5262 #define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ 5263 #define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ 5264 5265 #define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ 5266 #define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ 5267 5268 #define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ 5269 #define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ 5270 5271 #define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ 5272 #define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ 5273 5274 #define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ 5275 #define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ 5276 5277 #define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ 5278 #define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ 5279 5280 #define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ 5281 #define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ 5282 5283 #define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ 5284 #define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ 5285 5286 /* TC2.CTRLC bit masks and bit positions */ 5287 #define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ 5288 #define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ 5289 5290 #define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ 5291 #define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ 5292 5293 #define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ 5294 #define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ 5295 5296 #define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ 5297 #define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ 5298 5299 #define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ 5300 #define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ 5301 5302 #define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ 5303 #define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ 5304 5305 #define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ 5306 #define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ 5307 5308 #define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ 5309 #define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ 5310 5311 /* TC2.CTRLE bit masks and bit positions */ 5312 #define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ 5313 #define TC2_BYTEM_gp 0 /* Byte Mode group position. */ 5314 #define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ 5315 #define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ 5316 #define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ 5317 #define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ 5318 5319 /* TC2.INTCTRLA bit masks and bit positions */ 5320 #define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ 5321 #define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ 5322 #define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ 5323 #define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ 5324 #define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ 5325 #define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ 5326 5327 #define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ 5328 #define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ 5329 #define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ 5330 #define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ 5331 #define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ 5332 #define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ 5333 5334 /* TC2.INTCTRLB bit masks and bit positions */ 5335 #define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ 5336 #define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ 5337 #define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ 5338 #define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ 5339 #define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ 5340 #define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ 5341 5342 #define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ 5343 #define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ 5344 #define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ 5345 #define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ 5346 #define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ 5347 #define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ 5348 5349 #define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ 5350 #define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ 5351 #define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ 5352 #define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ 5353 #define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ 5354 #define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ 5355 5356 #define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ 5357 #define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ 5358 #define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ 5359 #define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ 5360 #define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ 5361 #define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ 5362 5363 /* TC2.CTRLF bit masks and bit positions */ 5364 #define TC2_CMD_gm 0x0C /* Command group mask. */ 5365 #define TC2_CMD_gp 2 /* Command group position. */ 5366 #define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ 5367 #define TC2_CMD0_bp 2 /* Command bit 0 position. */ 5368 #define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ 5369 #define TC2_CMD1_bp 3 /* Command bit 1 position. */ 5370 5371 #define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ 5372 #define TC2_CMDEN_gp 0 /* Command Enable group position. */ 5373 #define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ 5374 #define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ 5375 #define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ 5376 #define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ 5377 5378 /* TC2.INTFLAGS bit masks and bit positions */ 5379 #define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ 5380 #define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ 5381 5382 #define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ 5383 #define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ 5384 5385 #define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ 5386 #define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ 5387 5388 #define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ 5389 #define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ 5390 5391 #define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ 5392 #define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ 5393 5394 #define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ 5395 #define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ 5396 5397 /* AWEX - Timer/Counter Advanced Waveform Extension */ 5398 /* AWEX.CTRL bit masks and bit positions */ 5399 #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ 5400 #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ 5401 5402 #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ 5403 #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ 5404 5405 #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ 5406 #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ 5407 5408 #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ 5409 #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ 5410 5411 #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ 5412 #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ 5413 5414 #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ 5415 #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ 5416 5417 /* AWEX.FDCTRL bit masks and bit positions */ 5418 #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ 5419 #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ 5420 5421 #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ 5422 #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ 5423 5424 #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ 5425 #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ 5426 #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ 5427 #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ 5428 #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ 5429 #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ 5430 5431 /* AWEX.STATUS bit masks and bit positions */ 5432 #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ 5433 #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ 5434 5435 #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ 5436 #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ 5437 5438 #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ 5439 #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ 5440 5441 /* AWEX.STATUSSET bit masks and bit positions */ 5442 /* AWEX_FDF Predefined. */ 5443 /* AWEX_FDF Predefined. */ 5444 5445 /* AWEX_DTHSBUFV Predefined. */ 5446 /* AWEX_DTHSBUFV Predefined. */ 5447 5448 /* AWEX_DTLSBUFV Predefined. */ 5449 /* AWEX_DTLSBUFV Predefined. */ 5450 5451 /* HIRES - Timer/Counter High-Resolution Extension */ 5452 /* HIRES.CTRLA bit masks and bit positions */ 5453 #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ 5454 #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ 5455 #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ 5456 #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ 5457 #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ 5458 #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ 5459 5460 /* USART - Universal Asynchronous Receiver-Transmitter */ 5461 /* USART.STATUS bit masks and bit positions */ 5462 #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ 5463 #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ 5464 5465 #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ 5466 #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ 5467 5468 #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ 5469 #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ 5470 5471 #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ 5472 #define USART_FERR_bp 4 /* Frame Error bit position. */ 5473 5474 #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ 5475 #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ 5476 5477 #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ 5478 #define USART_PERR_bp 2 /* Parity Error bit position. */ 5479 5480 #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ 5481 #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ 5482 5483 /* USART.CTRLA bit masks and bit positions */ 5484 #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ 5485 #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ 5486 #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ 5487 #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ 5488 #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ 5489 #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ 5490 5491 #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ 5492 #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ 5493 #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ 5494 #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ 5495 #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ 5496 #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ 5497 5498 #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ 5499 #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ 5500 #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ 5501 #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ 5502 #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ 5503 #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ 5504 5505 /* USART.CTRLB bit masks and bit positions */ 5506 #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ 5507 #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ 5508 5509 #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ 5510 #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ 5511 5512 #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ 5513 #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ 5514 5515 #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ 5516 #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ 5517 5518 #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ 5519 #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ 5520 5521 /* USART.CTRLC bit masks and bit positions */ 5522 #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ 5523 #define USART_CMODE_gp 6 /* Communication Mode group position. */ 5524 #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ 5525 #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ 5526 #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ 5527 #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ 5528 5529 #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ 5530 #define USART_PMODE_gp 4 /* Parity Mode group position. */ 5531 #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ 5532 #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ 5533 #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ 5534 #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ 5535 5536 #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ 5537 #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ 5538 5539 #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ 5540 #define USART_CHSIZE_gp 0 /* Character Size group position. */ 5541 #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ 5542 #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ 5543 #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ 5544 #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ 5545 #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ 5546 #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ 5547 5548 /* USART.BAUDCTRLA bit masks and bit positions */ 5549 #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ 5550 #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ 5551 #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ 5552 #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ 5553 #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ 5554 #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ 5555 #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ 5556 #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ 5557 #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ 5558 #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ 5559 #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ 5560 #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ 5561 #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ 5562 #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ 5563 #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ 5564 #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ 5565 #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ 5566 #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ 5567 5568 /* USART.BAUDCTRLB bit masks and bit positions */ 5569 #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ 5570 #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ 5571 #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ 5572 #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ 5573 #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ 5574 #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ 5575 #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ 5576 #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ 5577 #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ 5578 #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ 5579 5580 /* USART_BSEL Predefined. */ 5581 /* USART_BSEL Predefined. */ 5582 5583 /* SPI - Serial Peripheral Interface */ 5584 /* SPI.CTRL bit masks and bit positions */ 5585 #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ 5586 #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ 5587 5588 #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ 5589 #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ 5590 5591 #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ 5592 #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ 5593 5594 #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ 5595 #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ 5596 5597 #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ 5598 #define SPI_MODE_gp 2 /* SPI Mode group position. */ 5599 #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ 5600 #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ 5601 #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ 5602 #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ 5603 5604 #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ 5605 #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ 5606 #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ 5607 #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ 5608 #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ 5609 #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ 5610 5611 /* SPI.INTCTRL bit masks and bit positions */ 5612 #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ 5613 #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ 5614 #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ 5615 #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ 5616 #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ 5617 #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ 5618 5619 /* SPI.STATUS bit masks and bit positions */ 5620 #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ 5621 #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ 5622 5623 #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ 5624 #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ 5625 5626 /* IRCOM - IR Communication Module */ 5627 /* IRCOM.CTRL bit masks and bit positions */ 5628 #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ 5629 #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ 5630 #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ 5631 #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ 5632 #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ 5633 #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ 5634 #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ 5635 #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ 5636 #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ 5637 #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ 5638 5639 /* FUSE - Fuses and Lockbits */ 5640 /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ 5641 #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ 5642 #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ 5643 #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ 5644 #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ 5645 #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ 5646 #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ 5647 #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ 5648 #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ 5649 #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ 5650 #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ 5651 5652 #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ 5653 #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ 5654 #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ 5655 #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ 5656 #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ 5657 #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ 5658 #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ 5659 #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ 5660 #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ 5661 #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ 5662 5663 /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ 5664 #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ 5665 #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ 5666 5667 #define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ 5668 #define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ 5669 5670 #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ 5671 #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ 5672 #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ 5673 #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ 5674 #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ 5675 #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ 5676 5677 /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ 5678 #define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ 5679 #define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ 5680 5681 #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ 5682 #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ 5683 #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ 5684 #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ 5685 #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ 5686 #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ 5687 5688 #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ 5689 #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ 5690 5691 /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ 5692 #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ 5693 #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ 5694 #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ 5695 #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ 5696 #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ 5697 #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ 5698 5699 #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ 5700 #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ 5701 5702 #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ 5703 #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ 5704 #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ 5705 #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ 5706 #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ 5707 #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ 5708 #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ 5709 #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ 5710 5711 /* LOCKBIT - Fuses and Lockbits */ 5712 /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ 5713 #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ 5714 #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ 5715 #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ 5716 #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ 5717 #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ 5718 #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ 5719 5720 #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ 5721 #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ 5722 #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ 5723 #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ 5724 #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ 5725 #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ 5726 5727 #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ 5728 #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ 5729 #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ 5730 #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ 5731 #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ 5732 #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ 5733 5734 #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ 5735 #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ 5736 #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ 5737 #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ 5738 #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ 5739 #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ 5740 5741 5742 5743 // Generic Port Pins 5744 5745 #define PIN0_bm 0x01 5746 #define PIN0_bp 0 5747 #define PIN1_bm 0x02 5748 #define PIN1_bp 1 5749 #define PIN2_bm 0x04 5750 #define PIN2_bp 2 5751 #define PIN3_bm 0x08 5752 #define PIN3_bp 3 5753 #define PIN4_bm 0x10 5754 #define PIN4_bp 4 5755 #define PIN5_bm 0x20 5756 #define PIN5_bp 5 5757 #define PIN6_bm 0x40 5758 #define PIN6_bp 6 5759 #define PIN7_bm 0x80 5760 #define PIN7_bp 7 5761 5762 /* ========== Interrupt Vector Definitions ========== */ 5763 /* Vector 0 is the reset vector */ 5764 5765 /* OSC interrupt vectors */ 5766 #define OSC_OSCF_vect_num 1 5767 #define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ 5768 5769 /* PORTC interrupt vectors */ 5770 #define PORTC_INT0_vect_num 2 5771 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ 5772 #define PORTC_INT1_vect_num 3 5773 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ 5774 5775 /* PORTR interrupt vectors */ 5776 #define PORTR_INT0_vect_num 4 5777 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ 5778 #define PORTR_INT1_vect_num 5 5779 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ 5780 5781 /* RTC interrupt vectors */ 5782 #define RTC_OVF_vect_num 10 5783 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ 5784 #define RTC_COMP_vect_num 11 5785 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ 5786 5787 /* TWIC interrupt vectors */ 5788 #define TWIC_TWIS_vect_num 12 5789 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ 5790 #define TWIC_TWIM_vect_num 13 5791 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ 5792 5793 /* TCC0 interrupt vectors */ 5794 #define TCC0_OVF_vect_num 14 5795 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ 5796 5797 /* TCC2 interrupt vectors */ 5798 #define TCC2_LUNF_vect_num 14 5799 #define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ 5800 5801 /* TCC0 interrupt vectors */ 5802 #define TCC0_ERR_vect_num 15 5803 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ 5804 5805 /* TCC2 interrupt vectors */ 5806 #define TCC2_HUNF_vect_num 15 5807 #define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ 5808 5809 /* TCC0 interrupt vectors */ 5810 #define TCC0_CCA_vect_num 16 5811 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ 5812 5813 /* TCC2 interrupt vectors */ 5814 #define TCC2_LCMPA_vect_num 16 5815 #define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ 5816 5817 /* TCC0 interrupt vectors */ 5818 #define TCC0_CCB_vect_num 17 5819 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ 5820 5821 /* TCC2 interrupt vectors */ 5822 #define TCC2_LCMPB_vect_num 17 5823 #define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ 5824 5825 /* TCC0 interrupt vectors */ 5826 #define TCC0_CCC_vect_num 18 5827 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ 5828 5829 /* TCC2 interrupt vectors */ 5830 #define TCC2_LCMPC_vect_num 18 5831 #define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ 5832 5833 /* TCC0 interrupt vectors */ 5834 #define TCC0_CCD_vect_num 19 5835 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ 5836 5837 /* TCC2 interrupt vectors */ 5838 #define TCC2_LCMPD_vect_num 19 5839 #define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ 5840 5841 /* TCC1 interrupt vectors */ 5842 #define TCC1_OVF_vect_num 20 5843 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ 5844 #define TCC1_ERR_vect_num 21 5845 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ 5846 #define TCC1_CCA_vect_num 22 5847 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ 5848 #define TCC1_CCB_vect_num 23 5849 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ 5850 5851 /* SPIC interrupt vectors */ 5852 #define SPIC_INT_vect_num 24 5853 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ 5854 5855 /* USARTC0 interrupt vectors */ 5856 #define USARTC0_RXC_vect_num 25 5857 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ 5858 #define USARTC0_DRE_vect_num 26 5859 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ 5860 #define USARTC0_TXC_vect_num 27 5861 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ 5862 5863 /* NVM interrupt vectors */ 5864 #define NVM_EE_vect_num 32 5865 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ 5866 #define NVM_SPM_vect_num 33 5867 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ 5868 5869 /* PORTB interrupt vectors */ 5870 #define PORTB_INT0_vect_num 34 5871 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ 5872 #define PORTB_INT1_vect_num 35 5873 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ 5874 5875 /* PORTE interrupt vectors */ 5876 #define PORTE_INT0_vect_num 43 5877 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ 5878 #define PORTE_INT1_vect_num 44 5879 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ 5880 5881 /* TWIE interrupt vectors */ 5882 #define TWIE_TWIS_vect_num 45 5883 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ 5884 #define TWIE_TWIM_vect_num 46 5885 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ 5886 5887 /* TCE0 interrupt vectors */ 5888 #define TCE0_OVF_vect_num 47 5889 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ 5890 5891 /* TCE2 interrupt vectors */ 5892 #define TCE2_LUNF_vect_num 47 5893 #define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ 5894 5895 /* TCE0 interrupt vectors */ 5896 #define TCE0_ERR_vect_num 48 5897 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ 5898 5899 /* TCE2 interrupt vectors */ 5900 #define TCE2_HUNF_vect_num 48 5901 #define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ 5902 5903 /* TCE0 interrupt vectors */ 5904 #define TCE0_CCA_vect_num 49 5905 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ 5906 5907 /* TCE2 interrupt vectors */ 5908 #define TCE2_LCMPA_vect_num 49 5909 #define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ 5910 5911 /* TCE0 interrupt vectors */ 5912 #define TCE0_CCB_vect_num 50 5913 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ 5914 5915 /* TCE2 interrupt vectors */ 5916 #define TCE2_LCMPB_vect_num 50 5917 #define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ 5918 5919 /* TCE0 interrupt vectors */ 5920 #define TCE0_CCC_vect_num 51 5921 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ 5922 5923 /* TCE2 interrupt vectors */ 5924 #define TCE2_LCMPC_vect_num 51 5925 #define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ 5926 5927 /* TCE0 interrupt vectors */ 5928 #define TCE0_CCD_vect_num 52 5929 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ 5930 5931 /* TCE2 interrupt vectors */ 5932 #define TCE2_LCMPD_vect_num 52 5933 #define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ 5934 5935 /* USARTE0 interrupt vectors */ 5936 #define USARTE0_RXC_vect_num 58 5937 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ 5938 #define USARTE0_DRE_vect_num 59 5939 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ 5940 #define USARTE0_TXC_vect_num 60 5941 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ 5942 5943 /* PORTD interrupt vectors */ 5944 #define PORTD_INT0_vect_num 64 5945 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ 5946 #define PORTD_INT1_vect_num 65 5947 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ 5948 5949 /* PORTA interrupt vectors */ 5950 #define PORTA_INT0_vect_num 66 5951 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ 5952 #define PORTA_INT1_vect_num 67 5953 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ 5954 5955 /* ACA interrupt vectors */ 5956 #define ACA_AC0_vect_num 68 5957 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ 5958 #define ACA_AC1_vect_num 69 5959 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ 5960 #define ACA_ACW_vect_num 70 5961 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ 5962 5963 /* ADCA interrupt vectors */ 5964 #define ADCA_CH0_vect_num 71 5965 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ 5966 5967 /* TCD0 interrupt vectors */ 5968 #define TCD0_OVF_vect_num 77 5969 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ 5970 5971 /* TCD2 interrupt vectors */ 5972 #define TCD2_LUNF_vect_num 77 5973 #define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ 5974 5975 /* TCD0 interrupt vectors */ 5976 #define TCD0_ERR_vect_num 78 5977 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ 5978 5979 /* TCD2 interrupt vectors */ 5980 #define TCD2_HUNF_vect_num 78 5981 #define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ 5982 5983 /* TCD0 interrupt vectors */ 5984 #define TCD0_CCA_vect_num 79 5985 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ 5986 5987 /* TCD2 interrupt vectors */ 5988 #define TCD2_LCMPA_vect_num 79 5989 #define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ 5990 5991 /* TCD0 interrupt vectors */ 5992 #define TCD0_CCB_vect_num 80 5993 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ 5994 5995 /* TCD2 interrupt vectors */ 5996 #define TCD2_LCMPB_vect_num 80 5997 #define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ 5998 5999 /* TCD0 interrupt vectors */ 6000 #define TCD0_CCC_vect_num 81 6001 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ 6002 6003 /* TCD2 interrupt vectors */ 6004 #define TCD2_LCMPC_vect_num 81 6005 #define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ 6006 6007 /* TCD0 interrupt vectors */ 6008 #define TCD0_CCD_vect_num 82 6009 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ 6010 6011 /* TCD2 interrupt vectors */ 6012 #define TCD2_LCMPD_vect_num 82 6013 #define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ 6014 6015 /* SPID interrupt vectors */ 6016 #define SPID_INT_vect_num 87 6017 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ 6018 6019 /* USARTD0 interrupt vectors */ 6020 #define USARTD0_RXC_vect_num 88 6021 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ 6022 #define USARTD0_DRE_vect_num 89 6023 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ 6024 #define USARTD0_TXC_vect_num 90 6025 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ 6026 6027 /* PORTF interrupt vectors */ 6028 #define PORTF_INT0_vect_num 104 6029 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ 6030 #define PORTF_INT1_vect_num 105 6031 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ 6032 6033 /* TCF0 interrupt vectors */ 6034 #define TCF0_OVF_vect_num 108 6035 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ 6036 6037 /* TCF2 interrupt vectors */ 6038 #define TCF2_LUNF_vect_num 108 6039 #define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ 6040 6041 /* TCF0 interrupt vectors */ 6042 #define TCF0_ERR_vect_num 109 6043 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ 6044 6045 /* TCF2 interrupt vectors */ 6046 #define TCF2_HUNF_vect_num 109 6047 #define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ 6048 6049 /* TCF0 interrupt vectors */ 6050 #define TCF0_CCA_vect_num 110 6051 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ 6052 6053 /* TCF2 interrupt vectors */ 6054 #define TCF2_LCMPA_vect_num 110 6055 #define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ 6056 6057 /* TCF0 interrupt vectors */ 6058 #define TCF0_CCB_vect_num 111 6059 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ 6060 6061 /* TCF2 interrupt vectors */ 6062 #define TCF2_LCMPB_vect_num 111 6063 #define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ 6064 6065 /* TCF0 interrupt vectors */ 6066 #define TCF0_CCC_vect_num 112 6067 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ 6068 6069 /* TCF2 interrupt vectors */ 6070 #define TCF2_LCMPC_vect_num 112 6071 #define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ 6072 6073 /* TCF0 interrupt vectors */ 6074 #define TCF0_CCD_vect_num 113 6075 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ 6076 6077 /* TCF2 interrupt vectors */ 6078 #define TCF2_LCMPD_vect_num 113 6079 #define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ 6080 6081 /* USB interrupt vectors */ 6082 #define USB_BUSEVENT_vect_num 125 6083 #define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ 6084 #define USB_TRNCOMPL_vect_num 126 6085 #define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ 6086 6087 #define _VECTOR_SIZE 4 /* Size of individual vector. */ 6088 #define _VECTORS_SIZE (127 * _VECTOR_SIZE) 6089 6090 6091 /* ========== Constants ========== */ 6092 6093 #define PROGMEM_START (0x0000) 6094 #define PROGMEM_SIZE (139264) 6095 #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) 6096 6097 #define APP_SECTION_START (0x0000) 6098 #define APP_SECTION_SIZE (131072) 6099 #define APP_SECTION_PAGE_SIZE (512) 6100 #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) 6101 6102 #define APPTABLE_SECTION_START (0x1E000) 6103 #define APPTABLE_SECTION_SIZE (8192) 6104 #define APPTABLE_SECTION_PAGE_SIZE (512) 6105 #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) 6106 6107 #define BOOT_SECTION_START (0x20000) 6108 #define BOOT_SECTION_SIZE (8192) 6109 #define BOOT_SECTION_PAGE_SIZE (512) 6110 #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) 6111 6112 #define DATAMEM_START (0x0000) 6113 #define DATAMEM_SIZE (16384) 6114 #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) 6115 6116 #define IO_START (0x0000) 6117 #define IO_SIZE (4096) 6118 #define IO_PAGE_SIZE (0) 6119 #define IO_END (IO_START + IO_SIZE - 1) 6120 6121 #define MAPPED_EEPROM_START (0x1000) 6122 #define MAPPED_EEPROM_SIZE (2048) 6123 #define MAPPED_EEPROM_PAGE_SIZE (0) 6124 #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) 6125 6126 #define INTERNAL_SRAM_START (0x2000) 6127 #define INTERNAL_SRAM_SIZE (8192) 6128 #define INTERNAL_SRAM_PAGE_SIZE (0) 6129 #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) 6130 6131 #define EEPROM_START (0x0000) 6132 #define EEPROM_SIZE (2048) 6133 #define EEPROM_PAGE_SIZE (32) 6134 #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) 6135 6136 #define SIGNATURES_START (0x0000) 6137 #define SIGNATURES_SIZE (3) 6138 #define SIGNATURES_PAGE_SIZE (0) 6139 #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) 6140 6141 #define FUSES_START (0x0000) 6142 #define FUSES_SIZE (6) 6143 #define FUSES_PAGE_SIZE (0) 6144 #define FUSES_END (FUSES_START + FUSES_SIZE - 1) 6145 6146 #define LOCKBITS_START (0x0000) 6147 #define LOCKBITS_SIZE (1) 6148 #define LOCKBITS_PAGE_SIZE (0) 6149 #define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) 6150 6151 #define USER_SIGNATURES_START (0x0000) 6152 #define USER_SIGNATURES_SIZE (512) 6153 #define USER_SIGNATURES_PAGE_SIZE (512) 6154 #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) 6155 6156 #define PROD_SIGNATURES_START (0x0000) 6157 #define PROD_SIGNATURES_SIZE (64) 6158 #define PROD_SIGNATURES_PAGE_SIZE (512) 6159 #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) 6160 6161 #define FLASHSTART PROGMEM_START 6162 #define FLASHEND PROGMEM_END 6163 #define SPM_PAGESIZE 512 6164 #define RAMSTART INTERNAL_SRAM_START 6165 #define RAMSIZE INTERNAL_SRAM_SIZE 6166 #define RAMEND INTERNAL_SRAM_END 6167 #define E2END EEPROM_END 6168 #define E2PAGESIZE EEPROM_PAGE_SIZE 6169 6170 6171 /* ========== Fuses ========== */ 6172 #define FUSE_MEMORY_SIZE 6 6173 6174 /* Fuse Byte 0 Reserved */ 6175 6176 /* Fuse Byte 1 */ 6177 #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ 6178 #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ 6179 #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ 6180 #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ 6181 #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ 6182 #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ 6183 #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ 6184 #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ 6185 #define FUSE1_DEFAULT (0xFF) 6186 6187 /* Fuse Byte 2 */ 6188 #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ 6189 #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ 6190 #define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ 6191 #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ 6192 #define FUSE2_DEFAULT (0xFF) 6193 6194 /* Fuse Byte 3 Reserved */ 6195 6196 /* Fuse Byte 4 */ 6197 #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ 6198 #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ 6199 #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ 6200 #define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ 6201 #define FUSE4_DEFAULT (0xFF) 6202 6203 /* Fuse Byte 5 */ 6204 #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ 6205 #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ 6206 #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ 6207 #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ 6208 #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ 6209 #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ 6210 #define FUSE5_DEFAULT (0xFF) 6211 6212 /* ========== Lock Bits ========== */ 6213 #define __LOCK_BITS_EXIST 6214 #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST 6215 #define __BOOT_LOCK_APPLICATION_BITS_EXIST 6216 #define __BOOT_LOCK_BOOT_BITS_EXIST 6217 6218 /* ========== Signature ========== */ 6219 #define SIGNATURE_0 0x1E 6220 #define SIGNATURE_1 0x97 6221 #define SIGNATURE_2 0x52 6222 6223 /* ========== Power Reduction Condition Definitions ========== */ 6224 6225 /* PR.PRGEN */ 6226 #define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) 6227 #define __AVR_HAVE_PRGEN_USB 6228 #define __AVR_HAVE_PRGEN_AES 6229 #define __AVR_HAVE_PRGEN_RTC 6230 #define __AVR_HAVE_PRGEN_EVSYS 6231 #define __AVR_HAVE_PRGEN_DMA 6232 6233 /* PR.PRPA */ 6234 #define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) 6235 #define __AVR_HAVE_PRPA_ADC 6236 #define __AVR_HAVE_PRPA_AC 6237 6238 /* PR.PRPC */ 6239 #define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) 6240 #define __AVR_HAVE_PRPC_TWI 6241 #define __AVR_HAVE_PRPC_USART1 6242 #define __AVR_HAVE_PRPC_USART0 6243 #define __AVR_HAVE_PRPC_SPI 6244 #define __AVR_HAVE_PRPC_HIRES 6245 #define __AVR_HAVE_PRPC_TC1 6246 #define __AVR_HAVE_PRPC_TC0 6247 6248 /* PR.PRPD */ 6249 #define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) 6250 #define __AVR_HAVE_PRPD_USART0 6251 #define __AVR_HAVE_PRPD_SPI 6252 #define __AVR_HAVE_PRPD_TC0 6253 6254 /* PR.PRPE */ 6255 #define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) 6256 #define __AVR_HAVE_PRPE_TWI 6257 #define __AVR_HAVE_PRPE_USART0 6258 #define __AVR_HAVE_PRPE_TC0 6259 6260 /* PR.PRPF */ 6261 #define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) 6262 #define __AVR_HAVE_PRPF_USART0 6263 #define __AVR_HAVE_PRPF_TC0 6264 6265 6266 #endif /* #ifdef _AVR_ATXMEGA128C3_H_INCLUDED */ 6267 6268