1 /* Copyright (c) 2009-2010 Atmel Corporation 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: iox256a3b.h 2482 2015-08-06 08:54:17Z pitchumani $ */ 32 33 /* avr/iox256a3b.h - definitions for ATxmega256A3B */ 34 35 /* This file should only be included from <avr/io.h>, never directly. */ 36 37 #ifndef _AVR_IO_H_ 38 # error "Include <avr/io.h> instead of this file." 39 #endif 40 41 #ifndef _AVR_IOXXX_H_ 42 # define _AVR_IOXXX_H_ "iox256a3b.h" 43 #else 44 # error "Attempt to include more than one <avr/ioXXX.h> file." 45 #endif 46 47 48 #ifndef _AVR_ATxmega256A3B_H_ 49 #define _AVR_ATxmega256A3B_H_ 1 50 51 52 /* Ungrouped common registers */ 53 #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ 54 #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ 55 #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ 56 #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ 57 #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ 58 #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ 59 #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ 60 #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ 61 #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ 62 #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ 63 #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ 64 #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ 65 #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ 66 #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ 67 #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ 68 #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ 69 70 /* Deprecated*/ 71 #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ 72 #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ 73 #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ 74 #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ 75 #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ 76 #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ 77 #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ 78 #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ 79 #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ 80 #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ 81 #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ 82 #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ 83 #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ 84 #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ 85 #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ 86 #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ 87 88 89 #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ 90 #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ 91 #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ 92 #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ 93 #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ 94 #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ 95 #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ 96 #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ 97 #define SREG _SFR_MEM8(0x003F) /* Status Register */ 98 99 100 /* C Language Only */ 101 #if !defined (__ASSEMBLER__) 102 103 #include <stdint.h> 104 105 typedef volatile uint8_t register8_t; 106 typedef volatile uint16_t register16_t; 107 typedef volatile uint32_t register32_t; 108 109 110 #ifdef _WORDREGISTER 111 #undef _WORDREGISTER 112 #endif 113 #define _WORDREGISTER(regname) \ 114 __extension__ union \ 115 { \ 116 register16_t regname; \ 117 struct \ 118 { \ 119 register8_t regname ## L; \ 120 register8_t regname ## H; \ 121 }; \ 122 } 123 124 #ifdef _DWORDREGISTER 125 #undef _DWORDREGISTER 126 #endif 127 #define _DWORDREGISTER(regname) \ 128 __extension__ union \ 129 { \ 130 register32_t regname; \ 131 struct \ 132 { \ 133 register8_t regname ## 0; \ 134 register8_t regname ## 1; \ 135 register8_t regname ## 2; \ 136 register8_t regname ## 3; \ 137 }; \ 138 } 139 140 141 /* 142 ========================================================================== 143 IO Module Structures 144 ========================================================================== 145 */ 146 147 148 /* 149 -------------------------------------------------------------------------- 150 XOCD - On-Chip Debug System 151 -------------------------------------------------------------------------- 152 */ 153 154 /* On-Chip Debug System */ 155 typedef struct OCD_struct 156 { 157 register8_t OCDR0; /* OCD Register 0 */ 158 register8_t OCDR1; /* OCD Register 1 */ 159 } OCD_t; 160 161 162 /* CCP signatures */ 163 typedef enum CCP_enum 164 { 165 CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ 166 CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ 167 } CCP_t; 168 169 170 /* 171 -------------------------------------------------------------------------- 172 CLK - Clock System 173 -------------------------------------------------------------------------- 174 */ 175 176 /* Clock System */ 177 typedef struct CLK_struct 178 { 179 register8_t CTRL; /* Control Register */ 180 register8_t PSCTRL; /* Prescaler Control Register */ 181 register8_t LOCK; /* Lock register */ 182 register8_t RTCCTRL; /* RTC Control Register */ 183 } CLK_t; 184 185 /* 186 -------------------------------------------------------------------------- 187 CLK - Clock System 188 -------------------------------------------------------------------------- 189 */ 190 191 /* Power Reduction */ 192 typedef struct PR_struct 193 { 194 register8_t PRGEN; /* General Power Reduction */ 195 register8_t PRPA; /* Power Reduction Port A */ 196 register8_t PRPB; /* Power Reduction Port B */ 197 register8_t PRPC; /* Power Reduction Port C */ 198 register8_t PRPD; /* Power Reduction Port D */ 199 register8_t PRPE; /* Power Reduction Port E */ 200 register8_t PRPF; /* Power Reduction Port F */ 201 } PR_t; 202 203 /* System Clock Selection */ 204 typedef enum CLK_SCLKSEL_enum 205 { 206 CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ 207 CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ 208 CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ 209 CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ 210 CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ 211 } CLK_SCLKSEL_t; 212 213 /* Prescaler A Division Factor */ 214 typedef enum CLK_PSADIV_enum 215 { 216 CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ 217 CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ 218 CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ 219 CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ 220 CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ 221 CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ 222 CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ 223 CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ 224 CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ 225 CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ 226 } CLK_PSADIV_t; 227 228 /* Prescaler B and C Division Factor */ 229 typedef enum CLK_PSBCDIV_enum 230 { 231 CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ 232 CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ 233 CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ 234 CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ 235 } CLK_PSBCDIV_t; 236 237 /* RTC Clock Source */ 238 typedef enum CLK_RTCSRC_enum 239 { 240 CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ 241 CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ 242 CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ 243 CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ 244 } CLK_RTCSRC_t; 245 246 247 /* 248 -------------------------------------------------------------------------- 249 SLEEP - Sleep Controller 250 -------------------------------------------------------------------------- 251 */ 252 253 /* Sleep Controller */ 254 typedef struct SLEEP_struct 255 { 256 register8_t CTRL; /* Control Register */ 257 } SLEEP_t; 258 259 /* Sleep Mode */ 260 typedef enum SLEEP_SMODE_enum 261 { 262 SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ 263 SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ 264 SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ 265 SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ 266 SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ 267 } SLEEP_SMODE_t; 268 269 270 #define SLEEP_MODE_IDLE (0x00<<1) 271 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 272 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 273 #define SLEEP_MODE_STANDBY (0x06<<1) 274 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 275 276 /* 277 -------------------------------------------------------------------------- 278 OSC - Oscillator 279 -------------------------------------------------------------------------- 280 */ 281 282 /* Oscillator */ 283 typedef struct OSC_struct 284 { 285 register8_t CTRL; /* Control Register */ 286 register8_t STATUS; /* Status Register */ 287 register8_t XOSCCTRL; /* External Oscillator Control Register */ 288 register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ 289 register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ 290 register8_t PLLCTRL; /* PLL Control REgister */ 291 register8_t DFLLCTRL; /* DFLL Control Register */ 292 } OSC_t; 293 294 /* Oscillator Frequency Range */ 295 typedef enum OSC_FRQRANGE_enum 296 { 297 OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ 298 OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ 299 OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ 300 OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ 301 } OSC_FRQRANGE_t; 302 303 /* External Oscillator Selection and Startup Time */ 304 typedef enum OSC_XOSCSEL_enum 305 { 306 OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ 307 OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ 308 OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ 309 OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ 310 OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ 311 } OSC_XOSCSEL_t; 312 313 /* PLL Clock Source */ 314 typedef enum OSC_PLLSRC_enum 315 { 316 OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ 317 OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ 318 OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ 319 } OSC_PLLSRC_t; 320 321 322 /* 323 -------------------------------------------------------------------------- 324 DFLL - DFLL 325 -------------------------------------------------------------------------- 326 */ 327 328 /* DFLL */ 329 typedef struct DFLL_struct 330 { 331 register8_t CTRL; /* Control Register */ 332 register8_t reserved_0x01; 333 register8_t CALA; /* Calibration Register A */ 334 register8_t CALB; /* Calibration Register B */ 335 register8_t COMP0; /* Oscillator Compare Register 0 */ 336 register8_t COMP1; /* Oscillator Compare Register 1 */ 337 register8_t COMP2; /* Oscillator Compare Register 2 */ 338 register8_t reserved_0x07; 339 } DFLL_t; 340 341 342 /* 343 -------------------------------------------------------------------------- 344 RST - Reset 345 -------------------------------------------------------------------------- 346 */ 347 348 /* Reset */ 349 typedef struct RST_struct 350 { 351 register8_t STATUS; /* Status Register */ 352 register8_t CTRL; /* Control Register */ 353 } RST_t; 354 355 356 /* 357 -------------------------------------------------------------------------- 358 WDT - Watch-Dog Timer 359 -------------------------------------------------------------------------- 360 */ 361 362 /* Watch-Dog Timer */ 363 typedef struct WDT_struct 364 { 365 register8_t CTRL; /* Control */ 366 register8_t WINCTRL; /* Windowed Mode Control */ 367 register8_t STATUS; /* Status */ 368 } WDT_t; 369 370 /* Period setting */ 371 typedef enum WDT_PER_enum 372 { 373 WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ 374 WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ 375 WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ 376 WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ 377 WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ 378 WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ 379 WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ 380 WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ 381 WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ 382 WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ 383 WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ 384 } WDT_PER_t; 385 386 /* Closed window period */ 387 typedef enum WDT_WPER_enum 388 { 389 WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ 390 WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ 391 WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ 392 WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ 393 WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ 394 WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ 395 WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ 396 WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ 397 WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ 398 WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ 399 WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ 400 } WDT_WPER_t; 401 402 403 /* 404 -------------------------------------------------------------------------- 405 MCU - MCU Control 406 -------------------------------------------------------------------------- 407 */ 408 409 /* MCU Control */ 410 typedef struct MCU_struct 411 { 412 register8_t DEVID0; /* Device ID byte 0 */ 413 register8_t DEVID1; /* Device ID byte 1 */ 414 register8_t DEVID2; /* Device ID byte 2 */ 415 register8_t REVID; /* Revision ID */ 416 register8_t JTAGUID; /* JTAG User ID */ 417 register8_t reserved_0x05; 418 register8_t MCUCR; /* MCU Control */ 419 register8_t reserved_0x07; 420 register8_t EVSYSLOCK; /* Event System Lock */ 421 register8_t AWEXLOCK; /* AWEX Lock */ 422 register8_t reserved_0x0A; 423 register8_t reserved_0x0B; 424 } MCU_t; 425 426 427 /* 428 -------------------------------------------------------------------------- 429 PMIC - Programmable Multi-level Interrupt Controller 430 -------------------------------------------------------------------------- 431 */ 432 433 /* Programmable Multi-level Interrupt Controller */ 434 typedef struct PMIC_struct 435 { 436 register8_t STATUS; /* Status Register */ 437 register8_t INTPRI; /* Interrupt Priority */ 438 register8_t CTRL; /* Control Register */ 439 } PMIC_t; 440 441 442 /* 443 -------------------------------------------------------------------------- 444 DMA - DMA Controller 445 -------------------------------------------------------------------------- 446 */ 447 448 /* DMA Channel */ 449 typedef struct DMA_CH_struct 450 { 451 register8_t CTRLA; /* Channel Control */ 452 register8_t CTRLB; /* Channel Control */ 453 register8_t ADDRCTRL; /* Address Control */ 454 register8_t TRIGSRC; /* Channel Trigger Source */ 455 _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ 456 register8_t REPCNT; /* Channel Repeat Count */ 457 register8_t reserved_0x07; 458 register8_t SRCADDR0; /* Channel Source Address 0 */ 459 register8_t SRCADDR1; /* Channel Source Address 1 */ 460 register8_t SRCADDR2; /* Channel Source Address 2 */ 461 register8_t reserved_0x0B; 462 register8_t DESTADDR0; /* Channel Destination Address 0 */ 463 register8_t DESTADDR1; /* Channel Destination Address 1 */ 464 register8_t DESTADDR2; /* Channel Destination Address 2 */ 465 register8_t reserved_0x0F; 466 } DMA_CH_t; 467 468 /* 469 -------------------------------------------------------------------------- 470 DMA - DMA Controller 471 -------------------------------------------------------------------------- 472 */ 473 474 /* DMA Controller */ 475 typedef struct DMA_struct 476 { 477 register8_t CTRL; /* Control */ 478 register8_t reserved_0x01; 479 register8_t reserved_0x02; 480 register8_t INTFLAGS; /* Transfer Interrupt Status */ 481 register8_t STATUS; /* Status */ 482 register8_t reserved_0x05; 483 _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ 484 register8_t reserved_0x08; 485 register8_t reserved_0x09; 486 register8_t reserved_0x0A; 487 register8_t reserved_0x0B; 488 register8_t reserved_0x0C; 489 register8_t reserved_0x0D; 490 register8_t reserved_0x0E; 491 register8_t reserved_0x0F; 492 DMA_CH_t CH0; /* DMA Channel 0 */ 493 DMA_CH_t CH1; /* DMA Channel 1 */ 494 DMA_CH_t CH2; /* DMA Channel 2 */ 495 DMA_CH_t CH3; /* DMA Channel 3 */ 496 } DMA_t; 497 498 /* Burst mode */ 499 typedef enum DMA_CH_BURSTLEN_enum 500 { 501 DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ 502 DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ 503 DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ 504 DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ 505 } DMA_CH_BURSTLEN_t; 506 507 /* Source address reload mode */ 508 typedef enum DMA_CH_SRCRELOAD_enum 509 { 510 DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ 511 DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ 512 DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ 513 DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ 514 } DMA_CH_SRCRELOAD_t; 515 516 /* Source addressing mode */ 517 typedef enum DMA_CH_SRCDIR_enum 518 { 519 DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ 520 DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ 521 DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ 522 } DMA_CH_SRCDIR_t; 523 524 /* Destination adress reload mode */ 525 typedef enum DMA_CH_DESTRELOAD_enum 526 { 527 DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ 528 DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ 529 DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ 530 DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ 531 } DMA_CH_DESTRELOAD_t; 532 533 /* Destination adressing mode */ 534 typedef enum DMA_CH_DESTDIR_enum 535 { 536 DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ 537 DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ 538 DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ 539 } DMA_CH_DESTDIR_t; 540 541 /* Transfer trigger source */ 542 typedef enum DMA_CH_TRIGSRC_enum 543 { 544 DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ 545 DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ 546 DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ 547 DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ 548 DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ 549 DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ 550 DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ 551 DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ 552 DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ 553 DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ 554 DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ 555 DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ 556 DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ 557 DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ 558 DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ 559 DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ 560 DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ 561 DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ 562 DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ 563 DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ 564 DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ 565 DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ 566 DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ 567 DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ 568 DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ 569 DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ 570 DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ 571 DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ 572 DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ 573 DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ 574 DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ 575 DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ 576 DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ 577 DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ 578 DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ 579 DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ 580 DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ 581 DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ 582 DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ 583 DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ 584 DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ 585 DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ 586 DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ 587 DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ 588 DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ 589 DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ 590 DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ 591 DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ 592 DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ 593 DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ 594 DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ 595 DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ 596 DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ 597 DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ 598 DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ 599 DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ 600 DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ 601 DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ 602 DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ 603 DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ 604 DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ 605 DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ 606 DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ 607 DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ 608 DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ 609 DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ 610 DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ 611 DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ 612 DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ 613 DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ 614 DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ 615 DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ 616 DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ 617 DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ 618 DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ 619 DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ 620 DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ 621 DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ 622 } DMA_CH_TRIGSRC_t; 623 624 /* Double buffering mode */ 625 typedef enum DMA_DBUFMODE_enum 626 { 627 DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ 628 DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ 629 DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ 630 DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ 631 } DMA_DBUFMODE_t; 632 633 /* Priority mode */ 634 typedef enum DMA_PRIMODE_enum 635 { 636 DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ 637 DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ 638 DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ 639 DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ 640 } DMA_PRIMODE_t; 641 642 /* Interrupt level */ 643 typedef enum DMA_CH_ERRINTLVL_enum 644 { 645 DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ 646 DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ 647 DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ 648 DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ 649 } DMA_CH_ERRINTLVL_t; 650 651 /* Interrupt level */ 652 typedef enum DMA_CH_TRNINTLVL_enum 653 { 654 DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 655 DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ 656 DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ 657 DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ 658 } DMA_CH_TRNINTLVL_t; 659 660 661 /* 662 -------------------------------------------------------------------------- 663 EVSYS - Event System 664 -------------------------------------------------------------------------- 665 */ 666 667 /* Event System */ 668 typedef struct EVSYS_struct 669 { 670 register8_t CH0MUX; /* Event Channel 0 Multiplexer */ 671 register8_t CH1MUX; /* Event Channel 1 Multiplexer */ 672 register8_t CH2MUX; /* Event Channel 2 Multiplexer */ 673 register8_t CH3MUX; /* Event Channel 3 Multiplexer */ 674 register8_t CH4MUX; /* Event Channel 4 Multiplexer */ 675 register8_t CH5MUX; /* Event Channel 5 Multiplexer */ 676 register8_t CH6MUX; /* Event Channel 6 Multiplexer */ 677 register8_t CH7MUX; /* Event Channel 7 Multiplexer */ 678 register8_t CH0CTRL; /* Channel 0 Control Register */ 679 register8_t CH1CTRL; /* Channel 1 Control Register */ 680 register8_t CH2CTRL; /* Channel 2 Control Register */ 681 register8_t CH3CTRL; /* Channel 3 Control Register */ 682 register8_t CH4CTRL; /* Channel 4 Control Register */ 683 register8_t CH5CTRL; /* Channel 5 Control Register */ 684 register8_t CH6CTRL; /* Channel 6 Control Register */ 685 register8_t CH7CTRL; /* Channel 7 Control Register */ 686 register8_t STROBE; /* Event Strobe */ 687 register8_t DATA; /* Event Data */ 688 } EVSYS_t; 689 690 /* Quadrature Decoder Index Recognition Mode */ 691 typedef enum EVSYS_QDIRM_enum 692 { 693 EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ 694 EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ 695 EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ 696 EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ 697 } EVSYS_QDIRM_t; 698 699 /* Digital filter coefficient */ 700 typedef enum EVSYS_DIGFILT_enum 701 { 702 EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ 703 EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ 704 EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ 705 EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ 706 EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ 707 EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ 708 EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ 709 EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ 710 } EVSYS_DIGFILT_t; 711 712 /* Event Channel multiplexer input selection */ 713 typedef enum EVSYS_CHMUX_enum 714 { 715 EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ 716 EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ 717 EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ 718 EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ 719 EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ 720 EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ 721 EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ 722 EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ 723 EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ 724 EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ 725 EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ 726 EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ 727 EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ 728 EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ 729 EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ 730 EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ 731 EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ 732 EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ 733 EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ 734 EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ 735 EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ 736 EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ 737 EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ 738 EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ 739 EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ 740 EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ 741 EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ 742 EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ 743 EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ 744 EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ 745 EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ 746 EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ 747 EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ 748 EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ 749 EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ 750 EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ 751 EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ 752 EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ 753 EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ 754 EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ 755 EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ 756 EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ 757 EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ 758 EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ 759 EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ 760 EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ 761 EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ 762 EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ 763 EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ 764 EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ 765 EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ 766 EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ 767 EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ 768 EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ 769 EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ 770 EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ 771 EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ 772 EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ 773 EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ 774 EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ 775 EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ 776 EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ 777 EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ 778 EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ 779 EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ 780 EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ 781 EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ 782 EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ 783 EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ 784 EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ 785 EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ 786 EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ 787 EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ 788 EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ 789 EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ 790 EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ 791 EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ 792 EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ 793 EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ 794 EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ 795 EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ 796 EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ 797 EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ 798 EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ 799 EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ 800 EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ 801 EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ 802 EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ 803 EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ 804 EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ 805 EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ 806 EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ 807 EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ 808 EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ 809 EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ 810 EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ 811 EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ 812 EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ 813 EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ 814 EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ 815 EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ 816 EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ 817 EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ 818 EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ 819 EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ 820 EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ 821 EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ 822 EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ 823 EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ 824 EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ 825 EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ 826 EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ 827 EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ 828 EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ 829 EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ 830 EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ 831 EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ 832 EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ 833 EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ 834 EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ 835 EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ 836 } EVSYS_CHMUX_t; 837 838 839 /* 840 -------------------------------------------------------------------------- 841 NVM - Non Volatile Memory Controller 842 -------------------------------------------------------------------------- 843 */ 844 845 /* Non-volatile Memory Controller */ 846 typedef struct NVM_struct 847 { 848 register8_t ADDR0; /* Address Register 0 */ 849 register8_t ADDR1; /* Address Register 1 */ 850 register8_t ADDR2; /* Address Register 2 */ 851 register8_t reserved_0x03; 852 register8_t DATA0; /* Data Register 0 */ 853 register8_t DATA1; /* Data Register 1 */ 854 register8_t DATA2; /* Data Register 2 */ 855 register8_t reserved_0x07; 856 register8_t reserved_0x08; 857 register8_t reserved_0x09; 858 register8_t CMD; /* Command */ 859 register8_t CTRLA; /* Control Register A */ 860 register8_t CTRLB; /* Control Register B */ 861 register8_t INTCTRL; /* Interrupt Control */ 862 register8_t reserved_0x0E; 863 register8_t STATUS; /* Status */ 864 register8_t LOCK_BITS; /* Lock Bits */ 865 } NVM_t; 866 867 /* 868 -------------------------------------------------------------------------- 869 NVM - Non Volatile Memory Controller 870 -------------------------------------------------------------------------- 871 */ 872 873 /* Lock Bits */ 874 typedef struct NVM_LOCKBITS_struct 875 { 876 register8_t LOCKBITS; /* Lock Bits */ 877 } NVM_LOCKBITS_t; 878 879 /* 880 -------------------------------------------------------------------------- 881 NVM - Non Volatile Memory Controller 882 -------------------------------------------------------------------------- 883 */ 884 885 /* Fuses */ 886 typedef struct NVM_FUSES_struct 887 { 888 register8_t FUSEBYTE0; /* JTAG User ID */ 889 register8_t FUSEBYTE1; /* Watchdog Configuration */ 890 register8_t FUSEBYTE2; /* Reset Configuration */ 891 register8_t reserved_0x03; 892 register8_t FUSEBYTE4; /* Start-up Configuration */ 893 register8_t FUSEBYTE5; /* EESAVE and BOD Level */ 894 } NVM_FUSES_t; 895 896 /* 897 -------------------------------------------------------------------------- 898 NVM - Non Volatile Memory Controller 899 -------------------------------------------------------------------------- 900 */ 901 902 /* Production Signatures */ 903 typedef struct NVM_PROD_SIGNATURES_struct 904 { 905 register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ 906 register8_t reserved_0x01; 907 register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ 908 register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ 909 register8_t reserved_0x04; 910 register8_t reserved_0x05; 911 register8_t reserved_0x06; 912 register8_t reserved_0x07; 913 register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ 914 register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ 915 register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ 916 register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ 917 register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ 918 register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ 919 register8_t reserved_0x0E; 920 register8_t reserved_0x0F; 921 register8_t WAFNUM; /* Wafer Number */ 922 register8_t reserved_0x11; 923 register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ 924 register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ 925 register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ 926 register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ 927 register8_t reserved_0x16; 928 register8_t reserved_0x17; 929 register8_t reserved_0x18; 930 register8_t reserved_0x19; 931 register8_t reserved_0x1A; 932 register8_t reserved_0x1B; 933 register8_t reserved_0x1C; 934 register8_t reserved_0x1D; 935 register8_t reserved_0x1E; 936 register8_t reserved_0x1F; 937 register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ 938 register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ 939 register8_t reserved_0x22; 940 register8_t reserved_0x23; 941 register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ 942 register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ 943 register8_t reserved_0x26; 944 register8_t reserved_0x27; 945 register8_t reserved_0x28; 946 register8_t reserved_0x29; 947 register8_t reserved_0x2A; 948 register8_t reserved_0x2B; 949 register8_t reserved_0x2C; 950 register8_t reserved_0x2D; 951 register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ 952 register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ 953 register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ 954 register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ 955 register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ 956 register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ 957 register8_t reserved_0x34; 958 register8_t reserved_0x35; 959 register8_t reserved_0x36; 960 register8_t reserved_0x37; 961 register8_t reserved_0x38; 962 register8_t reserved_0x39; 963 register8_t reserved_0x3A; 964 register8_t reserved_0x3B; 965 register8_t reserved_0x3C; 966 register8_t reserved_0x3D; 967 register8_t reserved_0x3E; 968 } NVM_PROD_SIGNATURES_t; 969 970 /* NVM Command */ 971 typedef enum NVM_CMD_enum 972 { 973 NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ 974 NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ 975 NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ 976 NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ 977 NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ 978 NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ 979 NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ 980 NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ 981 NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ 982 NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ 983 NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ 984 NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ 985 NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ 986 NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ 987 NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ 988 NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ 989 NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ 990 NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ 991 NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ 992 NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ 993 NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ 994 NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ 995 NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ 996 NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ 997 NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ 998 NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ 999 } NVM_CMD_t; 1000 1001 /* SPM ready interrupt level */ 1002 typedef enum NVM_SPMLVL_enum 1003 { 1004 NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ 1005 NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ 1006 NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ 1007 NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ 1008 } NVM_SPMLVL_t; 1009 1010 /* EEPROM ready interrupt level */ 1011 typedef enum NVM_EELVL_enum 1012 { 1013 NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1014 NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ 1015 NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ 1016 NVM_EELVL_HI_gc = (0x03<<0), /* High level */ 1017 } NVM_EELVL_t; 1018 1019 /* Boot lock bits - boot setcion */ 1020 typedef enum NVM_BLBB_enum 1021 { 1022 NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ 1023 NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ 1024 NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ 1025 NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ 1026 } NVM_BLBB_t; 1027 1028 /* Boot lock bits - application section */ 1029 typedef enum NVM_BLBA_enum 1030 { 1031 NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ 1032 NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ 1033 NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ 1034 NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ 1035 } NVM_BLBA_t; 1036 1037 /* Boot lock bits - application table section */ 1038 typedef enum NVM_BLBAT_enum 1039 { 1040 NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ 1041 NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ 1042 NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ 1043 NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ 1044 } NVM_BLBAT_t; 1045 1046 /* Lock bits */ 1047 typedef enum NVM_LB_enum 1048 { 1049 NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ 1050 NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ 1051 NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ 1052 } NVM_LB_t; 1053 1054 /* Boot Loader Section Reset Vector */ 1055 typedef enum BOOTRST_enum 1056 { 1057 BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ 1058 BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ 1059 } BOOTRST_t; 1060 1061 /* BOD operation */ 1062 typedef enum BOD_enum 1063 { 1064 BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ 1065 BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ 1066 BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ 1067 } BOD_t; 1068 1069 /* Watchdog (Window) Timeout Period */ 1070 typedef enum WD_enum 1071 { 1072 WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ 1073 WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ 1074 WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ 1075 WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ 1076 WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ 1077 WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ 1078 WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ 1079 WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ 1080 WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ 1081 WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ 1082 WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ 1083 } WD_t; 1084 1085 /* Start-up Time */ 1086 typedef enum SUT_enum 1087 { 1088 SUT_0MS_gc = (0x03<<2), /* 0 ms */ 1089 SUT_4MS_gc = (0x01<<2), /* 4 ms */ 1090 SUT_64MS_gc = (0x00<<2), /* 64 ms */ 1091 } SUT_t; 1092 1093 /* Brown Out Detection Voltage Level */ 1094 typedef enum BODLVL_enum 1095 { 1096 BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ 1097 BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ 1098 BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ 1099 BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ 1100 BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ 1101 BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ 1102 BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ 1103 } BODLVL_t; 1104 1105 1106 /* 1107 -------------------------------------------------------------------------- 1108 AC - Analog Comparator 1109 -------------------------------------------------------------------------- 1110 */ 1111 1112 /* Analog Comparator */ 1113 typedef struct AC_struct 1114 { 1115 register8_t AC0CTRL; /* Comparator 0 Control */ 1116 register8_t AC1CTRL; /* Comparator 1 Control */ 1117 register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ 1118 register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ 1119 register8_t CTRLA; /* Control Register A */ 1120 register8_t CTRLB; /* Control Register B */ 1121 register8_t WINCTRL; /* Window Mode Control */ 1122 register8_t STATUS; /* Status */ 1123 } AC_t; 1124 1125 /* Interrupt mode */ 1126 typedef enum AC_INTMODE_enum 1127 { 1128 AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ 1129 AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ 1130 AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ 1131 } AC_INTMODE_t; 1132 1133 /* Interrupt level */ 1134 typedef enum AC_INTLVL_enum 1135 { 1136 AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ 1137 AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ 1138 AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ 1139 AC_INTLVL_HI_gc = (0x03<<4), /* High level */ 1140 } AC_INTLVL_t; 1141 1142 /* Hysteresis mode selection */ 1143 typedef enum AC_HYSMODE_enum 1144 { 1145 AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ 1146 AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ 1147 AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ 1148 } AC_HYSMODE_t; 1149 1150 /* Positive input multiplexer selection */ 1151 typedef enum AC_MUXPOS_enum 1152 { 1153 AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ 1154 AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ 1155 AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ 1156 AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ 1157 AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ 1158 AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ 1159 AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ 1160 AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ 1161 } AC_MUXPOS_t; 1162 1163 /* Negative input multiplexer selection */ 1164 typedef enum AC_MUXNEG_enum 1165 { 1166 AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ 1167 AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ 1168 AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ 1169 AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ 1170 AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ 1171 AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ 1172 AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ 1173 AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ 1174 } AC_MUXNEG_t; 1175 1176 /* Windows interrupt mode */ 1177 typedef enum AC_WINTMODE_enum 1178 { 1179 AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ 1180 AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ 1181 AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ 1182 AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ 1183 } AC_WINTMODE_t; 1184 1185 /* Window interrupt level */ 1186 typedef enum AC_WINTLVL_enum 1187 { 1188 AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1189 AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ 1190 AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ 1191 AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ 1192 } AC_WINTLVL_t; 1193 1194 /* Window mode state */ 1195 typedef enum AC_WSTATE_enum 1196 { 1197 AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ 1198 AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ 1199 AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ 1200 } AC_WSTATE_t; 1201 1202 1203 /* 1204 -------------------------------------------------------------------------- 1205 ADC - Analog/Digital Converter 1206 -------------------------------------------------------------------------- 1207 */ 1208 1209 /* ADC Channel */ 1210 typedef struct ADC_CH_struct 1211 { 1212 register8_t CTRL; /* Control Register */ 1213 register8_t MUXCTRL; /* MUX Control */ 1214 register8_t INTCTRL; /* Channel Interrupt Control */ 1215 register8_t INTFLAGS; /* Interrupt Flags */ 1216 _WORDREGISTER(RES); /* Channel Result */ 1217 register8_t reserved_0x6; 1218 register8_t reserved_0x7; 1219 } ADC_CH_t; 1220 1221 /* 1222 -------------------------------------------------------------------------- 1223 ADC - Analog/Digital Converter 1224 -------------------------------------------------------------------------- 1225 */ 1226 1227 /* Analog-to-Digital Converter */ 1228 typedef struct ADC_struct 1229 { 1230 register8_t CTRLA; /* Control Register A */ 1231 register8_t CTRLB; /* Control Register B */ 1232 register8_t REFCTRL; /* Reference Control */ 1233 register8_t EVCTRL; /* Event Control */ 1234 register8_t PRESCALER; /* Clock Prescaler */ 1235 register8_t reserved_0x05; 1236 register8_t INTFLAGS; /* Interrupt Flags */ 1237 register8_t reserved_0x07; 1238 register8_t reserved_0x08; 1239 register8_t reserved_0x09; 1240 register8_t reserved_0x0A; 1241 register8_t reserved_0x0B; 1242 _WORDREGISTER(CAL); /* Calibration Value */ 1243 register8_t reserved_0x0E; 1244 register8_t reserved_0x0F; 1245 _WORDREGISTER(CH0RES); /* Channel 0 Result */ 1246 _WORDREGISTER(CH1RES); /* Channel 1 Result */ 1247 _WORDREGISTER(CH2RES); /* Channel 2 Result */ 1248 _WORDREGISTER(CH3RES); /* Channel 3 Result */ 1249 _WORDREGISTER(CMP); /* Compare Value */ 1250 register8_t reserved_0x1A; 1251 register8_t reserved_0x1B; 1252 register8_t reserved_0x1C; 1253 register8_t reserved_0x1D; 1254 register8_t reserved_0x1E; 1255 register8_t reserved_0x1F; 1256 ADC_CH_t CH0; /* ADC Channel 0 */ 1257 ADC_CH_t CH1; /* ADC Channel 1 */ 1258 ADC_CH_t CH2; /* ADC Channel 2 */ 1259 ADC_CH_t CH3; /* ADC Channel 3 */ 1260 } ADC_t; 1261 1262 /* Positive input multiplexer selection */ 1263 typedef enum ADC_CH_MUXPOS_enum 1264 { 1265 ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ 1266 ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ 1267 ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ 1268 ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ 1269 ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ 1270 ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ 1271 ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ 1272 ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ 1273 } ADC_CH_MUXPOS_t; 1274 1275 /* Internal input multiplexer selections */ 1276 typedef enum ADC_CH_MUXINT_enum 1277 { 1278 ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ 1279 ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ 1280 ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ 1281 ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ 1282 } ADC_CH_MUXINT_t; 1283 1284 /* Negative input multiplexer selection */ 1285 typedef enum ADC_CH_MUXNEG_enum 1286 { 1287 ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ 1288 ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ 1289 ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ 1290 ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ 1291 ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ 1292 ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ 1293 ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ 1294 ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ 1295 } ADC_CH_MUXNEG_t; 1296 1297 /* Input mode */ 1298 typedef enum ADC_CH_INPUTMODE_enum 1299 { 1300 ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ 1301 ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ 1302 ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ 1303 ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ 1304 } ADC_CH_INPUTMODE_t; 1305 1306 /* Gain factor */ 1307 typedef enum ADC_CH_GAIN_enum 1308 { 1309 ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ 1310 ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ 1311 ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ 1312 ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ 1313 ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ 1314 ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ 1315 ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ 1316 } ADC_CH_GAIN_t; 1317 1318 /* Conversion result resolution */ 1319 typedef enum ADC_RESOLUTION_enum 1320 { 1321 ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ 1322 ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ 1323 ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ 1324 } ADC_RESOLUTION_t; 1325 1326 /* Voltage reference selection */ 1327 typedef enum ADC_REFSEL_enum 1328 { 1329 ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ 1330 ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ 1331 ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ 1332 ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ 1333 } ADC_REFSEL_t; 1334 1335 /* Channel sweep selection */ 1336 typedef enum ADC_SWEEP_enum 1337 { 1338 ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ 1339 ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ 1340 ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ 1341 ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ 1342 } ADC_SWEEP_t; 1343 1344 /* Event channel input selection */ 1345 typedef enum ADC_EVSEL_enum 1346 { 1347 ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ 1348 ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ 1349 ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ 1350 ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ 1351 ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ 1352 ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ 1353 ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ 1354 ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ 1355 } ADC_EVSEL_t; 1356 1357 /* Event action selection */ 1358 typedef enum ADC_EVACT_enum 1359 { 1360 ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ 1361 ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ 1362 ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ 1363 ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ 1364 ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ 1365 ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ 1366 ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ 1367 } ADC_EVACT_t; 1368 1369 /* Interupt mode */ 1370 typedef enum ADC_CH_INTMODE_enum 1371 { 1372 ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ 1373 ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ 1374 ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ 1375 } ADC_CH_INTMODE_t; 1376 1377 /* Interrupt level */ 1378 typedef enum ADC_CH_INTLVL_enum 1379 { 1380 ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1381 ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ 1382 ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ 1383 ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ 1384 } ADC_CH_INTLVL_t; 1385 1386 /* DMA request selection */ 1387 typedef enum ADC_DMASEL_enum 1388 { 1389 ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ 1390 ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ 1391 ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ 1392 ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ 1393 } ADC_DMASEL_t; 1394 1395 /* Clock prescaler */ 1396 typedef enum ADC_PRESCALER_enum 1397 { 1398 ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ 1399 ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ 1400 ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ 1401 ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ 1402 ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ 1403 ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ 1404 ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ 1405 ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ 1406 } ADC_PRESCALER_t; 1407 1408 1409 /* 1410 -------------------------------------------------------------------------- 1411 DAC - Digital/Analog Converter 1412 -------------------------------------------------------------------------- 1413 */ 1414 1415 /* Digital-to-Analog Converter */ 1416 typedef struct DAC_struct 1417 { 1418 register8_t CTRLA; /* Control Register A */ 1419 register8_t CTRLB; /* Control Register B */ 1420 register8_t CTRLC; /* Control Register C */ 1421 register8_t EVCTRL; /* Event Input Control */ 1422 register8_t TIMCTRL; /* Timing Control */ 1423 register8_t STATUS; /* Status */ 1424 register8_t reserved_0x06; 1425 register8_t reserved_0x07; 1426 register8_t GAINCAL; /* Gain Calibration */ 1427 register8_t OFFSETCAL; /* Offset Calibration */ 1428 register8_t reserved_0x0A; 1429 register8_t reserved_0x0B; 1430 register8_t reserved_0x0C; 1431 register8_t reserved_0x0D; 1432 register8_t reserved_0x0E; 1433 register8_t reserved_0x0F; 1434 register8_t reserved_0x10; 1435 register8_t reserved_0x11; 1436 register8_t reserved_0x12; 1437 register8_t reserved_0x13; 1438 register8_t reserved_0x14; 1439 register8_t reserved_0x15; 1440 register8_t reserved_0x16; 1441 register8_t reserved_0x17; 1442 _WORDREGISTER(CH0DATA); /* Channel 0 Data */ 1443 _WORDREGISTER(CH1DATA); /* Channel 1 Data */ 1444 } DAC_t; 1445 1446 /* Output channel selection */ 1447 typedef enum DAC_CHSEL_enum 1448 { 1449 DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ 1450 DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ 1451 } DAC_CHSEL_t; 1452 1453 /* Reference voltage selection */ 1454 typedef enum DAC_REFSEL_enum 1455 { 1456 DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ 1457 DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ 1458 DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ 1459 DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ 1460 } DAC_REFSEL_t; 1461 1462 /* Event channel selection */ 1463 typedef enum DAC_EVSEL_enum 1464 { 1465 DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ 1466 DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ 1467 DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ 1468 DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ 1469 DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ 1470 DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ 1471 DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ 1472 DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ 1473 } DAC_EVSEL_t; 1474 1475 /* Conversion interval */ 1476 typedef enum DAC_CONINTVAL_enum 1477 { 1478 DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ 1479 DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ 1480 DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ 1481 DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ 1482 DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ 1483 DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ 1484 DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ 1485 DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ 1486 } DAC_CONINTVAL_t; 1487 1488 /* Refresh rate */ 1489 typedef enum DAC_REFRESH_enum 1490 { 1491 DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ 1492 DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ 1493 DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ 1494 DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ 1495 DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ 1496 DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ 1497 DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ 1498 DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ 1499 DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ 1500 DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ 1501 DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ 1502 DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ 1503 DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ 1504 DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ 1505 } DAC_REFRESH_t; 1506 1507 1508 /* 1509 -------------------------------------------------------------------------- 1510 RTC32 - 32-bit Real-Time Counter 1511 -------------------------------------------------------------------------- 1512 */ 1513 1514 /* 32-bit Real-Time Clounter */ 1515 typedef struct RTC32_struct 1516 { 1517 register8_t CTRL; /* Control Register */ 1518 register8_t SYNCCTRL; /* Synchronization Control/Status Register */ 1519 register8_t INTCTRL; /* Interrupt Control Register */ 1520 register8_t INTFLAGS; /* Interrupt Flags */ 1521 _DWORDREGISTER(CNT); /* Count Register */ 1522 _DWORDREGISTER(PER); /* Period Register */ 1523 _DWORDREGISTER(COMP); /* Compare Register */ 1524 } RTC32_t; 1525 1526 /* Compare Interrupt level */ 1527 typedef enum RTC32_COMPINTLVL_enum 1528 { 1529 RTC32_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1530 RTC32_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1531 RTC32_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1532 RTC32_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ 1533 } RTC32_COMPINTLVL_t; 1534 1535 /* Overflow Interrupt level */ 1536 typedef enum RTC32_OVFINTLVL_enum 1537 { 1538 RTC32_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1539 RTC32_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1540 RTC32_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1541 RTC32_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ 1542 } RTC32_OVFINTLVL_t; 1543 1544 1545 /* 1546 -------------------------------------------------------------------------- 1547 EBI - External Bus Interface 1548 -------------------------------------------------------------------------- 1549 */ 1550 1551 /* EBI Chip Select Module */ 1552 typedef struct EBI_CS_struct 1553 { 1554 register8_t CTRLA; /* Chip Select Control Register A */ 1555 register8_t CTRLB; /* Chip Select Control Register B */ 1556 _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ 1557 } EBI_CS_t; 1558 1559 /* 1560 -------------------------------------------------------------------------- 1561 EBI - External Bus Interface 1562 -------------------------------------------------------------------------- 1563 */ 1564 1565 /* External Bus Interface */ 1566 typedef struct EBI_struct 1567 { 1568 register8_t CTRL; /* Control */ 1569 register8_t SDRAMCTRLA; /* SDRAM Control Register A */ 1570 register8_t reserved_0x02; 1571 register8_t reserved_0x03; 1572 _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ 1573 _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ 1574 register8_t SDRAMCTRLB; /* SDRAM Control Register B */ 1575 register8_t SDRAMCTRLC; /* SDRAM Control Register C */ 1576 register8_t reserved_0x0A; 1577 register8_t reserved_0x0B; 1578 register8_t reserved_0x0C; 1579 register8_t reserved_0x0D; 1580 register8_t reserved_0x0E; 1581 register8_t reserved_0x0F; 1582 EBI_CS_t CS0; /* Chip Select 0 */ 1583 EBI_CS_t CS1; /* Chip Select 1 */ 1584 EBI_CS_t CS2; /* Chip Select 2 */ 1585 EBI_CS_t CS3; /* Chip Select 3 */ 1586 } EBI_t; 1587 1588 /* Chip Select adress space */ 1589 typedef enum EBI_CS_ASIZE_enum 1590 { 1591 EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ 1592 EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ 1593 EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ 1594 EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ 1595 EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ 1596 EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ 1597 EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ 1598 EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ 1599 EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ 1600 EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ 1601 EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ 1602 EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ 1603 EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ 1604 EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ 1605 EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ 1606 EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ 1607 EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ 1608 } EBI_CS_ASIZE_t; 1609 1610 /* */ 1611 typedef enum EBI_CS_SRWS_enum 1612 { 1613 EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ 1614 EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ 1615 EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ 1616 EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ 1617 EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ 1618 EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ 1619 EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ 1620 EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ 1621 } EBI_CS_SRWS_t; 1622 1623 /* Chip Select address mode */ 1624 typedef enum EBI_CS_MODE_enum 1625 { 1626 EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ 1627 EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ 1628 EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ 1629 EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ 1630 } EBI_CS_MODE_t; 1631 1632 /* Chip Select SDRAM mode */ 1633 typedef enum EBI_CS_SDMODE_enum 1634 { 1635 EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ 1636 EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ 1637 } EBI_CS_SDMODE_t; 1638 1639 /* */ 1640 typedef enum EBI_SDDATAW_enum 1641 { 1642 EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ 1643 EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ 1644 } EBI_SDDATAW_t; 1645 1646 /* */ 1647 typedef enum EBI_LPCMODE_enum 1648 { 1649 EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ 1650 EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ 1651 } EBI_LPCMODE_t; 1652 1653 /* */ 1654 typedef enum EBI_SRMODE_enum 1655 { 1656 EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ 1657 EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ 1658 EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ 1659 EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ 1660 } EBI_SRMODE_t; 1661 1662 /* */ 1663 typedef enum EBI_IFMODE_enum 1664 { 1665 EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ 1666 EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ 1667 EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ 1668 EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ 1669 } EBI_IFMODE_t; 1670 1671 /* */ 1672 typedef enum EBI_SDCOL_enum 1673 { 1674 EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ 1675 EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ 1676 EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ 1677 EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ 1678 } EBI_SDCOL_t; 1679 1680 /* */ 1681 typedef enum EBI_MRDLY_enum 1682 { 1683 EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ 1684 EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ 1685 EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ 1686 EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ 1687 } EBI_MRDLY_t; 1688 1689 /* */ 1690 typedef enum EBI_ROWCYCDLY_enum 1691 { 1692 EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ 1693 EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ 1694 EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ 1695 EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ 1696 EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ 1697 EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ 1698 EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ 1699 EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ 1700 } EBI_ROWCYCDLY_t; 1701 1702 /* */ 1703 typedef enum EBI_RPDLY_enum 1704 { 1705 EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ 1706 EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ 1707 EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ 1708 EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ 1709 EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ 1710 EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ 1711 EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ 1712 EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ 1713 } EBI_RPDLY_t; 1714 1715 /* */ 1716 typedef enum EBI_WRDLY_enum 1717 { 1718 EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ 1719 EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ 1720 EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ 1721 EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ 1722 } EBI_WRDLY_t; 1723 1724 /* */ 1725 typedef enum EBI_ESRDLY_enum 1726 { 1727 EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ 1728 EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ 1729 EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ 1730 EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ 1731 EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ 1732 EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ 1733 EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ 1734 EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ 1735 } EBI_ESRDLY_t; 1736 1737 /* */ 1738 typedef enum EBI_ROWCOLDLY_enum 1739 { 1740 EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ 1741 EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ 1742 EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ 1743 EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ 1744 EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ 1745 EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ 1746 EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ 1747 EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ 1748 } EBI_ROWCOLDLY_t; 1749 1750 1751 /* 1752 -------------------------------------------------------------------------- 1753 TWI - Two-Wire Interface 1754 -------------------------------------------------------------------------- 1755 */ 1756 1757 /* */ 1758 typedef struct TWI_MASTER_struct 1759 { 1760 register8_t CTRLA; /* Control Register A */ 1761 register8_t CTRLB; /* Control Register B */ 1762 register8_t CTRLC; /* Control Register C */ 1763 register8_t STATUS; /* Status Register */ 1764 register8_t BAUD; /* Baurd Rate Control Register */ 1765 register8_t ADDR; /* Address Register */ 1766 register8_t DATA; /* Data Register */ 1767 } TWI_MASTER_t; 1768 1769 /* 1770 -------------------------------------------------------------------------- 1771 TWI - Two-Wire Interface 1772 -------------------------------------------------------------------------- 1773 */ 1774 1775 /* */ 1776 typedef struct TWI_SLAVE_struct 1777 { 1778 register8_t CTRLA; /* Control Register A */ 1779 register8_t CTRLB; /* Control Register B */ 1780 register8_t STATUS; /* Status Register */ 1781 register8_t ADDR; /* Address Register */ 1782 register8_t DATA; /* Data Register */ 1783 register8_t ADDRMASK; /* Address Mask Register */ 1784 } TWI_SLAVE_t; 1785 1786 /* 1787 -------------------------------------------------------------------------- 1788 TWI - Two-Wire Interface 1789 -------------------------------------------------------------------------- 1790 */ 1791 1792 /* Two-Wire Interface */ 1793 typedef struct TWI_struct 1794 { 1795 register8_t CTRL; /* TWI Common Control Register */ 1796 TWI_MASTER_t MASTER; /* TWI master module */ 1797 TWI_SLAVE_t SLAVE; /* TWI slave module */ 1798 } TWI_t; 1799 1800 /* Master Interrupt Level */ 1801 typedef enum TWI_MASTER_INTLVL_enum 1802 { 1803 TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1804 TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ 1805 TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1806 TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ 1807 } TWI_MASTER_INTLVL_t; 1808 1809 /* Inactive Timeout */ 1810 typedef enum TWI_MASTER_TIMEOUT_enum 1811 { 1812 TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ 1813 TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ 1814 TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ 1815 TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ 1816 } TWI_MASTER_TIMEOUT_t; 1817 1818 /* Master Command */ 1819 typedef enum TWI_MASTER_CMD_enum 1820 { 1821 TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ 1822 TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ 1823 TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ 1824 TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ 1825 } TWI_MASTER_CMD_t; 1826 1827 /* Master Bus State */ 1828 typedef enum TWI_MASTER_BUSSTATE_enum 1829 { 1830 TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ 1831 TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ 1832 TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ 1833 TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ 1834 } TWI_MASTER_BUSSTATE_t; 1835 1836 /* Slave Interrupt Level */ 1837 typedef enum TWI_SLAVE_INTLVL_enum 1838 { 1839 TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1840 TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ 1841 TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1842 TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ 1843 } TWI_SLAVE_INTLVL_t; 1844 1845 /* Slave Command */ 1846 typedef enum TWI_SLAVE_CMD_enum 1847 { 1848 TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ 1849 TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ 1850 TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ 1851 } TWI_SLAVE_CMD_t; 1852 1853 1854 /* 1855 -------------------------------------------------------------------------- 1856 PORT - Port Configuration 1857 -------------------------------------------------------------------------- 1858 */ 1859 1860 /* I/O port Configuration */ 1861 typedef struct PORTCFG_struct 1862 { 1863 register8_t MPCMASK; /* Multi-pin Configuration Mask */ 1864 register8_t reserved_0x01; 1865 register8_t VPCTRLA; /* Virtual Port Control Register A */ 1866 register8_t VPCTRLB; /* Virtual Port Control Register B */ 1867 register8_t CLKEVOUT; /* Clock and Event Out Register */ 1868 } PORTCFG_t; 1869 1870 /* 1871 -------------------------------------------------------------------------- 1872 PORT - Port Configuration 1873 -------------------------------------------------------------------------- 1874 */ 1875 1876 /* Virtual Port */ 1877 typedef struct VPORT_struct 1878 { 1879 register8_t DIR; /* I/O Port Data Direction */ 1880 register8_t OUT; /* I/O Port Output */ 1881 register8_t IN; /* I/O Port Input */ 1882 register8_t INTFLAGS; /* Interrupt Flag Register */ 1883 } VPORT_t; 1884 1885 /* 1886 -------------------------------------------------------------------------- 1887 PORT - Port Configuration 1888 -------------------------------------------------------------------------- 1889 */ 1890 1891 /* I/O Ports */ 1892 typedef struct PORT_struct 1893 { 1894 register8_t DIR; /* I/O Port Data Direction */ 1895 register8_t DIRSET; /* I/O Port Data Direction Set */ 1896 register8_t DIRCLR; /* I/O Port Data Direction Clear */ 1897 register8_t DIRTGL; /* I/O Port Data Direction Toggle */ 1898 register8_t OUT; /* I/O Port Output */ 1899 register8_t OUTSET; /* I/O Port Output Set */ 1900 register8_t OUTCLR; /* I/O Port Output Clear */ 1901 register8_t OUTTGL; /* I/O Port Output Toggle */ 1902 register8_t IN; /* I/O port Input */ 1903 register8_t INTCTRL; /* Interrupt Control Register */ 1904 register8_t INT0MASK; /* Port Interrupt 0 Mask */ 1905 register8_t INT1MASK; /* Port Interrupt 1 Mask */ 1906 register8_t INTFLAGS; /* Interrupt Flag Register */ 1907 register8_t reserved_0x0D; 1908 register8_t reserved_0x0E; 1909 register8_t reserved_0x0F; 1910 register8_t PIN0CTRL; /* Pin 0 Control Register */ 1911 register8_t PIN1CTRL; /* Pin 1 Control Register */ 1912 register8_t PIN2CTRL; /* Pin 2 Control Register */ 1913 register8_t PIN3CTRL; /* Pin 3 Control Register */ 1914 register8_t PIN4CTRL; /* Pin 4 Control Register */ 1915 register8_t PIN5CTRL; /* Pin 5 Control Register */ 1916 register8_t PIN6CTRL; /* Pin 6 Control Register */ 1917 register8_t PIN7CTRL; /* Pin 7 Control Register */ 1918 } PORT_t; 1919 1920 /* Virtual Port 0 Mapping */ 1921 typedef enum PORTCFG_VP0MAP_enum 1922 { 1923 PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ 1924 PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ 1925 PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ 1926 PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ 1927 PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ 1928 PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ 1929 PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ 1930 PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ 1931 PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ 1932 PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ 1933 PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ 1934 PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ 1935 PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ 1936 PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ 1937 PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ 1938 PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ 1939 } PORTCFG_VP0MAP_t; 1940 1941 /* Virtual Port 1 Mapping */ 1942 typedef enum PORTCFG_VP1MAP_enum 1943 { 1944 PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ 1945 PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ 1946 PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ 1947 PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ 1948 PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ 1949 PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ 1950 PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ 1951 PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ 1952 PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ 1953 PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ 1954 PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ 1955 PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ 1956 PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ 1957 PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ 1958 PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ 1959 PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ 1960 } PORTCFG_VP1MAP_t; 1961 1962 /* Virtual Port 2 Mapping */ 1963 typedef enum PORTCFG_VP2MAP_enum 1964 { 1965 PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ 1966 PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ 1967 PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ 1968 PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ 1969 PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ 1970 PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ 1971 PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ 1972 PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ 1973 PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ 1974 PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ 1975 PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ 1976 PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ 1977 PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ 1978 PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ 1979 PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ 1980 PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ 1981 } PORTCFG_VP2MAP_t; 1982 1983 /* Virtual Port 3 Mapping */ 1984 typedef enum PORTCFG_VP3MAP_enum 1985 { 1986 PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ 1987 PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ 1988 PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ 1989 PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ 1990 PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ 1991 PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ 1992 PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ 1993 PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ 1994 PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ 1995 PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ 1996 PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ 1997 PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ 1998 PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ 1999 PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ 2000 PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ 2001 PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ 2002 } PORTCFG_VP3MAP_t; 2003 2004 /* Clock Output Port */ 2005 typedef enum PORTCFG_CLKOUT_enum 2006 { 2007 PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ 2008 PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ 2009 PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ 2010 PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ 2011 } PORTCFG_CLKOUT_t; 2012 2013 /* Event Output Port */ 2014 typedef enum PORTCFG_EVOUT_enum 2015 { 2016 PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ 2017 PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ 2018 PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ 2019 PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ 2020 } PORTCFG_EVOUT_t; 2021 2022 /* Port Interrupt 0 Level */ 2023 typedef enum PORT_INT0LVL_enum 2024 { 2025 PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2026 PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ 2027 PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ 2028 PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ 2029 } PORT_INT0LVL_t; 2030 2031 /* Port Interrupt 1 Level */ 2032 typedef enum PORT_INT1LVL_enum 2033 { 2034 PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 2035 PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ 2036 PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ 2037 PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ 2038 } PORT_INT1LVL_t; 2039 2040 /* Output/Pull Configuration */ 2041 typedef enum PORT_OPC_enum 2042 { 2043 PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ 2044 PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ 2045 PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ 2046 PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ 2047 PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ 2048 PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ 2049 PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ 2050 PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ 2051 } PORT_OPC_t; 2052 2053 /* Input/Sense Configuration */ 2054 typedef enum PORT_ISC_enum 2055 { 2056 PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ 2057 PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ 2058 PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ 2059 PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ 2060 PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ 2061 } PORT_ISC_t; 2062 2063 2064 /* 2065 -------------------------------------------------------------------------- 2066 TC - 16-bit Timer/Counter With PWM 2067 -------------------------------------------------------------------------- 2068 */ 2069 2070 /* 16-bit Timer/Counter 0 */ 2071 typedef struct TC0_struct 2072 { 2073 register8_t CTRLA; /* Control Register A */ 2074 register8_t CTRLB; /* Control Register B */ 2075 register8_t CTRLC; /* Control register C */ 2076 register8_t CTRLD; /* Control Register D */ 2077 register8_t CTRLE; /* Control Register E */ 2078 register8_t reserved_0x05; 2079 register8_t INTCTRLA; /* Interrupt Control Register A */ 2080 register8_t INTCTRLB; /* Interrupt Control Register B */ 2081 register8_t CTRLFCLR; /* Control Register F Clear */ 2082 register8_t CTRLFSET; /* Control Register F Set */ 2083 register8_t CTRLGCLR; /* Control Register G Clear */ 2084 register8_t CTRLGSET; /* Control Register G Set */ 2085 register8_t INTFLAGS; /* Interrupt Flag Register */ 2086 register8_t reserved_0x0D; 2087 register8_t reserved_0x0E; 2088 register8_t TEMP; /* Temporary Register For 16-bit Access */ 2089 register8_t reserved_0x10; 2090 register8_t reserved_0x11; 2091 register8_t reserved_0x12; 2092 register8_t reserved_0x13; 2093 register8_t reserved_0x14; 2094 register8_t reserved_0x15; 2095 register8_t reserved_0x16; 2096 register8_t reserved_0x17; 2097 register8_t reserved_0x18; 2098 register8_t reserved_0x19; 2099 register8_t reserved_0x1A; 2100 register8_t reserved_0x1B; 2101 register8_t reserved_0x1C; 2102 register8_t reserved_0x1D; 2103 register8_t reserved_0x1E; 2104 register8_t reserved_0x1F; 2105 _WORDREGISTER(CNT); /* Count */ 2106 register8_t reserved_0x22; 2107 register8_t reserved_0x23; 2108 register8_t reserved_0x24; 2109 register8_t reserved_0x25; 2110 _WORDREGISTER(PER); /* Period */ 2111 _WORDREGISTER(CCA); /* Compare or Capture A */ 2112 _WORDREGISTER(CCB); /* Compare or Capture B */ 2113 _WORDREGISTER(CCC); /* Compare or Capture C */ 2114 _WORDREGISTER(CCD); /* Compare or Capture D */ 2115 register8_t reserved_0x30; 2116 register8_t reserved_0x31; 2117 register8_t reserved_0x32; 2118 register8_t reserved_0x33; 2119 register8_t reserved_0x34; 2120 register8_t reserved_0x35; 2121 _WORDREGISTER(PERBUF); /* Period Buffer */ 2122 _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ 2123 _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ 2124 _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ 2125 _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ 2126 } TC0_t; 2127 2128 /* 2129 -------------------------------------------------------------------------- 2130 TC - 16-bit Timer/Counter With PWM 2131 -------------------------------------------------------------------------- 2132 */ 2133 2134 /* 16-bit Timer/Counter 1 */ 2135 typedef struct TC1_struct 2136 { 2137 register8_t CTRLA; /* Control Register A */ 2138 register8_t CTRLB; /* Control Register B */ 2139 register8_t CTRLC; /* Control register C */ 2140 register8_t CTRLD; /* Control Register D */ 2141 register8_t CTRLE; /* Control Register E */ 2142 register8_t reserved_0x05; 2143 register8_t INTCTRLA; /* Interrupt Control Register A */ 2144 register8_t INTCTRLB; /* Interrupt Control Register B */ 2145 register8_t CTRLFCLR; /* Control Register F Clear */ 2146 register8_t CTRLFSET; /* Control Register F Set */ 2147 register8_t CTRLGCLR; /* Control Register G Clear */ 2148 register8_t CTRLGSET; /* Control Register G Set */ 2149 register8_t INTFLAGS; /* Interrupt Flag Register */ 2150 register8_t reserved_0x0D; 2151 register8_t reserved_0x0E; 2152 register8_t TEMP; /* Temporary Register For 16-bit Access */ 2153 register8_t reserved_0x10; 2154 register8_t reserved_0x11; 2155 register8_t reserved_0x12; 2156 register8_t reserved_0x13; 2157 register8_t reserved_0x14; 2158 register8_t reserved_0x15; 2159 register8_t reserved_0x16; 2160 register8_t reserved_0x17; 2161 register8_t reserved_0x18; 2162 register8_t reserved_0x19; 2163 register8_t reserved_0x1A; 2164 register8_t reserved_0x1B; 2165 register8_t reserved_0x1C; 2166 register8_t reserved_0x1D; 2167 register8_t reserved_0x1E; 2168 register8_t reserved_0x1F; 2169 _WORDREGISTER(CNT); /* Count */ 2170 register8_t reserved_0x22; 2171 register8_t reserved_0x23; 2172 register8_t reserved_0x24; 2173 register8_t reserved_0x25; 2174 _WORDREGISTER(PER); /* Period */ 2175 _WORDREGISTER(CCA); /* Compare or Capture A */ 2176 _WORDREGISTER(CCB); /* Compare or Capture B */ 2177 register8_t reserved_0x2C; 2178 register8_t reserved_0x2D; 2179 register8_t reserved_0x2E; 2180 register8_t reserved_0x2F; 2181 register8_t reserved_0x30; 2182 register8_t reserved_0x31; 2183 register8_t reserved_0x32; 2184 register8_t reserved_0x33; 2185 register8_t reserved_0x34; 2186 register8_t reserved_0x35; 2187 _WORDREGISTER(PERBUF); /* Period Buffer */ 2188 _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ 2189 _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ 2190 } TC1_t; 2191 2192 /* 2193 -------------------------------------------------------------------------- 2194 TC - 16-bit Timer/Counter With PWM 2195 -------------------------------------------------------------------------- 2196 */ 2197 2198 /* Advanced Waveform Extension */ 2199 typedef struct AWEX_struct 2200 { 2201 register8_t CTRL; /* Control Register */ 2202 register8_t reserved_0x01; 2203 register8_t FDEMASK; /* Fault Detection Event Mask */ 2204 register8_t FDCTRL; /* Fault Detection Control Register */ 2205 register8_t STATUS; /* Status Register */ 2206 register8_t reserved_0x05; 2207 register8_t DTBOTH; /* Dead Time Both Sides */ 2208 register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ 2209 register8_t DTLS; /* Dead Time Low Side */ 2210 register8_t DTHS; /* Dead Time High Side */ 2211 register8_t DTLSBUF; /* Dead Time Low Side Buffer */ 2212 register8_t DTHSBUF; /* Dead Time High Side Buffer */ 2213 register8_t OUTOVEN; /* Output Override Enable */ 2214 } AWEX_t; 2215 2216 /* 2217 -------------------------------------------------------------------------- 2218 TC - 16-bit Timer/Counter With PWM 2219 -------------------------------------------------------------------------- 2220 */ 2221 2222 /* High-Resolution Extension */ 2223 typedef struct HIRES_struct 2224 { 2225 register8_t CTRLA; /* Control Register */ 2226 } HIRES_t; 2227 2228 /* Clock Selection */ 2229 typedef enum TC_CLKSEL_enum 2230 { 2231 TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ 2232 TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ 2233 TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ 2234 TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ 2235 TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ 2236 TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ 2237 TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ 2238 TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ 2239 TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ 2240 TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ 2241 TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ 2242 TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ 2243 TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ 2244 TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ 2245 TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ 2246 TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ 2247 } TC_CLKSEL_t; 2248 2249 /* Waveform Generation Mode */ 2250 typedef enum TC_WGMODE_enum 2251 { 2252 TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ 2253 TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ 2254 TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ 2255 TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ 2256 TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ 2257 TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ 2258 } TC_WGMODE_t; 2259 2260 /* Event Action */ 2261 typedef enum TC_EVACT_enum 2262 { 2263 TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ 2264 TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ 2265 TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ 2266 TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ 2267 TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ 2268 TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ 2269 TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ 2270 TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ 2271 } TC_EVACT_t; 2272 2273 /* Event Selection */ 2274 typedef enum TC_EVSEL_enum 2275 { 2276 TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ 2277 TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ 2278 TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ 2279 TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ 2280 TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ 2281 TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ 2282 TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ 2283 TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ 2284 TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ 2285 } TC_EVSEL_t; 2286 2287 /* Error Interrupt Level */ 2288 typedef enum TC_ERRINTLVL_enum 2289 { 2290 TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 2291 TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ 2292 TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 2293 TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ 2294 } TC_ERRINTLVL_t; 2295 2296 /* Overflow Interrupt Level */ 2297 typedef enum TC_OVFINTLVL_enum 2298 { 2299 TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2300 TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 2301 TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2302 TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ 2303 } TC_OVFINTLVL_t; 2304 2305 /* Compare or Capture D Interrupt Level */ 2306 typedef enum TC_CCDINTLVL_enum 2307 { 2308 TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 2309 TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ 2310 TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ 2311 TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ 2312 } TC_CCDINTLVL_t; 2313 2314 /* Compare or Capture C Interrupt Level */ 2315 typedef enum TC_CCCINTLVL_enum 2316 { 2317 TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 2318 TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 2319 TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 2320 TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ 2321 } TC_CCCINTLVL_t; 2322 2323 /* Compare or Capture B Interrupt Level */ 2324 typedef enum TC_CCBINTLVL_enum 2325 { 2326 TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 2327 TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ 2328 TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 2329 TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ 2330 } TC_CCBINTLVL_t; 2331 2332 /* Compare or Capture A Interrupt Level */ 2333 typedef enum TC_CCAINTLVL_enum 2334 { 2335 TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2336 TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ 2337 TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2338 TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ 2339 } TC_CCAINTLVL_t; 2340 2341 /* Timer/Counter Command */ 2342 typedef enum TC_CMD_enum 2343 { 2344 TC_CMD_NONE_gc = (0x00<<2), /* No Command */ 2345 TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ 2346 TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ 2347 TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ 2348 } TC_CMD_t; 2349 2350 /* Fault Detect Action */ 2351 typedef enum AWEX_FDACT_enum 2352 { 2353 AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ 2354 AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ 2355 AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ 2356 } AWEX_FDACT_t; 2357 2358 /* High Resolution Enable */ 2359 typedef enum HIRES_HREN_enum 2360 { 2361 HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ 2362 HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ 2363 HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ 2364 HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ 2365 } HIRES_HREN_t; 2366 2367 2368 /* 2369 -------------------------------------------------------------------------- 2370 USART - Universal Asynchronous Receiver-Transmitter 2371 -------------------------------------------------------------------------- 2372 */ 2373 2374 /* Universal Synchronous/Asynchronous Receiver/Transmitter */ 2375 typedef struct USART_struct 2376 { 2377 register8_t DATA; /* Data Register */ 2378 register8_t STATUS; /* Status Register */ 2379 register8_t reserved_0x02; 2380 register8_t CTRLA; /* Control Register A */ 2381 register8_t CTRLB; /* Control Register B */ 2382 register8_t CTRLC; /* Control Register C */ 2383 register8_t BAUDCTRLA; /* Baud Rate Control Register A */ 2384 register8_t BAUDCTRLB; /* Baud Rate Control Register B */ 2385 } USART_t; 2386 2387 /* Receive Complete Interrupt level */ 2388 typedef enum USART_RXCINTLVL_enum 2389 { 2390 USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 2391 USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 2392 USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 2393 USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ 2394 } USART_RXCINTLVL_t; 2395 2396 /* Transmit Complete Interrupt level */ 2397 typedef enum USART_TXCINTLVL_enum 2398 { 2399 USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 2400 USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ 2401 USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 2402 USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ 2403 } USART_TXCINTLVL_t; 2404 2405 /* Data Register Empty Interrupt level */ 2406 typedef enum USART_DREINTLVL_enum 2407 { 2408 USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2409 USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ 2410 USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2411 USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ 2412 } USART_DREINTLVL_t; 2413 2414 /* Character Size */ 2415 typedef enum USART_CHSIZE_enum 2416 { 2417 USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ 2418 USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ 2419 USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ 2420 USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ 2421 USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ 2422 } USART_CHSIZE_t; 2423 2424 /* Communication Mode */ 2425 typedef enum USART_CMODE_enum 2426 { 2427 USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ 2428 USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ 2429 USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ 2430 USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ 2431 } USART_CMODE_t; 2432 2433 /* Parity Mode */ 2434 typedef enum USART_PMODE_enum 2435 { 2436 USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ 2437 USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ 2438 USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ 2439 } USART_PMODE_t; 2440 2441 2442 /* 2443 -------------------------------------------------------------------------- 2444 SPI - Serial Peripheral Interface 2445 -------------------------------------------------------------------------- 2446 */ 2447 2448 /* Serial Peripheral Interface */ 2449 typedef struct SPI_struct 2450 { 2451 register8_t CTRL; /* Control Register */ 2452 register8_t INTCTRL; /* Interrupt Control Register */ 2453 register8_t STATUS; /* Status Register */ 2454 register8_t DATA; /* Data Register */ 2455 } SPI_t; 2456 2457 /* SPI Mode */ 2458 typedef enum SPI_MODE_enum 2459 { 2460 SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ 2461 SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ 2462 SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ 2463 SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ 2464 } SPI_MODE_t; 2465 2466 /* Prescaler setting */ 2467 typedef enum SPI_PRESCALER_enum 2468 { 2469 SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ 2470 SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ 2471 SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ 2472 SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ 2473 } SPI_PRESCALER_t; 2474 2475 /* Interrupt level */ 2476 typedef enum SPI_INTLVL_enum 2477 { 2478 SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2479 SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ 2480 SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2481 SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ 2482 } SPI_INTLVL_t; 2483 2484 2485 /* 2486 -------------------------------------------------------------------------- 2487 IRCOM - IR Communication Module 2488 -------------------------------------------------------------------------- 2489 */ 2490 2491 /* IR Communication Module */ 2492 typedef struct IRCOM_struct 2493 { 2494 register8_t CTRL; /* Control Register */ 2495 register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ 2496 register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ 2497 } IRCOM_t; 2498 2499 /* Event channel selection */ 2500 typedef enum IRDA_EVSEL_enum 2501 { 2502 IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ 2503 IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ 2504 IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ 2505 IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ 2506 IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ 2507 IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ 2508 IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ 2509 IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ 2510 IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ 2511 } IRDA_EVSEL_t; 2512 2513 2514 /* 2515 -------------------------------------------------------------------------- 2516 AES - AES Module 2517 -------------------------------------------------------------------------- 2518 */ 2519 2520 /* AES Module */ 2521 typedef struct AES_struct 2522 { 2523 register8_t CTRL; /* AES Control Register */ 2524 register8_t STATUS; /* AES Status Register */ 2525 register8_t STATE; /* AES State Register */ 2526 register8_t KEY; /* AES Key Register */ 2527 register8_t INTCTRL; /* AES Interrupt Control Register */ 2528 } AES_t; 2529 2530 /* Interrupt level */ 2531 typedef enum AES_INTLVL_enum 2532 { 2533 AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2534 AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ 2535 AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2536 AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ 2537 } AES_INTLVL_t; 2538 2539 2540 /* 2541 -------------------------------------------------------------------------- 2542 VBAT - VBAT Battery Backup Module 2543 -------------------------------------------------------------------------- 2544 */ 2545 2546 /* VBAT Battery Backup Module */ 2547 typedef struct VBAT_struct 2548 { 2549 register8_t CTRL; /* Control Register */ 2550 register8_t STATUS; /* Status Register */ 2551 register8_t BACKUP0; /* Battery Bacup Register 0 */ 2552 register8_t BACKUP1; /* Battery Backup Register 1 */ 2553 } VBAT_t; 2554 2555 2556 2557 /* 2558 ========================================================================== 2559 IO Module Instances. Mapped to memory. 2560 ========================================================================== 2561 */ 2562 2563 #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ 2564 #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ 2565 #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ 2566 #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ 2567 #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ 2568 #define CLK (*(CLK_t *) 0x0040) /* Clock System */ 2569 #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ 2570 #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ 2571 #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ 2572 #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ 2573 #define PR (*(PR_t *) 0x0070) /* Power Reduction */ 2574 #define RST (*(RST_t *) 0x0078) /* Reset Controller */ 2575 #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ 2576 #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ 2577 #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ 2578 #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ 2579 #define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ 2580 #define VBAT (*(VBAT_t *) 0x00F0) /* VBAT Battery Backup Module */ 2581 #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ 2582 #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ 2583 #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ 2584 #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ 2585 #define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ 2586 #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ 2587 #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ 2588 #define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ 2589 #define RTC32 (*(RTC32_t *) 0x0420) /* 32-bit Real-Time Counter */ 2590 #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ 2591 #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ 2592 #define PORTA (*(PORT_t *) 0x0600) /* Port A */ 2593 #define PORTB (*(PORT_t *) 0x0620) /* Port B */ 2594 #define PORTC (*(PORT_t *) 0x0640) /* Port C */ 2595 #define PORTD (*(PORT_t *) 0x0660) /* Port D */ 2596 #define PORTE (*(PORT_t *) 0x0680) /* Port E */ 2597 #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ 2598 #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ 2599 #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ 2600 #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ 2601 #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ 2602 #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ 2603 #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ 2604 #define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ 2605 #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ 2606 #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ 2607 #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ 2608 #define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ 2609 #define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ 2610 #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ 2611 #define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ 2612 #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ 2613 #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ 2614 #define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ 2615 #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ 2616 #define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ 2617 #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ 2618 #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ 2619 #define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ 2620 #define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ 2621 #define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ 2622 2623 2624 #endif /* !defined (__ASSEMBLER__) */ 2625 2626 2627 /* ========== Flattened fully qualified IO register names ========== */ 2628 2629 /* GPIO - General Purpose IO Registers */ 2630 #define GPIO_GPIOR0 _SFR_MEM8(0x0000) 2631 #define GPIO_GPIOR1 _SFR_MEM8(0x0001) 2632 #define GPIO_GPIOR2 _SFR_MEM8(0x0002) 2633 #define GPIO_GPIOR3 _SFR_MEM8(0x0003) 2634 #define GPIO_GPIOR4 _SFR_MEM8(0x0004) 2635 #define GPIO_GPIOR5 _SFR_MEM8(0x0005) 2636 #define GPIO_GPIOR6 _SFR_MEM8(0x0006) 2637 #define GPIO_GPIOR7 _SFR_MEM8(0x0007) 2638 #define GPIO_GPIOR8 _SFR_MEM8(0x0008) 2639 #define GPIO_GPIOR9 _SFR_MEM8(0x0009) 2640 #define GPIO_GPIORA _SFR_MEM8(0x000A) 2641 #define GPIO_GPIORB _SFR_MEM8(0x000B) 2642 #define GPIO_GPIORC _SFR_MEM8(0x000C) 2643 #define GPIO_GPIORD _SFR_MEM8(0x000D) 2644 #define GPIO_GPIORE _SFR_MEM8(0x000E) 2645 #define GPIO_GPIORF _SFR_MEM8(0x000F) 2646 2647 /* Deprecated */ 2648 #define GPIO_GPIO0 _SFR_MEM8(0x0000) 2649 #define GPIO_GPIO1 _SFR_MEM8(0x0001) 2650 #define GPIO_GPIO2 _SFR_MEM8(0x0002) 2651 #define GPIO_GPIO3 _SFR_MEM8(0x0003) 2652 #define GPIO_GPIO4 _SFR_MEM8(0x0004) 2653 #define GPIO_GPIO5 _SFR_MEM8(0x0005) 2654 #define GPIO_GPIO6 _SFR_MEM8(0x0006) 2655 #define GPIO_GPIO7 _SFR_MEM8(0x0007) 2656 #define GPIO_GPIO8 _SFR_MEM8(0x0008) 2657 #define GPIO_GPIO9 _SFR_MEM8(0x0009) 2658 #define GPIO_GPIOA _SFR_MEM8(0x000A) 2659 #define GPIO_GPIOB _SFR_MEM8(0x000B) 2660 #define GPIO_GPIOC _SFR_MEM8(0x000C) 2661 #define GPIO_GPIOD _SFR_MEM8(0x000D) 2662 #define GPIO_GPIOE _SFR_MEM8(0x000E) 2663 #define GPIO_GPIOF _SFR_MEM8(0x000F) 2664 2665 2666 /* VPORT0 - Virtual Port 0 */ 2667 #define VPORT0_DIR _SFR_MEM8(0x0010) 2668 #define VPORT0_OUT _SFR_MEM8(0x0011) 2669 #define VPORT0_IN _SFR_MEM8(0x0012) 2670 #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) 2671 2672 /* VPORT1 - Virtual Port 1 */ 2673 #define VPORT1_DIR _SFR_MEM8(0x0014) 2674 #define VPORT1_OUT _SFR_MEM8(0x0015) 2675 #define VPORT1_IN _SFR_MEM8(0x0016) 2676 #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) 2677 2678 /* VPORT2 - Virtual Port 2 */ 2679 #define VPORT2_DIR _SFR_MEM8(0x0018) 2680 #define VPORT2_OUT _SFR_MEM8(0x0019) 2681 #define VPORT2_IN _SFR_MEM8(0x001A) 2682 #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) 2683 2684 /* VPORT3 - Virtual Port 3 */ 2685 #define VPORT3_DIR _SFR_MEM8(0x001C) 2686 #define VPORT3_OUT _SFR_MEM8(0x001D) 2687 #define VPORT3_IN _SFR_MEM8(0x001E) 2688 #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) 2689 2690 /* OCD - On-Chip Debug System */ 2691 #define OCD_OCDR0 _SFR_MEM8(0x002E) 2692 #define OCD_OCDR1 _SFR_MEM8(0x002F) 2693 2694 /* CPU - CPU Registers */ 2695 #define CPU_CCP _SFR_MEM8(0x0034) 2696 #define CPU_RAMPD _SFR_MEM8(0x0038) 2697 #define CPU_RAMPX _SFR_MEM8(0x0039) 2698 #define CPU_RAMPY _SFR_MEM8(0x003A) 2699 #define CPU_RAMPZ _SFR_MEM8(0x003B) 2700 #define CPU_EIND _SFR_MEM8(0x003C) 2701 #define CPU_SPL _SFR_MEM8(0x003D) 2702 #define CPU_SPH _SFR_MEM8(0x003E) 2703 #define CPU_SREG _SFR_MEM8(0x003F) 2704 2705 /* CLK - Clock System */ 2706 #define CLK_CTRL _SFR_MEM8(0x0040) 2707 #define CLK_PSCTRL _SFR_MEM8(0x0041) 2708 #define CLK_LOCK _SFR_MEM8(0x0042) 2709 #define CLK_RTCCTRL _SFR_MEM8(0x0043) 2710 2711 /* SLEEP - Sleep Controller */ 2712 #define SLEEP_CTRL _SFR_MEM8(0x0048) 2713 2714 /* OSC - Oscillator Control */ 2715 #define OSC_CTRL _SFR_MEM8(0x0050) 2716 #define OSC_STATUS _SFR_MEM8(0x0051) 2717 #define OSC_XOSCCTRL _SFR_MEM8(0x0052) 2718 #define OSC_XOSCFAIL _SFR_MEM8(0x0053) 2719 #define OSC_RC32KCAL _SFR_MEM8(0x0054) 2720 #define OSC_PLLCTRL _SFR_MEM8(0x0055) 2721 #define OSC_DFLLCTRL _SFR_MEM8(0x0056) 2722 2723 /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ 2724 #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) 2725 #define DFLLRC32M_CALA _SFR_MEM8(0x0062) 2726 #define DFLLRC32M_CALB _SFR_MEM8(0x0063) 2727 #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) 2728 #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) 2729 #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) 2730 2731 /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ 2732 #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) 2733 #define DFLLRC2M_CALA _SFR_MEM8(0x006A) 2734 #define DFLLRC2M_CALB _SFR_MEM8(0x006B) 2735 #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) 2736 #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) 2737 #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) 2738 2739 /* PR - Power Reduction */ 2740 #define PR_PRGEN _SFR_MEM8(0x0070) 2741 #define PR_PRPA _SFR_MEM8(0x0071) 2742 #define PR_PRPB _SFR_MEM8(0x0072) 2743 #define PR_PRPC _SFR_MEM8(0x0073) 2744 #define PR_PRPD _SFR_MEM8(0x0074) 2745 #define PR_PRPE _SFR_MEM8(0x0075) 2746 #define PR_PRPF _SFR_MEM8(0x0076) 2747 2748 /* RST - Reset Controller */ 2749 #define RST_STATUS _SFR_MEM8(0x0078) 2750 #define RST_CTRL _SFR_MEM8(0x0079) 2751 2752 /* WDT - Watch-Dog Timer */ 2753 #define WDT_CTRL _SFR_MEM8(0x0080) 2754 #define WDT_WINCTRL _SFR_MEM8(0x0081) 2755 #define WDT_STATUS _SFR_MEM8(0x0082) 2756 2757 /* MCU - MCU Control */ 2758 #define MCU_DEVID0 _SFR_MEM8(0x0090) 2759 #define MCU_DEVID1 _SFR_MEM8(0x0091) 2760 #define MCU_DEVID2 _SFR_MEM8(0x0092) 2761 #define MCU_REVID _SFR_MEM8(0x0093) 2762 #define MCU_JTAGUID _SFR_MEM8(0x0094) 2763 #define MCU_MCUCR _SFR_MEM8(0x0096) 2764 #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) 2765 #define MCU_AWEXLOCK _SFR_MEM8(0x0099) 2766 2767 /* PMIC - Programmable Interrupt Controller */ 2768 #define PMIC_STATUS _SFR_MEM8(0x00A0) 2769 #define PMIC_INTPRI _SFR_MEM8(0x00A1) 2770 #define PMIC_CTRL _SFR_MEM8(0x00A2) 2771 2772 /* PORTCFG - Port Configuration */ 2773 #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) 2774 #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) 2775 #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) 2776 #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) 2777 2778 /* AES - AES Crypto Module */ 2779 #define AES_CTRL _SFR_MEM8(0x00C0) 2780 #define AES_STATUS _SFR_MEM8(0x00C1) 2781 #define AES_STATE _SFR_MEM8(0x00C2) 2782 #define AES_KEY _SFR_MEM8(0x00C3) 2783 #define AES_INTCTRL _SFR_MEM8(0x00C4) 2784 2785 /* VBAT - VBAT Battery Backup Module */ 2786 #define VBAT_CTRL _SFR_MEM8(0x00F0) 2787 #define VBAT_STATUS _SFR_MEM8(0x00F1) 2788 #define VBAT_BACKUP0 _SFR_MEM8(0x00F2) 2789 #define VBAT_BACKUP1 _SFR_MEM8(0x00F3) 2790 2791 /* DMA - DMA Controller */ 2792 #define DMA_CTRL _SFR_MEM8(0x0100) 2793 #define DMA_INTFLAGS _SFR_MEM8(0x0103) 2794 #define DMA_STATUS _SFR_MEM8(0x0104) 2795 #define DMA_TEMP _SFR_MEM16(0x0106) 2796 #define DMA_CH0_CTRLA _SFR_MEM8(0x0110) 2797 #define DMA_CH0_CTRLB _SFR_MEM8(0x0111) 2798 #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) 2799 #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) 2800 #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) 2801 #define DMA_CH0_REPCNT _SFR_MEM8(0x0116) 2802 #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) 2803 #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) 2804 #define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) 2805 #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) 2806 #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) 2807 #define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) 2808 #define DMA_CH1_CTRLA _SFR_MEM8(0x0120) 2809 #define DMA_CH1_CTRLB _SFR_MEM8(0x0121) 2810 #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) 2811 #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) 2812 #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) 2813 #define DMA_CH1_REPCNT _SFR_MEM8(0x0126) 2814 #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) 2815 #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) 2816 #define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) 2817 #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) 2818 #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) 2819 #define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) 2820 #define DMA_CH2_CTRLA _SFR_MEM8(0x0130) 2821 #define DMA_CH2_CTRLB _SFR_MEM8(0x0131) 2822 #define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) 2823 #define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) 2824 #define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) 2825 #define DMA_CH2_REPCNT _SFR_MEM8(0x0136) 2826 #define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) 2827 #define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) 2828 #define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) 2829 #define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) 2830 #define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) 2831 #define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) 2832 #define DMA_CH3_CTRLA _SFR_MEM8(0x0140) 2833 #define DMA_CH3_CTRLB _SFR_MEM8(0x0141) 2834 #define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) 2835 #define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) 2836 #define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) 2837 #define DMA_CH3_REPCNT _SFR_MEM8(0x0146) 2838 #define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) 2839 #define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) 2840 #define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) 2841 #define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) 2842 #define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) 2843 #define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) 2844 2845 /* EVSYS - Event System */ 2846 #define EVSYS_CH0MUX _SFR_MEM8(0x0180) 2847 #define EVSYS_CH1MUX _SFR_MEM8(0x0181) 2848 #define EVSYS_CH2MUX _SFR_MEM8(0x0182) 2849 #define EVSYS_CH3MUX _SFR_MEM8(0x0183) 2850 #define EVSYS_CH4MUX _SFR_MEM8(0x0184) 2851 #define EVSYS_CH5MUX _SFR_MEM8(0x0185) 2852 #define EVSYS_CH6MUX _SFR_MEM8(0x0186) 2853 #define EVSYS_CH7MUX _SFR_MEM8(0x0187) 2854 #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) 2855 #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) 2856 #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) 2857 #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) 2858 #define EVSYS_CH4CTRL _SFR_MEM8(0x018C) 2859 #define EVSYS_CH5CTRL _SFR_MEM8(0x018D) 2860 #define EVSYS_CH6CTRL _SFR_MEM8(0x018E) 2861 #define EVSYS_CH7CTRL _SFR_MEM8(0x018F) 2862 #define EVSYS_STROBE _SFR_MEM8(0x0190) 2863 #define EVSYS_DATA _SFR_MEM8(0x0191) 2864 2865 /* NVM - Non Volatile Memory Controller */ 2866 #define NVM_ADDR0 _SFR_MEM8(0x01C0) 2867 #define NVM_ADDR1 _SFR_MEM8(0x01C1) 2868 #define NVM_ADDR2 _SFR_MEM8(0x01C2) 2869 #define NVM_DATA0 _SFR_MEM8(0x01C4) 2870 #define NVM_DATA1 _SFR_MEM8(0x01C5) 2871 #define NVM_DATA2 _SFR_MEM8(0x01C6) 2872 #define NVM_CMD _SFR_MEM8(0x01CA) 2873 #define NVM_CTRLA _SFR_MEM8(0x01CB) 2874 #define NVM_CTRLB _SFR_MEM8(0x01CC) 2875 #define NVM_INTCTRL _SFR_MEM8(0x01CD) 2876 #define NVM_STATUS _SFR_MEM8(0x01CF) 2877 #define NVM_LOCKBITS _SFR_MEM8(0x01D0) 2878 2879 /* ADCA - Analog to Digital Converter A */ 2880 #define ADCA_CTRLA _SFR_MEM8(0x0200) 2881 #define ADCA_CTRLB _SFR_MEM8(0x0201) 2882 #define ADCA_REFCTRL _SFR_MEM8(0x0202) 2883 #define ADCA_EVCTRL _SFR_MEM8(0x0203) 2884 #define ADCA_PRESCALER _SFR_MEM8(0x0204) 2885 #define ADCA_INTFLAGS _SFR_MEM8(0x0206) 2886 #define ADCA_CAL _SFR_MEM16(0x020C) 2887 #define ADCA_CH0RES _SFR_MEM16(0x0210) 2888 #define ADCA_CH1RES _SFR_MEM16(0x0212) 2889 #define ADCA_CH2RES _SFR_MEM16(0x0214) 2890 #define ADCA_CH3RES _SFR_MEM16(0x0216) 2891 #define ADCA_CMP _SFR_MEM16(0x0218) 2892 #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) 2893 #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) 2894 #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) 2895 #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) 2896 #define ADCA_CH0_RES _SFR_MEM16(0x0224) 2897 #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) 2898 #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) 2899 #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) 2900 #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) 2901 #define ADCA_CH1_RES _SFR_MEM16(0x022C) 2902 #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) 2903 #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) 2904 #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) 2905 #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) 2906 #define ADCA_CH2_RES _SFR_MEM16(0x0234) 2907 #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) 2908 #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) 2909 #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) 2910 #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) 2911 #define ADCA_CH3_RES _SFR_MEM16(0x023C) 2912 2913 /* ADCB - Analog to Digital Converter B */ 2914 #define ADCB_CTRLA _SFR_MEM8(0x0240) 2915 #define ADCB_CTRLB _SFR_MEM8(0x0241) 2916 #define ADCB_REFCTRL _SFR_MEM8(0x0242) 2917 #define ADCB_EVCTRL _SFR_MEM8(0x0243) 2918 #define ADCB_PRESCALER _SFR_MEM8(0x0244) 2919 #define ADCB_INTFLAGS _SFR_MEM8(0x0246) 2920 #define ADCB_CAL _SFR_MEM16(0x024C) 2921 #define ADCB_CH0RES _SFR_MEM16(0x0250) 2922 #define ADCB_CH1RES _SFR_MEM16(0x0252) 2923 #define ADCB_CH2RES _SFR_MEM16(0x0254) 2924 #define ADCB_CH3RES _SFR_MEM16(0x0256) 2925 #define ADCB_CMP _SFR_MEM16(0x0258) 2926 #define ADCB_CH0_CTRL _SFR_MEM8(0x0260) 2927 #define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) 2928 #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) 2929 #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) 2930 #define ADCB_CH0_RES _SFR_MEM16(0x0264) 2931 #define ADCB_CH1_CTRL _SFR_MEM8(0x0268) 2932 #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) 2933 #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) 2934 #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) 2935 #define ADCB_CH1_RES _SFR_MEM16(0x026C) 2936 #define ADCB_CH2_CTRL _SFR_MEM8(0x0270) 2937 #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) 2938 #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) 2939 #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) 2940 #define ADCB_CH2_RES _SFR_MEM16(0x0274) 2941 #define ADCB_CH3_CTRL _SFR_MEM8(0x0278) 2942 #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) 2943 #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) 2944 #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) 2945 #define ADCB_CH3_RES _SFR_MEM16(0x027C) 2946 2947 /* DACB - Digital to Analog Converter B */ 2948 #define DACB_CTRLA _SFR_MEM8(0x0320) 2949 #define DACB_CTRLB _SFR_MEM8(0x0321) 2950 #define DACB_CTRLC _SFR_MEM8(0x0322) 2951 #define DACB_EVCTRL _SFR_MEM8(0x0323) 2952 #define DACB_TIMCTRL _SFR_MEM8(0x0324) 2953 #define DACB_STATUS _SFR_MEM8(0x0325) 2954 #define DACB_GAINCAL _SFR_MEM8(0x0328) 2955 #define DACB_OFFSETCAL _SFR_MEM8(0x0329) 2956 #define DACB_CH0DATA _SFR_MEM16(0x0338) 2957 #define DACB_CH1DATA _SFR_MEM16(0x033A) 2958 2959 /* ACA - Analog Comparator A */ 2960 #define ACA_AC0CTRL _SFR_MEM8(0x0380) 2961 #define ACA_AC1CTRL _SFR_MEM8(0x0381) 2962 #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) 2963 #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) 2964 #define ACA_CTRLA _SFR_MEM8(0x0384) 2965 #define ACA_CTRLB _SFR_MEM8(0x0385) 2966 #define ACA_WINCTRL _SFR_MEM8(0x0386) 2967 #define ACA_STATUS _SFR_MEM8(0x0387) 2968 2969 /* ACB - Analog Comparator B */ 2970 #define ACB_AC0CTRL _SFR_MEM8(0x0390) 2971 #define ACB_AC1CTRL _SFR_MEM8(0x0391) 2972 #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) 2973 #define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) 2974 #define ACB_CTRLA _SFR_MEM8(0x0394) 2975 #define ACB_CTRLB _SFR_MEM8(0x0395) 2976 #define ACB_WINCTRL _SFR_MEM8(0x0396) 2977 #define ACB_STATUS _SFR_MEM8(0x0397) 2978 2979 /* RTC32 - 32-bit Real-Time Counter */ 2980 #define RTC32_CTRL _SFR_MEM8(0x0420) 2981 #define RTC32_SYNCCTRL _SFR_MEM8(0x0421) 2982 #define RTC32_INTCTRL _SFR_MEM8(0x0422) 2983 #define RTC32_INTFLAGS _SFR_MEM8(0x0423) 2984 2985 /* TWIC - Two-Wire Interface C */ 2986 #define TWIC_CTRL _SFR_MEM8(0x0480) 2987 #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) 2988 #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) 2989 #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) 2990 #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) 2991 #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) 2992 #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) 2993 #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) 2994 #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) 2995 #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) 2996 #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) 2997 #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) 2998 #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) 2999 #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) 3000 3001 /* TWIE - Two-Wire Interface E */ 3002 #define TWIE_CTRL _SFR_MEM8(0x04A0) 3003 #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) 3004 #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) 3005 #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) 3006 #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) 3007 #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) 3008 #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) 3009 #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) 3010 #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) 3011 #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) 3012 #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) 3013 #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) 3014 #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) 3015 #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) 3016 3017 /* PORTA - Port A */ 3018 #define PORTA_DIR _SFR_MEM8(0x0600) 3019 #define PORTA_DIRSET _SFR_MEM8(0x0601) 3020 #define PORTA_DIRCLR _SFR_MEM8(0x0602) 3021 #define PORTA_DIRTGL _SFR_MEM8(0x0603) 3022 #define PORTA_OUT _SFR_MEM8(0x0604) 3023 #define PORTA_OUTSET _SFR_MEM8(0x0605) 3024 #define PORTA_OUTCLR _SFR_MEM8(0x0606) 3025 #define PORTA_OUTTGL _SFR_MEM8(0x0607) 3026 #define PORTA_IN _SFR_MEM8(0x0608) 3027 #define PORTA_INTCTRL _SFR_MEM8(0x0609) 3028 #define PORTA_INT0MASK _SFR_MEM8(0x060A) 3029 #define PORTA_INT1MASK _SFR_MEM8(0x060B) 3030 #define PORTA_INTFLAGS _SFR_MEM8(0x060C) 3031 #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) 3032 #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) 3033 #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) 3034 #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) 3035 #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) 3036 #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) 3037 #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) 3038 #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) 3039 3040 /* PORTB - Port B */ 3041 #define PORTB_DIR _SFR_MEM8(0x0620) 3042 #define PORTB_DIRSET _SFR_MEM8(0x0621) 3043 #define PORTB_DIRCLR _SFR_MEM8(0x0622) 3044 #define PORTB_DIRTGL _SFR_MEM8(0x0623) 3045 #define PORTB_OUT _SFR_MEM8(0x0624) 3046 #define PORTB_OUTSET _SFR_MEM8(0x0625) 3047 #define PORTB_OUTCLR _SFR_MEM8(0x0626) 3048 #define PORTB_OUTTGL _SFR_MEM8(0x0627) 3049 #define PORTB_IN _SFR_MEM8(0x0628) 3050 #define PORTB_INTCTRL _SFR_MEM8(0x0629) 3051 #define PORTB_INT0MASK _SFR_MEM8(0x062A) 3052 #define PORTB_INT1MASK _SFR_MEM8(0x062B) 3053 #define PORTB_INTFLAGS _SFR_MEM8(0x062C) 3054 #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) 3055 #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) 3056 #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) 3057 #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) 3058 #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) 3059 #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) 3060 #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) 3061 #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) 3062 3063 /* PORTC - Port C */ 3064 #define PORTC_DIR _SFR_MEM8(0x0640) 3065 #define PORTC_DIRSET _SFR_MEM8(0x0641) 3066 #define PORTC_DIRCLR _SFR_MEM8(0x0642) 3067 #define PORTC_DIRTGL _SFR_MEM8(0x0643) 3068 #define PORTC_OUT _SFR_MEM8(0x0644) 3069 #define PORTC_OUTSET _SFR_MEM8(0x0645) 3070 #define PORTC_OUTCLR _SFR_MEM8(0x0646) 3071 #define PORTC_OUTTGL _SFR_MEM8(0x0647) 3072 #define PORTC_IN _SFR_MEM8(0x0648) 3073 #define PORTC_INTCTRL _SFR_MEM8(0x0649) 3074 #define PORTC_INT0MASK _SFR_MEM8(0x064A) 3075 #define PORTC_INT1MASK _SFR_MEM8(0x064B) 3076 #define PORTC_INTFLAGS _SFR_MEM8(0x064C) 3077 #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) 3078 #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) 3079 #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) 3080 #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) 3081 #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) 3082 #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) 3083 #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) 3084 #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) 3085 3086 /* PORTD - Port D */ 3087 #define PORTD_DIR _SFR_MEM8(0x0660) 3088 #define PORTD_DIRSET _SFR_MEM8(0x0661) 3089 #define PORTD_DIRCLR _SFR_MEM8(0x0662) 3090 #define PORTD_DIRTGL _SFR_MEM8(0x0663) 3091 #define PORTD_OUT _SFR_MEM8(0x0664) 3092 #define PORTD_OUTSET _SFR_MEM8(0x0665) 3093 #define PORTD_OUTCLR _SFR_MEM8(0x0666) 3094 #define PORTD_OUTTGL _SFR_MEM8(0x0667) 3095 #define PORTD_IN _SFR_MEM8(0x0668) 3096 #define PORTD_INTCTRL _SFR_MEM8(0x0669) 3097 #define PORTD_INT0MASK _SFR_MEM8(0x066A) 3098 #define PORTD_INT1MASK _SFR_MEM8(0x066B) 3099 #define PORTD_INTFLAGS _SFR_MEM8(0x066C) 3100 #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) 3101 #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) 3102 #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) 3103 #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) 3104 #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) 3105 #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) 3106 #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) 3107 #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) 3108 3109 /* PORTE - Port E */ 3110 #define PORTE_DIR _SFR_MEM8(0x0680) 3111 #define PORTE_DIRSET _SFR_MEM8(0x0681) 3112 #define PORTE_DIRCLR _SFR_MEM8(0x0682) 3113 #define PORTE_DIRTGL _SFR_MEM8(0x0683) 3114 #define PORTE_OUT _SFR_MEM8(0x0684) 3115 #define PORTE_OUTSET _SFR_MEM8(0x0685) 3116 #define PORTE_OUTCLR _SFR_MEM8(0x0686) 3117 #define PORTE_OUTTGL _SFR_MEM8(0x0687) 3118 #define PORTE_IN _SFR_MEM8(0x0688) 3119 #define PORTE_INTCTRL _SFR_MEM8(0x0689) 3120 #define PORTE_INT0MASK _SFR_MEM8(0x068A) 3121 #define PORTE_INT1MASK _SFR_MEM8(0x068B) 3122 #define PORTE_INTFLAGS _SFR_MEM8(0x068C) 3123 #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) 3124 #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) 3125 #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) 3126 #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) 3127 #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) 3128 #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) 3129 #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) 3130 #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) 3131 3132 /* PORTF - Port F */ 3133 #define PORTF_DIR _SFR_MEM8(0x06A0) 3134 #define PORTF_DIRSET _SFR_MEM8(0x06A1) 3135 #define PORTF_DIRCLR _SFR_MEM8(0x06A2) 3136 #define PORTF_DIRTGL _SFR_MEM8(0x06A3) 3137 #define PORTF_OUT _SFR_MEM8(0x06A4) 3138 #define PORTF_OUTSET _SFR_MEM8(0x06A5) 3139 #define PORTF_OUTCLR _SFR_MEM8(0x06A6) 3140 #define PORTF_OUTTGL _SFR_MEM8(0x06A7) 3141 #define PORTF_IN _SFR_MEM8(0x06A8) 3142 #define PORTF_INTCTRL _SFR_MEM8(0x06A9) 3143 #define PORTF_INT0MASK _SFR_MEM8(0x06AA) 3144 #define PORTF_INT1MASK _SFR_MEM8(0x06AB) 3145 #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) 3146 #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) 3147 #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) 3148 #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) 3149 #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) 3150 #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) 3151 #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) 3152 #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) 3153 #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) 3154 3155 /* PORTR - Port R */ 3156 #define PORTR_DIR _SFR_MEM8(0x07E0) 3157 #define PORTR_DIRSET _SFR_MEM8(0x07E1) 3158 #define PORTR_DIRCLR _SFR_MEM8(0x07E2) 3159 #define PORTR_DIRTGL _SFR_MEM8(0x07E3) 3160 #define PORTR_OUT _SFR_MEM8(0x07E4) 3161 #define PORTR_OUTSET _SFR_MEM8(0x07E5) 3162 #define PORTR_OUTCLR _SFR_MEM8(0x07E6) 3163 #define PORTR_OUTTGL _SFR_MEM8(0x07E7) 3164 #define PORTR_IN _SFR_MEM8(0x07E8) 3165 #define PORTR_INTCTRL _SFR_MEM8(0x07E9) 3166 #define PORTR_INT0MASK _SFR_MEM8(0x07EA) 3167 #define PORTR_INT1MASK _SFR_MEM8(0x07EB) 3168 #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) 3169 #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) 3170 #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) 3171 #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) 3172 #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) 3173 #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) 3174 #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) 3175 #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) 3176 #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) 3177 3178 /* TCC0 - Timer/Counter C0 */ 3179 #define TCC0_CTRLA _SFR_MEM8(0x0800) 3180 #define TCC0_CTRLB _SFR_MEM8(0x0801) 3181 #define TCC0_CTRLC _SFR_MEM8(0x0802) 3182 #define TCC0_CTRLD _SFR_MEM8(0x0803) 3183 #define TCC0_CTRLE _SFR_MEM8(0x0804) 3184 #define TCC0_INTCTRLA _SFR_MEM8(0x0806) 3185 #define TCC0_INTCTRLB _SFR_MEM8(0x0807) 3186 #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) 3187 #define TCC0_CTRLFSET _SFR_MEM8(0x0809) 3188 #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) 3189 #define TCC0_CTRLGSET _SFR_MEM8(0x080B) 3190 #define TCC0_INTFLAGS _SFR_MEM8(0x080C) 3191 #define TCC0_TEMP _SFR_MEM8(0x080F) 3192 #define TCC0_CNT _SFR_MEM16(0x0820) 3193 #define TCC0_PER _SFR_MEM16(0x0826) 3194 #define TCC0_CCA _SFR_MEM16(0x0828) 3195 #define TCC0_CCB _SFR_MEM16(0x082A) 3196 #define TCC0_CCC _SFR_MEM16(0x082C) 3197 #define TCC0_CCD _SFR_MEM16(0x082E) 3198 #define TCC0_PERBUF _SFR_MEM16(0x0836) 3199 #define TCC0_CCABUF _SFR_MEM16(0x0838) 3200 #define TCC0_CCBBUF _SFR_MEM16(0x083A) 3201 #define TCC0_CCCBUF _SFR_MEM16(0x083C) 3202 #define TCC0_CCDBUF _SFR_MEM16(0x083E) 3203 3204 /* TCC1 - Timer/Counter C1 */ 3205 #define TCC1_CTRLA _SFR_MEM8(0x0840) 3206 #define TCC1_CTRLB _SFR_MEM8(0x0841) 3207 #define TCC1_CTRLC _SFR_MEM8(0x0842) 3208 #define TCC1_CTRLD _SFR_MEM8(0x0843) 3209 #define TCC1_CTRLE _SFR_MEM8(0x0844) 3210 #define TCC1_INTCTRLA _SFR_MEM8(0x0846) 3211 #define TCC1_INTCTRLB _SFR_MEM8(0x0847) 3212 #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) 3213 #define TCC1_CTRLFSET _SFR_MEM8(0x0849) 3214 #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) 3215 #define TCC1_CTRLGSET _SFR_MEM8(0x084B) 3216 #define TCC1_INTFLAGS _SFR_MEM8(0x084C) 3217 #define TCC1_TEMP _SFR_MEM8(0x084F) 3218 #define TCC1_CNT _SFR_MEM16(0x0860) 3219 #define TCC1_PER _SFR_MEM16(0x0866) 3220 #define TCC1_CCA _SFR_MEM16(0x0868) 3221 #define TCC1_CCB _SFR_MEM16(0x086A) 3222 #define TCC1_PERBUF _SFR_MEM16(0x0876) 3223 #define TCC1_CCABUF _SFR_MEM16(0x0878) 3224 #define TCC1_CCBBUF _SFR_MEM16(0x087A) 3225 3226 /* AWEXC - Advanced Waveform Extension C */ 3227 #define AWEXC_CTRL _SFR_MEM8(0x0880) 3228 #define AWEXC_FDEMASK _SFR_MEM8(0x0882) 3229 #define AWEXC_FDCTRL _SFR_MEM8(0x0883) 3230 #define AWEXC_STATUS _SFR_MEM8(0x0884) 3231 #define AWEXC_DTBOTH _SFR_MEM8(0x0886) 3232 #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) 3233 #define AWEXC_DTLS _SFR_MEM8(0x0888) 3234 #define AWEXC_DTHS _SFR_MEM8(0x0889) 3235 #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) 3236 #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) 3237 #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) 3238 3239 /* HIRESC - High-Resolution Extension C */ 3240 #define HIRESC_CTRLA _SFR_MEM8(0x0890) 3241 3242 /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ 3243 #define USARTC0_DATA _SFR_MEM8(0x08A0) 3244 #define USARTC0_STATUS _SFR_MEM8(0x08A1) 3245 #define USARTC0_CTRLA _SFR_MEM8(0x08A3) 3246 #define USARTC0_CTRLB _SFR_MEM8(0x08A4) 3247 #define USARTC0_CTRLC _SFR_MEM8(0x08A5) 3248 #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) 3249 #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) 3250 3251 /* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ 3252 #define USARTC1_DATA _SFR_MEM8(0x08B0) 3253 #define USARTC1_STATUS _SFR_MEM8(0x08B1) 3254 #define USARTC1_CTRLA _SFR_MEM8(0x08B3) 3255 #define USARTC1_CTRLB _SFR_MEM8(0x08B4) 3256 #define USARTC1_CTRLC _SFR_MEM8(0x08B5) 3257 #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) 3258 #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) 3259 3260 /* SPIC - Serial Peripheral Interface C */ 3261 #define SPIC_CTRL _SFR_MEM8(0x08C0) 3262 #define SPIC_INTCTRL _SFR_MEM8(0x08C1) 3263 #define SPIC_STATUS _SFR_MEM8(0x08C2) 3264 #define SPIC_DATA _SFR_MEM8(0x08C3) 3265 3266 /* IRCOM - IR Communication Module */ 3267 #define IRCOM_CTRL _SFR_MEM8(0x08F8) 3268 #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) 3269 #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) 3270 3271 /* TCD0 - Timer/Counter D0 */ 3272 #define TCD0_CTRLA _SFR_MEM8(0x0900) 3273 #define TCD0_CTRLB _SFR_MEM8(0x0901) 3274 #define TCD0_CTRLC _SFR_MEM8(0x0902) 3275 #define TCD0_CTRLD _SFR_MEM8(0x0903) 3276 #define TCD0_CTRLE _SFR_MEM8(0x0904) 3277 #define TCD0_INTCTRLA _SFR_MEM8(0x0906) 3278 #define TCD0_INTCTRLB _SFR_MEM8(0x0907) 3279 #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) 3280 #define TCD0_CTRLFSET _SFR_MEM8(0x0909) 3281 #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) 3282 #define TCD0_CTRLGSET _SFR_MEM8(0x090B) 3283 #define TCD0_INTFLAGS _SFR_MEM8(0x090C) 3284 #define TCD0_TEMP _SFR_MEM8(0x090F) 3285 #define TCD0_CNT _SFR_MEM16(0x0920) 3286 #define TCD0_PER _SFR_MEM16(0x0926) 3287 #define TCD0_CCA _SFR_MEM16(0x0928) 3288 #define TCD0_CCB _SFR_MEM16(0x092A) 3289 #define TCD0_CCC _SFR_MEM16(0x092C) 3290 #define TCD0_CCD _SFR_MEM16(0x092E) 3291 #define TCD0_PERBUF _SFR_MEM16(0x0936) 3292 #define TCD0_CCABUF _SFR_MEM16(0x0938) 3293 #define TCD0_CCBBUF _SFR_MEM16(0x093A) 3294 #define TCD0_CCCBUF _SFR_MEM16(0x093C) 3295 #define TCD0_CCDBUF _SFR_MEM16(0x093E) 3296 3297 /* TCD1 - Timer/Counter D1 */ 3298 #define TCD1_CTRLA _SFR_MEM8(0x0940) 3299 #define TCD1_CTRLB _SFR_MEM8(0x0941) 3300 #define TCD1_CTRLC _SFR_MEM8(0x0942) 3301 #define TCD1_CTRLD _SFR_MEM8(0x0943) 3302 #define TCD1_CTRLE _SFR_MEM8(0x0944) 3303 #define TCD1_INTCTRLA _SFR_MEM8(0x0946) 3304 #define TCD1_INTCTRLB _SFR_MEM8(0x0947) 3305 #define TCD1_CTRLFCLR _SFR_MEM8(0x0948) 3306 #define TCD1_CTRLFSET _SFR_MEM8(0x0949) 3307 #define TCD1_CTRLGCLR _SFR_MEM8(0x094A) 3308 #define TCD1_CTRLGSET _SFR_MEM8(0x094B) 3309 #define TCD1_INTFLAGS _SFR_MEM8(0x094C) 3310 #define TCD1_TEMP _SFR_MEM8(0x094F) 3311 #define TCD1_CNT _SFR_MEM16(0x0960) 3312 #define TCD1_PER _SFR_MEM16(0x0966) 3313 #define TCD1_CCA _SFR_MEM16(0x0968) 3314 #define TCD1_CCB _SFR_MEM16(0x096A) 3315 #define TCD1_PERBUF _SFR_MEM16(0x0976) 3316 #define TCD1_CCABUF _SFR_MEM16(0x0978) 3317 #define TCD1_CCBBUF _SFR_MEM16(0x097A) 3318 3319 /* HIRESD - High-Resolution Extension D */ 3320 #define HIRESD_CTRLA _SFR_MEM8(0x0990) 3321 3322 /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ 3323 #define USARTD0_DATA _SFR_MEM8(0x09A0) 3324 #define USARTD0_STATUS _SFR_MEM8(0x09A1) 3325 #define USARTD0_CTRLA _SFR_MEM8(0x09A3) 3326 #define USARTD0_CTRLB _SFR_MEM8(0x09A4) 3327 #define USARTD0_CTRLC _SFR_MEM8(0x09A5) 3328 #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) 3329 #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) 3330 3331 /* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ 3332 #define USARTD1_DATA _SFR_MEM8(0x09B0) 3333 #define USARTD1_STATUS _SFR_MEM8(0x09B1) 3334 #define USARTD1_CTRLA _SFR_MEM8(0x09B3) 3335 #define USARTD1_CTRLB _SFR_MEM8(0x09B4) 3336 #define USARTD1_CTRLC _SFR_MEM8(0x09B5) 3337 #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) 3338 #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) 3339 3340 /* SPID - Serial Peripheral Interface D */ 3341 #define SPID_CTRL _SFR_MEM8(0x09C0) 3342 #define SPID_INTCTRL _SFR_MEM8(0x09C1) 3343 #define SPID_STATUS _SFR_MEM8(0x09C2) 3344 #define SPID_DATA _SFR_MEM8(0x09C3) 3345 3346 /* TCE0 - Timer/Counter E0 */ 3347 #define TCE0_CTRLA _SFR_MEM8(0x0A00) 3348 #define TCE0_CTRLB _SFR_MEM8(0x0A01) 3349 #define TCE0_CTRLC _SFR_MEM8(0x0A02) 3350 #define TCE0_CTRLD _SFR_MEM8(0x0A03) 3351 #define TCE0_CTRLE _SFR_MEM8(0x0A04) 3352 #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) 3353 #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) 3354 #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) 3355 #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) 3356 #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) 3357 #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) 3358 #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) 3359 #define TCE0_TEMP _SFR_MEM8(0x0A0F) 3360 #define TCE0_CNT _SFR_MEM16(0x0A20) 3361 #define TCE0_PER _SFR_MEM16(0x0A26) 3362 #define TCE0_CCA _SFR_MEM16(0x0A28) 3363 #define TCE0_CCB _SFR_MEM16(0x0A2A) 3364 #define TCE0_CCC _SFR_MEM16(0x0A2C) 3365 #define TCE0_CCD _SFR_MEM16(0x0A2E) 3366 #define TCE0_PERBUF _SFR_MEM16(0x0A36) 3367 #define TCE0_CCABUF _SFR_MEM16(0x0A38) 3368 #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) 3369 #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) 3370 #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) 3371 3372 /* TCE1 - Timer/Counter E1 */ 3373 #define TCE1_CTRLA _SFR_MEM8(0x0A40) 3374 #define TCE1_CTRLB _SFR_MEM8(0x0A41) 3375 #define TCE1_CTRLC _SFR_MEM8(0x0A42) 3376 #define TCE1_CTRLD _SFR_MEM8(0x0A43) 3377 #define TCE1_CTRLE _SFR_MEM8(0x0A44) 3378 #define TCE1_INTCTRLA _SFR_MEM8(0x0A46) 3379 #define TCE1_INTCTRLB _SFR_MEM8(0x0A47) 3380 #define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) 3381 #define TCE1_CTRLFSET _SFR_MEM8(0x0A49) 3382 #define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) 3383 #define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) 3384 #define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) 3385 #define TCE1_TEMP _SFR_MEM8(0x0A4F) 3386 #define TCE1_CNT _SFR_MEM16(0x0A60) 3387 #define TCE1_PER _SFR_MEM16(0x0A66) 3388 #define TCE1_CCA _SFR_MEM16(0x0A68) 3389 #define TCE1_CCB _SFR_MEM16(0x0A6A) 3390 #define TCE1_PERBUF _SFR_MEM16(0x0A76) 3391 #define TCE1_CCABUF _SFR_MEM16(0x0A78) 3392 #define TCE1_CCBBUF _SFR_MEM16(0x0A7A) 3393 3394 /* AWEXE - Advanced Waveform Extension E */ 3395 #define AWEXE_CTRL _SFR_MEM8(0x0A80) 3396 #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) 3397 #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) 3398 #define AWEXE_STATUS _SFR_MEM8(0x0A84) 3399 #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) 3400 #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) 3401 #define AWEXE_DTLS _SFR_MEM8(0x0A88) 3402 #define AWEXE_DTHS _SFR_MEM8(0x0A89) 3403 #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) 3404 #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) 3405 #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) 3406 3407 /* HIRESE - High-Resolution Extension E */ 3408 #define HIRESE_CTRLA _SFR_MEM8(0x0A90) 3409 3410 /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ 3411 #define USARTE0_DATA _SFR_MEM8(0x0AA0) 3412 #define USARTE0_STATUS _SFR_MEM8(0x0AA1) 3413 #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) 3414 #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) 3415 #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) 3416 #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) 3417 #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) 3418 3419 /* TCF0 - Timer/Counter F0 */ 3420 #define TCF0_CTRLA _SFR_MEM8(0x0B00) 3421 #define TCF0_CTRLB _SFR_MEM8(0x0B01) 3422 #define TCF0_CTRLC _SFR_MEM8(0x0B02) 3423 #define TCF0_CTRLD _SFR_MEM8(0x0B03) 3424 #define TCF0_CTRLE _SFR_MEM8(0x0B04) 3425 #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) 3426 #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) 3427 #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) 3428 #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) 3429 #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) 3430 #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) 3431 #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) 3432 #define TCF0_TEMP _SFR_MEM8(0x0B0F) 3433 #define TCF0_CNT _SFR_MEM16(0x0B20) 3434 #define TCF0_PER _SFR_MEM16(0x0B26) 3435 #define TCF0_CCA _SFR_MEM16(0x0B28) 3436 #define TCF0_CCB _SFR_MEM16(0x0B2A) 3437 #define TCF0_CCC _SFR_MEM16(0x0B2C) 3438 #define TCF0_CCD _SFR_MEM16(0x0B2E) 3439 #define TCF0_PERBUF _SFR_MEM16(0x0B36) 3440 #define TCF0_CCABUF _SFR_MEM16(0x0B38) 3441 #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) 3442 #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) 3443 #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) 3444 3445 /* HIRESF - High-Resolution Extension F */ 3446 #define HIRESF_CTRLA _SFR_MEM8(0x0B90) 3447 3448 /* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ 3449 #define USARTF0_DATA _SFR_MEM8(0x0BA0) 3450 #define USARTF0_STATUS _SFR_MEM8(0x0BA1) 3451 #define USARTF0_CTRLA _SFR_MEM8(0x0BA3) 3452 #define USARTF0_CTRLB _SFR_MEM8(0x0BA4) 3453 #define USARTF0_CTRLC _SFR_MEM8(0x0BA5) 3454 #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) 3455 #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) 3456 3457 /* SPIF - Serial Peripheral Interface F */ 3458 #define SPIF_CTRL _SFR_MEM8(0x0BC0) 3459 #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) 3460 #define SPIF_STATUS _SFR_MEM8(0x0BC2) 3461 #define SPIF_DATA _SFR_MEM8(0x0BC3) 3462 3463 3464 3465 /*================== Bitfield Definitions ================== */ 3466 3467 /* XOCD - On-Chip Debug System */ 3468 /* OCD.OCDR1 bit masks and bit positions */ 3469 #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ 3470 #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ 3471 3472 3473 /* CPU - CPU */ 3474 /* CPU.CCP bit masks and bit positions */ 3475 #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ 3476 #define CPU_CCP_gp 0 /* CCP signature group position. */ 3477 #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ 3478 #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ 3479 #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ 3480 #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ 3481 #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ 3482 #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ 3483 #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ 3484 #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ 3485 #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ 3486 #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ 3487 #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ 3488 #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ 3489 #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ 3490 #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ 3491 #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ 3492 #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ 3493 3494 3495 /* CPU.SREG bit masks and bit positions */ 3496 #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ 3497 #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ 3498 3499 #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ 3500 #define CPU_T_bp 6 /* Transfer Bit bit position. */ 3501 3502 #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ 3503 #define CPU_H_bp 5 /* Half Carry Flag bit position. */ 3504 3505 #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ 3506 #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ 3507 3508 #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ 3509 #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ 3510 3511 #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ 3512 #define CPU_N_bp 2 /* Negative Flag bit position. */ 3513 3514 #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ 3515 #define CPU_Z_bp 1 /* Zero Flag bit position. */ 3516 3517 #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ 3518 #define CPU_C_bp 0 /* Carry Flag bit position. */ 3519 3520 3521 /* CLK - Clock System */ 3522 /* CLK.CTRL bit masks and bit positions */ 3523 #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ 3524 #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ 3525 #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ 3526 #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ 3527 #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ 3528 #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ 3529 #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ 3530 #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ 3531 3532 3533 /* CLK.PSCTRL bit masks and bit positions */ 3534 #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ 3535 #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ 3536 #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ 3537 #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ 3538 #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ 3539 #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ 3540 #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ 3541 #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ 3542 #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ 3543 #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ 3544 #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ 3545 #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ 3546 3547 #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ 3548 #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ 3549 #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ 3550 #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ 3551 #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ 3552 #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ 3553 3554 3555 /* CLK.LOCK bit masks and bit positions */ 3556 #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ 3557 #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ 3558 3559 3560 /* CLK.RTCCTRL bit masks and bit positions */ 3561 #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ 3562 #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ 3563 #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ 3564 #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ 3565 #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ 3566 #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ 3567 #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ 3568 #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ 3569 3570 #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ 3571 #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ 3572 3573 3574 /* PR.PRGEN bit masks and bit positions */ 3575 #define PR_AES_bm 0x10 /* AES bit mask. */ 3576 #define PR_AES_bp 4 /* AES bit position. */ 3577 3578 #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ 3579 #define PR_EBI_bp 3 /* External Bus Interface bit position. */ 3580 3581 #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ 3582 #define PR_RTC_bp 2 /* Real-time Counter bit position. */ 3583 3584 #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ 3585 #define PR_EVSYS_bp 1 /* Event System bit position. */ 3586 3587 #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ 3588 #define PR_DMA_bp 0 /* DMA-Controller bit position. */ 3589 3590 3591 /* PR.PRPA bit masks and bit positions */ 3592 #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ 3593 #define PR_DAC_bp 2 /* Port A DAC bit position. */ 3594 3595 #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ 3596 #define PR_ADC_bp 1 /* Port A ADC bit position. */ 3597 3598 #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ 3599 #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ 3600 3601 3602 /* PR.PRPB bit masks and bit positions */ 3603 /* PR_DAC_bm Predefined. */ 3604 /* PR_DAC_bp Predefined. */ 3605 3606 /* PR_ADC_bm Predefined. */ 3607 /* PR_ADC_bp Predefined. */ 3608 3609 /* PR_AC_bm Predefined. */ 3610 /* PR_AC_bp Predefined. */ 3611 3612 3613 /* PR.PRPC bit masks and bit positions */ 3614 #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ 3615 #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ 3616 3617 #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ 3618 #define PR_USART1_bp 5 /* Port C USART1 bit position. */ 3619 3620 #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ 3621 #define PR_USART0_bp 4 /* Port C USART0 bit position. */ 3622 3623 #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ 3624 #define PR_SPI_bp 3 /* Port C SPI bit position. */ 3625 3626 #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ 3627 #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ 3628 3629 #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ 3630 #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ 3631 3632 #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ 3633 #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ 3634 3635 3636 /* PR.PRPD bit masks and bit positions */ 3637 /* PR_TWI_bm Predefined. */ 3638 /* PR_TWI_bp Predefined. */ 3639 3640 /* PR_USART1_bm Predefined. */ 3641 /* PR_USART1_bp Predefined. */ 3642 3643 /* PR_USART0_bm Predefined. */ 3644 /* PR_USART0_bp Predefined. */ 3645 3646 /* PR_SPI_bm Predefined. */ 3647 /* PR_SPI_bp Predefined. */ 3648 3649 /* PR_HIRES_bm Predefined. */ 3650 /* PR_HIRES_bp Predefined. */ 3651 3652 /* PR_TC1_bm Predefined. */ 3653 /* PR_TC1_bp Predefined. */ 3654 3655 /* PR_TC0_bm Predefined. */ 3656 /* PR_TC0_bp Predefined. */ 3657 3658 3659 /* PR.PRPE bit masks and bit positions */ 3660 /* PR_TWI_bm Predefined. */ 3661 /* PR_TWI_bp Predefined. */ 3662 3663 /* PR_USART1_bm Predefined. */ 3664 /* PR_USART1_bp Predefined. */ 3665 3666 /* PR_USART0_bm Predefined. */ 3667 /* PR_USART0_bp Predefined. */ 3668 3669 /* PR_SPI_bm Predefined. */ 3670 /* PR_SPI_bp Predefined. */ 3671 3672 /* PR_HIRES_bm Predefined. */ 3673 /* PR_HIRES_bp Predefined. */ 3674 3675 /* PR_TC1_bm Predefined. */ 3676 /* PR_TC1_bp Predefined. */ 3677 3678 /* PR_TC0_bm Predefined. */ 3679 /* PR_TC0_bp Predefined. */ 3680 3681 3682 /* PR.PRPF bit masks and bit positions */ 3683 /* PR_TWI_bm Predefined. */ 3684 /* PR_TWI_bp Predefined. */ 3685 3686 /* PR_USART1_bm Predefined. */ 3687 /* PR_USART1_bp Predefined. */ 3688 3689 /* PR_USART0_bm Predefined. */ 3690 /* PR_USART0_bp Predefined. */ 3691 3692 /* PR_SPI_bm Predefined. */ 3693 /* PR_SPI_bp Predefined. */ 3694 3695 /* PR_HIRES_bm Predefined. */ 3696 /* PR_HIRES_bp Predefined. */ 3697 3698 /* PR_TC1_bm Predefined. */ 3699 /* PR_TC1_bp Predefined. */ 3700 3701 /* PR_TC0_bm Predefined. */ 3702 /* PR_TC0_bp Predefined. */ 3703 3704 3705 /* SLEEP - Sleep Controller */ 3706 /* SLEEP.CTRL bit masks and bit positions */ 3707 #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ 3708 #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ 3709 #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ 3710 #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ 3711 #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ 3712 #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ 3713 #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ 3714 #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ 3715 3716 #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ 3717 #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ 3718 3719 3720 /* OSC - Oscillator */ 3721 /* OSC.CTRL bit masks and bit positions */ 3722 #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ 3723 #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ 3724 3725 #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ 3726 #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ 3727 3728 #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ 3729 #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ 3730 3731 #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ 3732 #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ 3733 3734 #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ 3735 #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ 3736 3737 3738 /* OSC.STATUS bit masks and bit positions */ 3739 #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ 3740 #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ 3741 3742 #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ 3743 #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ 3744 3745 #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ 3746 #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ 3747 3748 #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ 3749 #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ 3750 3751 #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ 3752 #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ 3753 3754 3755 /* OSC.XOSCCTRL bit masks and bit positions */ 3756 #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ 3757 #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ 3758 #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ 3759 #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ 3760 #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ 3761 #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ 3762 3763 #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ 3764 #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ 3765 3766 #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ 3767 #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ 3768 #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ 3769 #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ 3770 #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ 3771 #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ 3772 #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ 3773 #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ 3774 #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ 3775 #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ 3776 3777 3778 /* OSC.XOSCFAIL bit masks and bit positions */ 3779 #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ 3780 #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ 3781 3782 #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ 3783 #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ 3784 3785 3786 /* OSC.PLLCTRL bit masks and bit positions */ 3787 #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ 3788 #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ 3789 #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ 3790 #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ 3791 #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ 3792 #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ 3793 3794 #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ 3795 #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ 3796 #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ 3797 #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ 3798 #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ 3799 #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ 3800 #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ 3801 #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ 3802 #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ 3803 #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ 3804 #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ 3805 #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ 3806 3807 3808 /* OSC.DFLLCTRL bit masks and bit positions */ 3809 #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ 3810 #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ 3811 3812 #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ 3813 #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ 3814 3815 3816 /* DFLL - DFLL */ 3817 /* DFLL.CTRL bit masks and bit positions */ 3818 #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ 3819 #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ 3820 3821 3822 /* DFLL.CALA bit masks and bit positions */ 3823 #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ 3824 #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ 3825 #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ 3826 #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ 3827 #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ 3828 #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ 3829 #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ 3830 #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ 3831 #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ 3832 #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ 3833 #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ 3834 #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ 3835 #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ 3836 #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ 3837 #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ 3838 #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ 3839 3840 3841 /* DFLL.CALB bit masks and bit positions */ 3842 #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ 3843 #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ 3844 #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ 3845 #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ 3846 #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ 3847 #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ 3848 #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ 3849 #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ 3850 #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ 3851 #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ 3852 #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ 3853 #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ 3854 #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ 3855 #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ 3856 3857 3858 /* RST - Reset */ 3859 /* RST.STATUS bit masks and bit positions */ 3860 #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ 3861 #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ 3862 3863 #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ 3864 #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ 3865 3866 #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ 3867 #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ 3868 3869 #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ 3870 #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ 3871 3872 #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ 3873 #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ 3874 3875 #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ 3876 #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ 3877 3878 #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ 3879 #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ 3880 3881 3882 /* RST.CTRL bit masks and bit positions */ 3883 #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ 3884 #define RST_SWRST_bp 0 /* Software Reset bit position. */ 3885 3886 3887 /* WDT - Watch-Dog Timer */ 3888 /* WDT.CTRL bit masks and bit positions */ 3889 #define WDT_PER_gm 0x3C /* Period group mask. */ 3890 #define WDT_PER_gp 2 /* Period group position. */ 3891 #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ 3892 #define WDT_PER0_bp 2 /* Period bit 0 position. */ 3893 #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ 3894 #define WDT_PER1_bp 3 /* Period bit 1 position. */ 3895 #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ 3896 #define WDT_PER2_bp 4 /* Period bit 2 position. */ 3897 #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ 3898 #define WDT_PER3_bp 5 /* Period bit 3 position. */ 3899 3900 #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ 3901 #define WDT_ENABLE_bp 1 /* Enable bit position. */ 3902 3903 #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ 3904 #define WDT_CEN_bp 0 /* Change Enable bit position. */ 3905 3906 3907 /* WDT.WINCTRL bit masks and bit positions */ 3908 #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ 3909 #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ 3910 #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ 3911 #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ 3912 #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ 3913 #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ 3914 #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ 3915 #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ 3916 #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ 3917 #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ 3918 3919 #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ 3920 #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ 3921 3922 #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ 3923 #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ 3924 3925 3926 /* WDT.STATUS bit masks and bit positions */ 3927 #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ 3928 #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ 3929 3930 3931 /* MCU - MCU Control */ 3932 /* MCU.MCUCR bit masks and bit positions */ 3933 #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ 3934 #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ 3935 3936 3937 /* MCU.EVSYSLOCK bit masks and bit positions */ 3938 #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ 3939 #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ 3940 3941 #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ 3942 #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ 3943 3944 3945 /* MCU.AWEXLOCK bit masks and bit positions */ 3946 #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ 3947 #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ 3948 3949 #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ 3950 #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ 3951 3952 3953 /* PMIC - Programmable Multi-level Interrupt Controller */ 3954 /* PMIC.STATUS bit masks and bit positions */ 3955 #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ 3956 #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ 3957 3958 #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ 3959 #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ 3960 3961 #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ 3962 #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ 3963 3964 #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ 3965 #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ 3966 3967 3968 /* PMIC.CTRL bit masks and bit positions */ 3969 #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ 3970 #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ 3971 3972 #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ 3973 #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ 3974 3975 #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ 3976 #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ 3977 3978 #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ 3979 #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ 3980 3981 #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ 3982 #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ 3983 3984 3985 /* DMA - DMA Controller */ 3986 /* DMA_CH.CTRLA bit masks and bit positions */ 3987 #define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ 3988 #define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ 3989 3990 #define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ 3991 #define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ 3992 3993 #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ 3994 #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ 3995 3996 #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ 3997 #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ 3998 3999 #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ 4000 #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ 4001 4002 #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ 4003 #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ 4004 #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ 4005 #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ 4006 #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ 4007 #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ 4008 4009 4010 /* DMA_CH.CTRLB bit masks and bit positions */ 4011 #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ 4012 #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ 4013 4014 #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ 4015 #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ 4016 4017 #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ 4018 #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ 4019 4020 #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ 4021 #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ 4022 4023 #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ 4024 #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ 4025 #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ 4026 #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ 4027 #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ 4028 #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ 4029 4030 #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ 4031 #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ 4032 #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ 4033 #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ 4034 #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ 4035 #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ 4036 4037 4038 /* DMA_CH.ADDRCTRL bit masks and bit positions */ 4039 #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ 4040 #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ 4041 #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ 4042 #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ 4043 #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ 4044 #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ 4045 4046 #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ 4047 #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ 4048 #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ 4049 #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ 4050 #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ 4051 #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ 4052 4053 #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ 4054 #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ 4055 #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ 4056 #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ 4057 #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ 4058 #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ 4059 4060 #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ 4061 #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ 4062 #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ 4063 #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ 4064 #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ 4065 #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ 4066 4067 4068 /* DMA_CH.TRIGSRC bit masks and bit positions */ 4069 #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ 4070 #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ 4071 #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ 4072 #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ 4073 #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ 4074 #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ 4075 #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ 4076 #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ 4077 #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ 4078 #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ 4079 #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ 4080 #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ 4081 #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ 4082 #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ 4083 #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ 4084 #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ 4085 #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ 4086 #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ 4087 4088 4089 /* DMA.CTRL bit masks and bit positions */ 4090 #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ 4091 #define DMA_ENABLE_bp 7 /* Enable bit position. */ 4092 4093 #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ 4094 #define DMA_RESET_bp 6 /* Software Reset bit position. */ 4095 4096 #define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ 4097 #define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ 4098 #define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ 4099 #define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ 4100 #define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ 4101 #define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ 4102 4103 #define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ 4104 #define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ 4105 #define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ 4106 #define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ 4107 #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ 4108 #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ 4109 4110 4111 /* DMA.INTFLAGS bit masks and bit positions */ 4112 #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ 4113 #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ 4114 4115 #define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ 4116 #define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ 4117 4118 #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ 4119 #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ 4120 4121 #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ 4122 #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ 4123 4124 #define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ 4125 #define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ 4126 4127 #define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ 4128 #define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ 4129 4130 #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ 4131 #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ 4132 4133 #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ 4134 #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ 4135 4136 4137 /* DMA.STATUS bit masks and bit positions */ 4138 #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ 4139 #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ 4140 4141 #define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ 4142 #define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ 4143 4144 #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ 4145 #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ 4146 4147 #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ 4148 #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ 4149 4150 #define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ 4151 #define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ 4152 4153 #define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ 4154 #define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ 4155 4156 #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ 4157 #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ 4158 4159 #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ 4160 #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ 4161 4162 4163 /* EVSYS - Event System */ 4164 /* EVSYS.CH0MUX bit masks and bit positions */ 4165 #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ 4166 #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ 4167 #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ 4168 #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ 4169 #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ 4170 #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ 4171 #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ 4172 #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ 4173 #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ 4174 #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ 4175 #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ 4176 #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ 4177 #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ 4178 #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ 4179 #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ 4180 #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ 4181 #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ 4182 #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ 4183 4184 4185 /* EVSYS.CH1MUX bit masks and bit positions */ 4186 /* EVSYS_CHMUX_gm Predefined. */ 4187 /* EVSYS_CHMUX_gp Predefined. */ 4188 /* EVSYS_CHMUX0_bm Predefined. */ 4189 /* EVSYS_CHMUX0_bp Predefined. */ 4190 /* EVSYS_CHMUX1_bm Predefined. */ 4191 /* EVSYS_CHMUX1_bp Predefined. */ 4192 /* EVSYS_CHMUX2_bm Predefined. */ 4193 /* EVSYS_CHMUX2_bp Predefined. */ 4194 /* EVSYS_CHMUX3_bm Predefined. */ 4195 /* EVSYS_CHMUX3_bp Predefined. */ 4196 /* EVSYS_CHMUX4_bm Predefined. */ 4197 /* EVSYS_CHMUX4_bp Predefined. */ 4198 /* EVSYS_CHMUX5_bm Predefined. */ 4199 /* EVSYS_CHMUX5_bp Predefined. */ 4200 /* EVSYS_CHMUX6_bm Predefined. */ 4201 /* EVSYS_CHMUX6_bp Predefined. */ 4202 /* EVSYS_CHMUX7_bm Predefined. */ 4203 /* EVSYS_CHMUX7_bp Predefined. */ 4204 4205 4206 /* EVSYS.CH2MUX bit masks and bit positions */ 4207 /* EVSYS_CHMUX_gm Predefined. */ 4208 /* EVSYS_CHMUX_gp Predefined. */ 4209 /* EVSYS_CHMUX0_bm Predefined. */ 4210 /* EVSYS_CHMUX0_bp Predefined. */ 4211 /* EVSYS_CHMUX1_bm Predefined. */ 4212 /* EVSYS_CHMUX1_bp Predefined. */ 4213 /* EVSYS_CHMUX2_bm Predefined. */ 4214 /* EVSYS_CHMUX2_bp Predefined. */ 4215 /* EVSYS_CHMUX3_bm Predefined. */ 4216 /* EVSYS_CHMUX3_bp Predefined. */ 4217 /* EVSYS_CHMUX4_bm Predefined. */ 4218 /* EVSYS_CHMUX4_bp Predefined. */ 4219 /* EVSYS_CHMUX5_bm Predefined. */ 4220 /* EVSYS_CHMUX5_bp Predefined. */ 4221 /* EVSYS_CHMUX6_bm Predefined. */ 4222 /* EVSYS_CHMUX6_bp Predefined. */ 4223 /* EVSYS_CHMUX7_bm Predefined. */ 4224 /* EVSYS_CHMUX7_bp Predefined. */ 4225 4226 4227 /* EVSYS.CH3MUX bit masks and bit positions */ 4228 /* EVSYS_CHMUX_gm Predefined. */ 4229 /* EVSYS_CHMUX_gp Predefined. */ 4230 /* EVSYS_CHMUX0_bm Predefined. */ 4231 /* EVSYS_CHMUX0_bp Predefined. */ 4232 /* EVSYS_CHMUX1_bm Predefined. */ 4233 /* EVSYS_CHMUX1_bp Predefined. */ 4234 /* EVSYS_CHMUX2_bm Predefined. */ 4235 /* EVSYS_CHMUX2_bp Predefined. */ 4236 /* EVSYS_CHMUX3_bm Predefined. */ 4237 /* EVSYS_CHMUX3_bp Predefined. */ 4238 /* EVSYS_CHMUX4_bm Predefined. */ 4239 /* EVSYS_CHMUX4_bp Predefined. */ 4240 /* EVSYS_CHMUX5_bm Predefined. */ 4241 /* EVSYS_CHMUX5_bp Predefined. */ 4242 /* EVSYS_CHMUX6_bm Predefined. */ 4243 /* EVSYS_CHMUX6_bp Predefined. */ 4244 /* EVSYS_CHMUX7_bm Predefined. */ 4245 /* EVSYS_CHMUX7_bp Predefined. */ 4246 4247 4248 /* EVSYS.CH4MUX bit masks and bit positions */ 4249 /* EVSYS_CHMUX_gm Predefined. */ 4250 /* EVSYS_CHMUX_gp Predefined. */ 4251 /* EVSYS_CHMUX0_bm Predefined. */ 4252 /* EVSYS_CHMUX0_bp Predefined. */ 4253 /* EVSYS_CHMUX1_bm Predefined. */ 4254 /* EVSYS_CHMUX1_bp Predefined. */ 4255 /* EVSYS_CHMUX2_bm Predefined. */ 4256 /* EVSYS_CHMUX2_bp Predefined. */ 4257 /* EVSYS_CHMUX3_bm Predefined. */ 4258 /* EVSYS_CHMUX3_bp Predefined. */ 4259 /* EVSYS_CHMUX4_bm Predefined. */ 4260 /* EVSYS_CHMUX4_bp Predefined. */ 4261 /* EVSYS_CHMUX5_bm Predefined. */ 4262 /* EVSYS_CHMUX5_bp Predefined. */ 4263 /* EVSYS_CHMUX6_bm Predefined. */ 4264 /* EVSYS_CHMUX6_bp Predefined. */ 4265 /* EVSYS_CHMUX7_bm Predefined. */ 4266 /* EVSYS_CHMUX7_bp Predefined. */ 4267 4268 4269 /* EVSYS.CH5MUX bit masks and bit positions */ 4270 /* EVSYS_CHMUX_gm Predefined. */ 4271 /* EVSYS_CHMUX_gp Predefined. */ 4272 /* EVSYS_CHMUX0_bm Predefined. */ 4273 /* EVSYS_CHMUX0_bp Predefined. */ 4274 /* EVSYS_CHMUX1_bm Predefined. */ 4275 /* EVSYS_CHMUX1_bp Predefined. */ 4276 /* EVSYS_CHMUX2_bm Predefined. */ 4277 /* EVSYS_CHMUX2_bp Predefined. */ 4278 /* EVSYS_CHMUX3_bm Predefined. */ 4279 /* EVSYS_CHMUX3_bp Predefined. */ 4280 /* EVSYS_CHMUX4_bm Predefined. */ 4281 /* EVSYS_CHMUX4_bp Predefined. */ 4282 /* EVSYS_CHMUX5_bm Predefined. */ 4283 /* EVSYS_CHMUX5_bp Predefined. */ 4284 /* EVSYS_CHMUX6_bm Predefined. */ 4285 /* EVSYS_CHMUX6_bp Predefined. */ 4286 /* EVSYS_CHMUX7_bm Predefined. */ 4287 /* EVSYS_CHMUX7_bp Predefined. */ 4288 4289 4290 /* EVSYS.CH6MUX bit masks and bit positions */ 4291 /* EVSYS_CHMUX_gm Predefined. */ 4292 /* EVSYS_CHMUX_gp Predefined. */ 4293 /* EVSYS_CHMUX0_bm Predefined. */ 4294 /* EVSYS_CHMUX0_bp Predefined. */ 4295 /* EVSYS_CHMUX1_bm Predefined. */ 4296 /* EVSYS_CHMUX1_bp Predefined. */ 4297 /* EVSYS_CHMUX2_bm Predefined. */ 4298 /* EVSYS_CHMUX2_bp Predefined. */ 4299 /* EVSYS_CHMUX3_bm Predefined. */ 4300 /* EVSYS_CHMUX3_bp Predefined. */ 4301 /* EVSYS_CHMUX4_bm Predefined. */ 4302 /* EVSYS_CHMUX4_bp Predefined. */ 4303 /* EVSYS_CHMUX5_bm Predefined. */ 4304 /* EVSYS_CHMUX5_bp Predefined. */ 4305 /* EVSYS_CHMUX6_bm Predefined. */ 4306 /* EVSYS_CHMUX6_bp Predefined. */ 4307 /* EVSYS_CHMUX7_bm Predefined. */ 4308 /* EVSYS_CHMUX7_bp Predefined. */ 4309 4310 4311 /* EVSYS.CH7MUX bit masks and bit positions */ 4312 /* EVSYS_CHMUX_gm Predefined. */ 4313 /* EVSYS_CHMUX_gp Predefined. */ 4314 /* EVSYS_CHMUX0_bm Predefined. */ 4315 /* EVSYS_CHMUX0_bp Predefined. */ 4316 /* EVSYS_CHMUX1_bm Predefined. */ 4317 /* EVSYS_CHMUX1_bp Predefined. */ 4318 /* EVSYS_CHMUX2_bm Predefined. */ 4319 /* EVSYS_CHMUX2_bp Predefined. */ 4320 /* EVSYS_CHMUX3_bm Predefined. */ 4321 /* EVSYS_CHMUX3_bp Predefined. */ 4322 /* EVSYS_CHMUX4_bm Predefined. */ 4323 /* EVSYS_CHMUX4_bp Predefined. */ 4324 /* EVSYS_CHMUX5_bm Predefined. */ 4325 /* EVSYS_CHMUX5_bp Predefined. */ 4326 /* EVSYS_CHMUX6_bm Predefined. */ 4327 /* EVSYS_CHMUX6_bp Predefined. */ 4328 /* EVSYS_CHMUX7_bm Predefined. */ 4329 /* EVSYS_CHMUX7_bp Predefined. */ 4330 4331 4332 /* EVSYS.CH0CTRL bit masks and bit positions */ 4333 #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ 4334 #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ 4335 #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ 4336 #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ 4337 #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ 4338 #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ 4339 4340 #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ 4341 #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ 4342 4343 #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ 4344 #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ 4345 4346 #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ 4347 #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ 4348 #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ 4349 #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ 4350 #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ 4351 #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ 4352 #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ 4353 #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ 4354 4355 4356 /* EVSYS.CH1CTRL bit masks and bit positions */ 4357 /* EVSYS_DIGFILT_gm Predefined. */ 4358 /* EVSYS_DIGFILT_gp Predefined. */ 4359 /* EVSYS_DIGFILT0_bm Predefined. */ 4360 /* EVSYS_DIGFILT0_bp Predefined. */ 4361 /* EVSYS_DIGFILT1_bm Predefined. */ 4362 /* EVSYS_DIGFILT1_bp Predefined. */ 4363 /* EVSYS_DIGFILT2_bm Predefined. */ 4364 /* EVSYS_DIGFILT2_bp Predefined. */ 4365 4366 4367 /* EVSYS.CH2CTRL bit masks and bit positions */ 4368 /* EVSYS_QDIRM_gm Predefined. */ 4369 /* EVSYS_QDIRM_gp Predefined. */ 4370 /* EVSYS_QDIRM0_bm Predefined. */ 4371 /* EVSYS_QDIRM0_bp Predefined. */ 4372 /* EVSYS_QDIRM1_bm Predefined. */ 4373 /* EVSYS_QDIRM1_bp Predefined. */ 4374 4375 /* EVSYS_QDIEN_bm Predefined. */ 4376 /* EVSYS_QDIEN_bp Predefined. */ 4377 4378 /* EVSYS_QDEN_bm Predefined. */ 4379 /* EVSYS_QDEN_bp Predefined. */ 4380 4381 /* EVSYS_DIGFILT_gm Predefined. */ 4382 /* EVSYS_DIGFILT_gp Predefined. */ 4383 /* EVSYS_DIGFILT0_bm Predefined. */ 4384 /* EVSYS_DIGFILT0_bp Predefined. */ 4385 /* EVSYS_DIGFILT1_bm Predefined. */ 4386 /* EVSYS_DIGFILT1_bp Predefined. */ 4387 /* EVSYS_DIGFILT2_bm Predefined. */ 4388 /* EVSYS_DIGFILT2_bp Predefined. */ 4389 4390 4391 /* EVSYS.CH3CTRL bit masks and bit positions */ 4392 /* EVSYS_DIGFILT_gm Predefined. */ 4393 /* EVSYS_DIGFILT_gp Predefined. */ 4394 /* EVSYS_DIGFILT0_bm Predefined. */ 4395 /* EVSYS_DIGFILT0_bp Predefined. */ 4396 /* EVSYS_DIGFILT1_bm Predefined. */ 4397 /* EVSYS_DIGFILT1_bp Predefined. */ 4398 /* EVSYS_DIGFILT2_bm Predefined. */ 4399 /* EVSYS_DIGFILT2_bp Predefined. */ 4400 4401 4402 /* EVSYS.CH4CTRL bit masks and bit positions */ 4403 /* EVSYS_QDIRM_gm Predefined. */ 4404 /* EVSYS_QDIRM_gp Predefined. */ 4405 /* EVSYS_QDIRM0_bm Predefined. */ 4406 /* EVSYS_QDIRM0_bp Predefined. */ 4407 /* EVSYS_QDIRM1_bm Predefined. */ 4408 /* EVSYS_QDIRM1_bp Predefined. */ 4409 4410 /* EVSYS_QDIEN_bm Predefined. */ 4411 /* EVSYS_QDIEN_bp Predefined. */ 4412 4413 /* EVSYS_QDEN_bm Predefined. */ 4414 /* EVSYS_QDEN_bp Predefined. */ 4415 4416 /* EVSYS_DIGFILT_gm Predefined. */ 4417 /* EVSYS_DIGFILT_gp Predefined. */ 4418 /* EVSYS_DIGFILT0_bm Predefined. */ 4419 /* EVSYS_DIGFILT0_bp Predefined. */ 4420 /* EVSYS_DIGFILT1_bm Predefined. */ 4421 /* EVSYS_DIGFILT1_bp Predefined. */ 4422 /* EVSYS_DIGFILT2_bm Predefined. */ 4423 /* EVSYS_DIGFILT2_bp Predefined. */ 4424 4425 4426 /* EVSYS.CH5CTRL bit masks and bit positions */ 4427 /* EVSYS_DIGFILT_gm Predefined. */ 4428 /* EVSYS_DIGFILT_gp Predefined. */ 4429 /* EVSYS_DIGFILT0_bm Predefined. */ 4430 /* EVSYS_DIGFILT0_bp Predefined. */ 4431 /* EVSYS_DIGFILT1_bm Predefined. */ 4432 /* EVSYS_DIGFILT1_bp Predefined. */ 4433 /* EVSYS_DIGFILT2_bm Predefined. */ 4434 /* EVSYS_DIGFILT2_bp Predefined. */ 4435 4436 4437 /* EVSYS.CH6CTRL bit masks and bit positions */ 4438 /* EVSYS_DIGFILT_gm Predefined. */ 4439 /* EVSYS_DIGFILT_gp Predefined. */ 4440 /* EVSYS_DIGFILT0_bm Predefined. */ 4441 /* EVSYS_DIGFILT0_bp Predefined. */ 4442 /* EVSYS_DIGFILT1_bm Predefined. */ 4443 /* EVSYS_DIGFILT1_bp Predefined. */ 4444 /* EVSYS_DIGFILT2_bm Predefined. */ 4445 /* EVSYS_DIGFILT2_bp Predefined. */ 4446 4447 4448 /* EVSYS.CH7CTRL bit masks and bit positions */ 4449 /* EVSYS_DIGFILT_gm Predefined. */ 4450 /* EVSYS_DIGFILT_gp Predefined. */ 4451 /* EVSYS_DIGFILT0_bm Predefined. */ 4452 /* EVSYS_DIGFILT0_bp Predefined. */ 4453 /* EVSYS_DIGFILT1_bm Predefined. */ 4454 /* EVSYS_DIGFILT1_bp Predefined. */ 4455 /* EVSYS_DIGFILT2_bm Predefined. */ 4456 /* EVSYS_DIGFILT2_bp Predefined. */ 4457 4458 4459 /* NVM - Non Volatile Memory Controller */ 4460 /* NVM.CMD bit masks and bit positions */ 4461 #define NVM_CMD_gm 0xFF /* Command group mask. */ 4462 #define NVM_CMD_gp 0 /* Command group position. */ 4463 #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ 4464 #define NVM_CMD0_bp 0 /* Command bit 0 position. */ 4465 #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ 4466 #define NVM_CMD1_bp 1 /* Command bit 1 position. */ 4467 #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ 4468 #define NVM_CMD2_bp 2 /* Command bit 2 position. */ 4469 #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ 4470 #define NVM_CMD3_bp 3 /* Command bit 3 position. */ 4471 #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ 4472 #define NVM_CMD4_bp 4 /* Command bit 4 position. */ 4473 #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ 4474 #define NVM_CMD5_bp 5 /* Command bit 5 position. */ 4475 #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ 4476 #define NVM_CMD6_bp 6 /* Command bit 6 position. */ 4477 #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ 4478 #define NVM_CMD7_bp 7 /* Command bit 7 position. */ 4479 4480 4481 /* NVM.CTRLA bit masks and bit positions */ 4482 #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ 4483 #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ 4484 4485 4486 /* NVM.CTRLB bit masks and bit positions */ 4487 #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ 4488 #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ 4489 4490 #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ 4491 #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ 4492 4493 #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ 4494 #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ 4495 4496 #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ 4497 #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ 4498 4499 4500 /* NVM.INTCTRL bit masks and bit positions */ 4501 #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ 4502 #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ 4503 #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ 4504 #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ 4505 #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ 4506 #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ 4507 4508 #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ 4509 #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ 4510 #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ 4511 #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ 4512 #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ 4513 #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ 4514 4515 4516 /* NVM.STATUS bit masks and bit positions */ 4517 #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ 4518 #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ 4519 4520 #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ 4521 #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ 4522 4523 #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ 4524 #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ 4525 4526 #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ 4527 #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ 4528 4529 4530 /* NVM.LOCKBITS bit masks and bit positions */ 4531 #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ 4532 #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ 4533 #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ 4534 #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ 4535 #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ 4536 #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ 4537 4538 #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ 4539 #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ 4540 #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ 4541 #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ 4542 #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ 4543 #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ 4544 4545 #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ 4546 #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ 4547 #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ 4548 #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ 4549 #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ 4550 #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ 4551 4552 #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ 4553 #define NVM_LB_gp 0 /* Lock Bits group position. */ 4554 #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ 4555 #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ 4556 #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ 4557 #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ 4558 4559 4560 /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ 4561 #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ 4562 #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ 4563 #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ 4564 #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ 4565 #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ 4566 #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ 4567 4568 #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ 4569 #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ 4570 #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ 4571 #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ 4572 #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ 4573 #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ 4574 4575 #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ 4576 #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ 4577 #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ 4578 #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ 4579 #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ 4580 #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ 4581 4582 #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ 4583 #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ 4584 #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ 4585 #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ 4586 #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ 4587 #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ 4588 4589 4590 /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ 4591 #define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ 4592 #define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ 4593 #define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ 4594 #define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ 4595 #define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ 4596 #define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ 4597 #define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ 4598 #define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ 4599 #define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ 4600 #define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ 4601 #define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ 4602 #define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ 4603 #define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ 4604 #define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ 4605 #define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ 4606 #define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ 4607 #define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ 4608 #define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ 4609 4610 4611 /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ 4612 #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ 4613 #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ 4614 #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ 4615 #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ 4616 #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ 4617 #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ 4618 #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ 4619 #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ 4620 #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ 4621 #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ 4622 4623 #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ 4624 #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ 4625 #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ 4626 #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ 4627 #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ 4628 #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ 4629 #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ 4630 #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ 4631 #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ 4632 #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ 4633 4634 4635 /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ 4636 #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ 4637 #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ 4638 4639 #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ 4640 #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ 4641 4642 #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ 4643 #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ 4644 #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ 4645 #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ 4646 #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ 4647 #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ 4648 4649 4650 /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ 4651 #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ 4652 #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ 4653 #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ 4654 #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ 4655 #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ 4656 #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ 4657 4658 #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ 4659 #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ 4660 4661 #define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ 4662 #define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ 4663 4664 4665 /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ 4666 #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ 4667 #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ 4668 #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ 4669 #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ 4670 #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ 4671 #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ 4672 4673 #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ 4674 #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ 4675 4676 #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ 4677 #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ 4678 #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ 4679 #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ 4680 #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ 4681 #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ 4682 #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ 4683 #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ 4684 4685 4686 /* AC - Analog Comparator */ 4687 /* AC.AC0CTRL bit masks and bit positions */ 4688 #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ 4689 #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ 4690 #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ 4691 #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ 4692 #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ 4693 #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ 4694 4695 #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ 4696 #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ 4697 #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ 4698 #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ 4699 #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ 4700 #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ 4701 4702 #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ 4703 #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ 4704 4705 #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ 4706 #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ 4707 #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ 4708 #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ 4709 #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ 4710 #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ 4711 4712 #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ 4713 #define AC_ENABLE_bp 0 /* Enable bit position. */ 4714 4715 4716 /* AC.AC1CTRL bit masks and bit positions */ 4717 /* AC_INTMODE_gm Predefined. */ 4718 /* AC_INTMODE_gp Predefined. */ 4719 /* AC_INTMODE0_bm Predefined. */ 4720 /* AC_INTMODE0_bp Predefined. */ 4721 /* AC_INTMODE1_bm Predefined. */ 4722 /* AC_INTMODE1_bp Predefined. */ 4723 4724 /* AC_INTLVL_gm Predefined. */ 4725 /* AC_INTLVL_gp Predefined. */ 4726 /* AC_INTLVL0_bm Predefined. */ 4727 /* AC_INTLVL0_bp Predefined. */ 4728 /* AC_INTLVL1_bm Predefined. */ 4729 /* AC_INTLVL1_bp Predefined. */ 4730 4731 /* AC_HSMODE_bm Predefined. */ 4732 /* AC_HSMODE_bp Predefined. */ 4733 4734 /* AC_HYSMODE_gm Predefined. */ 4735 /* AC_HYSMODE_gp Predefined. */ 4736 /* AC_HYSMODE0_bm Predefined. */ 4737 /* AC_HYSMODE0_bp Predefined. */ 4738 /* AC_HYSMODE1_bm Predefined. */ 4739 /* AC_HYSMODE1_bp Predefined. */ 4740 4741 /* AC_ENABLE_bm Predefined. */ 4742 /* AC_ENABLE_bp Predefined. */ 4743 4744 4745 /* AC.AC0MUXCTRL bit masks and bit positions */ 4746 #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ 4747 #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ 4748 #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ 4749 #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ 4750 #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ 4751 #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ 4752 #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ 4753 #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ 4754 4755 #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ 4756 #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ 4757 #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ 4758 #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ 4759 #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ 4760 #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ 4761 #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ 4762 #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ 4763 4764 4765 /* AC.AC1MUXCTRL bit masks and bit positions */ 4766 /* AC_MUXPOS_gm Predefined. */ 4767 /* AC_MUXPOS_gp Predefined. */ 4768 /* AC_MUXPOS0_bm Predefined. */ 4769 /* AC_MUXPOS0_bp Predefined. */ 4770 /* AC_MUXPOS1_bm Predefined. */ 4771 /* AC_MUXPOS1_bp Predefined. */ 4772 /* AC_MUXPOS2_bm Predefined. */ 4773 /* AC_MUXPOS2_bp Predefined. */ 4774 4775 /* AC_MUXNEG_gm Predefined. */ 4776 /* AC_MUXNEG_gp Predefined. */ 4777 /* AC_MUXNEG0_bm Predefined. */ 4778 /* AC_MUXNEG0_bp Predefined. */ 4779 /* AC_MUXNEG1_bm Predefined. */ 4780 /* AC_MUXNEG1_bp Predefined. */ 4781 /* AC_MUXNEG2_bm Predefined. */ 4782 /* AC_MUXNEG2_bp Predefined. */ 4783 4784 4785 /* AC.CTRLA bit masks and bit positions */ 4786 #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ 4787 #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ 4788 4789 4790 /* AC.CTRLB bit masks and bit positions */ 4791 #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ 4792 #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ 4793 #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ 4794 #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ 4795 #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ 4796 #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ 4797 #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ 4798 #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ 4799 #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ 4800 #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ 4801 #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ 4802 #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ 4803 #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ 4804 #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ 4805 4806 4807 /* AC.WINCTRL bit masks and bit positions */ 4808 #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ 4809 #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ 4810 4811 #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ 4812 #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ 4813 #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ 4814 #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ 4815 #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ 4816 #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ 4817 4818 #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ 4819 #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ 4820 #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ 4821 #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ 4822 #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ 4823 #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ 4824 4825 4826 /* AC.STATUS bit masks and bit positions */ 4827 #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ 4828 #define AC_WSTATE_gp 6 /* Window Mode State group position. */ 4829 #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ 4830 #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ 4831 #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ 4832 #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ 4833 4834 #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ 4835 #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ 4836 4837 #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ 4838 #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ 4839 4840 #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ 4841 #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ 4842 4843 #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ 4844 #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ 4845 4846 #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ 4847 #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ 4848 4849 4850 /* ADC - Analog/Digital Converter */ 4851 /* ADC_CH.CTRL bit masks and bit positions */ 4852 #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ 4853 #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ 4854 4855 #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ 4856 #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ 4857 #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ 4858 #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ 4859 #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ 4860 #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ 4861 #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ 4862 #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ 4863 4864 #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ 4865 #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ 4866 #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ 4867 #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ 4868 #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ 4869 #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ 4870 4871 4872 /* ADC_CH.MUXCTRL bit masks and bit positions */ 4873 #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ 4874 #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ 4875 #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ 4876 #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ 4877 #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ 4878 #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ 4879 #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ 4880 #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ 4881 #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ 4882 #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ 4883 4884 #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ 4885 #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ 4886 #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ 4887 #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ 4888 #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ 4889 #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ 4890 #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ 4891 #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ 4892 #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ 4893 #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ 4894 4895 #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ 4896 #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ 4897 #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ 4898 #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ 4899 #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ 4900 #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ 4901 4902 4903 /* ADC_CH.INTCTRL bit masks and bit positions */ 4904 #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ 4905 #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ 4906 #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ 4907 #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ 4908 #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ 4909 #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ 4910 4911 #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ 4912 #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ 4913 #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ 4914 #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ 4915 #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ 4916 #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ 4917 4918 4919 /* ADC_CH.INTFLAGS bit masks and bit positions */ 4920 #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ 4921 #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ 4922 4923 4924 /* ADC.CTRLA bit masks and bit positions */ 4925 #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ 4926 #define ADC_DMASEL_gp 6 /* DMA Selection group position. */ 4927 #define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ 4928 #define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ 4929 #define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ 4930 #define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ 4931 4932 #define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ 4933 #define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ 4934 4935 #define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ 4936 #define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ 4937 4938 #define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ 4939 #define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ 4940 4941 #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ 4942 #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ 4943 4944 #define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ 4945 #define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ 4946 4947 #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ 4948 #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ 4949 4950 4951 /* ADC.CTRLB bit masks and bit positions */ 4952 #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ 4953 #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ 4954 4955 #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ 4956 #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ 4957 4958 #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ 4959 #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ 4960 #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ 4961 #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ 4962 #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ 4963 #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ 4964 4965 4966 /* ADC.REFCTRL bit masks and bit positions */ 4967 #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ 4968 #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ 4969 #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ 4970 #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ 4971 #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ 4972 #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ 4973 4974 #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ 4975 #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ 4976 4977 #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ 4978 #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ 4979 4980 4981 /* ADC.EVCTRL bit masks and bit positions */ 4982 #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ 4983 #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ 4984 #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ 4985 #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ 4986 #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ 4987 #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ 4988 4989 #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ 4990 #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ 4991 #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ 4992 #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ 4993 #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ 4994 #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ 4995 #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ 4996 #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ 4997 4998 #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ 4999 #define ADC_EVACT_gp 0 /* Event Action Select group position. */ 5000 #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ 5001 #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ 5002 #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ 5003 #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ 5004 #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ 5005 #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ 5006 5007 5008 /* ADC.PRESCALER bit masks and bit positions */ 5009 #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ 5010 #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ 5011 #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ 5012 #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ 5013 #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ 5014 #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ 5015 #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ 5016 #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ 5017 5018 5019 /* ADC.INTFLAGS bit masks and bit positions */ 5020 #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ 5021 #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ 5022 5023 #define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ 5024 #define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ 5025 5026 #define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ 5027 #define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ 5028 5029 #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ 5030 #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ 5031 5032 5033 /* DAC - Digital/Analog Converter */ 5034 /* DAC.CTRLA bit masks and bit positions */ 5035 #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ 5036 #define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ 5037 5038 #define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ 5039 #define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ 5040 5041 #define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ 5042 #define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ 5043 5044 #define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ 5045 #define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ 5046 5047 #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ 5048 #define DAC_ENABLE_bp 0 /* Enable bit position. */ 5049 5050 5051 /* DAC.CTRLB bit masks and bit positions */ 5052 #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ 5053 #define DAC_CHSEL_gp 5 /* Channel Select group position. */ 5054 #define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ 5055 #define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ 5056 #define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ 5057 #define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ 5058 5059 #define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ 5060 #define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ 5061 5062 #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ 5063 #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ 5064 5065 5066 /* DAC.CTRLC bit masks and bit positions */ 5067 #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ 5068 #define DAC_REFSEL_gp 3 /* Reference Select group position. */ 5069 #define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ 5070 #define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ 5071 #define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ 5072 #define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ 5073 5074 #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ 5075 #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ 5076 5077 5078 /* DAC.EVCTRL bit masks and bit positions */ 5079 #define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ 5080 #define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ 5081 #define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ 5082 #define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ 5083 #define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ 5084 #define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ 5085 #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ 5086 #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ 5087 5088 5089 /* DAC.TIMCTRL bit masks and bit positions */ 5090 #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ 5091 #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ 5092 #define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ 5093 #define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ 5094 #define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ 5095 #define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ 5096 #define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ 5097 #define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ 5098 5099 #define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ 5100 #define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ 5101 #define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ 5102 #define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ 5103 #define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ 5104 #define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ 5105 #define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ 5106 #define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ 5107 #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ 5108 #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ 5109 5110 5111 /* DAC.STATUS bit masks and bit positions */ 5112 #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ 5113 #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ 5114 5115 #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ 5116 #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ 5117 5118 5119 /* RTC32 - 32-bit Real-Time Counter */ 5120 /* RTC32.CTRL bit masks and bit positions */ 5121 #define RTC32_ENABLE_bm 0x01 /* RTC enable bit mask. */ 5122 #define RTC32_ENABLE_bp 0 /* RTC enable bit position. */ 5123 5124 5125 /* RTC32.SYNCCTRL bit masks and bit positions */ 5126 #define RTC32_SYNCCNT_bm 0x10 /* Synchronization Busy Flag bit mask. */ 5127 #define RTC32_SYNCCNT_bp 4 /* Synchronization Busy Flag bit position. */ 5128 5129 #define RTC32_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ 5130 #define RTC32_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ 5131 5132 5133 /* RTC32.INTCTRL bit masks and bit positions */ 5134 #define RTC32_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ 5135 #define RTC32_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ 5136 #define RTC32_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ 5137 #define RTC32_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ 5138 #define RTC32_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ 5139 #define RTC32_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ 5140 5141 #define RTC32_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ 5142 #define RTC32_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ 5143 #define RTC32_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ 5144 #define RTC32_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ 5145 #define RTC32_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ 5146 #define RTC32_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ 5147 5148 5149 /* RTC32.INTFLAGS bit masks and bit positions */ 5150 #define RTC32_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ 5151 #define RTC32_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ 5152 5153 #define RTC32_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 5154 #define RTC32_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 5155 5156 5157 /* EBI - External Bus Interface */ 5158 /* EBI_CS.CTRLA bit masks and bit positions */ 5159 #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ 5160 #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ 5161 #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ 5162 #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ 5163 #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ 5164 #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ 5165 #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ 5166 #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ 5167 #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ 5168 #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ 5169 #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ 5170 #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ 5171 5172 #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ 5173 #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ 5174 #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ 5175 #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ 5176 #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ 5177 #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ 5178 5179 5180 /* EBI_CS.CTRLB bit masks and bit positions */ 5181 #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ 5182 #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ 5183 #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ 5184 #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ 5185 #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ 5186 #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ 5187 #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ 5188 #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ 5189 5190 #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ 5191 #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ 5192 5193 #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ 5194 #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ 5195 5196 #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ 5197 #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ 5198 #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ 5199 #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ 5200 #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ 5201 #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ 5202 5203 5204 /* EBI.CTRL bit masks and bit positions */ 5205 #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ 5206 #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ 5207 #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ 5208 #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ 5209 #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ 5210 #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ 5211 5212 #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ 5213 #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ 5214 #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ 5215 #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ 5216 #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ 5217 #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ 5218 5219 #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ 5220 #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ 5221 #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ 5222 #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ 5223 #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ 5224 #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ 5225 5226 #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ 5227 #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ 5228 #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ 5229 #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ 5230 #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ 5231 #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ 5232 5233 5234 /* EBI.SDRAMCTRLA bit masks and bit positions */ 5235 #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ 5236 #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ 5237 5238 #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ 5239 #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ 5240 5241 #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ 5242 #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ 5243 #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ 5244 #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ 5245 #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ 5246 #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ 5247 5248 5249 /* EBI.SDRAMCTRLB bit masks and bit positions */ 5250 #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ 5251 #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ 5252 #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ 5253 #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ 5254 #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ 5255 #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ 5256 5257 #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ 5258 #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ 5259 #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ 5260 #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ 5261 #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ 5262 #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ 5263 #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ 5264 #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ 5265 5266 #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ 5267 #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ 5268 #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ 5269 #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ 5270 #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ 5271 #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ 5272 #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ 5273 #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ 5274 5275 5276 /* EBI.SDRAMCTRLC bit masks and bit positions */ 5277 #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ 5278 #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ 5279 #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ 5280 #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ 5281 #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ 5282 #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ 5283 5284 #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ 5285 #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ 5286 #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ 5287 #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ 5288 #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ 5289 #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ 5290 #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ 5291 #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ 5292 5293 #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ 5294 #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ 5295 #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ 5296 #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ 5297 #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ 5298 #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ 5299 #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ 5300 #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ 5301 5302 5303 /* TWI - Two-Wire Interface */ 5304 /* TWI_MASTER.CTRLA bit masks and bit positions */ 5305 #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ 5306 #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ 5307 #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ 5308 #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ 5309 #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ 5310 #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ 5311 5312 #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ 5313 #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ 5314 5315 #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ 5316 #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ 5317 5318 #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ 5319 #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ 5320 5321 5322 /* TWI_MASTER.CTRLB bit masks and bit positions */ 5323 #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ 5324 #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ 5325 #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ 5326 #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ 5327 #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ 5328 #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ 5329 5330 #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ 5331 #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ 5332 5333 #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ 5334 #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ 5335 5336 5337 /* TWI_MASTER.CTRLC bit masks and bit positions */ 5338 #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ 5339 #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ 5340 5341 #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ 5342 #define TWI_MASTER_CMD_gp 0 /* Command group position. */ 5343 #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ 5344 #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ 5345 #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ 5346 #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ 5347 5348 5349 /* TWI_MASTER.STATUS bit masks and bit positions */ 5350 #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ 5351 #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ 5352 5353 #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ 5354 #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ 5355 5356 #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ 5357 #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ 5358 5359 #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ 5360 #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ 5361 5362 #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ 5363 #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ 5364 5365 #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ 5366 #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ 5367 5368 #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ 5369 #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ 5370 #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ 5371 #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ 5372 #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ 5373 #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ 5374 5375 5376 /* TWI_SLAVE.CTRLA bit masks and bit positions */ 5377 #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ 5378 #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ 5379 #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ 5380 #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ 5381 #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ 5382 #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ 5383 5384 #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ 5385 #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ 5386 5387 #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ 5388 #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ 5389 5390 #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ 5391 #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ 5392 5393 #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ 5394 #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ 5395 5396 #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ 5397 #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ 5398 5399 #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ 5400 #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ 5401 5402 5403 /* TWI_SLAVE.CTRLB bit masks and bit positions */ 5404 #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ 5405 #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ 5406 5407 #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ 5408 #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ 5409 #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ 5410 #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ 5411 #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ 5412 #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ 5413 5414 5415 /* TWI_SLAVE.STATUS bit masks and bit positions */ 5416 #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ 5417 #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ 5418 5419 #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ 5420 #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ 5421 5422 #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ 5423 #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ 5424 5425 #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ 5426 #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ 5427 5428 #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ 5429 #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ 5430 5431 #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ 5432 #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ 5433 5434 #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ 5435 #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ 5436 5437 #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ 5438 #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ 5439 5440 5441 /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ 5442 #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ 5443 #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ 5444 #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ 5445 #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ 5446 #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ 5447 #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ 5448 #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ 5449 #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ 5450 #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ 5451 #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ 5452 #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ 5453 #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ 5454 #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ 5455 #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ 5456 #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ 5457 #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ 5458 5459 #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ 5460 #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ 5461 5462 5463 /* TWI.CTRL bit masks and bit positions */ 5464 #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ 5465 #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ 5466 5467 #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ 5468 #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ 5469 5470 5471 /* PORT - Port Configuration */ 5472 /* PORTCFG.VPCTRLA bit masks and bit positions */ 5473 #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ 5474 #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ 5475 #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ 5476 #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ 5477 #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ 5478 #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ 5479 #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ 5480 #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ 5481 #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ 5482 #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ 5483 5484 #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ 5485 #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ 5486 #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ 5487 #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ 5488 #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ 5489 #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ 5490 #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ 5491 #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ 5492 #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ 5493 #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ 5494 5495 5496 /* PORTCFG.VPCTRLB bit masks and bit positions */ 5497 #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ 5498 #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ 5499 #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ 5500 #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ 5501 #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ 5502 #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ 5503 #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ 5504 #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ 5505 #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ 5506 #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ 5507 5508 #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ 5509 #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ 5510 #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ 5511 #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ 5512 #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ 5513 #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ 5514 #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ 5515 #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ 5516 #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ 5517 #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ 5518 5519 5520 /* PORTCFG.CLKEVOUT bit masks and bit positions */ 5521 #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ 5522 #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ 5523 #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ 5524 #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ 5525 #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ 5526 #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ 5527 5528 #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ 5529 #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ 5530 #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ 5531 #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ 5532 #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ 5533 #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ 5534 5535 5536 /* VPORT.INTFLAGS bit masks and bit positions */ 5537 #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ 5538 #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ 5539 5540 #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ 5541 #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ 5542 5543 5544 /* PORT.INTCTRL bit masks and bit positions */ 5545 #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ 5546 #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ 5547 #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ 5548 #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ 5549 #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ 5550 #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ 5551 5552 #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ 5553 #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ 5554 #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ 5555 #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ 5556 #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ 5557 #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ 5558 5559 5560 /* PORT.INTFLAGS bit masks and bit positions */ 5561 #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ 5562 #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ 5563 5564 #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ 5565 #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ 5566 5567 5568 /* PORT.PIN0CTRL bit masks and bit positions */ 5569 #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ 5570 #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ 5571 5572 #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ 5573 #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ 5574 5575 #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ 5576 #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ 5577 #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ 5578 #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ 5579 #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ 5580 #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ 5581 #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ 5582 #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ 5583 5584 #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ 5585 #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ 5586 #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ 5587 #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ 5588 #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ 5589 #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ 5590 #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ 5591 #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ 5592 5593 5594 /* PORT.PIN1CTRL bit masks and bit positions */ 5595 /* PORT_SRLEN_bm Predefined. */ 5596 /* PORT_SRLEN_bp Predefined. */ 5597 5598 /* PORT_INVEN_bm Predefined. */ 5599 /* PORT_INVEN_bp Predefined. */ 5600 5601 /* PORT_OPC_gm Predefined. */ 5602 /* PORT_OPC_gp Predefined. */ 5603 /* PORT_OPC0_bm Predefined. */ 5604 /* PORT_OPC0_bp Predefined. */ 5605 /* PORT_OPC1_bm Predefined. */ 5606 /* PORT_OPC1_bp Predefined. */ 5607 /* PORT_OPC2_bm Predefined. */ 5608 /* PORT_OPC2_bp Predefined. */ 5609 5610 /* PORT_ISC_gm Predefined. */ 5611 /* PORT_ISC_gp Predefined. */ 5612 /* PORT_ISC0_bm Predefined. */ 5613 /* PORT_ISC0_bp Predefined. */ 5614 /* PORT_ISC1_bm Predefined. */ 5615 /* PORT_ISC1_bp Predefined. */ 5616 /* PORT_ISC2_bm Predefined. */ 5617 /* PORT_ISC2_bp Predefined. */ 5618 5619 5620 /* PORT.PIN2CTRL bit masks and bit positions */ 5621 /* PORT_SRLEN_bm Predefined. */ 5622 /* PORT_SRLEN_bp Predefined. */ 5623 5624 /* PORT_INVEN_bm Predefined. */ 5625 /* PORT_INVEN_bp Predefined. */ 5626 5627 /* PORT_OPC_gm Predefined. */ 5628 /* PORT_OPC_gp Predefined. */ 5629 /* PORT_OPC0_bm Predefined. */ 5630 /* PORT_OPC0_bp Predefined. */ 5631 /* PORT_OPC1_bm Predefined. */ 5632 /* PORT_OPC1_bp Predefined. */ 5633 /* PORT_OPC2_bm Predefined. */ 5634 /* PORT_OPC2_bp Predefined. */ 5635 5636 /* PORT_ISC_gm Predefined. */ 5637 /* PORT_ISC_gp Predefined. */ 5638 /* PORT_ISC0_bm Predefined. */ 5639 /* PORT_ISC0_bp Predefined. */ 5640 /* PORT_ISC1_bm Predefined. */ 5641 /* PORT_ISC1_bp Predefined. */ 5642 /* PORT_ISC2_bm Predefined. */ 5643 /* PORT_ISC2_bp Predefined. */ 5644 5645 5646 /* PORT.PIN3CTRL bit masks and bit positions */ 5647 /* PORT_SRLEN_bm Predefined. */ 5648 /* PORT_SRLEN_bp Predefined. */ 5649 5650 /* PORT_INVEN_bm Predefined. */ 5651 /* PORT_INVEN_bp Predefined. */ 5652 5653 /* PORT_OPC_gm Predefined. */ 5654 /* PORT_OPC_gp Predefined. */ 5655 /* PORT_OPC0_bm Predefined. */ 5656 /* PORT_OPC0_bp Predefined. */ 5657 /* PORT_OPC1_bm Predefined. */ 5658 /* PORT_OPC1_bp Predefined. */ 5659 /* PORT_OPC2_bm Predefined. */ 5660 /* PORT_OPC2_bp Predefined. */ 5661 5662 /* PORT_ISC_gm Predefined. */ 5663 /* PORT_ISC_gp Predefined. */ 5664 /* PORT_ISC0_bm Predefined. */ 5665 /* PORT_ISC0_bp Predefined. */ 5666 /* PORT_ISC1_bm Predefined. */ 5667 /* PORT_ISC1_bp Predefined. */ 5668 /* PORT_ISC2_bm Predefined. */ 5669 /* PORT_ISC2_bp Predefined. */ 5670 5671 5672 /* PORT.PIN4CTRL bit masks and bit positions */ 5673 /* PORT_SRLEN_bm Predefined. */ 5674 /* PORT_SRLEN_bp Predefined. */ 5675 5676 /* PORT_INVEN_bm Predefined. */ 5677 /* PORT_INVEN_bp Predefined. */ 5678 5679 /* PORT_OPC_gm Predefined. */ 5680 /* PORT_OPC_gp Predefined. */ 5681 /* PORT_OPC0_bm Predefined. */ 5682 /* PORT_OPC0_bp Predefined. */ 5683 /* PORT_OPC1_bm Predefined. */ 5684 /* PORT_OPC1_bp Predefined. */ 5685 /* PORT_OPC2_bm Predefined. */ 5686 /* PORT_OPC2_bp Predefined. */ 5687 5688 /* PORT_ISC_gm Predefined. */ 5689 /* PORT_ISC_gp Predefined. */ 5690 /* PORT_ISC0_bm Predefined. */ 5691 /* PORT_ISC0_bp Predefined. */ 5692 /* PORT_ISC1_bm Predefined. */ 5693 /* PORT_ISC1_bp Predefined. */ 5694 /* PORT_ISC2_bm Predefined. */ 5695 /* PORT_ISC2_bp Predefined. */ 5696 5697 5698 /* PORT.PIN5CTRL bit masks and bit positions */ 5699 /* PORT_SRLEN_bm Predefined. */ 5700 /* PORT_SRLEN_bp Predefined. */ 5701 5702 /* PORT_INVEN_bm Predefined. */ 5703 /* PORT_INVEN_bp Predefined. */ 5704 5705 /* PORT_OPC_gm Predefined. */ 5706 /* PORT_OPC_gp Predefined. */ 5707 /* PORT_OPC0_bm Predefined. */ 5708 /* PORT_OPC0_bp Predefined. */ 5709 /* PORT_OPC1_bm Predefined. */ 5710 /* PORT_OPC1_bp Predefined. */ 5711 /* PORT_OPC2_bm Predefined. */ 5712 /* PORT_OPC2_bp Predefined. */ 5713 5714 /* PORT_ISC_gm Predefined. */ 5715 /* PORT_ISC_gp Predefined. */ 5716 /* PORT_ISC0_bm Predefined. */ 5717 /* PORT_ISC0_bp Predefined. */ 5718 /* PORT_ISC1_bm Predefined. */ 5719 /* PORT_ISC1_bp Predefined. */ 5720 /* PORT_ISC2_bm Predefined. */ 5721 /* PORT_ISC2_bp Predefined. */ 5722 5723 5724 /* PORT.PIN6CTRL bit masks and bit positions */ 5725 /* PORT_SRLEN_bm Predefined. */ 5726 /* PORT_SRLEN_bp Predefined. */ 5727 5728 /* PORT_INVEN_bm Predefined. */ 5729 /* PORT_INVEN_bp Predefined. */ 5730 5731 /* PORT_OPC_gm Predefined. */ 5732 /* PORT_OPC_gp Predefined. */ 5733 /* PORT_OPC0_bm Predefined. */ 5734 /* PORT_OPC0_bp Predefined. */ 5735 /* PORT_OPC1_bm Predefined. */ 5736 /* PORT_OPC1_bp Predefined. */ 5737 /* PORT_OPC2_bm Predefined. */ 5738 /* PORT_OPC2_bp Predefined. */ 5739 5740 /* PORT_ISC_gm Predefined. */ 5741 /* PORT_ISC_gp Predefined. */ 5742 /* PORT_ISC0_bm Predefined. */ 5743 /* PORT_ISC0_bp Predefined. */ 5744 /* PORT_ISC1_bm Predefined. */ 5745 /* PORT_ISC1_bp Predefined. */ 5746 /* PORT_ISC2_bm Predefined. */ 5747 /* PORT_ISC2_bp Predefined. */ 5748 5749 5750 /* PORT.PIN7CTRL bit masks and bit positions */ 5751 /* PORT_SRLEN_bm Predefined. */ 5752 /* PORT_SRLEN_bp Predefined. */ 5753 5754 /* PORT_INVEN_bm Predefined. */ 5755 /* PORT_INVEN_bp Predefined. */ 5756 5757 /* PORT_OPC_gm Predefined. */ 5758 /* PORT_OPC_gp Predefined. */ 5759 /* PORT_OPC0_bm Predefined. */ 5760 /* PORT_OPC0_bp Predefined. */ 5761 /* PORT_OPC1_bm Predefined. */ 5762 /* PORT_OPC1_bp Predefined. */ 5763 /* PORT_OPC2_bm Predefined. */ 5764 /* PORT_OPC2_bp Predefined. */ 5765 5766 /* PORT_ISC_gm Predefined. */ 5767 /* PORT_ISC_gp Predefined. */ 5768 /* PORT_ISC0_bm Predefined. */ 5769 /* PORT_ISC0_bp Predefined. */ 5770 /* PORT_ISC1_bm Predefined. */ 5771 /* PORT_ISC1_bp Predefined. */ 5772 /* PORT_ISC2_bm Predefined. */ 5773 /* PORT_ISC2_bp Predefined. */ 5774 5775 5776 /* TC - 16-bit Timer/Counter With PWM */ 5777 /* TC0.CTRLA bit masks and bit positions */ 5778 #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 5779 #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ 5780 #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 5781 #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 5782 #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 5783 #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 5784 #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 5785 #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 5786 #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 5787 #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 5788 5789 5790 /* TC0.CTRLB bit masks and bit positions */ 5791 #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ 5792 #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ 5793 5794 #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ 5795 #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ 5796 5797 #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ 5798 #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ 5799 5800 #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ 5801 #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ 5802 5803 #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ 5804 #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ 5805 #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ 5806 #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ 5807 #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ 5808 #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ 5809 #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ 5810 #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ 5811 5812 5813 /* TC0.CTRLC bit masks and bit positions */ 5814 #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ 5815 #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ 5816 5817 #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ 5818 #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ 5819 5820 #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ 5821 #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ 5822 5823 #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ 5824 #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ 5825 5826 5827 /* TC0.CTRLD bit masks and bit positions */ 5828 #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ 5829 #define TC0_EVACT_gp 5 /* Event Action group position. */ 5830 #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ 5831 #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ 5832 #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ 5833 #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ 5834 #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ 5835 #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ 5836 5837 #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ 5838 #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ 5839 5840 #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ 5841 #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ 5842 #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ 5843 #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ 5844 #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ 5845 #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ 5846 #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ 5847 #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ 5848 #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ 5849 #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ 5850 5851 5852 /* TC0.CTRLE bit masks and bit positions */ 5853 #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ 5854 #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ 5855 5856 #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ 5857 #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ 5858 5859 5860 /* TC0.INTCTRLA bit masks and bit positions */ 5861 #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ 5862 #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ 5863 #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ 5864 #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ 5865 #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ 5866 #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ 5867 5868 #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ 5869 #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ 5870 #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ 5871 #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ 5872 #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ 5873 #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ 5874 5875 5876 /* TC0.INTCTRLB bit masks and bit positions */ 5877 #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ 5878 #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ 5879 #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ 5880 #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ 5881 #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ 5882 #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ 5883 5884 #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ 5885 #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ 5886 #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ 5887 #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ 5888 #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ 5889 #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ 5890 5891 #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ 5892 #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ 5893 #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ 5894 #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ 5895 #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ 5896 #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ 5897 5898 #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ 5899 #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ 5900 #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ 5901 #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ 5902 #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ 5903 #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ 5904 5905 5906 /* TC0.CTRLFCLR bit masks and bit positions */ 5907 #define TC0_CMD_gm 0x0C /* Command group mask. */ 5908 #define TC0_CMD_gp 2 /* Command group position. */ 5909 #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ 5910 #define TC0_CMD0_bp 2 /* Command bit 0 position. */ 5911 #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ 5912 #define TC0_CMD1_bp 3 /* Command bit 1 position. */ 5913 5914 #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ 5915 #define TC0_LUPD_bp 1 /* Lock Update bit position. */ 5916 5917 #define TC0_DIR_bm 0x01 /* Direction bit mask. */ 5918 #define TC0_DIR_bp 0 /* Direction bit position. */ 5919 5920 5921 /* TC0.CTRLFSET bit masks and bit positions */ 5922 /* TC0_CMD_gm Predefined. */ 5923 /* TC0_CMD_gp Predefined. */ 5924 /* TC0_CMD0_bm Predefined. */ 5925 /* TC0_CMD0_bp Predefined. */ 5926 /* TC0_CMD1_bm Predefined. */ 5927 /* TC0_CMD1_bp Predefined. */ 5928 5929 /* TC0_LUPD_bm Predefined. */ 5930 /* TC0_LUPD_bp Predefined. */ 5931 5932 /* TC0_DIR_bm Predefined. */ 5933 /* TC0_DIR_bp Predefined. */ 5934 5935 5936 /* TC0.CTRLGCLR bit masks and bit positions */ 5937 #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ 5938 #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ 5939 5940 #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ 5941 #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ 5942 5943 #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ 5944 #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ 5945 5946 #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ 5947 #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ 5948 5949 #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ 5950 #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ 5951 5952 5953 /* TC0.CTRLGSET bit masks and bit positions */ 5954 /* TC0_CCDBV_bm Predefined. */ 5955 /* TC0_CCDBV_bp Predefined. */ 5956 5957 /* TC0_CCCBV_bm Predefined. */ 5958 /* TC0_CCCBV_bp Predefined. */ 5959 5960 /* TC0_CCBBV_bm Predefined. */ 5961 /* TC0_CCBBV_bp Predefined. */ 5962 5963 /* TC0_CCABV_bm Predefined. */ 5964 /* TC0_CCABV_bp Predefined. */ 5965 5966 /* TC0_PERBV_bm Predefined. */ 5967 /* TC0_PERBV_bp Predefined. */ 5968 5969 5970 /* TC0.INTFLAGS bit masks and bit positions */ 5971 #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ 5972 #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ 5973 5974 #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ 5975 #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ 5976 5977 #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ 5978 #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ 5979 5980 #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ 5981 #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ 5982 5983 #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ 5984 #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ 5985 5986 #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 5987 #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 5988 5989 5990 /* TC1.CTRLA bit masks and bit positions */ 5991 #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 5992 #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ 5993 #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 5994 #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 5995 #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 5996 #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 5997 #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 5998 #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 5999 #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 6000 #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 6001 6002 6003 /* TC1.CTRLB bit masks and bit positions */ 6004 #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ 6005 #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ 6006 6007 #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ 6008 #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ 6009 6010 #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ 6011 #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ 6012 #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ 6013 #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ 6014 #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ 6015 #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ 6016 #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ 6017 #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ 6018 6019 6020 /* TC1.CTRLC bit masks and bit positions */ 6021 #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ 6022 #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ 6023 6024 #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ 6025 #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ 6026 6027 6028 /* TC1.CTRLD bit masks and bit positions */ 6029 #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ 6030 #define TC1_EVACT_gp 5 /* Event Action group position. */ 6031 #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ 6032 #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ 6033 #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ 6034 #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ 6035 #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ 6036 #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ 6037 6038 #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ 6039 #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ 6040 6041 #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ 6042 #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ 6043 #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ 6044 #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ 6045 #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ 6046 #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ 6047 #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ 6048 #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ 6049 #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ 6050 #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ 6051 6052 6053 /* TC1.CTRLE bit masks and bit positions */ 6054 #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ 6055 #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ 6056 6057 #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ 6058 #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ 6059 6060 6061 /* TC1.INTCTRLA bit masks and bit positions */ 6062 #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ 6063 #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ 6064 #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ 6065 #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ 6066 #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ 6067 #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ 6068 6069 #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ 6070 #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ 6071 #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ 6072 #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ 6073 #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ 6074 #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ 6075 6076 6077 /* TC1.INTCTRLB bit masks and bit positions */ 6078 #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ 6079 #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ 6080 #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ 6081 #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ 6082 #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ 6083 #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ 6084 6085 #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ 6086 #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ 6087 #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ 6088 #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ 6089 #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ 6090 #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ 6091 6092 6093 /* TC1.CTRLFCLR bit masks and bit positions */ 6094 #define TC1_CMD_gm 0x0C /* Command group mask. */ 6095 #define TC1_CMD_gp 2 /* Command group position. */ 6096 #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ 6097 #define TC1_CMD0_bp 2 /* Command bit 0 position. */ 6098 #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ 6099 #define TC1_CMD1_bp 3 /* Command bit 1 position. */ 6100 6101 #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ 6102 #define TC1_LUPD_bp 1 /* Lock Update bit position. */ 6103 6104 #define TC1_DIR_bm 0x01 /* Direction bit mask. */ 6105 #define TC1_DIR_bp 0 /* Direction bit position. */ 6106 6107 6108 /* TC1.CTRLFSET bit masks and bit positions */ 6109 /* TC1_CMD_gm Predefined. */ 6110 /* TC1_CMD_gp Predefined. */ 6111 /* TC1_CMD0_bm Predefined. */ 6112 /* TC1_CMD0_bp Predefined. */ 6113 /* TC1_CMD1_bm Predefined. */ 6114 /* TC1_CMD1_bp Predefined. */ 6115 6116 /* TC1_LUPD_bm Predefined. */ 6117 /* TC1_LUPD_bp Predefined. */ 6118 6119 /* TC1_DIR_bm Predefined. */ 6120 /* TC1_DIR_bp Predefined. */ 6121 6122 6123 /* TC1.CTRLGCLR bit masks and bit positions */ 6124 #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ 6125 #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ 6126 6127 #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ 6128 #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ 6129 6130 #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ 6131 #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ 6132 6133 6134 /* TC1.CTRLGSET bit masks and bit positions */ 6135 /* TC1_CCBBV_bm Predefined. */ 6136 /* TC1_CCBBV_bp Predefined. */ 6137 6138 /* TC1_CCABV_bm Predefined. */ 6139 /* TC1_CCABV_bp Predefined. */ 6140 6141 /* TC1_PERBV_bm Predefined. */ 6142 /* TC1_PERBV_bp Predefined. */ 6143 6144 6145 /* TC1.INTFLAGS bit masks and bit positions */ 6146 #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ 6147 #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ 6148 6149 #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ 6150 #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ 6151 6152 #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ 6153 #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ 6154 6155 #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 6156 #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 6157 6158 6159 /* AWEX.CTRL bit masks and bit positions */ 6160 #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ 6161 #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ 6162 6163 #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ 6164 #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ 6165 6166 #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ 6167 #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ 6168 6169 #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ 6170 #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ 6171 6172 #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ 6173 #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ 6174 6175 #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ 6176 #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ 6177 6178 6179 /* AWEX.FDCTRL bit masks and bit positions */ 6180 #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ 6181 #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ 6182 6183 #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ 6184 #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ 6185 6186 #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ 6187 #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ 6188 #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ 6189 #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ 6190 #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ 6191 #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ 6192 6193 6194 /* AWEX.STATUS bit masks and bit positions */ 6195 #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ 6196 #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ 6197 6198 #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ 6199 #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ 6200 6201 #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ 6202 #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ 6203 6204 6205 /* HIRES.CTRL bit masks and bit positions */ 6206 #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ 6207 #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ 6208 #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ 6209 #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ 6210 #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ 6211 #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ 6212 6213 6214 /* USART - Universal Asynchronous Receiver-Transmitter */ 6215 /* USART.STATUS bit masks and bit positions */ 6216 #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ 6217 #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ 6218 6219 #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ 6220 #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ 6221 6222 #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ 6223 #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ 6224 6225 #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ 6226 #define USART_FERR_bp 4 /* Frame Error bit position. */ 6227 6228 #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ 6229 #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ 6230 6231 #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ 6232 #define USART_PERR_bp 2 /* Parity Error bit position. */ 6233 6234 #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ 6235 #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ 6236 6237 6238 /* USART.CTRLA bit masks and bit positions */ 6239 #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ 6240 #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ 6241 #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ 6242 #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ 6243 #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ 6244 #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ 6245 6246 #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ 6247 #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ 6248 #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ 6249 #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ 6250 #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ 6251 #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ 6252 6253 #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ 6254 #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ 6255 #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ 6256 #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ 6257 #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ 6258 #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ 6259 6260 6261 /* USART.CTRLB bit masks and bit positions */ 6262 #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ 6263 #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ 6264 6265 #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ 6266 #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ 6267 6268 #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ 6269 #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ 6270 6271 #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ 6272 #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ 6273 6274 #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ 6275 #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ 6276 6277 6278 /* USART.CTRLC bit masks and bit positions */ 6279 #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ 6280 #define USART_CMODE_gp 6 /* Communication Mode group position. */ 6281 #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ 6282 #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ 6283 #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ 6284 #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ 6285 6286 #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ 6287 #define USART_PMODE_gp 4 /* Parity Mode group position. */ 6288 #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ 6289 #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ 6290 #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ 6291 #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ 6292 6293 #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ 6294 #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ 6295 6296 #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ 6297 #define USART_CHSIZE_gp 0 /* Character Size group position. */ 6298 #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ 6299 #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ 6300 #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ 6301 #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ 6302 #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ 6303 #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ 6304 6305 6306 /* USART.BAUDCTRLA bit masks and bit positions */ 6307 #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ 6308 #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ 6309 #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ 6310 #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ 6311 #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ 6312 #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ 6313 #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ 6314 #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ 6315 #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ 6316 #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ 6317 #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ 6318 #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ 6319 #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ 6320 #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ 6321 #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ 6322 #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ 6323 #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ 6324 #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ 6325 6326 6327 /* USART.BAUDCTRLB bit masks and bit positions */ 6328 #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ 6329 #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ 6330 #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ 6331 #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ 6332 #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ 6333 #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ 6334 #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ 6335 #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ 6336 #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ 6337 #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ 6338 6339 /* USART_BSEL_gm Predefined. */ 6340 /* USART_BSEL_gp Predefined. */ 6341 /* USART_BSEL0_bm Predefined. */ 6342 /* USART_BSEL0_bp Predefined. */ 6343 /* USART_BSEL1_bm Predefined. */ 6344 /* USART_BSEL1_bp Predefined. */ 6345 /* USART_BSEL2_bm Predefined. */ 6346 /* USART_BSEL2_bp Predefined. */ 6347 /* USART_BSEL3_bm Predefined. */ 6348 /* USART_BSEL3_bp Predefined. */ 6349 6350 6351 /* SPI - Serial Peripheral Interface */ 6352 /* SPI.CTRL bit masks and bit positions */ 6353 #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ 6354 #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ 6355 6356 #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ 6357 #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ 6358 6359 #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ 6360 #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ 6361 6362 #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ 6363 #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ 6364 6365 #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ 6366 #define SPI_MODE_gp 2 /* SPI Mode group position. */ 6367 #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ 6368 #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ 6369 #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ 6370 #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ 6371 6372 #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ 6373 #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ 6374 #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ 6375 #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ 6376 #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ 6377 #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ 6378 6379 6380 /* SPI.INTCTRL bit masks and bit positions */ 6381 #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ 6382 #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ 6383 #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ 6384 #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ 6385 #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ 6386 #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ 6387 6388 6389 /* SPI.STATUS bit masks and bit positions */ 6390 #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ 6391 #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ 6392 6393 #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ 6394 #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ 6395 6396 6397 /* IRCOM - IR Communication Module */ 6398 /* IRCOM.CTRL bit masks and bit positions */ 6399 #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ 6400 #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ 6401 #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ 6402 #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ 6403 #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ 6404 #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ 6405 #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ 6406 #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ 6407 #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ 6408 #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ 6409 6410 6411 /* AES - AES Module */ 6412 /* AES.CTRL bit masks and bit positions */ 6413 #define AES_START_bm 0x80 /* Start/Run bit mask. */ 6414 #define AES_START_bp 7 /* Start/Run bit position. */ 6415 6416 #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ 6417 #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ 6418 6419 #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ 6420 #define AES_RESET_bp 5 /* AES Software Reset bit position. */ 6421 6422 #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ 6423 #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ 6424 6425 #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ 6426 #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ 6427 6428 6429 /* AES.STATUS bit masks and bit positions */ 6430 #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ 6431 #define AES_ERROR_bp 7 /* AES Error bit position. */ 6432 6433 #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ 6434 #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ 6435 6436 6437 /* AES.INTCTRL bit masks and bit positions */ 6438 #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ 6439 #define AES_INTLVL_gp 0 /* Interrupt level group position. */ 6440 #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ 6441 #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ 6442 #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ 6443 #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ 6444 6445 6446 /* VBAT - VBAT Battery Backup Module */ 6447 /* VBAT.CTRL bit masks and bit positions */ 6448 #define VBAT_XOSCSEL_bm 0x10 /* 32-kHz Crystal Oscillator Output Selection bit mask. */ 6449 #define VBAT_XOSCSEL_bp 4 /* 32-kHz Crystal Oscillator Output Selection bit position. */ 6450 6451 #define VBAT_XOSCEN_bm 0x08 /* Crystal Oscillator Enable bit mask. */ 6452 #define VBAT_XOSCEN_bp 3 /* Crystal Oscillator Enable bit position. */ 6453 6454 #define VBAT_XOSCFDEN_bm 0x04 /* Crystal Oscillator Failure Detection Monitor Enable bit mask. */ 6455 #define VBAT_XOSCFDEN_bp 2 /* Crystal Oscillator Failure Detection Monitor Enable bit position. */ 6456 6457 #define VBAT_ACCEN_bm 0x02 /* Battery Backup Access Enable bit mask. */ 6458 #define VBAT_ACCEN_bp 1 /* Battery Backup Access Enable bit position. */ 6459 6460 #define VBAT_RESET_bm 0x01 /* Battery Backup Reset bit mask. */ 6461 #define VBAT_RESET_bp 0 /* Battery Backup Reset bit position. */ 6462 6463 6464 /* VBAT.STATUS bit masks and bit positions */ 6465 #define VBAT_BBPWR_bm 0x80 /* Battery backup Power bit mask. */ 6466 #define VBAT_BBPWR_bp 7 /* Battery backup Power bit position. */ 6467 6468 #define VBAT_XOSCRDY_bm 0x08 /* Crystal Oscillator Ready bit mask. */ 6469 #define VBAT_XOSCRDY_bp 3 /* Crystal Oscillator Ready bit position. */ 6470 6471 #define VBAT_XOSCFAIL_bm 0x04 /* Crystal Oscillator Failure bit mask. */ 6472 #define VBAT_XOSCFAIL_bp 2 /* Crystal Oscillator Failure bit position. */ 6473 6474 #define VBAT_BBBORF_bm 0x02 /* Battery Backup Brown-Out Reset Flag bit mask. */ 6475 #define VBAT_BBBORF_bp 1 /* Battery Backup Brown-Out Reset Flag bit position. */ 6476 6477 #define VBAT_BBPORF_bm 0x01 /* Battery Backup Power-On Reset Flag bit mask. */ 6478 #define VBAT_BBPORF_bp 0 /* Battery Backup Power-On Reset Flag bit position. */ 6479 6480 6481 6482 // Generic Port Pins 6483 6484 #define PIN0_bm 0x01 6485 #define PIN0_bp 0 6486 #define PIN1_bm 0x02 6487 #define PIN1_bp 1 6488 #define PIN2_bm 0x04 6489 #define PIN2_bp 2 6490 #define PIN3_bm 0x08 6491 #define PIN3_bp 3 6492 #define PIN4_bm 0x10 6493 #define PIN4_bp 4 6494 #define PIN5_bm 0x20 6495 #define PIN5_bp 5 6496 #define PIN6_bm 0x40 6497 #define PIN6_bp 6 6498 #define PIN7_bm 0x80 6499 #define PIN7_bp 7 6500 6501 6502 /* ========== Interrupt Vector Definitions ========== */ 6503 /* Vector 0 is the reset vector */ 6504 6505 /* OSC interrupt vectors */ 6506 #define OSC_XOSCF_vect_num 1 6507 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ 6508 6509 /* PORTC interrupt vectors */ 6510 #define PORTC_INT0_vect_num 2 6511 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ 6512 #define PORTC_INT1_vect_num 3 6513 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ 6514 6515 /* PORTR interrupt vectors */ 6516 #define PORTR_INT0_vect_num 4 6517 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ 6518 #define PORTR_INT1_vect_num 5 6519 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ 6520 6521 /* DMA interrupt vectors */ 6522 #define DMA_CH0_vect_num 6 6523 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ 6524 #define DMA_CH1_vect_num 7 6525 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ 6526 #define DMA_CH2_vect_num 8 6527 #define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ 6528 #define DMA_CH3_vect_num 9 6529 #define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ 6530 6531 /* RTC32 interrupt vectors */ 6532 #define RTC32_OVF_vect_num 10 6533 #define RTC32_OVF_vect _VECTOR(10) /* Overflow Interrupt */ 6534 #define RTC32_COMP_vect_num 11 6535 #define RTC32_COMP_vect _VECTOR(11) /* Compare Interrupt */ 6536 6537 /* TWIC interrupt vectors */ 6538 #define TWIC_TWIS_vect_num 12 6539 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ 6540 #define TWIC_TWIM_vect_num 13 6541 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ 6542 6543 /* TCC0 interrupt vectors */ 6544 #define TCC0_OVF_vect_num 14 6545 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ 6546 #define TCC0_ERR_vect_num 15 6547 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ 6548 #define TCC0_CCA_vect_num 16 6549 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ 6550 #define TCC0_CCB_vect_num 17 6551 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ 6552 #define TCC0_CCC_vect_num 18 6553 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ 6554 #define TCC0_CCD_vect_num 19 6555 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ 6556 6557 /* TCC1 interrupt vectors */ 6558 #define TCC1_OVF_vect_num 20 6559 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ 6560 #define TCC1_ERR_vect_num 21 6561 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ 6562 #define TCC1_CCA_vect_num 22 6563 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ 6564 #define TCC1_CCB_vect_num 23 6565 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ 6566 6567 /* SPIC interrupt vectors */ 6568 #define SPIC_INT_vect_num 24 6569 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ 6570 6571 /* USARTC0 interrupt vectors */ 6572 #define USARTC0_RXC_vect_num 25 6573 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ 6574 #define USARTC0_DRE_vect_num 26 6575 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ 6576 #define USARTC0_TXC_vect_num 27 6577 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ 6578 6579 /* USARTC1 interrupt vectors */ 6580 #define USARTC1_RXC_vect_num 28 6581 #define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ 6582 #define USARTC1_DRE_vect_num 29 6583 #define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ 6584 #define USARTC1_TXC_vect_num 30 6585 #define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ 6586 6587 /* AES interrupt vectors */ 6588 #define AES_INT_vect_num 31 6589 #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ 6590 6591 /* NVM interrupt vectors */ 6592 #define NVM_EE_vect_num 32 6593 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ 6594 #define NVM_SPM_vect_num 33 6595 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ 6596 6597 /* PORTB interrupt vectors */ 6598 #define PORTB_INT0_vect_num 34 6599 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ 6600 #define PORTB_INT1_vect_num 35 6601 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ 6602 6603 /* ACB interrupt vectors */ 6604 #define ACB_AC0_vect_num 36 6605 #define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ 6606 #define ACB_AC1_vect_num 37 6607 #define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ 6608 #define ACB_ACW_vect_num 38 6609 #define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ 6610 6611 /* ADCB interrupt vectors */ 6612 #define ADCB_CH0_vect_num 39 6613 #define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ 6614 #define ADCB_CH1_vect_num 40 6615 #define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ 6616 #define ADCB_CH2_vect_num 41 6617 #define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ 6618 #define ADCB_CH3_vect_num 42 6619 #define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ 6620 6621 /* PORTE interrupt vectors */ 6622 #define PORTE_INT0_vect_num 43 6623 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ 6624 #define PORTE_INT1_vect_num 44 6625 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ 6626 6627 /* TWIE interrupt vectors */ 6628 #define TWIE_TWIS_vect_num 45 6629 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ 6630 #define TWIE_TWIM_vect_num 46 6631 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ 6632 6633 /* TCE0 interrupt vectors */ 6634 #define TCE0_OVF_vect_num 47 6635 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ 6636 #define TCE0_ERR_vect_num 48 6637 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ 6638 #define TCE0_CCA_vect_num 49 6639 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ 6640 #define TCE0_CCB_vect_num 50 6641 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ 6642 #define TCE0_CCC_vect_num 51 6643 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ 6644 #define TCE0_CCD_vect_num 52 6645 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ 6646 6647 /* TCE1 interrupt vectors */ 6648 #define TCE1_OVF_vect_num 53 6649 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ 6650 #define TCE1_ERR_vect_num 54 6651 #define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ 6652 #define TCE1_CCA_vect_num 55 6653 #define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ 6654 #define TCE1_CCB_vect_num 56 6655 #define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ 6656 6657 /* USARTE0 interrupt vectors */ 6658 #define USARTE0_RXC_vect_num 58 6659 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ 6660 #define USARTE0_DRE_vect_num 59 6661 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ 6662 #define USARTE0_TXC_vect_num 60 6663 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ 6664 6665 /* PORTD interrupt vectors */ 6666 #define PORTD_INT0_vect_num 64 6667 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ 6668 #define PORTD_INT1_vect_num 65 6669 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ 6670 6671 /* PORTA interrupt vectors */ 6672 #define PORTA_INT0_vect_num 66 6673 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ 6674 #define PORTA_INT1_vect_num 67 6675 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ 6676 6677 /* ACA interrupt vectors */ 6678 #define ACA_AC0_vect_num 68 6679 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ 6680 #define ACA_AC1_vect_num 69 6681 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ 6682 #define ACA_ACW_vect_num 70 6683 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ 6684 6685 /* ADCA interrupt vectors */ 6686 #define ADCA_CH0_vect_num 71 6687 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ 6688 #define ADCA_CH1_vect_num 72 6689 #define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ 6690 #define ADCA_CH2_vect_num 73 6691 #define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ 6692 #define ADCA_CH3_vect_num 74 6693 #define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ 6694 6695 /* TCD0 interrupt vectors */ 6696 #define TCD0_OVF_vect_num 77 6697 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ 6698 #define TCD0_ERR_vect_num 78 6699 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ 6700 #define TCD0_CCA_vect_num 79 6701 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ 6702 #define TCD0_CCB_vect_num 80 6703 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ 6704 #define TCD0_CCC_vect_num 81 6705 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ 6706 #define TCD0_CCD_vect_num 82 6707 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ 6708 6709 /* TCD1 interrupt vectors */ 6710 #define TCD1_OVF_vect_num 83 6711 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ 6712 #define TCD1_ERR_vect_num 84 6713 #define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ 6714 #define TCD1_CCA_vect_num 85 6715 #define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ 6716 #define TCD1_CCB_vect_num 86 6717 #define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ 6718 6719 /* SPID interrupt vectors */ 6720 #define SPID_INT_vect_num 87 6721 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ 6722 6723 /* USARTD0 interrupt vectors */ 6724 #define USARTD0_RXC_vect_num 88 6725 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ 6726 #define USARTD0_DRE_vect_num 89 6727 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ 6728 #define USARTD0_TXC_vect_num 90 6729 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ 6730 6731 /* USARTD1 interrupt vectors */ 6732 #define USARTD1_RXC_vect_num 91 6733 #define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ 6734 #define USARTD1_DRE_vect_num 92 6735 #define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ 6736 #define USARTD1_TXC_vect_num 93 6737 #define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ 6738 6739 /* PORTF interrupt vectors */ 6740 #define PORTF_INT0_vect_num 104 6741 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ 6742 #define PORTF_INT1_vect_num 105 6743 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ 6744 6745 /* TCF0 interrupt vectors */ 6746 #define TCF0_OVF_vect_num 108 6747 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ 6748 #define TCF0_ERR_vect_num 109 6749 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ 6750 #define TCF0_CCA_vect_num 110 6751 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ 6752 #define TCF0_CCB_vect_num 111 6753 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ 6754 #define TCF0_CCC_vect_num 112 6755 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ 6756 #define TCF0_CCD_vect_num 113 6757 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ 6758 6759 /* USARTF0 interrupt vectors */ 6760 #define USARTF0_RXC_vect_num 119 6761 #define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ 6762 #define USARTF0_DRE_vect_num 120 6763 #define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ 6764 #define USARTF0_TXC_vect_num 121 6765 #define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ 6766 6767 6768 #define _VECTOR_SIZE 4 /* Size of individual vector. */ 6769 #define _VECTORS_SIZE (122 * _VECTOR_SIZE) 6770 6771 6772 /* ========== Constants ========== */ 6773 6774 #define PROGMEM_START (0x0000) 6775 #define PROGMEM_SIZE (270336) 6776 #define PROGMEM_PAGE_SIZE (512) 6777 #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) 6778 6779 #define APP_SECTION_START (0x0000) 6780 #define APP_SECTION_SIZE (262144) 6781 #define APP_SECTION_PAGE_SIZE (512) 6782 #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) 6783 6784 #define APPTABLE_SECTION_START (0x3E000) 6785 #define APPTABLE_SECTION_SIZE (8192) 6786 #define APPTABLE_SECTION_PAGE_SIZE (512) 6787 #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) 6788 6789 #define BOOT_SECTION_START (0x40000) 6790 #define BOOT_SECTION_SIZE (8192) 6791 #define BOOT_SECTION_PAGE_SIZE (512) 6792 #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) 6793 6794 #define DATAMEM_START (0x0000) 6795 #define DATAMEM_SIZE (24576) 6796 #define DATAMEM_PAGE_SIZE (0) 6797 #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) 6798 6799 #define IO_START (0x0000) 6800 #define IO_SIZE (4096) 6801 #define IO_PAGE_SIZE (0) 6802 #define IO_END (IO_START + IO_SIZE - 1) 6803 6804 #define MAPPED_EEPROM_START (0x1000) 6805 #define MAPPED_EEPROM_SIZE (4096) 6806 #define MAPPED_EEPROM_PAGE_SIZE (0) 6807 #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) 6808 6809 #define INTERNAL_SRAM_START (0x2000) 6810 #define INTERNAL_SRAM_SIZE (16384) 6811 #define INTERNAL_SRAM_PAGE_SIZE (0) 6812 #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) 6813 6814 #define EEPROM_START (0x0000) 6815 #define EEPROM_SIZE (4096) 6816 #define EEPROM_PAGE_SIZE (32) 6817 #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) 6818 6819 #define FUSE_START (0x0000) 6820 #define FUSE_SIZE (6) 6821 #define FUSE_PAGE_SIZE (0) 6822 #define FUSE_END (FUSE_START + FUSE_SIZE - 1) 6823 6824 #define LOCKBIT_START (0x0000) 6825 #define LOCKBIT_SIZE (1) 6826 #define LOCKBIT_PAGE_SIZE (0) 6827 #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) 6828 6829 #define SIGNATURES_START (0x0000) 6830 #define SIGNATURES_SIZE (3) 6831 #define SIGNATURES_PAGE_SIZE (0) 6832 #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) 6833 6834 #define USER_SIGNATURES_START (0x0000) 6835 #define USER_SIGNATURES_SIZE (512) 6836 #define USER_SIGNATURES_PAGE_SIZE (0) 6837 #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) 6838 6839 #define PROD_SIGNATURES_START (0x0000) 6840 #define PROD_SIGNATURES_SIZE (52) 6841 #define PROD_SIGNATURES_PAGE_SIZE (0) 6842 #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) 6843 6844 #define FLASHEND PROGMEM_END 6845 #define SPM_PAGESIZE PROGMEM_PAGE_SIZE 6846 #define RAMSTART INTERNAL_SRAM_START 6847 #define RAMSIZE INTERNAL_SRAM_SIZE 6848 #define RAMEND INTERNAL_SRAM_END 6849 #define XRAMSTART EXTERNAL_SRAM_START 6850 #define XRAMSIZE EXTERNAL_SRAM_SIZE 6851 #define XRAMEND INTERNAL_SRAM_END 6852 #define E2END EEPROM_END 6853 #define E2PAGESIZE EEPROM_PAGE_SIZE 6854 6855 6856 /* ========== Fuses ========== */ 6857 #define FUSE_MEMORY_SIZE 6 6858 6859 /* Fuse Byte 0 */ 6860 #define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ 6861 #define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ 6862 #define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ 6863 #define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ 6864 #define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ 6865 #define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ 6866 #define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ 6867 #define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ 6868 #define FUSE0_DEFAULT (0xFF) 6869 6870 /* Fuse Byte 1 */ 6871 #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ 6872 #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ 6873 #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ 6874 #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ 6875 #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ 6876 #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ 6877 #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ 6878 #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ 6879 #define FUSE1_DEFAULT (0xFF) 6880 6881 /* Fuse Byte 2 */ 6882 #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ 6883 #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ 6884 #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ 6885 #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ 6886 #define FUSE2_DEFAULT (0xFF) 6887 6888 /* Fuse Byte 3 Reserved */ 6889 6890 /* Fuse Byte 4 */ 6891 #define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ 6892 #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ 6893 #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ 6894 #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ 6895 #define FUSE4_DEFAULT (0xFF) 6896 6897 /* Fuse Byte 5 */ 6898 #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ 6899 #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ 6900 #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ 6901 #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ 6902 #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ 6903 #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ 6904 #define FUSE5_DEFAULT (0xFF) 6905 6906 6907 /* ========== Lock Bits ========== */ 6908 #define __LOCK_BITS_EXIST 6909 #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST 6910 #define __BOOT_LOCK_APPLICATION_BITS_EXIST 6911 #define __BOOT_LOCK_BOOT_BITS_EXIST 6912 6913 6914 /* ========== Signature ========== */ 6915 #define SIGNATURE_0 0x1E 6916 #define SIGNATURE_1 0x98 6917 #define SIGNATURE_2 0x43 6918 6919 /* ========== Power Reduction Condition Definitions ========== */ 6920 6921 /* PR.PRGEN */ 6922 #define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) 6923 #define __AVR_HAVE_PRGEN_AES 6924 #define __AVR_HAVE_PRGEN_EBI 6925 #define __AVR_HAVE_PRGEN_RTC 6926 #define __AVR_HAVE_PRGEN_EVSYS 6927 #define __AVR_HAVE_PRGEN_DMA 6928 6929 /* PR.PRPA */ 6930 #define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) 6931 #define __AVR_HAVE_PRPA_DAC 6932 #define __AVR_HAVE_PRPA_ADC 6933 #define __AVR_HAVE_PRPA_AC 6934 6935 /* PR.PRPB */ 6936 #define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) 6937 #define __AVR_HAVE_PRPB_DAC 6938 #define __AVR_HAVE_PRPB_ADC 6939 #define __AVR_HAVE_PRPB_AC 6940 6941 /* PR.PRPC */ 6942 #define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) 6943 #define __AVR_HAVE_PRPC_TWI 6944 #define __AVR_HAVE_PRPC_USART1 6945 #define __AVR_HAVE_PRPC_USART0 6946 #define __AVR_HAVE_PRPC_SPI 6947 #define __AVR_HAVE_PRPC_HIRES 6948 #define __AVR_HAVE_PRPC_TC1 6949 #define __AVR_HAVE_PRPC_TC0 6950 6951 /* PR.PRPD */ 6952 #define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) 6953 #define __AVR_HAVE_PRPD_TWI 6954 #define __AVR_HAVE_PRPD_USART1 6955 #define __AVR_HAVE_PRPD_USART0 6956 #define __AVR_HAVE_PRPD_SPI 6957 #define __AVR_HAVE_PRPD_HIRES 6958 #define __AVR_HAVE_PRPD_TC1 6959 #define __AVR_HAVE_PRPD_TC0 6960 6961 /* PR.PRPE */ 6962 #define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) 6963 #define __AVR_HAVE_PRPE_TWI 6964 #define __AVR_HAVE_PRPE_USART1 6965 #define __AVR_HAVE_PRPE_USART0 6966 #define __AVR_HAVE_PRPE_SPI 6967 #define __AVR_HAVE_PRPE_HIRES 6968 #define __AVR_HAVE_PRPE_TC1 6969 #define __AVR_HAVE_PRPE_TC0 6970 6971 /* PR.PRPF */ 6972 #define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) 6973 #define __AVR_HAVE_PRPF_TWI 6974 #define __AVR_HAVE_PRPF_USART1 6975 #define __AVR_HAVE_PRPF_USART0 6976 #define __AVR_HAVE_PRPF_SPI 6977 #define __AVR_HAVE_PRPF_HIRES 6978 #define __AVR_HAVE_PRPF_TC1 6979 #define __AVR_HAVE_PRPF_TC0 6980 6981 6982 #endif /* _AVR_ATxmega256A3B_H_ */ 6983 6984