1 /* Copyright (c) 2009-2010 Atmel Corporation 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: iox256d3.h 2482 2015-08-06 08:54:17Z pitchumani $ */ 32 33 /* avr/iox256d3.h - definitions for ATxmega256D3 */ 34 35 /* This file should only be included from <avr/io.h>, never directly. */ 36 37 #ifndef _AVR_IO_H_ 38 # error "Include <avr/io.h> instead of this file." 39 #endif 40 41 #ifndef _AVR_IOXXX_H_ 42 # define _AVR_IOXXX_H_ "iox256d3.h" 43 #else 44 # error "Attempt to include more than one <avr/ioXXX.h> file." 45 #endif 46 47 48 #ifndef _AVR_ATxmega256D3_H_ 49 #define _AVR_ATxmega256D3_H_ 1 50 51 52 /* Ungrouped common registers */ 53 #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ 54 #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ 55 #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ 56 #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ 57 #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ 58 #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ 59 #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ 60 #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ 61 #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ 62 #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ 63 #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ 64 #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ 65 #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ 66 #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ 67 #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ 68 #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ 69 70 #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ 71 #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ 72 #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ 73 #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ 74 #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ 75 #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ 76 #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ 77 #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ 78 #define SREG _SFR_MEM8(0x003F) /* Status Register */ 79 80 81 /* C Language Only */ 82 #if !defined (__ASSEMBLER__) 83 84 #include <stdint.h> 85 86 typedef volatile uint8_t register8_t; 87 typedef volatile uint16_t register16_t; 88 typedef volatile uint32_t register32_t; 89 90 91 #ifdef _WORDREGISTER 92 #undef _WORDREGISTER 93 #endif 94 #define _WORDREGISTER(regname) \ 95 __extension__ union \ 96 { \ 97 register16_t regname; \ 98 struct \ 99 { \ 100 register8_t regname ## L; \ 101 register8_t regname ## H; \ 102 }; \ 103 } 104 105 #ifdef _DWORDREGISTER 106 #undef _DWORDREGISTER 107 #endif 108 #define _DWORDREGISTER(regname) \ 109 __extension__ union \ 110 { \ 111 register32_t regname; \ 112 struct \ 113 { \ 114 register8_t regname ## 0; \ 115 register8_t regname ## 1; \ 116 register8_t regname ## 2; \ 117 register8_t regname ## 3; \ 118 }; \ 119 } 120 121 122 /* 123 ========================================================================== 124 IO Module Structures 125 ========================================================================== 126 */ 127 128 129 /* 130 -------------------------------------------------------------------------- 131 XOCD - On-Chip Debug System 132 -------------------------------------------------------------------------- 133 */ 134 135 /* On-Chip Debug System */ 136 typedef struct OCD_struct 137 { 138 register8_t OCDR0; /* OCD Register 0 */ 139 register8_t OCDR1; /* OCD Register 1 */ 140 } OCD_t; 141 142 143 /* CCP signatures */ 144 typedef enum CCP_enum 145 { 146 CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ 147 CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ 148 } CCP_t; 149 150 151 /* 152 -------------------------------------------------------------------------- 153 CLK - Clock System 154 -------------------------------------------------------------------------- 155 */ 156 157 /* Clock System */ 158 typedef struct CLK_struct 159 { 160 register8_t CTRL; /* Control Register */ 161 register8_t PSCTRL; /* Prescaler Control Register */ 162 register8_t LOCK; /* Lock register */ 163 register8_t RTCCTRL; /* RTC Control Register */ 164 } CLK_t; 165 166 167 /* Power Reduction */ 168 typedef struct PR_struct 169 { 170 register8_t PRGEN; /* General Power Reduction */ 171 register8_t PRPA; /* Power Reduction Port A */ 172 register8_t reserved_0x02; 173 register8_t PRPC; /* Power Reduction Port C */ 174 register8_t PRPD; /* Power Reduction Port D */ 175 register8_t PRPE; /* Power Reduction Port E */ 176 register8_t PRPF; /* Power Reduction Port F */ 177 } PR_t; 178 179 /* System Clock Selection */ 180 typedef enum CLK_SCLKSEL_enum 181 { 182 CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ 183 CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ 184 CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ 185 CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ 186 CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ 187 } CLK_SCLKSEL_t; 188 189 /* Prescaler A Division Factor */ 190 typedef enum CLK_PSADIV_enum 191 { 192 CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ 193 CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ 194 CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ 195 CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ 196 CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ 197 CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ 198 CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ 199 CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ 200 CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ 201 CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ 202 } CLK_PSADIV_t; 203 204 /* Prescaler B and C Division Factor */ 205 typedef enum CLK_PSBCDIV_enum 206 { 207 CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ 208 CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ 209 CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ 210 CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ 211 } CLK_PSBCDIV_t; 212 213 /* RTC Clock Source */ 214 typedef enum CLK_RTCSRC_enum 215 { 216 CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ 217 CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ 218 CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ 219 CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ 220 } CLK_RTCSRC_t; 221 222 223 /* 224 -------------------------------------------------------------------------- 225 SLEEP - Sleep Controller 226 -------------------------------------------------------------------------- 227 */ 228 229 /* Sleep Controller */ 230 typedef struct SLEEP_struct 231 { 232 register8_t CTRL; /* Control Register */ 233 } SLEEP_t; 234 235 /* Sleep Mode */ 236 typedef enum SLEEP_SMODE_enum 237 { 238 SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ 239 SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ 240 SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ 241 SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ 242 SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ 243 } SLEEP_SMODE_t; 244 245 246 #define SLEEP_MODE_IDLE (0x00<<1) 247 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 248 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 249 #define SLEEP_MODE_STANDBY (0x06<<1) 250 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 251 252 253 /* 254 -------------------------------------------------------------------------- 255 OSC - Oscillator 256 -------------------------------------------------------------------------- 257 */ 258 259 /* Oscillator */ 260 typedef struct OSC_struct 261 { 262 register8_t CTRL; /* Control Register */ 263 register8_t STATUS; /* Status Register */ 264 register8_t XOSCCTRL; /* External Oscillator Control Register */ 265 register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ 266 register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ 267 register8_t PLLCTRL; /* PLL Control REgister */ 268 register8_t DFLLCTRL; /* DFLL Control Register */ 269 } OSC_t; 270 271 /* Oscillator Frequency Range */ 272 typedef enum OSC_FRQRANGE_enum 273 { 274 OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ 275 OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ 276 OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ 277 OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ 278 } OSC_FRQRANGE_t; 279 280 /* External Oscillator Selection and Startup Time */ 281 typedef enum OSC_XOSCSEL_enum 282 { 283 OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ 284 OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ 285 OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ 286 OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ 287 OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ 288 } OSC_XOSCSEL_t; 289 290 /* PLL Clock Source */ 291 typedef enum OSC_PLLSRC_enum 292 { 293 OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ 294 OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ 295 OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ 296 } OSC_PLLSRC_t; 297 298 299 /* 300 -------------------------------------------------------------------------- 301 DFLL - DFLL 302 -------------------------------------------------------------------------- 303 */ 304 305 /* DFLL */ 306 typedef struct DFLL_struct 307 { 308 register8_t CTRL; /* Control Register */ 309 register8_t reserved_0x01; 310 register8_t CALA; /* Calibration Register A */ 311 register8_t CALB; /* Calibration Register B */ 312 register8_t COMP0; /* Oscillator Compare Register 0 */ 313 register8_t COMP1; /* Oscillator Compare Register 1 */ 314 register8_t COMP2; /* Oscillator Compare Register 2 */ 315 register8_t reserved_0x07; 316 } DFLL_t; 317 318 319 /* 320 -------------------------------------------------------------------------- 321 RST - Reset 322 -------------------------------------------------------------------------- 323 */ 324 325 /* Reset */ 326 typedef struct RST_struct 327 { 328 register8_t STATUS; /* Status Register */ 329 register8_t CTRL; /* Control Register */ 330 } RST_t; 331 332 333 /* 334 -------------------------------------------------------------------------- 335 WDT - Watch-Dog Timer 336 -------------------------------------------------------------------------- 337 */ 338 339 /* Watch-Dog Timer */ 340 typedef struct WDT_struct 341 { 342 register8_t CTRL; /* Control */ 343 register8_t WINCTRL; /* Windowed Mode Control */ 344 register8_t STATUS; /* Status */ 345 } WDT_t; 346 347 /* Period setting */ 348 typedef enum WDT_PER_enum 349 { 350 WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ 351 WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ 352 WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ 353 WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ 354 WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ 355 WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ 356 WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ 357 WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ 358 WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ 359 WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ 360 WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ 361 } WDT_PER_t; 362 363 /* Closed window period */ 364 typedef enum WDT_WPER_enum 365 { 366 WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ 367 WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ 368 WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ 369 WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ 370 WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ 371 WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ 372 WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ 373 WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ 374 WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ 375 WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ 376 WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ 377 } WDT_WPER_t; 378 379 380 /* 381 -------------------------------------------------------------------------- 382 MCU - MCU Control 383 -------------------------------------------------------------------------- 384 */ 385 386 /* MCU Control */ 387 typedef struct MCU_struct 388 { 389 register8_t DEVID0; /* Device ID byte 0 */ 390 register8_t DEVID1; /* Device ID byte 1 */ 391 register8_t DEVID2; /* Device ID byte 2 */ 392 register8_t REVID; /* Revision ID */ 393 register8_t JTAGUID; /* JTAG User ID */ 394 register8_t reserved_0x05; 395 register8_t MCUCR; /* MCU Control */ 396 register8_t reserved_0x07; 397 register8_t EVSYSLOCK; /* Event System Lock */ 398 register8_t AWEXLOCK; /* AWEX Lock */ 399 register8_t reserved_0x0A; 400 register8_t reserved_0x0B; 401 } MCU_t; 402 403 404 /* 405 -------------------------------------------------------------------------- 406 PMIC - Programmable Multi-level Interrupt Controller 407 -------------------------------------------------------------------------- 408 */ 409 410 /* Programmable Multi-level Interrupt Controller */ 411 typedef struct PMIC_struct 412 { 413 register8_t STATUS; /* Status Register */ 414 register8_t INTPRI; /* Interrupt Priority */ 415 register8_t CTRL; /* Control Register */ 416 } PMIC_t; 417 418 419 /* 420 -------------------------------------------------------------------------- 421 CRC - Cyclic Redundancy Checker 422 -------------------------------------------------------------------------- 423 */ 424 425 /* Cyclic Redundancy Checker */ 426 typedef struct CRC_struct 427 { 428 register8_t CTRL; /* Control Register */ 429 register8_t STATUS; /* Status Register */ 430 register8_t reserved_0x02; 431 register8_t DATAIN; /* Data Input */ 432 register8_t CHECKSUM0; /* Checksum byte 0 */ 433 register8_t CHECKSUM1; /* Checksum byte 1 */ 434 register8_t CHECKSUM2; /* Checksum byte 2 */ 435 register8_t CHECKSUM3; /* Checksum byte 3 */ 436 } CRC_t; 437 438 /* Reset */ 439 typedef enum CRC_RESET_enum 440 { 441 CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ 442 CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ 443 CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ 444 } CRC_RESET_t; 445 446 /* Input Source */ 447 typedef enum CRC_SOURCE_enum 448 { 449 CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ 450 CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ 451 CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ 452 CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ 453 CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ 454 CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ 455 CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ 456 } CRC_SOURCE_t; 457 458 459 /* 460 -------------------------------------------------------------------------- 461 EVSYS - Event System 462 -------------------------------------------------------------------------- 463 */ 464 465 /* Event System */ 466 typedef struct EVSYS_struct 467 { 468 register8_t CH0MUX; /* Event Channel 0 Multiplexer */ 469 register8_t CH1MUX; /* Event Channel 1 Multiplexer */ 470 register8_t CH2MUX; /* Event Channel 2 Multiplexer */ 471 register8_t CH3MUX; /* Event Channel 3 Multiplexer */ 472 register8_t reserved_0x04; 473 register8_t reserved_0x05; 474 register8_t reserved_0x06; 475 register8_t reserved_0x07; 476 register8_t CH0CTRL; /* Channel 0 Control Register */ 477 register8_t CH1CTRL; /* Channel 1 Control Register */ 478 register8_t CH2CTRL; /* Channel 2 Control Register */ 479 register8_t CH3CTRL; /* Channel 3 Control Register */ 480 register8_t reserved_0x0C; 481 register8_t reserved_0x0D; 482 register8_t reserved_0x0E; 483 register8_t reserved_0x0F; 484 register8_t STROBE; /* Event Strobe */ 485 register8_t DATA; /* Event Data */ 486 } EVSYS_t; 487 488 /* Quadrature Decoder Index Recognition Mode */ 489 typedef enum EVSYS_QDIRM_enum 490 { 491 EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ 492 EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ 493 EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ 494 EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ 495 } EVSYS_QDIRM_t; 496 497 /* Digital filter coefficient */ 498 typedef enum EVSYS_DIGFILT_enum 499 { 500 EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ 501 EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ 502 EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ 503 EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ 504 EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ 505 EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ 506 EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ 507 EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ 508 } EVSYS_DIGFILT_t; 509 510 /* Event Channel multiplexer input selection */ 511 typedef enum EVSYS_CHMUX_enum 512 { 513 EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ 514 EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ 515 EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ 516 EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ 517 EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ 518 EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ 519 EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ 520 EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ 521 EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ 522 EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ 523 EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ 524 EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ 525 EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ 526 EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ 527 EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ 528 EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ 529 EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ 530 EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ 531 EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ 532 EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ 533 EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ 534 EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ 535 EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ 536 EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ 537 EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ 538 EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ 539 EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ 540 EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ 541 EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ 542 EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ 543 EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ 544 EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ 545 EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ 546 EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ 547 EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ 548 EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ 549 EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ 550 EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ 551 EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ 552 EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ 553 EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ 554 EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ 555 EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ 556 EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ 557 EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ 558 EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ 559 EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ 560 EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ 561 EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ 562 EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ 563 EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ 564 EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ 565 EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ 566 EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ 567 EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ 568 EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ 569 EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ 570 EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ 571 EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ 572 EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ 573 EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ 574 EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ 575 EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ 576 EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ 577 EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ 578 EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ 579 EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ 580 EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ 581 EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ 582 EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ 583 EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ 584 EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ 585 EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ 586 EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ 587 EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ 588 EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ 589 EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ 590 EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ 591 EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ 592 EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ 593 EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ 594 EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ 595 EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ 596 EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ 597 EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ 598 EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ 599 EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ 600 EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ 601 EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ 602 EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ 603 EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ 604 EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ 605 EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ 606 EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ 607 EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ 608 EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ 609 EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ 610 EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ 611 EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ 612 EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ 613 EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ 614 EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ 615 EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ 616 EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ 617 EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ 618 EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ 619 EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ 620 EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ 621 EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ 622 EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ 623 EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ 624 } EVSYS_CHMUX_t; 625 626 627 /* 628 -------------------------------------------------------------------------- 629 NVM - Non Volatile Memory Controller 630 -------------------------------------------------------------------------- 631 */ 632 633 /* Non-volatile Memory Controller */ 634 typedef struct NVM_struct 635 { 636 register8_t ADDR0; /* Address Register 0 */ 637 register8_t ADDR1; /* Address Register 1 */ 638 register8_t ADDR2; /* Address Register 2 */ 639 register8_t reserved_0x03; 640 register8_t DATA0; /* Data Register 0 */ 641 register8_t DATA1; /* Data Register 1 */ 642 register8_t DATA2; /* Data Register 2 */ 643 register8_t reserved_0x07; 644 register8_t reserved_0x08; 645 register8_t reserved_0x09; 646 register8_t CMD; /* Command */ 647 register8_t CTRLA; /* Control Register A */ 648 register8_t CTRLB; /* Control Register B */ 649 register8_t INTCTRL; /* Interrupt Control */ 650 register8_t reserved_0x0E; 651 register8_t STATUS; /* Status */ 652 register8_t LOCK_BITS; /* Lock Bits */ 653 } NVM_t; 654 655 /* 656 -------------------------------------------------------------------------- 657 NVM - Non Volatile Memory Controller 658 -------------------------------------------------------------------------- 659 */ 660 661 /* Lock Bits */ 662 typedef struct NVM_LOCKBITS_struct 663 { 664 register8_t LOCKBITS; /* Lock Bits */ 665 } NVM_LOCKBITS_t; 666 667 /* 668 -------------------------------------------------------------------------- 669 NVM - Non Volatile Memory Controller 670 -------------------------------------------------------------------------- 671 */ 672 673 /* Fuses */ 674 typedef struct NVM_FUSES_struct 675 { 676 register8_t FUSEBYTE0; /* User ID */ 677 register8_t FUSEBYTE1; /* Watchdog Configuration */ 678 register8_t FUSEBYTE2; /* Reset Configuration */ 679 register8_t reserved_0x03; 680 register8_t FUSEBYTE4; /* Start-up Configuration */ 681 register8_t FUSEBYTE5; /* EESAVE and BOD Level */ 682 } NVM_FUSES_t; 683 684 /* 685 -------------------------------------------------------------------------- 686 NVM - Non Volatile Memory Controller 687 -------------------------------------------------------------------------- 688 */ 689 690 /* Production Signatures */ 691 typedef struct NVM_PROD_SIGNATURES_struct 692 { 693 register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ 694 register8_t reserved_0x01; 695 register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ 696 register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ 697 register8_t reserved_0x04; 698 register8_t reserved_0x05; 699 register8_t reserved_0x06; 700 register8_t reserved_0x07; 701 register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ 702 register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ 703 register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ 704 register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ 705 register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ 706 register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ 707 register8_t reserved_0x0E; 708 register8_t reserved_0x0F; 709 register8_t WAFNUM; /* Wafer Number */ 710 register8_t reserved_0x11; 711 register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ 712 register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ 713 register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ 714 register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ 715 register8_t reserved_0x16; 716 register8_t reserved_0x17; 717 register8_t reserved_0x18; 718 register8_t reserved_0x19; 719 register8_t reserved_0x1A; 720 register8_t reserved_0x1B; 721 register8_t reserved_0x1C; 722 register8_t reserved_0x1D; 723 register8_t reserved_0x1E; 724 register8_t reserved_0x1F; 725 register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ 726 register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ 727 register8_t reserved_0x22; 728 register8_t reserved_0x23; 729 register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ 730 register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ 731 register8_t reserved_0x26; 732 register8_t reserved_0x27; 733 register8_t reserved_0x28; 734 register8_t reserved_0x29; 735 register8_t reserved_0x2A; 736 register8_t reserved_0x2B; 737 register8_t reserved_0x2C; 738 register8_t reserved_0x2D; 739 register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ 740 register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ 741 register8_t reserved_0x30; 742 register8_t reserved_0x31; 743 register8_t reserved_0x32; 744 register8_t reserved_0x33; 745 register8_t reserved_0x34; 746 register8_t reserved_0x35; 747 register8_t reserved_0x36; 748 register8_t reserved_0x37; 749 register8_t reserved_0x38; 750 register8_t reserved_0x39; 751 register8_t reserved_0x3A; 752 register8_t reserved_0x3B; 753 register8_t reserved_0x3C; 754 register8_t reserved_0x3D; 755 register8_t reserved_0x3E; 756 } NVM_PROD_SIGNATURES_t; 757 758 /* NVM Command */ 759 typedef enum NVM_CMD_enum 760 { 761 NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ 762 NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ 763 NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ 764 NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ 765 NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ 766 NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ 767 NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ 768 NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ 769 NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ 770 NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ 771 NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ 772 NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ 773 NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ 774 NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ 775 NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ 776 NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ 777 NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ 778 NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ 779 NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ 780 NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ 781 NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ 782 NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ 783 NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ 784 NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ 785 NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ 786 NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ 787 } NVM_CMD_t; 788 789 /* SPM ready interrupt level */ 790 typedef enum NVM_SPMLVL_enum 791 { 792 NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ 793 NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ 794 NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ 795 NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ 796 } NVM_SPMLVL_t; 797 798 /* EEPROM ready interrupt level */ 799 typedef enum NVM_EELVL_enum 800 { 801 NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 802 NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ 803 NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ 804 NVM_EELVL_HI_gc = (0x03<<0), /* High level */ 805 } NVM_EELVL_t; 806 807 /* Boot lock bits - boot setcion */ 808 typedef enum NVM_BLBB_enum 809 { 810 NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ 811 NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ 812 NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ 813 NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ 814 } NVM_BLBB_t; 815 816 /* Boot lock bits - application section */ 817 typedef enum NVM_BLBA_enum 818 { 819 NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ 820 NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ 821 NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ 822 NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ 823 } NVM_BLBA_t; 824 825 /* Boot lock bits - application table section */ 826 typedef enum NVM_BLBAT_enum 827 { 828 NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ 829 NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ 830 NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ 831 NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ 832 } NVM_BLBAT_t; 833 834 /* Lock bits */ 835 typedef enum NVM_LB_enum 836 { 837 NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ 838 NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ 839 NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ 840 } NVM_LB_t; 841 842 /* Boot Loader Section Reset Vector */ 843 typedef enum BOOTRST_enum 844 { 845 BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ 846 BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ 847 } BOOTRST_t; 848 849 /* BOD operation */ 850 typedef enum BOD_enum 851 { 852 BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ 853 BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ 854 BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ 855 } BOD_t; 856 857 /* Watchdog (Window) Timeout Period */ 858 typedef enum WD_enum 859 { 860 WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ 861 WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ 862 WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ 863 WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ 864 WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ 865 WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ 866 WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ 867 WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ 868 WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ 869 WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ 870 WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ 871 } WD_t; 872 873 /* Start-up Time */ 874 typedef enum SUT_enum 875 { 876 SUT_0MS_gc = (0x03<<2), /* 0 ms */ 877 SUT_4MS_gc = (0x01<<2), /* 4 ms */ 878 SUT_64MS_gc = (0x00<<2), /* 64 ms */ 879 } SUT_t; 880 881 /* Brown Out Detection Voltage Level */ 882 typedef enum BODLVL_enum 883 { 884 BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ 885 BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ 886 BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ 887 BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ 888 BODLVL_2V6_gc = (0x03<<0), /* 2.6 V */ 889 BODLVL_2V9_gc = (0x02<<0), /* 2.9 V */ 890 BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ 891 } BODLVL_t; 892 893 894 /* 895 -------------------------------------------------------------------------- 896 AC - Analog Comparator 897 -------------------------------------------------------------------------- 898 */ 899 900 /* Analog Comparator */ 901 typedef struct AC_struct 902 { 903 register8_t AC0CTRL; /* Comparator 0 Control */ 904 register8_t AC1CTRL; /* Comparator 1 Control */ 905 register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ 906 register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ 907 register8_t CTRLA; /* Control Register A */ 908 register8_t CTRLB; /* Control Register B */ 909 register8_t WINCTRL; /* Window Mode Control */ 910 register8_t STATUS; /* Status */ 911 } AC_t; 912 913 /* Interrupt mode */ 914 typedef enum AC_INTMODE_enum 915 { 916 AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ 917 AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ 918 AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ 919 } AC_INTMODE_t; 920 921 /* Interrupt level */ 922 typedef enum AC_INTLVL_enum 923 { 924 AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ 925 AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ 926 AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ 927 AC_INTLVL_HI_gc = (0x03<<4), /* High level */ 928 } AC_INTLVL_t; 929 930 /* Hysteresis mode selection */ 931 typedef enum AC_HYSMODE_enum 932 { 933 AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ 934 AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ 935 AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ 936 } AC_HYSMODE_t; 937 938 /* Positive input multiplexer selection */ 939 typedef enum AC_MUXPOS_enum 940 { 941 AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ 942 AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ 943 AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ 944 AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ 945 AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ 946 AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ 947 AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ 948 } AC_MUXPOS_t; 949 950 /* Negative input multiplexer selection */ 951 typedef enum AC_MUXNEG_enum 952 { 953 AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ 954 AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ 955 AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ 956 AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ 957 AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ 958 AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ 959 AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ 960 } AC_MUXNEG_t; 961 962 /* Windows interrupt mode */ 963 typedef enum AC_WINTMODE_enum 964 { 965 AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ 966 AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ 967 AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ 968 AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ 969 } AC_WINTMODE_t; 970 971 /* Window interrupt level */ 972 typedef enum AC_WINTLVL_enum 973 { 974 AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 975 AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ 976 AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ 977 AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ 978 } AC_WINTLVL_t; 979 980 /* Window mode state */ 981 typedef enum AC_WSTATE_enum 982 { 983 AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ 984 AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ 985 AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ 986 } AC_WSTATE_t; 987 988 989 /* 990 -------------------------------------------------------------------------- 991 ADC - Analog/Digital Converter 992 -------------------------------------------------------------------------- 993 */ 994 995 /* ADC Channel */ 996 typedef struct ADC_CH_struct 997 { 998 register8_t CTRL; /* Control Register */ 999 register8_t MUXCTRL; /* MUX Control */ 1000 register8_t INTCTRL; /* Channel Interrupt Control */ 1001 register8_t INTFLAGS; /* Interrupt Flags */ 1002 _WORDREGISTER(RES); /* Channel Result */ 1003 register8_t reserved_0x6; 1004 register8_t reserved_0x7; 1005 } ADC_CH_t; 1006 1007 /* 1008 -------------------------------------------------------------------------- 1009 ADC - Analog/Digital Converter 1010 -------------------------------------------------------------------------- 1011 */ 1012 1013 /* Analog-to-Digital Converter */ 1014 typedef struct ADC_struct 1015 { 1016 register8_t CTRLA; /* Control Register A */ 1017 register8_t CTRLB; /* Control Register B */ 1018 register8_t REFCTRL; /* Reference Control */ 1019 register8_t EVCTRL; /* Event Control */ 1020 register8_t PRESCALER; /* Clock Prescaler */ 1021 register8_t reserved_0x05; 1022 register8_t INTFLAGS; /* Interrupt Flags */ 1023 register8_t TEMP; /* ACD Temporary Register */ 1024 register8_t reserved_0x08; 1025 register8_t reserved_0x09; 1026 register8_t reserved_0x0A; 1027 register8_t reserved_0x0B; 1028 _WORDREGISTER(CAL); /* Calibration Value */ 1029 register8_t reserved_0x0E; 1030 register8_t reserved_0x0F; 1031 _WORDREGISTER(CH0RES); /* Channel 0 Result */ 1032 register8_t reserved_0x12; 1033 register8_t reserved_0x13; 1034 register8_t reserved_0x14; 1035 register8_t reserved_0x15; 1036 register8_t reserved_0x16; 1037 register8_t reserved_0x17; 1038 _WORDREGISTER(CMP); /* Compare Value */ 1039 register8_t reserved_0x1A; 1040 register8_t reserved_0x1B; 1041 register8_t reserved_0x1C; 1042 register8_t reserved_0x1D; 1043 register8_t reserved_0x1E; 1044 register8_t reserved_0x1F; 1045 ADC_CH_t CH0; /* ADC Channel 0 */ 1046 } ADC_t; 1047 1048 /* Current Limitation */ 1049 typedef enum ADC_CURRLIMIT_enum 1050 { 1051 ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ 1052 ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ 1053 ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ 1054 ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ 1055 } ADC_CURRLIMIT_t; 1056 1057 /* Positive input multiplexer selection */ 1058 typedef enum ADC_CH_MUXPOS_enum 1059 { 1060 ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ 1061 ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ 1062 ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ 1063 ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ 1064 ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ 1065 ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ 1066 ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ 1067 ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ 1068 } ADC_CH_MUXPOS_t; 1069 1070 /* Negative input multiplexer selection */ 1071 typedef enum ADC_CH_MUXNEG_enum 1072 { 1073 ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ 1074 ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ 1075 ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ 1076 ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ 1077 ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ 1078 ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ 1079 ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ 1080 ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ 1081 } ADC_CH_MUXNEG_t; 1082 1083 /* Input mode */ 1084 typedef enum ADC_CH_INPUTMODE_enum 1085 { 1086 ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ 1087 ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ 1088 ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ 1089 ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ 1090 } ADC_CH_INPUTMODE_t; 1091 1092 /* Gain factor */ 1093 typedef enum ADC_CH_GAIN_enum 1094 { 1095 ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ 1096 ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ 1097 ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ 1098 ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ 1099 ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ 1100 ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ 1101 ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ 1102 ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ 1103 } ADC_CH_GAIN_t; 1104 1105 /* Conversion result resolution */ 1106 typedef enum ADC_RESOLUTION_enum 1107 { 1108 ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ 1109 ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ 1110 ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ 1111 } ADC_RESOLUTION_t; 1112 1113 /* Voltage reference selection */ 1114 typedef enum ADC_REFSEL_enum 1115 { 1116 ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ 1117 ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ 1118 ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ 1119 ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ 1120 } ADC_REFSEL_t; 1121 1122 /* Event channel input selection */ 1123 typedef enum ADC_EVSEL_enum 1124 { 1125 ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ 1126 ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ 1127 ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ 1128 ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ 1129 ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ 1130 ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ 1131 ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ 1132 ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ 1133 } ADC_EVSEL_t; 1134 1135 /* Event action selection */ 1136 typedef enum ADC_EVACT_enum 1137 { 1138 ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ 1139 ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ 1140 } ADC_EVACT_t; 1141 1142 /* Interupt mode */ 1143 typedef enum ADC_CH_INTMODE_enum 1144 { 1145 ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ 1146 ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ 1147 ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ 1148 } ADC_CH_INTMODE_t; 1149 1150 /* Interrupt level */ 1151 typedef enum ADC_CH_INTLVL_enum 1152 { 1153 ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1154 ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ 1155 ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ 1156 ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ 1157 } ADC_CH_INTLVL_t; 1158 1159 /* Clock prescaler */ 1160 typedef enum ADC_PRESCALER_enum 1161 { 1162 ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ 1163 ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ 1164 ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ 1165 ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ 1166 ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ 1167 ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ 1168 ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ 1169 ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ 1170 } ADC_PRESCALER_t; 1171 1172 1173 /* 1174 -------------------------------------------------------------------------- 1175 RTC - Real-Time Clounter 1176 -------------------------------------------------------------------------- 1177 */ 1178 1179 /* Real-Time Counter */ 1180 typedef struct RTC_struct 1181 { 1182 register8_t CTRL; /* Control Register */ 1183 register8_t STATUS; /* Status Register */ 1184 register8_t INTCTRL; /* Interrupt Control Register */ 1185 register8_t INTFLAGS; /* Interrupt Flags */ 1186 register8_t TEMP; /* Temporary register */ 1187 register8_t reserved_0x05; 1188 register8_t reserved_0x06; 1189 register8_t reserved_0x07; 1190 _WORDREGISTER(CNT); /* Count Register */ 1191 _WORDREGISTER(PER); /* Period Register */ 1192 _WORDREGISTER(COMP); /* Compare Register */ 1193 } RTC_t; 1194 1195 /* Prescaler Factor */ 1196 typedef enum RTC_PRESCALER_enum 1197 { 1198 RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ 1199 RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ 1200 RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ 1201 RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ 1202 RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ 1203 RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ 1204 RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ 1205 RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ 1206 } RTC_PRESCALER_t; 1207 1208 /* Compare Interrupt level */ 1209 typedef enum RTC_COMPINTLVL_enum 1210 { 1211 RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1212 RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1213 RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1214 RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ 1215 } RTC_COMPINTLVL_t; 1216 1217 /* Overflow Interrupt level */ 1218 typedef enum RTC_OVFINTLVL_enum 1219 { 1220 RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1221 RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1222 RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1223 RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ 1224 } RTC_OVFINTLVL_t; 1225 1226 1227 /* 1228 -------------------------------------------------------------------------- 1229 EBI - External Bus Interface 1230 -------------------------------------------------------------------------- 1231 */ 1232 1233 /* EBI Chip Select Module */ 1234 typedef struct EBI_CS_struct 1235 { 1236 register8_t CTRLA; /* Chip Select Control Register A */ 1237 register8_t CTRLB; /* Chip Select Control Register B */ 1238 _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ 1239 } EBI_CS_t; 1240 1241 /* 1242 -------------------------------------------------------------------------- 1243 EBI - External Bus Interface 1244 -------------------------------------------------------------------------- 1245 */ 1246 1247 /* External Bus Interface */ 1248 typedef struct EBI_struct 1249 { 1250 register8_t CTRL; /* Control */ 1251 register8_t SDRAMCTRLA; /* SDRAM Control Register A */ 1252 register8_t reserved_0x02; 1253 register8_t reserved_0x03; 1254 _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ 1255 _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ 1256 register8_t SDRAMCTRLB; /* SDRAM Control Register B */ 1257 register8_t SDRAMCTRLC; /* SDRAM Control Register C */ 1258 register8_t reserved_0x0A; 1259 register8_t reserved_0x0B; 1260 register8_t reserved_0x0C; 1261 register8_t reserved_0x0D; 1262 register8_t reserved_0x0E; 1263 register8_t reserved_0x0F; 1264 EBI_CS_t CS0; /* Chip Select 0 */ 1265 EBI_CS_t CS1; /* Chip Select 1 */ 1266 EBI_CS_t CS2; /* Chip Select 2 */ 1267 EBI_CS_t CS3; /* Chip Select 3 */ 1268 } EBI_t; 1269 1270 /* Chip Select adress space */ 1271 typedef enum EBI_CS_ASIZE_enum 1272 { 1273 EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ 1274 EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ 1275 EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ 1276 EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ 1277 EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ 1278 EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ 1279 EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ 1280 EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ 1281 EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ 1282 EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ 1283 EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ 1284 EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ 1285 EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ 1286 EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ 1287 EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ 1288 EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ 1289 EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ 1290 } EBI_CS_ASIZE_t; 1291 1292 /* */ 1293 typedef enum EBI_CS_SRWS_enum 1294 { 1295 EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ 1296 EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ 1297 EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ 1298 EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ 1299 EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ 1300 EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ 1301 EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ 1302 EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ 1303 } EBI_CS_SRWS_t; 1304 1305 /* Chip Select address mode */ 1306 typedef enum EBI_CS_MODE_enum 1307 { 1308 EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ 1309 EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ 1310 EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ 1311 EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ 1312 } EBI_CS_MODE_t; 1313 1314 /* Chip Select SDRAM mode */ 1315 typedef enum EBI_CS_SDMODE_enum 1316 { 1317 EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ 1318 EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ 1319 } EBI_CS_SDMODE_t; 1320 1321 /* */ 1322 typedef enum EBI_SDDATAW_enum 1323 { 1324 EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ 1325 EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ 1326 } EBI_SDDATAW_t; 1327 1328 /* */ 1329 typedef enum EBI_LPCMODE_enum 1330 { 1331 EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ 1332 EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ 1333 } EBI_LPCMODE_t; 1334 1335 /* */ 1336 typedef enum EBI_SRMODE_enum 1337 { 1338 EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ 1339 EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ 1340 EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ 1341 EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ 1342 } EBI_SRMODE_t; 1343 1344 /* */ 1345 typedef enum EBI_IFMODE_enum 1346 { 1347 EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ 1348 EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ 1349 EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ 1350 EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ 1351 } EBI_IFMODE_t; 1352 1353 /* */ 1354 typedef enum EBI_SDCOL_enum 1355 { 1356 EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ 1357 EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ 1358 EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ 1359 EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ 1360 } EBI_SDCOL_t; 1361 1362 /* */ 1363 typedef enum EBI_MRDLY_enum 1364 { 1365 EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ 1366 EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ 1367 EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ 1368 EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ 1369 } EBI_MRDLY_t; 1370 1371 /* */ 1372 typedef enum EBI_ROWCYCDLY_enum 1373 { 1374 EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ 1375 EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ 1376 EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ 1377 EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ 1378 EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ 1379 EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ 1380 EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ 1381 EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ 1382 } EBI_ROWCYCDLY_t; 1383 1384 /* */ 1385 typedef enum EBI_RPDLY_enum 1386 { 1387 EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ 1388 EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ 1389 EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ 1390 EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ 1391 EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ 1392 EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ 1393 EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ 1394 EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ 1395 } EBI_RPDLY_t; 1396 1397 /* */ 1398 typedef enum EBI_WRDLY_enum 1399 { 1400 EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ 1401 EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ 1402 EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ 1403 EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ 1404 } EBI_WRDLY_t; 1405 1406 /* */ 1407 typedef enum EBI_ESRDLY_enum 1408 { 1409 EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ 1410 EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ 1411 EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ 1412 EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ 1413 EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ 1414 EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ 1415 EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ 1416 EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ 1417 } EBI_ESRDLY_t; 1418 1419 /* */ 1420 typedef enum EBI_ROWCOLDLY_enum 1421 { 1422 EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ 1423 EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ 1424 EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ 1425 EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ 1426 EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ 1427 EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ 1428 EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ 1429 EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ 1430 } EBI_ROWCOLDLY_t; 1431 1432 1433 /* 1434 -------------------------------------------------------------------------- 1435 TWI - Two-Wire Interface 1436 -------------------------------------------------------------------------- 1437 */ 1438 1439 /* */ 1440 typedef struct TWI_MASTER_struct 1441 { 1442 register8_t CTRLA; /* Control Register A */ 1443 register8_t CTRLB; /* Control Register B */ 1444 register8_t CTRLC; /* Control Register C */ 1445 register8_t STATUS; /* Status Register */ 1446 register8_t BAUD; /* Baurd Rate Control Register */ 1447 register8_t ADDR; /* Address Register */ 1448 register8_t DATA; /* Data Register */ 1449 } TWI_MASTER_t; 1450 1451 /* 1452 -------------------------------------------------------------------------- 1453 TWI - Two-Wire Interface 1454 -------------------------------------------------------------------------- 1455 */ 1456 1457 /* */ 1458 typedef struct TWI_SLAVE_struct 1459 { 1460 register8_t CTRLA; /* Control Register A */ 1461 register8_t CTRLB; /* Control Register B */ 1462 register8_t STATUS; /* Status Register */ 1463 register8_t ADDR; /* Address Register */ 1464 register8_t DATA; /* Data Register */ 1465 register8_t ADDRMASK; /* Address Mask Register */ 1466 } TWI_SLAVE_t; 1467 1468 /* 1469 -------------------------------------------------------------------------- 1470 TWI - Two-Wire Interface 1471 -------------------------------------------------------------------------- 1472 */ 1473 1474 /* Two-Wire Interface */ 1475 typedef struct TWI_struct 1476 { 1477 register8_t CTRL; /* TWI Common Control Register */ 1478 TWI_MASTER_t MASTER; /* TWI master module */ 1479 TWI_SLAVE_t SLAVE; /* TWI slave module */ 1480 } TWI_t; 1481 1482 /* Master Interrupt Level */ 1483 typedef enum TWI_MASTER_INTLVL_enum 1484 { 1485 TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1486 TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ 1487 TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1488 TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ 1489 } TWI_MASTER_INTLVL_t; 1490 1491 /* Inactive Timeout */ 1492 typedef enum TWI_MASTER_TIMEOUT_enum 1493 { 1494 TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ 1495 TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ 1496 TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ 1497 TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ 1498 } TWI_MASTER_TIMEOUT_t; 1499 1500 /* Master Command */ 1501 typedef enum TWI_MASTER_CMD_enum 1502 { 1503 TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ 1504 TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ 1505 TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ 1506 TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ 1507 } TWI_MASTER_CMD_t; 1508 1509 /* Master Bus State */ 1510 typedef enum TWI_MASTER_BUSSTATE_enum 1511 { 1512 TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ 1513 TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ 1514 TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ 1515 TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ 1516 } TWI_MASTER_BUSSTATE_t; 1517 1518 /* Slave Interrupt Level */ 1519 typedef enum TWI_SLAVE_INTLVL_enum 1520 { 1521 TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1522 TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ 1523 TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1524 TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ 1525 } TWI_SLAVE_INTLVL_t; 1526 1527 /* Slave Command */ 1528 typedef enum TWI_SLAVE_CMD_enum 1529 { 1530 TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ 1531 TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ 1532 TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ 1533 } TWI_SLAVE_CMD_t; 1534 1535 1536 /* 1537 -------------------------------------------------------------------------- 1538 PORT - Port Configuration 1539 -------------------------------------------------------------------------- 1540 */ 1541 1542 /* I/O port Configuration */ 1543 typedef struct PORTCFG_struct 1544 { 1545 register8_t MPCMASK; /* Multi-pin Configuration Mask */ 1546 register8_t reserved_0x01; 1547 register8_t VPCTRLA; /* Virtual Port Control Register A */ 1548 register8_t VPCTRLB; /* Virtual Port Control Register B */ 1549 register8_t CLKEVOUT; /* Clock and Event Out Register */ 1550 } PORTCFG_t; 1551 1552 /* 1553 -------------------------------------------------------------------------- 1554 PORT - Port Configuration 1555 -------------------------------------------------------------------------- 1556 */ 1557 1558 /* Virtual Port */ 1559 typedef struct VPORT_struct 1560 { 1561 register8_t DIR; /* I/O Port Data Direction */ 1562 register8_t OUT; /* I/O Port Output */ 1563 register8_t IN; /* I/O Port Input */ 1564 register8_t INTFLAGS; /* Interrupt Flag Register */ 1565 } VPORT_t; 1566 1567 /* 1568 -------------------------------------------------------------------------- 1569 PORT - Port Configuration 1570 -------------------------------------------------------------------------- 1571 */ 1572 1573 /* I/O Ports */ 1574 typedef struct PORT_struct 1575 { 1576 register8_t DIR; /* I/O Port Data Direction */ 1577 register8_t DIRSET; /* I/O Port Data Direction Set */ 1578 register8_t DIRCLR; /* I/O Port Data Direction Clear */ 1579 register8_t DIRTGL; /* I/O Port Data Direction Toggle */ 1580 register8_t OUT; /* I/O Port Output */ 1581 register8_t OUTSET; /* I/O Port Output Set */ 1582 register8_t OUTCLR; /* I/O Port Output Clear */ 1583 register8_t OUTTGL; /* I/O Port Output Toggle */ 1584 register8_t IN; /* I/O port Input */ 1585 register8_t INTCTRL; /* Interrupt Control Register */ 1586 register8_t INT0MASK; /* Port Interrupt 0 Mask */ 1587 register8_t INT1MASK; /* Port Interrupt 1 Mask */ 1588 register8_t INTFLAGS; /* Interrupt Flag Register */ 1589 register8_t reserved_0x0D; 1590 register8_t reserved_0x0E; 1591 register8_t reserved_0x0F; 1592 register8_t PIN0CTRL; /* Pin 0 Control Register */ 1593 register8_t PIN1CTRL; /* Pin 1 Control Register */ 1594 register8_t PIN2CTRL; /* Pin 2 Control Register */ 1595 register8_t PIN3CTRL; /* Pin 3 Control Register */ 1596 register8_t PIN4CTRL; /* Pin 4 Control Register */ 1597 register8_t PIN5CTRL; /* Pin 5 Control Register */ 1598 register8_t PIN6CTRL; /* Pin 6 Control Register */ 1599 register8_t PIN7CTRL; /* Pin 7 Control Register */ 1600 } PORT_t; 1601 1602 /* Virtual Port 0 Mapping */ 1603 typedef enum PORTCFG_VP0MAP_enum 1604 { 1605 PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ 1606 PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ 1607 PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ 1608 PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ 1609 PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ 1610 PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ 1611 PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ 1612 PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ 1613 PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ 1614 PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ 1615 PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ 1616 PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ 1617 PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ 1618 PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ 1619 PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ 1620 PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ 1621 } PORTCFG_VP0MAP_t; 1622 1623 /* Virtual Port 1 Mapping */ 1624 typedef enum PORTCFG_VP1MAP_enum 1625 { 1626 PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ 1627 PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ 1628 PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ 1629 PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ 1630 PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ 1631 PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ 1632 PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ 1633 PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ 1634 PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ 1635 PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ 1636 PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ 1637 PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ 1638 PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ 1639 PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ 1640 PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ 1641 PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ 1642 } PORTCFG_VP1MAP_t; 1643 1644 /* Virtual Port 2 Mapping */ 1645 typedef enum PORTCFG_VP2MAP_enum 1646 { 1647 PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ 1648 PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ 1649 PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ 1650 PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ 1651 PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ 1652 PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ 1653 PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ 1654 PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ 1655 PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ 1656 PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ 1657 PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ 1658 PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ 1659 PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ 1660 PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ 1661 PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ 1662 PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ 1663 } PORTCFG_VP2MAP_t; 1664 1665 /* Virtual Port 3 Mapping */ 1666 typedef enum PORTCFG_VP3MAP_enum 1667 { 1668 PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ 1669 PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ 1670 PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ 1671 PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ 1672 PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ 1673 PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ 1674 PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ 1675 PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ 1676 PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ 1677 PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ 1678 PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ 1679 PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ 1680 PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ 1681 PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ 1682 PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ 1683 PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ 1684 } PORTCFG_VP3MAP_t; 1685 1686 /* Clock Output Port */ 1687 typedef enum PORTCFG_CLKOUT_enum 1688 { 1689 PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ 1690 PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ 1691 PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ 1692 PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ 1693 } PORTCFG_CLKOUT_t; 1694 1695 /* Event Output Port */ 1696 typedef enum PORTCFG_EVOUT_enum 1697 { 1698 PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ 1699 PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ 1700 PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ 1701 PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ 1702 } PORTCFG_EVOUT_t; 1703 1704 /* Port Interrupt 0 Level */ 1705 typedef enum PORT_INT0LVL_enum 1706 { 1707 PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1708 PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ 1709 PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ 1710 PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ 1711 } PORT_INT0LVL_t; 1712 1713 /* Port Interrupt 1 Level */ 1714 typedef enum PORT_INT1LVL_enum 1715 { 1716 PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1717 PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ 1718 PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ 1719 PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ 1720 } PORT_INT1LVL_t; 1721 1722 /* Output/Pull Configuration */ 1723 typedef enum PORT_OPC_enum 1724 { 1725 PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ 1726 PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ 1727 PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ 1728 PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ 1729 PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ 1730 PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ 1731 PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ 1732 PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ 1733 } PORT_OPC_t; 1734 1735 /* Input/Sense Configuration */ 1736 typedef enum PORT_ISC_enum 1737 { 1738 PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ 1739 PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ 1740 PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ 1741 PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ 1742 PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ 1743 } PORT_ISC_t; 1744 1745 1746 /* 1747 -------------------------------------------------------------------------- 1748 TC - 16-bit Timer/Counter With PWM 1749 -------------------------------------------------------------------------- 1750 */ 1751 1752 /* 16-bit Timer/Counter 0 */ 1753 typedef struct TC0_struct 1754 { 1755 register8_t CTRLA; /* Control Register A */ 1756 register8_t CTRLB; /* Control Register B */ 1757 register8_t CTRLC; /* Control register C */ 1758 register8_t CTRLD; /* Control Register D */ 1759 register8_t CTRLE; /* Control Register E */ 1760 register8_t reserved_0x05; 1761 register8_t INTCTRLA; /* Interrupt Control Register A */ 1762 register8_t INTCTRLB; /* Interrupt Control Register B */ 1763 register8_t CTRLFCLR; /* Control Register F Clear */ 1764 register8_t CTRLFSET; /* Control Register F Set */ 1765 register8_t CTRLGCLR; /* Control Register G Clear */ 1766 register8_t CTRLGSET; /* Control Register G Set */ 1767 register8_t INTFLAGS; /* Interrupt Flag Register */ 1768 register8_t reserved_0x0D; 1769 register8_t reserved_0x0E; 1770 register8_t TEMP; /* Temporary Register For 16-bit Access */ 1771 register8_t reserved_0x10; 1772 register8_t reserved_0x11; 1773 register8_t reserved_0x12; 1774 register8_t reserved_0x13; 1775 register8_t reserved_0x14; 1776 register8_t reserved_0x15; 1777 register8_t reserved_0x16; 1778 register8_t reserved_0x17; 1779 register8_t reserved_0x18; 1780 register8_t reserved_0x19; 1781 register8_t reserved_0x1A; 1782 register8_t reserved_0x1B; 1783 register8_t reserved_0x1C; 1784 register8_t reserved_0x1D; 1785 register8_t reserved_0x1E; 1786 register8_t reserved_0x1F; 1787 _WORDREGISTER(CNT); /* Count */ 1788 register8_t reserved_0x22; 1789 register8_t reserved_0x23; 1790 register8_t reserved_0x24; 1791 register8_t reserved_0x25; 1792 _WORDREGISTER(PER); /* Period */ 1793 _WORDREGISTER(CCA); /* Compare or Capture A */ 1794 _WORDREGISTER(CCB); /* Compare or Capture B */ 1795 _WORDREGISTER(CCC); /* Compare or Capture C */ 1796 _WORDREGISTER(CCD); /* Compare or Capture D */ 1797 register8_t reserved_0x30; 1798 register8_t reserved_0x31; 1799 register8_t reserved_0x32; 1800 register8_t reserved_0x33; 1801 register8_t reserved_0x34; 1802 register8_t reserved_0x35; 1803 _WORDREGISTER(PERBUF); /* Period Buffer */ 1804 _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ 1805 _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ 1806 _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ 1807 _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ 1808 } TC0_t; 1809 1810 /* 1811 -------------------------------------------------------------------------- 1812 TC - 16-bit Timer/Counter With PWM 1813 -------------------------------------------------------------------------- 1814 */ 1815 1816 /* 16-bit Timer/Counter 1 */ 1817 typedef struct TC1_struct 1818 { 1819 register8_t CTRLA; /* Control Register A */ 1820 register8_t CTRLB; /* Control Register B */ 1821 register8_t CTRLC; /* Control register C */ 1822 register8_t CTRLD; /* Control Register D */ 1823 register8_t CTRLE; /* Control Register E */ 1824 register8_t reserved_0x05; 1825 register8_t INTCTRLA; /* Interrupt Control Register A */ 1826 register8_t INTCTRLB; /* Interrupt Control Register B */ 1827 register8_t CTRLFCLR; /* Control Register F Clear */ 1828 register8_t CTRLFSET; /* Control Register F Set */ 1829 register8_t CTRLGCLR; /* Control Register G Clear */ 1830 register8_t CTRLGSET; /* Control Register G Set */ 1831 register8_t INTFLAGS; /* Interrupt Flag Register */ 1832 register8_t reserved_0x0D; 1833 register8_t reserved_0x0E; 1834 register8_t TEMP; /* Temporary Register For 16-bit Access */ 1835 register8_t reserved_0x10; 1836 register8_t reserved_0x11; 1837 register8_t reserved_0x12; 1838 register8_t reserved_0x13; 1839 register8_t reserved_0x14; 1840 register8_t reserved_0x15; 1841 register8_t reserved_0x16; 1842 register8_t reserved_0x17; 1843 register8_t reserved_0x18; 1844 register8_t reserved_0x19; 1845 register8_t reserved_0x1A; 1846 register8_t reserved_0x1B; 1847 register8_t reserved_0x1C; 1848 register8_t reserved_0x1D; 1849 register8_t reserved_0x1E; 1850 register8_t reserved_0x1F; 1851 _WORDREGISTER(CNT); /* Count */ 1852 register8_t reserved_0x22; 1853 register8_t reserved_0x23; 1854 register8_t reserved_0x24; 1855 register8_t reserved_0x25; 1856 _WORDREGISTER(PER); /* Period */ 1857 _WORDREGISTER(CCA); /* Compare or Capture A */ 1858 _WORDREGISTER(CCB); /* Compare or Capture B */ 1859 register8_t reserved_0x2C; 1860 register8_t reserved_0x2D; 1861 register8_t reserved_0x2E; 1862 register8_t reserved_0x2F; 1863 register8_t reserved_0x30; 1864 register8_t reserved_0x31; 1865 register8_t reserved_0x32; 1866 register8_t reserved_0x33; 1867 register8_t reserved_0x34; 1868 register8_t reserved_0x35; 1869 _WORDREGISTER(PERBUF); /* Period Buffer */ 1870 _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ 1871 _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ 1872 } TC1_t; 1873 1874 /* 1875 -------------------------------------------------------------------------- 1876 TC - 16-bit Timer/Counter With PWM 1877 -------------------------------------------------------------------------- 1878 */ 1879 1880 /* Advanced Waveform Extension */ 1881 typedef struct AWEX_struct 1882 { 1883 register8_t CTRL; /* Control Register */ 1884 register8_t reserved_0x01; 1885 register8_t FDEMASK; /* Fault Detection Event Mask */ 1886 register8_t FDCTRL; /* Fault Detection Control Register */ 1887 register8_t STATUS; /* Status Register */ 1888 register8_t reserved_0x05; 1889 register8_t DTBOTH; /* Dead Time Both Sides */ 1890 register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ 1891 register8_t DTLS; /* Dead Time Low Side */ 1892 register8_t DTHS; /* Dead Time High Side */ 1893 register8_t DTLSBUF; /* Dead Time Low Side Buffer */ 1894 register8_t DTHSBUF; /* Dead Time High Side Buffer */ 1895 register8_t OUTOVEN; /* Output Override Enable */ 1896 } AWEX_t; 1897 1898 /* 1899 -------------------------------------------------------------------------- 1900 TC - 16-bit Timer/Counter With PWM 1901 -------------------------------------------------------------------------- 1902 */ 1903 1904 /* High-Resolution Extension */ 1905 typedef struct HIRES_struct 1906 { 1907 register8_t CTRLA; /* Control Register */ 1908 } HIRES_t; 1909 1910 /* Clock Selection */ 1911 typedef enum TC_CLKSEL_enum 1912 { 1913 TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ 1914 TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ 1915 TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ 1916 TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ 1917 TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ 1918 TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ 1919 TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ 1920 TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ 1921 TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ 1922 TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ 1923 TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ 1924 TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ 1925 TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ 1926 TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ 1927 TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ 1928 TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ 1929 } TC_CLKSEL_t; 1930 1931 /* Waveform Generation Mode */ 1932 typedef enum TC_WGMODE_enum 1933 { 1934 TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ 1935 TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ 1936 TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ 1937 TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ 1938 TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ 1939 TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ 1940 } TC_WGMODE_t; 1941 1942 /* Event Action */ 1943 typedef enum TC_EVACT_enum 1944 { 1945 TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ 1946 TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ 1947 TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ 1948 TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ 1949 TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ 1950 TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ 1951 TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ 1952 } TC_EVACT_t; 1953 1954 /* Event Selection */ 1955 typedef enum TC_EVSEL_enum 1956 { 1957 TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ 1958 TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ 1959 TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ 1960 TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ 1961 TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ 1962 TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ 1963 TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ 1964 TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ 1965 TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ 1966 } TC_EVSEL_t; 1967 1968 /* Error Interrupt Level */ 1969 typedef enum TC_ERRINTLVL_enum 1970 { 1971 TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1972 TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1973 TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1974 TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ 1975 } TC_ERRINTLVL_t; 1976 1977 /* Overflow Interrupt Level */ 1978 typedef enum TC_OVFINTLVL_enum 1979 { 1980 TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1981 TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1982 TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1983 TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ 1984 } TC_OVFINTLVL_t; 1985 1986 /* Compare or Capture D Interrupt Level */ 1987 typedef enum TC_CCDINTLVL_enum 1988 { 1989 TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1990 TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ 1991 TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1992 TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ 1993 } TC_CCDINTLVL_t; 1994 1995 /* Compare or Capture C Interrupt Level */ 1996 typedef enum TC_CCCINTLVL_enum 1997 { 1998 TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 1999 TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 2000 TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 2001 TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ 2002 } TC_CCCINTLVL_t; 2003 2004 /* Compare or Capture B Interrupt Level */ 2005 typedef enum TC_CCBINTLVL_enum 2006 { 2007 TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 2008 TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ 2009 TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 2010 TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ 2011 } TC_CCBINTLVL_t; 2012 2013 /* Compare or Capture A Interrupt Level */ 2014 typedef enum TC_CCAINTLVL_enum 2015 { 2016 TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2017 TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ 2018 TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2019 TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ 2020 } TC_CCAINTLVL_t; 2021 2022 /* Timer/Counter Command */ 2023 typedef enum TC_CMD_enum 2024 { 2025 TC_CMD_NONE_gc = (0x00<<2), /* No Command */ 2026 TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ 2027 TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ 2028 TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ 2029 } TC_CMD_t; 2030 2031 /* Fault Detect Action */ 2032 typedef enum AWEX_FDACT_enum 2033 { 2034 AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ 2035 AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ 2036 AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ 2037 } AWEX_FDACT_t; 2038 2039 /* High Resolution Enable */ 2040 typedef enum HIRES_HREN_enum 2041 { 2042 HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ 2043 HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ 2044 HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ 2045 HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ 2046 } HIRES_HREN_t; 2047 2048 2049 /* 2050 -------------------------------------------------------------------------- 2051 USART - Universal Asynchronous Receiver-Transmitter 2052 -------------------------------------------------------------------------- 2053 */ 2054 2055 /* Universal Synchronous/Asynchronous Receiver/Transmitter */ 2056 typedef struct USART_struct 2057 { 2058 register8_t DATA; /* Data Register */ 2059 register8_t STATUS; /* Status Register */ 2060 register8_t reserved_0x02; 2061 register8_t CTRLA; /* Control Register A */ 2062 register8_t CTRLB; /* Control Register B */ 2063 register8_t CTRLC; /* Control Register C */ 2064 register8_t BAUDCTRLA; /* Baud Rate Control Register A */ 2065 register8_t BAUDCTRLB; /* Baud Rate Control Register B */ 2066 } USART_t; 2067 2068 /* Receive Complete Interrupt level */ 2069 typedef enum USART_RXCINTLVL_enum 2070 { 2071 USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 2072 USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 2073 USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 2074 USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ 2075 } USART_RXCINTLVL_t; 2076 2077 /* Transmit Complete Interrupt level */ 2078 typedef enum USART_TXCINTLVL_enum 2079 { 2080 USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 2081 USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ 2082 USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 2083 USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ 2084 } USART_TXCINTLVL_t; 2085 2086 /* Data Register Empty Interrupt level */ 2087 typedef enum USART_DREINTLVL_enum 2088 { 2089 USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2090 USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ 2091 USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2092 USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ 2093 } USART_DREINTLVL_t; 2094 2095 /* Character Size */ 2096 typedef enum USART_CHSIZE_enum 2097 { 2098 USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ 2099 USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ 2100 USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ 2101 USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ 2102 USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ 2103 } USART_CHSIZE_t; 2104 2105 /* Communication Mode */ 2106 typedef enum USART_CMODE_enum 2107 { 2108 USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ 2109 USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ 2110 USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ 2111 USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ 2112 } USART_CMODE_t; 2113 2114 /* Parity Mode */ 2115 typedef enum USART_PMODE_enum 2116 { 2117 USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ 2118 USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ 2119 USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ 2120 } USART_PMODE_t; 2121 2122 2123 /* 2124 -------------------------------------------------------------------------- 2125 SPI - Serial Peripheral Interface 2126 -------------------------------------------------------------------------- 2127 */ 2128 2129 /* Serial Peripheral Interface */ 2130 typedef struct SPI_struct 2131 { 2132 register8_t CTRL; /* Control Register */ 2133 register8_t INTCTRL; /* Interrupt Control Register */ 2134 register8_t STATUS; /* Status Register */ 2135 register8_t DATA; /* Data Register */ 2136 } SPI_t; 2137 2138 /* SPI Mode */ 2139 typedef enum SPI_MODE_enum 2140 { 2141 SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ 2142 SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ 2143 SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ 2144 SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ 2145 } SPI_MODE_t; 2146 2147 /* Prescaler setting */ 2148 typedef enum SPI_PRESCALER_enum 2149 { 2150 SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ 2151 SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ 2152 SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ 2153 SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ 2154 } SPI_PRESCALER_t; 2155 2156 /* Interrupt level */ 2157 typedef enum SPI_INTLVL_enum 2158 { 2159 SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2160 SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ 2161 SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2162 SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ 2163 } SPI_INTLVL_t; 2164 2165 2166 /* 2167 -------------------------------------------------------------------------- 2168 IRCOM - IR Communication Module 2169 -------------------------------------------------------------------------- 2170 */ 2171 2172 /* IR Communication Module */ 2173 typedef struct IRCOM_struct 2174 { 2175 register8_t CTRL; /* Control Register */ 2176 register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ 2177 register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ 2178 } IRCOM_t; 2179 2180 /* Event channel selection */ 2181 typedef enum IRDA_EVSEL_enum 2182 { 2183 IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ 2184 IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ 2185 IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ 2186 IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ 2187 IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ 2188 IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ 2189 IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ 2190 IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ 2191 IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ 2192 } IRDA_EVSEL_t; 2193 2194 2195 2196 /* 2197 ========================================================================== 2198 IO Module Instances. Mapped to memory. 2199 ========================================================================== 2200 */ 2201 2202 #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ 2203 #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ 2204 #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ 2205 #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ 2206 #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ 2207 #define CLK (*(CLK_t *) 0x0040) /* Clock System */ 2208 #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ 2209 #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ 2210 #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ 2211 #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ 2212 #define RST (*(RST_t *) 0x0078) /* Reset Controller */ 2213 #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ 2214 #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ 2215 #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ 2216 #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ 2217 #define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ 2218 #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ 2219 #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ 2220 #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ 2221 #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ 2222 #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ 2223 #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ 2224 #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ 2225 #define PORTA (*(PORT_t *) 0x0600) /* Port A */ 2226 #define PORTB (*(PORT_t *) 0x0620) /* Port B */ 2227 #define PORTC (*(PORT_t *) 0x0640) /* Port C */ 2228 #define PORTD (*(PORT_t *) 0x0660) /* Port D */ 2229 #define PORTE (*(PORT_t *) 0x0680) /* Port E */ 2230 #define PORTF (*(PORT_t *) 0x06A0) /* Port F */ 2231 #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ 2232 #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ 2233 #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ 2234 #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ 2235 #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ 2236 #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ 2237 #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ 2238 #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ 2239 #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ 2240 #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ 2241 #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ 2242 #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ 2243 #define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ 2244 #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ 2245 #define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ 2246 #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ 2247 2248 2249 #endif /* !defined (__ASSEMBLER__) */ 2250 2251 2252 /* ========== Flattened fully qualified IO register names ========== */ 2253 2254 /* GPIO - General Purpose IO Registers */ 2255 #define GPIO_GPIOR0 _SFR_MEM8(0x0000) 2256 #define GPIO_GPIOR1 _SFR_MEM8(0x0001) 2257 #define GPIO_GPIOR2 _SFR_MEM8(0x0002) 2258 #define GPIO_GPIOR3 _SFR_MEM8(0x0003) 2259 #define GPIO_GPIOR4 _SFR_MEM8(0x0004) 2260 #define GPIO_GPIOR5 _SFR_MEM8(0x0005) 2261 #define GPIO_GPIOR6 _SFR_MEM8(0x0006) 2262 #define GPIO_GPIOR7 _SFR_MEM8(0x0007) 2263 #define GPIO_GPIOR8 _SFR_MEM8(0x0008) 2264 #define GPIO_GPIOR9 _SFR_MEM8(0x0009) 2265 #define GPIO_GPIORA _SFR_MEM8(0x000A) 2266 #define GPIO_GPIORB _SFR_MEM8(0x000B) 2267 #define GPIO_GPIORC _SFR_MEM8(0x000C) 2268 #define GPIO_GPIORD _SFR_MEM8(0x000D) 2269 #define GPIO_GPIORE _SFR_MEM8(0x000E) 2270 #define GPIO_GPIORF _SFR_MEM8(0x000F) 2271 2272 /* VPORT0 - Virtual Port 0 */ 2273 #define VPORT0_DIR _SFR_MEM8(0x0010) 2274 #define VPORT0_OUT _SFR_MEM8(0x0011) 2275 #define VPORT0_IN _SFR_MEM8(0x0012) 2276 #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) 2277 2278 /* VPORT1 - Virtual Port 1 */ 2279 #define VPORT1_DIR _SFR_MEM8(0x0014) 2280 #define VPORT1_OUT _SFR_MEM8(0x0015) 2281 #define VPORT1_IN _SFR_MEM8(0x0016) 2282 #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) 2283 2284 /* VPORT2 - Virtual Port 2 */ 2285 #define VPORT2_DIR _SFR_MEM8(0x0018) 2286 #define VPORT2_OUT _SFR_MEM8(0x0019) 2287 #define VPORT2_IN _SFR_MEM8(0x001A) 2288 #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) 2289 2290 /* VPORT3 - Virtual Port 3 */ 2291 #define VPORT3_DIR _SFR_MEM8(0x001C) 2292 #define VPORT3_OUT _SFR_MEM8(0x001D) 2293 #define VPORT3_IN _SFR_MEM8(0x001E) 2294 #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) 2295 2296 /* OCD - On-Chip Debug System */ 2297 #define OCD_OCDR0 _SFR_MEM8(0x002E) 2298 #define OCD_OCDR1 _SFR_MEM8(0x002F) 2299 2300 /* CPU - CPU Registers */ 2301 #define CPU_CCP _SFR_MEM8(0x0034) 2302 #define CPU_RAMPD _SFR_MEM8(0x0038) 2303 #define CPU_RAMPX _SFR_MEM8(0x0039) 2304 #define CPU_RAMPY _SFR_MEM8(0x003A) 2305 #define CPU_RAMPZ _SFR_MEM8(0x003B) 2306 #define CPU_EIND _SFR_MEM8(0x003C) 2307 #define CPU_SPL _SFR_MEM8(0x003D) 2308 #define CPU_SPH _SFR_MEM8(0x003E) 2309 #define CPU_SREG _SFR_MEM8(0x003F) 2310 2311 /* CLK - Clock System */ 2312 #define CLK_CTRL _SFR_MEM8(0x0040) 2313 #define CLK_PSCTRL _SFR_MEM8(0x0041) 2314 #define CLK_LOCK _SFR_MEM8(0x0042) 2315 #define CLK_RTCCTRL _SFR_MEM8(0x0043) 2316 2317 /* SLEEP - Sleep Controller */ 2318 #define SLEEP_CTRL _SFR_MEM8(0x0048) 2319 2320 /* OSC - Oscillator Control */ 2321 #define OSC_CTRL _SFR_MEM8(0x0050) 2322 #define OSC_STATUS _SFR_MEM8(0x0051) 2323 #define OSC_XOSCCTRL _SFR_MEM8(0x0052) 2324 #define OSC_XOSCFAIL _SFR_MEM8(0x0053) 2325 #define OSC_RC32KCAL _SFR_MEM8(0x0054) 2326 #define OSC_PLLCTRL _SFR_MEM8(0x0055) 2327 #define OSC_DFLLCTRL _SFR_MEM8(0x0056) 2328 2329 /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ 2330 #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) 2331 #define DFLLRC32M_CALA _SFR_MEM8(0x0062) 2332 #define DFLLRC32M_CALB _SFR_MEM8(0x0063) 2333 #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) 2334 #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) 2335 #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) 2336 2337 /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ 2338 #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) 2339 #define DFLLRC2M_CALA _SFR_MEM8(0x006A) 2340 #define DFLLRC2M_CALB _SFR_MEM8(0x006B) 2341 #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) 2342 #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) 2343 #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) 2344 2345 /* PR - Power Reduction */ 2346 #define PR_PRGEN _SFR_MEM8(0x0070) 2347 #define PR_PRPA _SFR_MEM8(0x0071) 2348 #define PR_PRPC _SFR_MEM8(0x0073) 2349 #define PR_PRPD _SFR_MEM8(0x0074) 2350 #define PR_PRPE _SFR_MEM8(0x0075) 2351 #define PR_PRPF _SFR_MEM8(0x0076) 2352 2353 /* RST - Reset Controller */ 2354 #define RST_STATUS _SFR_MEM8(0x0078) 2355 #define RST_CTRL _SFR_MEM8(0x0079) 2356 2357 /* WDT - Watch-Dog Timer */ 2358 #define WDT_CTRL _SFR_MEM8(0x0080) 2359 #define WDT_WINCTRL _SFR_MEM8(0x0081) 2360 #define WDT_STATUS _SFR_MEM8(0x0082) 2361 2362 /* MCU - MCU Control */ 2363 #define MCU_DEVID0 _SFR_MEM8(0x0090) 2364 #define MCU_DEVID1 _SFR_MEM8(0x0091) 2365 #define MCU_DEVID2 _SFR_MEM8(0x0092) 2366 #define MCU_REVID _SFR_MEM8(0x0093) 2367 #define MCU_JTAGUID _SFR_MEM8(0x0094) 2368 #define MCU_MCUCR _SFR_MEM8(0x0096) 2369 #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) 2370 #define MCU_AWEXLOCK _SFR_MEM8(0x0099) 2371 2372 /* PMIC - Programmable Interrupt Controller */ 2373 #define PMIC_STATUS _SFR_MEM8(0x00A0) 2374 #define PMIC_INTPRI _SFR_MEM8(0x00A1) 2375 #define PMIC_CTRL _SFR_MEM8(0x00A2) 2376 2377 /* PORTCFG - Port Configuration */ 2378 #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) 2379 #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) 2380 #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) 2381 #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) 2382 2383 /* CRC - Cyclic Redundancy Checker */ 2384 #define CRC_CTRL _SFR_MEM8(0x00D0) 2385 #define CRC_STATUS _SFR_MEM8(0x00D1) 2386 #define CRC_DATAIN _SFR_MEM8(0x00D3) 2387 #define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) 2388 #define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) 2389 #define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) 2390 #define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) 2391 2392 /* EVSYS - Event System */ 2393 #define EVSYS_CH0MUX _SFR_MEM8(0x0180) 2394 #define EVSYS_CH1MUX _SFR_MEM8(0x0181) 2395 #define EVSYS_CH2MUX _SFR_MEM8(0x0182) 2396 #define EVSYS_CH3MUX _SFR_MEM8(0x0183) 2397 #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) 2398 #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) 2399 #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) 2400 #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) 2401 #define EVSYS_STROBE _SFR_MEM8(0x0190) 2402 #define EVSYS_DATA _SFR_MEM8(0x0191) 2403 2404 /* NVM - Non Volatile Memory Controller */ 2405 #define NVM_ADDR0 _SFR_MEM8(0x01C0) 2406 #define NVM_ADDR1 _SFR_MEM8(0x01C1) 2407 #define NVM_ADDR2 _SFR_MEM8(0x01C2) 2408 #define NVM_DATA0 _SFR_MEM8(0x01C4) 2409 #define NVM_DATA1 _SFR_MEM8(0x01C5) 2410 #define NVM_DATA2 _SFR_MEM8(0x01C6) 2411 #define NVM_CMD _SFR_MEM8(0x01CA) 2412 #define NVM_CTRLA _SFR_MEM8(0x01CB) 2413 #define NVM_CTRLB _SFR_MEM8(0x01CC) 2414 #define NVM_INTCTRL _SFR_MEM8(0x01CD) 2415 #define NVM_STATUS _SFR_MEM8(0x01CF) 2416 #define NVM_LOCKBITS _SFR_MEM8(0x01D0) 2417 2418 /* ADCA - Analog to Digital Converter A */ 2419 #define ADCA_CTRLA _SFR_MEM8(0x0200) 2420 #define ADCA_CTRLB _SFR_MEM8(0x0201) 2421 #define ADCA_REFCTRL _SFR_MEM8(0x0202) 2422 #define ADCA_EVCTRL _SFR_MEM8(0x0203) 2423 #define ADCA_PRESCALER _SFR_MEM8(0x0204) 2424 #define ADCA_INTFLAGS _SFR_MEM8(0x0206) 2425 #define ADCA_TEMP _SFR_MEM8(0x0207) 2426 #define ADCA_CAL _SFR_MEM16(0x020C) 2427 #define ADCA_CH0RES _SFR_MEM16(0x0210) 2428 #define ADCA_CMP _SFR_MEM16(0x0218) 2429 #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) 2430 #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) 2431 #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) 2432 #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) 2433 #define ADCA_CH0_RES _SFR_MEM16(0x0224) 2434 2435 /* ACA - Analog Comparator A */ 2436 #define ACA_AC0CTRL _SFR_MEM8(0x0380) 2437 #define ACA_AC1CTRL _SFR_MEM8(0x0381) 2438 #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) 2439 #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) 2440 #define ACA_CTRLA _SFR_MEM8(0x0384) 2441 #define ACA_CTRLB _SFR_MEM8(0x0385) 2442 #define ACA_WINCTRL _SFR_MEM8(0x0386) 2443 #define ACA_STATUS _SFR_MEM8(0x0387) 2444 2445 /* RTC - Real-Time Counter */ 2446 #define RTC_CTRL _SFR_MEM8(0x0400) 2447 #define RTC_STATUS _SFR_MEM8(0x0401) 2448 #define RTC_INTCTRL _SFR_MEM8(0x0402) 2449 #define RTC_INTFLAGS _SFR_MEM8(0x0403) 2450 #define RTC_TEMP _SFR_MEM8(0x0404) 2451 #define RTC_CNT _SFR_MEM16(0x0408) 2452 #define RTC_PER _SFR_MEM16(0x040A) 2453 #define RTC_COMP _SFR_MEM16(0x040C) 2454 2455 /* TWIC - Two-Wire Interface C */ 2456 #define TWIC_CTRL _SFR_MEM8(0x0480) 2457 #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) 2458 #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) 2459 #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) 2460 #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) 2461 #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) 2462 #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) 2463 #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) 2464 #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) 2465 #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) 2466 #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) 2467 #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) 2468 #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) 2469 #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) 2470 2471 /* TWIE - Two-Wire Interface E */ 2472 #define TWIE_CTRL _SFR_MEM8(0x04A0) 2473 #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) 2474 #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) 2475 #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) 2476 #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) 2477 #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) 2478 #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) 2479 #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) 2480 #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) 2481 #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) 2482 #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) 2483 #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) 2484 #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) 2485 #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) 2486 2487 /* PORTA - Port A */ 2488 #define PORTA_DIR _SFR_MEM8(0x0600) 2489 #define PORTA_DIRSET _SFR_MEM8(0x0601) 2490 #define PORTA_DIRCLR _SFR_MEM8(0x0602) 2491 #define PORTA_DIRTGL _SFR_MEM8(0x0603) 2492 #define PORTA_OUT _SFR_MEM8(0x0604) 2493 #define PORTA_OUTSET _SFR_MEM8(0x0605) 2494 #define PORTA_OUTCLR _SFR_MEM8(0x0606) 2495 #define PORTA_OUTTGL _SFR_MEM8(0x0607) 2496 #define PORTA_IN _SFR_MEM8(0x0608) 2497 #define PORTA_INTCTRL _SFR_MEM8(0x0609) 2498 #define PORTA_INT0MASK _SFR_MEM8(0x060A) 2499 #define PORTA_INT1MASK _SFR_MEM8(0x060B) 2500 #define PORTA_INTFLAGS _SFR_MEM8(0x060C) 2501 #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) 2502 #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) 2503 #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) 2504 #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) 2505 #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) 2506 #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) 2507 #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) 2508 #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) 2509 2510 /* PORTB - Port B */ 2511 #define PORTB_DIR _SFR_MEM8(0x0620) 2512 #define PORTB_DIRSET _SFR_MEM8(0x0621) 2513 #define PORTB_DIRCLR _SFR_MEM8(0x0622) 2514 #define PORTB_DIRTGL _SFR_MEM8(0x0623) 2515 #define PORTB_OUT _SFR_MEM8(0x0624) 2516 #define PORTB_OUTSET _SFR_MEM8(0x0625) 2517 #define PORTB_OUTCLR _SFR_MEM8(0x0626) 2518 #define PORTB_OUTTGL _SFR_MEM8(0x0627) 2519 #define PORTB_IN _SFR_MEM8(0x0628) 2520 #define PORTB_INTCTRL _SFR_MEM8(0x0629) 2521 #define PORTB_INT0MASK _SFR_MEM8(0x062A) 2522 #define PORTB_INT1MASK _SFR_MEM8(0x062B) 2523 #define PORTB_INTFLAGS _SFR_MEM8(0x062C) 2524 #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) 2525 #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) 2526 #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) 2527 #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) 2528 #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) 2529 #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) 2530 #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) 2531 #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) 2532 2533 /* PORTC - Port C */ 2534 #define PORTC_DIR _SFR_MEM8(0x0640) 2535 #define PORTC_DIRSET _SFR_MEM8(0x0641) 2536 #define PORTC_DIRCLR _SFR_MEM8(0x0642) 2537 #define PORTC_DIRTGL _SFR_MEM8(0x0643) 2538 #define PORTC_OUT _SFR_MEM8(0x0644) 2539 #define PORTC_OUTSET _SFR_MEM8(0x0645) 2540 #define PORTC_OUTCLR _SFR_MEM8(0x0646) 2541 #define PORTC_OUTTGL _SFR_MEM8(0x0647) 2542 #define PORTC_IN _SFR_MEM8(0x0648) 2543 #define PORTC_INTCTRL _SFR_MEM8(0x0649) 2544 #define PORTC_INT0MASK _SFR_MEM8(0x064A) 2545 #define PORTC_INT1MASK _SFR_MEM8(0x064B) 2546 #define PORTC_INTFLAGS _SFR_MEM8(0x064C) 2547 #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) 2548 #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) 2549 #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) 2550 #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) 2551 #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) 2552 #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) 2553 #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) 2554 #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) 2555 2556 /* PORTD - Port D */ 2557 #define PORTD_DIR _SFR_MEM8(0x0660) 2558 #define PORTD_DIRSET _SFR_MEM8(0x0661) 2559 #define PORTD_DIRCLR _SFR_MEM8(0x0662) 2560 #define PORTD_DIRTGL _SFR_MEM8(0x0663) 2561 #define PORTD_OUT _SFR_MEM8(0x0664) 2562 #define PORTD_OUTSET _SFR_MEM8(0x0665) 2563 #define PORTD_OUTCLR _SFR_MEM8(0x0666) 2564 #define PORTD_OUTTGL _SFR_MEM8(0x0667) 2565 #define PORTD_IN _SFR_MEM8(0x0668) 2566 #define PORTD_INTCTRL _SFR_MEM8(0x0669) 2567 #define PORTD_INT0MASK _SFR_MEM8(0x066A) 2568 #define PORTD_INT1MASK _SFR_MEM8(0x066B) 2569 #define PORTD_INTFLAGS _SFR_MEM8(0x066C) 2570 #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) 2571 #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) 2572 #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) 2573 #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) 2574 #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) 2575 #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) 2576 #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) 2577 #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) 2578 2579 /* PORTE - Port E */ 2580 #define PORTE_DIR _SFR_MEM8(0x0680) 2581 #define PORTE_DIRSET _SFR_MEM8(0x0681) 2582 #define PORTE_DIRCLR _SFR_MEM8(0x0682) 2583 #define PORTE_DIRTGL _SFR_MEM8(0x0683) 2584 #define PORTE_OUT _SFR_MEM8(0x0684) 2585 #define PORTE_OUTSET _SFR_MEM8(0x0685) 2586 #define PORTE_OUTCLR _SFR_MEM8(0x0686) 2587 #define PORTE_OUTTGL _SFR_MEM8(0x0687) 2588 #define PORTE_IN _SFR_MEM8(0x0688) 2589 #define PORTE_INTCTRL _SFR_MEM8(0x0689) 2590 #define PORTE_INT0MASK _SFR_MEM8(0x068A) 2591 #define PORTE_INT1MASK _SFR_MEM8(0x068B) 2592 #define PORTE_INTFLAGS _SFR_MEM8(0x068C) 2593 #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) 2594 #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) 2595 #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) 2596 #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) 2597 #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) 2598 #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) 2599 #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) 2600 #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) 2601 2602 /* PORTF - Port F */ 2603 #define PORTF_DIR _SFR_MEM8(0x06A0) 2604 #define PORTF_DIRSET _SFR_MEM8(0x06A1) 2605 #define PORTF_DIRCLR _SFR_MEM8(0x06A2) 2606 #define PORTF_DIRTGL _SFR_MEM8(0x06A3) 2607 #define PORTF_OUT _SFR_MEM8(0x06A4) 2608 #define PORTF_OUTSET _SFR_MEM8(0x06A5) 2609 #define PORTF_OUTCLR _SFR_MEM8(0x06A6) 2610 #define PORTF_OUTTGL _SFR_MEM8(0x06A7) 2611 #define PORTF_IN _SFR_MEM8(0x06A8) 2612 #define PORTF_INTCTRL _SFR_MEM8(0x06A9) 2613 #define PORTF_INT0MASK _SFR_MEM8(0x06AA) 2614 #define PORTF_INT1MASK _SFR_MEM8(0x06AB) 2615 #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) 2616 #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) 2617 #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) 2618 #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) 2619 #define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) 2620 #define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) 2621 #define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) 2622 #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) 2623 #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) 2624 2625 /* PORTR - Port R */ 2626 #define PORTR_DIR _SFR_MEM8(0x07E0) 2627 #define PORTR_DIRSET _SFR_MEM8(0x07E1) 2628 #define PORTR_DIRCLR _SFR_MEM8(0x07E2) 2629 #define PORTR_DIRTGL _SFR_MEM8(0x07E3) 2630 #define PORTR_OUT _SFR_MEM8(0x07E4) 2631 #define PORTR_OUTSET _SFR_MEM8(0x07E5) 2632 #define PORTR_OUTCLR _SFR_MEM8(0x07E6) 2633 #define PORTR_OUTTGL _SFR_MEM8(0x07E7) 2634 #define PORTR_IN _SFR_MEM8(0x07E8) 2635 #define PORTR_INTCTRL _SFR_MEM8(0x07E9) 2636 #define PORTR_INT0MASK _SFR_MEM8(0x07EA) 2637 #define PORTR_INT1MASK _SFR_MEM8(0x07EB) 2638 #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) 2639 #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) 2640 #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) 2641 #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) 2642 #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) 2643 #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) 2644 #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) 2645 #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) 2646 #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) 2647 2648 /* TCC0 - Timer/Counter C0 */ 2649 #define TCC0_CTRLA _SFR_MEM8(0x0800) 2650 #define TCC0_CTRLB _SFR_MEM8(0x0801) 2651 #define TCC0_CTRLC _SFR_MEM8(0x0802) 2652 #define TCC0_CTRLD _SFR_MEM8(0x0803) 2653 #define TCC0_CTRLE _SFR_MEM8(0x0804) 2654 #define TCC0_INTCTRLA _SFR_MEM8(0x0806) 2655 #define TCC0_INTCTRLB _SFR_MEM8(0x0807) 2656 #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) 2657 #define TCC0_CTRLFSET _SFR_MEM8(0x0809) 2658 #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) 2659 #define TCC0_CTRLGSET _SFR_MEM8(0x080B) 2660 #define TCC0_INTFLAGS _SFR_MEM8(0x080C) 2661 #define TCC0_TEMP _SFR_MEM8(0x080F) 2662 #define TCC0_CNT _SFR_MEM16(0x0820) 2663 #define TCC0_PER _SFR_MEM16(0x0826) 2664 #define TCC0_CCA _SFR_MEM16(0x0828) 2665 #define TCC0_CCB _SFR_MEM16(0x082A) 2666 #define TCC0_CCC _SFR_MEM16(0x082C) 2667 #define TCC0_CCD _SFR_MEM16(0x082E) 2668 #define TCC0_PERBUF _SFR_MEM16(0x0836) 2669 #define TCC0_CCABUF _SFR_MEM16(0x0838) 2670 #define TCC0_CCBBUF _SFR_MEM16(0x083A) 2671 #define TCC0_CCCBUF _SFR_MEM16(0x083C) 2672 #define TCC0_CCDBUF _SFR_MEM16(0x083E) 2673 2674 /* TCC1 - Timer/Counter C1 */ 2675 #define TCC1_CTRLA _SFR_MEM8(0x0840) 2676 #define TCC1_CTRLB _SFR_MEM8(0x0841) 2677 #define TCC1_CTRLC _SFR_MEM8(0x0842) 2678 #define TCC1_CTRLD _SFR_MEM8(0x0843) 2679 #define TCC1_CTRLE _SFR_MEM8(0x0844) 2680 #define TCC1_INTCTRLA _SFR_MEM8(0x0846) 2681 #define TCC1_INTCTRLB _SFR_MEM8(0x0847) 2682 #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) 2683 #define TCC1_CTRLFSET _SFR_MEM8(0x0849) 2684 #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) 2685 #define TCC1_CTRLGSET _SFR_MEM8(0x084B) 2686 #define TCC1_INTFLAGS _SFR_MEM8(0x084C) 2687 #define TCC1_TEMP _SFR_MEM8(0x084F) 2688 #define TCC1_CNT _SFR_MEM16(0x0860) 2689 #define TCC1_PER _SFR_MEM16(0x0866) 2690 #define TCC1_CCA _SFR_MEM16(0x0868) 2691 #define TCC1_CCB _SFR_MEM16(0x086A) 2692 #define TCC1_PERBUF _SFR_MEM16(0x0876) 2693 #define TCC1_CCABUF _SFR_MEM16(0x0878) 2694 #define TCC1_CCBBUF _SFR_MEM16(0x087A) 2695 2696 /* AWEXC - Advanced Waveform Extension C */ 2697 #define AWEXC_CTRL _SFR_MEM8(0x0880) 2698 #define AWEXC_FDEMASK _SFR_MEM8(0x0882) 2699 #define AWEXC_FDCTRL _SFR_MEM8(0x0883) 2700 #define AWEXC_STATUS _SFR_MEM8(0x0884) 2701 #define AWEXC_DTBOTH _SFR_MEM8(0x0886) 2702 #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) 2703 #define AWEXC_DTLS _SFR_MEM8(0x0888) 2704 #define AWEXC_DTHS _SFR_MEM8(0x0889) 2705 #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) 2706 #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) 2707 #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) 2708 2709 /* HIRESC - High-Resolution Extension C */ 2710 #define HIRESC_CTRLA _SFR_MEM8(0x0890) 2711 2712 /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ 2713 #define USARTC0_DATA _SFR_MEM8(0x08A0) 2714 #define USARTC0_STATUS _SFR_MEM8(0x08A1) 2715 #define USARTC0_CTRLA _SFR_MEM8(0x08A3) 2716 #define USARTC0_CTRLB _SFR_MEM8(0x08A4) 2717 #define USARTC0_CTRLC _SFR_MEM8(0x08A5) 2718 #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) 2719 #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) 2720 2721 /* SPIC - Serial Peripheral Interface C */ 2722 #define SPIC_CTRL _SFR_MEM8(0x08C0) 2723 #define SPIC_INTCTRL _SFR_MEM8(0x08C1) 2724 #define SPIC_STATUS _SFR_MEM8(0x08C2) 2725 #define SPIC_DATA _SFR_MEM8(0x08C3) 2726 2727 /* IRCOM - IR Communication Module */ 2728 #define IRCOM_CTRL _SFR_MEM8(0x08F8) 2729 #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) 2730 #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) 2731 2732 /* TCD0 - Timer/Counter D0 */ 2733 #define TCD0_CTRLA _SFR_MEM8(0x0900) 2734 #define TCD0_CTRLB _SFR_MEM8(0x0901) 2735 #define TCD0_CTRLC _SFR_MEM8(0x0902) 2736 #define TCD0_CTRLD _SFR_MEM8(0x0903) 2737 #define TCD0_CTRLE _SFR_MEM8(0x0904) 2738 #define TCD0_INTCTRLA _SFR_MEM8(0x0906) 2739 #define TCD0_INTCTRLB _SFR_MEM8(0x0907) 2740 #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) 2741 #define TCD0_CTRLFSET _SFR_MEM8(0x0909) 2742 #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) 2743 #define TCD0_CTRLGSET _SFR_MEM8(0x090B) 2744 #define TCD0_INTFLAGS _SFR_MEM8(0x090C) 2745 #define TCD0_TEMP _SFR_MEM8(0x090F) 2746 #define TCD0_CNT _SFR_MEM16(0x0920) 2747 #define TCD0_PER _SFR_MEM16(0x0926) 2748 #define TCD0_CCA _SFR_MEM16(0x0928) 2749 #define TCD0_CCB _SFR_MEM16(0x092A) 2750 #define TCD0_CCC _SFR_MEM16(0x092C) 2751 #define TCD0_CCD _SFR_MEM16(0x092E) 2752 #define TCD0_PERBUF _SFR_MEM16(0x0936) 2753 #define TCD0_CCABUF _SFR_MEM16(0x0938) 2754 #define TCD0_CCBBUF _SFR_MEM16(0x093A) 2755 #define TCD0_CCCBUF _SFR_MEM16(0x093C) 2756 #define TCD0_CCDBUF _SFR_MEM16(0x093E) 2757 2758 /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ 2759 #define USARTD0_DATA _SFR_MEM8(0x09A0) 2760 #define USARTD0_STATUS _SFR_MEM8(0x09A1) 2761 #define USARTD0_CTRLA _SFR_MEM8(0x09A3) 2762 #define USARTD0_CTRLB _SFR_MEM8(0x09A4) 2763 #define USARTD0_CTRLC _SFR_MEM8(0x09A5) 2764 #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) 2765 #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) 2766 2767 /* SPID - Serial Peripheral Interface D */ 2768 #define SPID_CTRL _SFR_MEM8(0x09C0) 2769 #define SPID_INTCTRL _SFR_MEM8(0x09C1) 2770 #define SPID_STATUS _SFR_MEM8(0x09C2) 2771 #define SPID_DATA _SFR_MEM8(0x09C3) 2772 2773 /* TCE0 - Timer/Counter E0 */ 2774 #define TCE0_CTRLA _SFR_MEM8(0x0A00) 2775 #define TCE0_CTRLB _SFR_MEM8(0x0A01) 2776 #define TCE0_CTRLC _SFR_MEM8(0x0A02) 2777 #define TCE0_CTRLD _SFR_MEM8(0x0A03) 2778 #define TCE0_CTRLE _SFR_MEM8(0x0A04) 2779 #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) 2780 #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) 2781 #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) 2782 #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) 2783 #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) 2784 #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) 2785 #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) 2786 #define TCE0_TEMP _SFR_MEM8(0x0A0F) 2787 #define TCE0_CNT _SFR_MEM16(0x0A20) 2788 #define TCE0_PER _SFR_MEM16(0x0A26) 2789 #define TCE0_CCA _SFR_MEM16(0x0A28) 2790 #define TCE0_CCB _SFR_MEM16(0x0A2A) 2791 #define TCE0_CCC _SFR_MEM16(0x0A2C) 2792 #define TCE0_CCD _SFR_MEM16(0x0A2E) 2793 #define TCE0_PERBUF _SFR_MEM16(0x0A36) 2794 #define TCE0_CCABUF _SFR_MEM16(0x0A38) 2795 #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) 2796 #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) 2797 #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) 2798 2799 /* AWEXE - Advanced Waveform Extension E */ 2800 #define AWEXE_CTRL _SFR_MEM8(0x0A80) 2801 #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) 2802 #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) 2803 #define AWEXE_STATUS _SFR_MEM8(0x0A84) 2804 #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) 2805 #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) 2806 #define AWEXE_DTLS _SFR_MEM8(0x0A88) 2807 #define AWEXE_DTHS _SFR_MEM8(0x0A89) 2808 #define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) 2809 #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) 2810 #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) 2811 2812 /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ 2813 #define USARTE0_DATA _SFR_MEM8(0x0AA0) 2814 #define USARTE0_STATUS _SFR_MEM8(0x0AA1) 2815 #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) 2816 #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) 2817 #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) 2818 #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) 2819 #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) 2820 2821 /* SPIE - Serial Peripheral Interface E */ 2822 #define SPIE_CTRL _SFR_MEM8(0x0AC0) 2823 #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) 2824 #define SPIE_STATUS _SFR_MEM8(0x0AC2) 2825 #define SPIE_DATA _SFR_MEM8(0x0AC3) 2826 2827 /* TCF0 - Timer/Counter F0 */ 2828 #define TCF0_CTRLA _SFR_MEM8(0x0B00) 2829 #define TCF0_CTRLB _SFR_MEM8(0x0B01) 2830 #define TCF0_CTRLC _SFR_MEM8(0x0B02) 2831 #define TCF0_CTRLD _SFR_MEM8(0x0B03) 2832 #define TCF0_CTRLE _SFR_MEM8(0x0B04) 2833 #define TCF0_INTCTRLA _SFR_MEM8(0x0B06) 2834 #define TCF0_INTCTRLB _SFR_MEM8(0x0B07) 2835 #define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) 2836 #define TCF0_CTRLFSET _SFR_MEM8(0x0B09) 2837 #define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) 2838 #define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) 2839 #define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) 2840 #define TCF0_TEMP _SFR_MEM8(0x0B0F) 2841 #define TCF0_CNT _SFR_MEM16(0x0B20) 2842 #define TCF0_PER _SFR_MEM16(0x0B26) 2843 #define TCF0_CCA _SFR_MEM16(0x0B28) 2844 #define TCF0_CCB _SFR_MEM16(0x0B2A) 2845 #define TCF0_CCC _SFR_MEM16(0x0B2C) 2846 #define TCF0_CCD _SFR_MEM16(0x0B2E) 2847 #define TCF0_PERBUF _SFR_MEM16(0x0B36) 2848 #define TCF0_CCABUF _SFR_MEM16(0x0B38) 2849 #define TCF0_CCBBUF _SFR_MEM16(0x0B3A) 2850 #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) 2851 #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) 2852 2853 2854 2855 /*================== Bitfield Definitions ================== */ 2856 2857 /* XOCD - On-Chip Debug System */ 2858 /* OCD.OCDR1 bit masks and bit positions */ 2859 #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ 2860 #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ 2861 2862 2863 /* CPU - CPU */ 2864 /* CPU.CCP bit masks and bit positions */ 2865 #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ 2866 #define CPU_CCP_gp 0 /* CCP signature group position. */ 2867 #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ 2868 #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ 2869 #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ 2870 #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ 2871 #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ 2872 #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ 2873 #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ 2874 #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ 2875 #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ 2876 #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ 2877 #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ 2878 #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ 2879 #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ 2880 #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ 2881 #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ 2882 #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ 2883 2884 2885 /* CPU.SREG bit masks and bit positions */ 2886 #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ 2887 #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ 2888 2889 #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ 2890 #define CPU_T_bp 6 /* Transfer Bit bit position. */ 2891 2892 #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ 2893 #define CPU_H_bp 5 /* Half Carry Flag bit position. */ 2894 2895 #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ 2896 #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ 2897 2898 #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ 2899 #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ 2900 2901 #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ 2902 #define CPU_N_bp 2 /* Negative Flag bit position. */ 2903 2904 #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ 2905 #define CPU_Z_bp 1 /* Zero Flag bit position. */ 2906 2907 #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ 2908 #define CPU_C_bp 0 /* Carry Flag bit position. */ 2909 2910 2911 /* CLK - Clock System */ 2912 /* CLK.CTRL bit masks and bit positions */ 2913 #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ 2914 #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ 2915 #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ 2916 #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ 2917 #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ 2918 #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ 2919 #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ 2920 #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ 2921 2922 2923 /* CLK.PSCTRL bit masks and bit positions */ 2924 #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ 2925 #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ 2926 #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ 2927 #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ 2928 #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ 2929 #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ 2930 #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ 2931 #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ 2932 #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ 2933 #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ 2934 #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ 2935 #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ 2936 2937 #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ 2938 #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ 2939 #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ 2940 #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ 2941 #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ 2942 #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ 2943 2944 2945 /* CLK.LOCK bit masks and bit positions */ 2946 #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ 2947 #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ 2948 2949 2950 /* CLK.RTCCTRL bit masks and bit positions */ 2951 #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ 2952 #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ 2953 #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ 2954 #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ 2955 #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ 2956 #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ 2957 #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ 2958 #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ 2959 2960 #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ 2961 #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ 2962 2963 /* PR.PRGEN bit masks and bit positions */ 2964 #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ 2965 #define PR_RTC_bp 2 /* Real-time Counter bit position. */ 2966 2967 #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ 2968 #define PR_EVSYS_bp 1 /* Event System bit position. */ 2969 2970 /* PR.PRPA bit masks and bit positions */ 2971 #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ 2972 #define PR_ADC_bp 1 /* Port A ADC bit position. */ 2973 2974 #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ 2975 #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ 2976 2977 /* PR.PRPC bit masks and bit positions */ 2978 #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ 2979 #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ 2980 2981 #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ 2982 #define PR_USART0_bp 4 /* Port C USART0 bit position. */ 2983 2984 #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ 2985 #define PR_SPI_bp 3 /* Port C SPI bit position. */ 2986 2987 #define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ 2988 #define PR_HIRES_bp 2 /* Port C HIRES bit position. */ 2989 2990 #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ 2991 #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ 2992 2993 #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ 2994 #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ 2995 2996 /* PR.PRPD bit masks and bit positions */ 2997 /* PR_USART0_bm Predefined. */ 2998 /* PR_USART0_bp Predefined. */ 2999 3000 /* PR_SPI_bm Predefined. */ 3001 /* PR_SPI_bp Predefined. */ 3002 3003 /* PR_TC0_bm Predefined. */ 3004 /* PR_TC0_bp Predefined. */ 3005 3006 /* PR.PRPE bit masks and bit positions */ 3007 /* PR_TWI_bm Predefined. */ 3008 /* PR_TWI_bp Predefined. */ 3009 3010 /* PR_USART0_bm Predefined. */ 3011 /* PR_USART0_bp Predefined. */ 3012 3013 /* PR_TC0_bm Predefined. */ 3014 /* PR_TC0_bp Predefined. */ 3015 3016 /* PR.PRPF bit masks and bit positions */ 3017 /* PR_USART0_bm Predefined. */ 3018 /* PR_USART0_bp Predefined. */ 3019 3020 /* PR_TC0_bm Predefined. */ 3021 /* PR_TC0_bp Predefined. */ 3022 3023 /* SLEEP - Sleep Controller */ 3024 /* SLEEP.CTRL bit masks and bit positions */ 3025 #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ 3026 #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ 3027 #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ 3028 #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ 3029 #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ 3030 #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ 3031 #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ 3032 #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ 3033 3034 #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ 3035 #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ 3036 3037 3038 /* OSC - Oscillator */ 3039 /* OSC.CTRL bit masks and bit positions */ 3040 #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ 3041 #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ 3042 3043 #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ 3044 #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ 3045 3046 #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ 3047 #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ 3048 3049 #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ 3050 #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ 3051 3052 #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ 3053 #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ 3054 3055 3056 /* OSC.STATUS bit masks and bit positions */ 3057 #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ 3058 #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ 3059 3060 #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ 3061 #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ 3062 3063 #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ 3064 #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ 3065 3066 #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ 3067 #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ 3068 3069 #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ 3070 #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ 3071 3072 3073 /* OSC.XOSCCTRL bit masks and bit positions */ 3074 #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ 3075 #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ 3076 #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ 3077 #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ 3078 #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ 3079 #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ 3080 3081 #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ 3082 #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ 3083 3084 #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ 3085 #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ 3086 #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ 3087 #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ 3088 #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ 3089 #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ 3090 #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ 3091 #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ 3092 #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ 3093 #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ 3094 3095 3096 /* OSC.XOSCFAIL bit masks and bit positions */ 3097 #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ 3098 #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ 3099 3100 #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ 3101 #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ 3102 3103 3104 /* OSC.PLLCTRL bit masks and bit positions */ 3105 #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ 3106 #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ 3107 #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ 3108 #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ 3109 #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ 3110 #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ 3111 3112 #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ 3113 #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ 3114 #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ 3115 #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ 3116 #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ 3117 #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ 3118 #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ 3119 #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ 3120 #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ 3121 #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ 3122 #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ 3123 #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ 3124 3125 3126 /* OSC.DFLLCTRL bit masks and bit positions */ 3127 #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ 3128 #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ 3129 3130 #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ 3131 #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ 3132 3133 3134 /* DFLL - DFLL */ 3135 /* DFLL.CTRL bit masks and bit positions */ 3136 #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ 3137 #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ 3138 3139 3140 /* DFLL.CALA bit masks and bit positions */ 3141 #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ 3142 #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ 3143 #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ 3144 #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ 3145 #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ 3146 #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ 3147 #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ 3148 #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ 3149 #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ 3150 #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ 3151 #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ 3152 #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ 3153 #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ 3154 #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ 3155 #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ 3156 #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ 3157 3158 3159 /* DFLL.CALB bit masks and bit positions */ 3160 #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ 3161 #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ 3162 #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ 3163 #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ 3164 #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ 3165 #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ 3166 #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ 3167 #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ 3168 #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ 3169 #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ 3170 #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ 3171 #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ 3172 #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ 3173 #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ 3174 3175 3176 /* RST - Reset */ 3177 /* RST.STATUS bit masks and bit positions */ 3178 #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ 3179 #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ 3180 3181 #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ 3182 #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ 3183 3184 #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ 3185 #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ 3186 3187 #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ 3188 #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ 3189 3190 #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ 3191 #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ 3192 3193 #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ 3194 #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ 3195 3196 #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ 3197 #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ 3198 3199 3200 /* RST.CTRL bit masks and bit positions */ 3201 #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ 3202 #define RST_SWRST_bp 0 /* Software Reset bit position. */ 3203 3204 3205 /* WDT - Watch-Dog Timer */ 3206 /* WDT.CTRL bit masks and bit positions */ 3207 #define WDT_PER_gm 0x3C /* Period group mask. */ 3208 #define WDT_PER_gp 2 /* Period group position. */ 3209 #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ 3210 #define WDT_PER0_bp 2 /* Period bit 0 position. */ 3211 #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ 3212 #define WDT_PER1_bp 3 /* Period bit 1 position. */ 3213 #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ 3214 #define WDT_PER2_bp 4 /* Period bit 2 position. */ 3215 #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ 3216 #define WDT_PER3_bp 5 /* Period bit 3 position. */ 3217 3218 #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ 3219 #define WDT_ENABLE_bp 1 /* Enable bit position. */ 3220 3221 #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ 3222 #define WDT_CEN_bp 0 /* Change Enable bit position. */ 3223 3224 3225 /* WDT.WINCTRL bit masks and bit positions */ 3226 #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ 3227 #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ 3228 #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ 3229 #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ 3230 #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ 3231 #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ 3232 #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ 3233 #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ 3234 #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ 3235 #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ 3236 3237 #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ 3238 #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ 3239 3240 #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ 3241 #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ 3242 3243 3244 /* WDT.STATUS bit masks and bit positions */ 3245 #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ 3246 #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ 3247 3248 3249 /* MCU - MCU Control */ 3250 /* MCU.MCUCR bit masks and bit positions */ 3251 #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ 3252 #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ 3253 3254 3255 /* MCU.EVSYSLOCK bit masks and bit positions */ 3256 #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ 3257 #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ 3258 3259 #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ 3260 #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ 3261 3262 3263 /* MCU.AWEXLOCK bit masks and bit positions */ 3264 #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ 3265 #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ 3266 3267 #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ 3268 #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ 3269 3270 3271 /* PMIC - Programmable Multi-level Interrupt Controller */ 3272 /* PMIC.STATUS bit masks and bit positions */ 3273 #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ 3274 #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ 3275 3276 #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ 3277 #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ 3278 3279 #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ 3280 #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ 3281 3282 #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ 3283 #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ 3284 3285 3286 /* PMIC.CTRL bit masks and bit positions */ 3287 #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ 3288 #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ 3289 3290 #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ 3291 #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ 3292 3293 #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ 3294 #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ 3295 3296 #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ 3297 #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ 3298 3299 #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ 3300 #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ 3301 3302 3303 /* CRC - Cyclic Redundancy Checker */ 3304 /* CRC.CTRL bit masks and bit positions */ 3305 #define CRC_RESET_gm 0xC0 /* Reset group mask. */ 3306 #define CRC_RESET_gp 6 /* Reset group position. */ 3307 #define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ 3308 #define CRC_RESET0_bp 6 /* Reset bit 0 position. */ 3309 #define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ 3310 #define CRC_RESET1_bp 7 /* Reset bit 1 position. */ 3311 3312 #define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ 3313 #define CRC_CRC32_bp 5 /* CRC Mode bit position. */ 3314 3315 #define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ 3316 #define CRC_SOURCE_gp 0 /* Input Source group position. */ 3317 #define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ 3318 #define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ 3319 #define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ 3320 #define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ 3321 #define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ 3322 #define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ 3323 #define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ 3324 #define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ 3325 3326 /* CRC.STATUS bit masks and bit positions */ 3327 #define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ 3328 #define CRC_ZERO_bp 1 /* Zero detection bit position. */ 3329 3330 #define CRC_BUSY_bm 0x01 /* Busy bit mask. */ 3331 #define CRC_BUSY_bp 0 /* Busy bit position. */ 3332 3333 3334 /* EVSYS - Event System */ 3335 /* EVSYS.CH0MUX bit masks and bit positions */ 3336 #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ 3337 #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ 3338 #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ 3339 #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ 3340 #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ 3341 #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ 3342 #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ 3343 #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ 3344 #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ 3345 #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ 3346 #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ 3347 #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ 3348 #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ 3349 #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ 3350 #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ 3351 #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ 3352 #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ 3353 #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ 3354 3355 3356 /* EVSYS.CH1MUX bit masks and bit positions */ 3357 /* EVSYS_CHMUX_gm Predefined. */ 3358 /* EVSYS_CHMUX_gp Predefined. */ 3359 /* EVSYS_CHMUX0_bm Predefined. */ 3360 /* EVSYS_CHMUX0_bp Predefined. */ 3361 /* EVSYS_CHMUX1_bm Predefined. */ 3362 /* EVSYS_CHMUX1_bp Predefined. */ 3363 /* EVSYS_CHMUX2_bm Predefined. */ 3364 /* EVSYS_CHMUX2_bp Predefined. */ 3365 /* EVSYS_CHMUX3_bm Predefined. */ 3366 /* EVSYS_CHMUX3_bp Predefined. */ 3367 /* EVSYS_CHMUX4_bm Predefined. */ 3368 /* EVSYS_CHMUX4_bp Predefined. */ 3369 /* EVSYS_CHMUX5_bm Predefined. */ 3370 /* EVSYS_CHMUX5_bp Predefined. */ 3371 /* EVSYS_CHMUX6_bm Predefined. */ 3372 /* EVSYS_CHMUX6_bp Predefined. */ 3373 /* EVSYS_CHMUX7_bm Predefined. */ 3374 /* EVSYS_CHMUX7_bp Predefined. */ 3375 3376 3377 /* EVSYS.CH2MUX bit masks and bit positions */ 3378 /* EVSYS_CHMUX_gm Predefined. */ 3379 /* EVSYS_CHMUX_gp Predefined. */ 3380 /* EVSYS_CHMUX0_bm Predefined. */ 3381 /* EVSYS_CHMUX0_bp Predefined. */ 3382 /* EVSYS_CHMUX1_bm Predefined. */ 3383 /* EVSYS_CHMUX1_bp Predefined. */ 3384 /* EVSYS_CHMUX2_bm Predefined. */ 3385 /* EVSYS_CHMUX2_bp Predefined. */ 3386 /* EVSYS_CHMUX3_bm Predefined. */ 3387 /* EVSYS_CHMUX3_bp Predefined. */ 3388 /* EVSYS_CHMUX4_bm Predefined. */ 3389 /* EVSYS_CHMUX4_bp Predefined. */ 3390 /* EVSYS_CHMUX5_bm Predefined. */ 3391 /* EVSYS_CHMUX5_bp Predefined. */ 3392 /* EVSYS_CHMUX6_bm Predefined. */ 3393 /* EVSYS_CHMUX6_bp Predefined. */ 3394 /* EVSYS_CHMUX7_bm Predefined. */ 3395 /* EVSYS_CHMUX7_bp Predefined. */ 3396 3397 3398 /* EVSYS.CH3MUX bit masks and bit positions */ 3399 /* EVSYS_CHMUX_gm Predefined. */ 3400 /* EVSYS_CHMUX_gp Predefined. */ 3401 /* EVSYS_CHMUX0_bm Predefined. */ 3402 /* EVSYS_CHMUX0_bp Predefined. */ 3403 /* EVSYS_CHMUX1_bm Predefined. */ 3404 /* EVSYS_CHMUX1_bp Predefined. */ 3405 /* EVSYS_CHMUX2_bm Predefined. */ 3406 /* EVSYS_CHMUX2_bp Predefined. */ 3407 /* EVSYS_CHMUX3_bm Predefined. */ 3408 /* EVSYS_CHMUX3_bp Predefined. */ 3409 /* EVSYS_CHMUX4_bm Predefined. */ 3410 /* EVSYS_CHMUX4_bp Predefined. */ 3411 /* EVSYS_CHMUX5_bm Predefined. */ 3412 /* EVSYS_CHMUX5_bp Predefined. */ 3413 /* EVSYS_CHMUX6_bm Predefined. */ 3414 /* EVSYS_CHMUX6_bp Predefined. */ 3415 /* EVSYS_CHMUX7_bm Predefined. */ 3416 /* EVSYS_CHMUX7_bp Predefined. */ 3417 3418 3419 /* EVSYS.CH0CTRL bit masks and bit positions */ 3420 #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ 3421 #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ 3422 #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ 3423 #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ 3424 #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ 3425 #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ 3426 3427 #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ 3428 #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ 3429 3430 #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ 3431 #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ 3432 3433 #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ 3434 #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ 3435 #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ 3436 #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ 3437 #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ 3438 #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ 3439 #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ 3440 #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ 3441 3442 3443 /* EVSYS.CH1CTRL bit masks and bit positions */ 3444 /* EVSYS_DIGFILT_gm Predefined. */ 3445 /* EVSYS_DIGFILT_gp Predefined. */ 3446 /* EVSYS_DIGFILT0_bm Predefined. */ 3447 /* EVSYS_DIGFILT0_bp Predefined. */ 3448 /* EVSYS_DIGFILT1_bm Predefined. */ 3449 /* EVSYS_DIGFILT1_bp Predefined. */ 3450 /* EVSYS_DIGFILT2_bm Predefined. */ 3451 /* EVSYS_DIGFILT2_bp Predefined. */ 3452 3453 3454 /* EVSYS.CH2CTRL bit masks and bit positions */ 3455 /* EVSYS_QDIRM_gm Predefined. */ 3456 /* EVSYS_QDIRM_gp Predefined. */ 3457 /* EVSYS_QDIRM0_bm Predefined. */ 3458 /* EVSYS_QDIRM0_bp Predefined. */ 3459 /* EVSYS_QDIRM1_bm Predefined. */ 3460 /* EVSYS_QDIRM1_bp Predefined. */ 3461 3462 /* EVSYS_QDIEN_bm Predefined. */ 3463 /* EVSYS_QDIEN_bp Predefined. */ 3464 3465 /* EVSYS_QDEN_bm Predefined. */ 3466 /* EVSYS_QDEN_bp Predefined. */ 3467 3468 /* EVSYS_DIGFILT_gm Predefined. */ 3469 /* EVSYS_DIGFILT_gp Predefined. */ 3470 /* EVSYS_DIGFILT0_bm Predefined. */ 3471 /* EVSYS_DIGFILT0_bp Predefined. */ 3472 /* EVSYS_DIGFILT1_bm Predefined. */ 3473 /* EVSYS_DIGFILT1_bp Predefined. */ 3474 /* EVSYS_DIGFILT2_bm Predefined. */ 3475 /* EVSYS_DIGFILT2_bp Predefined. */ 3476 3477 3478 /* EVSYS.CH3CTRL bit masks and bit positions */ 3479 /* EVSYS_DIGFILT_gm Predefined. */ 3480 /* EVSYS_DIGFILT_gp Predefined. */ 3481 /* EVSYS_DIGFILT0_bm Predefined. */ 3482 /* EVSYS_DIGFILT0_bp Predefined. */ 3483 /* EVSYS_DIGFILT1_bm Predefined. */ 3484 /* EVSYS_DIGFILT1_bp Predefined. */ 3485 /* EVSYS_DIGFILT2_bm Predefined. */ 3486 /* EVSYS_DIGFILT2_bp Predefined. */ 3487 3488 3489 /* NVM - Non Volatile Memory Controller */ 3490 /* NVM.CMD bit masks and bit positions */ 3491 #define NVM_CMD_gm 0xFF /* Command group mask. */ 3492 #define NVM_CMD_gp 0 /* Command group position. */ 3493 #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ 3494 #define NVM_CMD0_bp 0 /* Command bit 0 position. */ 3495 #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ 3496 #define NVM_CMD1_bp 1 /* Command bit 1 position. */ 3497 #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ 3498 #define NVM_CMD2_bp 2 /* Command bit 2 position. */ 3499 #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ 3500 #define NVM_CMD3_bp 3 /* Command bit 3 position. */ 3501 #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ 3502 #define NVM_CMD4_bp 4 /* Command bit 4 position. */ 3503 #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ 3504 #define NVM_CMD5_bp 5 /* Command bit 5 position. */ 3505 #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ 3506 #define NVM_CMD6_bp 6 /* Command bit 6 position. */ 3507 #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ 3508 #define NVM_CMD7_bp 7 /* Command bit 7 position. */ 3509 3510 3511 /* NVM.CTRLA bit masks and bit positions */ 3512 #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ 3513 #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ 3514 3515 3516 /* NVM.CTRLB bit masks and bit positions */ 3517 #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ 3518 #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ 3519 3520 #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ 3521 #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ 3522 3523 #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ 3524 #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ 3525 3526 #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ 3527 #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ 3528 3529 3530 /* NVM.INTCTRL bit masks and bit positions */ 3531 #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ 3532 #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ 3533 #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ 3534 #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ 3535 #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ 3536 #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ 3537 3538 #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ 3539 #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ 3540 #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ 3541 #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ 3542 #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ 3543 #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ 3544 3545 3546 /* NVM.STATUS bit masks and bit positions */ 3547 #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ 3548 #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ 3549 3550 #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ 3551 #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ 3552 3553 #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ 3554 #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ 3555 3556 #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ 3557 #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ 3558 3559 3560 /* NVM.LOCKBITS bit masks and bit positions */ 3561 #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ 3562 #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ 3563 #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ 3564 #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ 3565 #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ 3566 #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ 3567 3568 #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ 3569 #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ 3570 #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ 3571 #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ 3572 #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ 3573 #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ 3574 3575 #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ 3576 #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ 3577 #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ 3578 #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ 3579 #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ 3580 #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ 3581 3582 #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ 3583 #define NVM_LB_gp 0 /* Lock Bits group position. */ 3584 #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ 3585 #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ 3586 #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ 3587 #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ 3588 3589 3590 /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ 3591 #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ 3592 #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ 3593 #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ 3594 #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ 3595 #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ 3596 #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ 3597 3598 #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ 3599 #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ 3600 #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ 3601 #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ 3602 #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ 3603 #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ 3604 3605 #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ 3606 #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ 3607 #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ 3608 #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ 3609 #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ 3610 #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ 3611 3612 #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ 3613 #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ 3614 #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ 3615 #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ 3616 #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ 3617 #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ 3618 3619 3620 /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ 3621 #define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ 3622 #define NVM_FUSES_USERID_gp 0 /* User ID group position. */ 3623 #define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ 3624 #define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ 3625 #define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ 3626 #define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ 3627 #define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ 3628 #define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ 3629 #define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ 3630 #define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ 3631 #define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ 3632 #define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ 3633 #define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ 3634 #define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ 3635 #define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ 3636 #define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ 3637 #define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ 3638 #define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ 3639 3640 3641 /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ 3642 #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ 3643 #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ 3644 #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ 3645 #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ 3646 #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ 3647 #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ 3648 #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ 3649 #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ 3650 #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ 3651 #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ 3652 3653 #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ 3654 #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ 3655 #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ 3656 #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ 3657 #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ 3658 #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ 3659 #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ 3660 #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ 3661 #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ 3662 #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ 3663 3664 3665 /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ 3666 #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ 3667 #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ 3668 3669 #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ 3670 #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ 3671 3672 #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ 3673 #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ 3674 #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ 3675 #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ 3676 #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ 3677 #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ 3678 3679 3680 /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ 3681 #define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ 3682 #define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ 3683 3684 #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ 3685 #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ 3686 #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ 3687 #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ 3688 #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ 3689 #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ 3690 3691 #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ 3692 #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ 3693 3694 3695 /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ 3696 #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ 3697 #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ 3698 #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ 3699 #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ 3700 #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ 3701 #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ 3702 3703 #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ 3704 #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ 3705 3706 #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ 3707 #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ 3708 #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ 3709 #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ 3710 #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ 3711 #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ 3712 #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ 3713 #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ 3714 3715 3716 /* AC - Analog Comparator */ 3717 /* AC.AC0CTRL bit masks and bit positions */ 3718 #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ 3719 #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ 3720 #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ 3721 #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ 3722 #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ 3723 #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ 3724 3725 #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ 3726 #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ 3727 #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ 3728 #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ 3729 #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ 3730 #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ 3731 3732 #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ 3733 #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ 3734 3735 #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ 3736 #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ 3737 #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ 3738 #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ 3739 #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ 3740 #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ 3741 3742 #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ 3743 #define AC_ENABLE_bp 0 /* Enable bit position. */ 3744 3745 3746 /* AC.AC1CTRL bit masks and bit positions */ 3747 /* AC_INTMODE_gm Predefined. */ 3748 /* AC_INTMODE_gp Predefined. */ 3749 /* AC_INTMODE0_bm Predefined. */ 3750 /* AC_INTMODE0_bp Predefined. */ 3751 /* AC_INTMODE1_bm Predefined. */ 3752 /* AC_INTMODE1_bp Predefined. */ 3753 3754 /* AC_INTLVL_gm Predefined. */ 3755 /* AC_INTLVL_gp Predefined. */ 3756 /* AC_INTLVL0_bm Predefined. */ 3757 /* AC_INTLVL0_bp Predefined. */ 3758 /* AC_INTLVL1_bm Predefined. */ 3759 /* AC_INTLVL1_bp Predefined. */ 3760 3761 /* AC_HSMODE_bm Predefined. */ 3762 /* AC_HSMODE_bp Predefined. */ 3763 3764 /* AC_HYSMODE_gm Predefined. */ 3765 /* AC_HYSMODE_gp Predefined. */ 3766 /* AC_HYSMODE0_bm Predefined. */ 3767 /* AC_HYSMODE0_bp Predefined. */ 3768 /* AC_HYSMODE1_bm Predefined. */ 3769 /* AC_HYSMODE1_bp Predefined. */ 3770 3771 /* AC_ENABLE_bm Predefined. */ 3772 /* AC_ENABLE_bp Predefined. */ 3773 3774 3775 /* AC.AC0MUXCTRL bit masks and bit positions */ 3776 #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ 3777 #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ 3778 #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ 3779 #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ 3780 #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ 3781 #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ 3782 #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ 3783 #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ 3784 3785 #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ 3786 #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ 3787 #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ 3788 #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ 3789 #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ 3790 #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ 3791 #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ 3792 #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ 3793 3794 3795 /* AC.AC1MUXCTRL bit masks and bit positions */ 3796 /* AC_MUXPOS_gm Predefined. */ 3797 /* AC_MUXPOS_gp Predefined. */ 3798 /* AC_MUXPOS0_bm Predefined. */ 3799 /* AC_MUXPOS0_bp Predefined. */ 3800 /* AC_MUXPOS1_bm Predefined. */ 3801 /* AC_MUXPOS1_bp Predefined. */ 3802 /* AC_MUXPOS2_bm Predefined. */ 3803 /* AC_MUXPOS2_bp Predefined. */ 3804 3805 /* AC_MUXNEG_gm Predefined. */ 3806 /* AC_MUXNEG_gp Predefined. */ 3807 /* AC_MUXNEG0_bm Predefined. */ 3808 /* AC_MUXNEG0_bp Predefined. */ 3809 /* AC_MUXNEG1_bm Predefined. */ 3810 /* AC_MUXNEG1_bp Predefined. */ 3811 /* AC_MUXNEG2_bm Predefined. */ 3812 /* AC_MUXNEG2_bp Predefined. */ 3813 3814 3815 /* AC.CTRLA bit masks and bit positions */ 3816 #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ 3817 #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ 3818 3819 3820 /* AC.CTRLB bit masks and bit positions */ 3821 #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ 3822 #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ 3823 #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ 3824 #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ 3825 #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ 3826 #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ 3827 #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ 3828 #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ 3829 #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ 3830 #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ 3831 #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ 3832 #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ 3833 #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ 3834 #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ 3835 3836 3837 /* AC.WINCTRL bit masks and bit positions */ 3838 #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ 3839 #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ 3840 3841 #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ 3842 #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ 3843 #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ 3844 #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ 3845 #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ 3846 #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ 3847 3848 #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ 3849 #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ 3850 #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ 3851 #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ 3852 #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ 3853 #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ 3854 3855 3856 /* AC.STATUS bit masks and bit positions */ 3857 #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ 3858 #define AC_WSTATE_gp 6 /* Window Mode State group position. */ 3859 #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ 3860 #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ 3861 #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ 3862 #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ 3863 3864 #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ 3865 #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ 3866 3867 #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ 3868 #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ 3869 3870 #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ 3871 #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ 3872 3873 #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ 3874 #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ 3875 3876 #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ 3877 #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ 3878 3879 3880 /* ADC - Analog/Digital Converter */ 3881 /* ADC_CH.CTRL bit masks and bit positions */ 3882 #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ 3883 #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ 3884 3885 #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ 3886 #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ 3887 #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ 3888 #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ 3889 #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ 3890 #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ 3891 #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ 3892 #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ 3893 3894 #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ 3895 #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ 3896 #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ 3897 #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ 3898 #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ 3899 #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ 3900 3901 3902 /* ADC_CH.MUXCTRL bit masks and bit positions */ 3903 #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ 3904 #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ 3905 #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ 3906 #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ 3907 #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ 3908 #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ 3909 #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ 3910 #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ 3911 #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ 3912 #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ 3913 3914 #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ 3915 #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ 3916 #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ 3917 #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ 3918 #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ 3919 #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ 3920 3921 3922 /* ADC_CH.INTCTRL bit masks and bit positions */ 3923 #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ 3924 #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ 3925 #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ 3926 #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ 3927 #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ 3928 #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ 3929 3930 #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ 3931 #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ 3932 #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ 3933 #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ 3934 #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ 3935 #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ 3936 3937 3938 /* ADC_CH.INTFLAGS bit masks and bit positions */ 3939 #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ 3940 #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ 3941 3942 3943 /* ADC.CTRLA bit masks and bit positions */ 3944 #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ 3945 #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ 3946 3947 #define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ 3948 #define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ 3949 3950 #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ 3951 #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ 3952 3953 3954 /* ADC.CTRLB bit masks and bit positions */ 3955 #define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ 3956 #define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ 3957 #define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ 3958 #define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ 3959 #define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ 3960 #define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ 3961 3962 #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ 3963 #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ 3964 3965 #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ 3966 #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ 3967 3968 #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ 3969 #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ 3970 #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ 3971 #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ 3972 #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ 3973 #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ 3974 3975 3976 /* ADC.REFCTRL bit masks and bit positions */ 3977 #define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ 3978 #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ 3979 #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ 3980 #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ 3981 #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ 3982 #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ 3983 #define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ 3984 #define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ 3985 3986 #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ 3987 #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ 3988 3989 #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ 3990 #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ 3991 3992 3993 /* ADC.EVCTRL bit masks and bit positions */ 3994 #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ 3995 #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ 3996 #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ 3997 #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ 3998 #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ 3999 #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ 4000 #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ 4001 #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ 4002 4003 #define ADC_EVACT_bm 0x01 /* Event Action Select bit mask. */ 4004 #define ADC_EVACT_bp 0 /* Event Action Select bit position. */ 4005 4006 4007 /* ADC.PRESCALER bit masks and bit positions */ 4008 #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ 4009 #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ 4010 #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ 4011 #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ 4012 #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ 4013 #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ 4014 #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ 4015 #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ 4016 4017 4018 /* ADC.INTFLAGS bit masks and bit positions */ 4019 #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ 4020 #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ 4021 4022 4023 /* RTC - Real-Time Clounter */ 4024 /* RTC.CTRL bit masks and bit positions */ 4025 #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ 4026 #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ 4027 #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ 4028 #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ 4029 #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ 4030 #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ 4031 #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ 4032 #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ 4033 4034 4035 /* RTC.STATUS bit masks and bit positions */ 4036 #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ 4037 #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ 4038 4039 4040 /* RTC.INTCTRL bit masks and bit positions */ 4041 #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ 4042 #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ 4043 #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ 4044 #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ 4045 #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ 4046 #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ 4047 4048 #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ 4049 #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ 4050 #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ 4051 #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ 4052 #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ 4053 #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ 4054 4055 4056 /* RTC.INTFLAGS bit masks and bit positions */ 4057 #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ 4058 #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ 4059 4060 #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 4061 #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 4062 4063 4064 /* EBI - External Bus Interface */ 4065 /* EBI_CS.CTRLA bit masks and bit positions */ 4066 #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ 4067 #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ 4068 #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ 4069 #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ 4070 #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ 4071 #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ 4072 #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ 4073 #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ 4074 #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ 4075 #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ 4076 #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ 4077 #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ 4078 4079 #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ 4080 #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ 4081 #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ 4082 #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ 4083 #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ 4084 #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ 4085 4086 4087 /* EBI_CS.CTRLB bit masks and bit positions */ 4088 #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ 4089 #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ 4090 #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ 4091 #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ 4092 #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ 4093 #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ 4094 #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ 4095 #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ 4096 4097 #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ 4098 #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ 4099 4100 #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ 4101 #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ 4102 4103 #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ 4104 #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ 4105 #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ 4106 #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ 4107 #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ 4108 #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ 4109 4110 4111 /* EBI.CTRL bit masks and bit positions */ 4112 #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ 4113 #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ 4114 #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ 4115 #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ 4116 #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ 4117 #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ 4118 4119 #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ 4120 #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ 4121 #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ 4122 #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ 4123 #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ 4124 #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ 4125 4126 #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ 4127 #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ 4128 #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ 4129 #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ 4130 #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ 4131 #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ 4132 4133 #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ 4134 #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ 4135 #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ 4136 #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ 4137 #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ 4138 #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ 4139 4140 4141 /* EBI.SDRAMCTRLA bit masks and bit positions */ 4142 #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ 4143 #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ 4144 4145 #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ 4146 #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ 4147 4148 #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ 4149 #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ 4150 #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ 4151 #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ 4152 #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ 4153 #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ 4154 4155 4156 /* EBI.SDRAMCTRLB bit masks and bit positions */ 4157 #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ 4158 #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ 4159 #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ 4160 #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ 4161 #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ 4162 #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ 4163 4164 #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ 4165 #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ 4166 #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ 4167 #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ 4168 #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ 4169 #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ 4170 #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ 4171 #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ 4172 4173 #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ 4174 #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ 4175 #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ 4176 #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ 4177 #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ 4178 #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ 4179 #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ 4180 #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ 4181 4182 4183 /* EBI.SDRAMCTRLC bit masks and bit positions */ 4184 #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ 4185 #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ 4186 #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ 4187 #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ 4188 #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ 4189 #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ 4190 4191 #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ 4192 #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ 4193 #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ 4194 #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ 4195 #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ 4196 #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ 4197 #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ 4198 #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ 4199 4200 #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ 4201 #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ 4202 #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ 4203 #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ 4204 #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ 4205 #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ 4206 #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ 4207 #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ 4208 4209 4210 /* TWI - Two-Wire Interface */ 4211 /* TWI_MASTER.CTRLA bit masks and bit positions */ 4212 #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ 4213 #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ 4214 #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ 4215 #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ 4216 #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ 4217 #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ 4218 4219 #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ 4220 #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ 4221 4222 #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ 4223 #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ 4224 4225 #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ 4226 #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ 4227 4228 4229 /* TWI_MASTER.CTRLB bit masks and bit positions */ 4230 #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ 4231 #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ 4232 #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ 4233 #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ 4234 #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ 4235 #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ 4236 4237 #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ 4238 #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ 4239 4240 #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ 4241 #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ 4242 4243 4244 /* TWI_MASTER.CTRLC bit masks and bit positions */ 4245 #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ 4246 #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ 4247 4248 #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ 4249 #define TWI_MASTER_CMD_gp 0 /* Command group position. */ 4250 #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ 4251 #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ 4252 #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ 4253 #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ 4254 4255 4256 /* TWI_MASTER.STATUS bit masks and bit positions */ 4257 #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ 4258 #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ 4259 4260 #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ 4261 #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ 4262 4263 #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ 4264 #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ 4265 4266 #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ 4267 #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ 4268 4269 #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ 4270 #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ 4271 4272 #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ 4273 #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ 4274 4275 #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ 4276 #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ 4277 #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ 4278 #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ 4279 #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ 4280 #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ 4281 4282 4283 /* TWI_SLAVE.CTRLA bit masks and bit positions */ 4284 #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ 4285 #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ 4286 #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ 4287 #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ 4288 #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ 4289 #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ 4290 4291 #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ 4292 #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ 4293 4294 #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ 4295 #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ 4296 4297 #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ 4298 #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ 4299 4300 #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ 4301 #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ 4302 4303 #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ 4304 #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ 4305 4306 #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ 4307 #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ 4308 4309 4310 /* TWI_SLAVE.CTRLB bit masks and bit positions */ 4311 #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ 4312 #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ 4313 4314 #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ 4315 #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ 4316 #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ 4317 #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ 4318 #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ 4319 #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ 4320 4321 4322 /* TWI_SLAVE.STATUS bit masks and bit positions */ 4323 #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ 4324 #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ 4325 4326 #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ 4327 #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ 4328 4329 #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ 4330 #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ 4331 4332 #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ 4333 #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ 4334 4335 #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ 4336 #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ 4337 4338 #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ 4339 #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ 4340 4341 #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ 4342 #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ 4343 4344 #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ 4345 #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ 4346 4347 4348 /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ 4349 #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ 4350 #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ 4351 #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ 4352 #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ 4353 #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ 4354 #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ 4355 #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ 4356 #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ 4357 #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ 4358 #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ 4359 #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ 4360 #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ 4361 #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ 4362 #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ 4363 #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ 4364 #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ 4365 4366 #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ 4367 #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ 4368 4369 4370 /* TWI.CTRL bit masks and bit positions */ 4371 #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ 4372 #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ 4373 4374 #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ 4375 #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ 4376 4377 4378 /* PORT - Port Configuration */ 4379 /* PORTCFG.VPCTRLA bit masks and bit positions */ 4380 #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ 4381 #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ 4382 #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ 4383 #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ 4384 #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ 4385 #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ 4386 #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ 4387 #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ 4388 #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ 4389 #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ 4390 4391 #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ 4392 #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ 4393 #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ 4394 #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ 4395 #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ 4396 #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ 4397 #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ 4398 #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ 4399 #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ 4400 #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ 4401 4402 4403 /* PORTCFG.VPCTRLB bit masks and bit positions */ 4404 #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ 4405 #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ 4406 #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ 4407 #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ 4408 #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ 4409 #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ 4410 #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ 4411 #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ 4412 #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ 4413 #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ 4414 4415 #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ 4416 #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ 4417 #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ 4418 #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ 4419 #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ 4420 #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ 4421 #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ 4422 #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ 4423 #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ 4424 #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ 4425 4426 4427 /* PORTCFG.CLKEVOUT bit masks and bit positions */ 4428 #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ 4429 #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ 4430 #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ 4431 #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ 4432 #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ 4433 #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ 4434 4435 #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ 4436 #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ 4437 #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ 4438 #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ 4439 #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ 4440 #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ 4441 4442 4443 /* VPORT.INTFLAGS bit masks and bit positions */ 4444 #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ 4445 #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ 4446 4447 #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ 4448 #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ 4449 4450 4451 /* PORT.INTCTRL bit masks and bit positions */ 4452 #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ 4453 #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ 4454 #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ 4455 #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ 4456 #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ 4457 #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ 4458 4459 #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ 4460 #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ 4461 #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ 4462 #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ 4463 #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ 4464 #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ 4465 4466 4467 /* PORT.INTFLAGS bit masks and bit positions */ 4468 #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ 4469 #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ 4470 4471 #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ 4472 #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ 4473 4474 4475 /* PORT.PIN0CTRL bit masks and bit positions */ 4476 #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ 4477 #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ 4478 4479 #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ 4480 #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ 4481 4482 #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ 4483 #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ 4484 #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ 4485 #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ 4486 #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ 4487 #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ 4488 #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ 4489 #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ 4490 4491 #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ 4492 #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ 4493 #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ 4494 #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ 4495 #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ 4496 #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ 4497 #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ 4498 #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ 4499 4500 4501 /* PORT.PIN1CTRL bit masks and bit positions */ 4502 /* PORT_SRLEN_bm Predefined. */ 4503 /* PORT_SRLEN_bp Predefined. */ 4504 4505 /* PORT_INVEN_bm Predefined. */ 4506 /* PORT_INVEN_bp Predefined. */ 4507 4508 /* PORT_OPC_gm Predefined. */ 4509 /* PORT_OPC_gp Predefined. */ 4510 /* PORT_OPC0_bm Predefined. */ 4511 /* PORT_OPC0_bp Predefined. */ 4512 /* PORT_OPC1_bm Predefined. */ 4513 /* PORT_OPC1_bp Predefined. */ 4514 /* PORT_OPC2_bm Predefined. */ 4515 /* PORT_OPC2_bp Predefined. */ 4516 4517 /* PORT_ISC_gm Predefined. */ 4518 /* PORT_ISC_gp Predefined. */ 4519 /* PORT_ISC0_bm Predefined. */ 4520 /* PORT_ISC0_bp Predefined. */ 4521 /* PORT_ISC1_bm Predefined. */ 4522 /* PORT_ISC1_bp Predefined. */ 4523 /* PORT_ISC2_bm Predefined. */ 4524 /* PORT_ISC2_bp Predefined. */ 4525 4526 4527 /* PORT.PIN2CTRL bit masks and bit positions */ 4528 /* PORT_SRLEN_bm Predefined. */ 4529 /* PORT_SRLEN_bp Predefined. */ 4530 4531 /* PORT_INVEN_bm Predefined. */ 4532 /* PORT_INVEN_bp Predefined. */ 4533 4534 /* PORT_OPC_gm Predefined. */ 4535 /* PORT_OPC_gp Predefined. */ 4536 /* PORT_OPC0_bm Predefined. */ 4537 /* PORT_OPC0_bp Predefined. */ 4538 /* PORT_OPC1_bm Predefined. */ 4539 /* PORT_OPC1_bp Predefined. */ 4540 /* PORT_OPC2_bm Predefined. */ 4541 /* PORT_OPC2_bp Predefined. */ 4542 4543 /* PORT_ISC_gm Predefined. */ 4544 /* PORT_ISC_gp Predefined. */ 4545 /* PORT_ISC0_bm Predefined. */ 4546 /* PORT_ISC0_bp Predefined. */ 4547 /* PORT_ISC1_bm Predefined. */ 4548 /* PORT_ISC1_bp Predefined. */ 4549 /* PORT_ISC2_bm Predefined. */ 4550 /* PORT_ISC2_bp Predefined. */ 4551 4552 4553 /* PORT.PIN3CTRL bit masks and bit positions */ 4554 /* PORT_SRLEN_bm Predefined. */ 4555 /* PORT_SRLEN_bp Predefined. */ 4556 4557 /* PORT_INVEN_bm Predefined. */ 4558 /* PORT_INVEN_bp Predefined. */ 4559 4560 /* PORT_OPC_gm Predefined. */ 4561 /* PORT_OPC_gp Predefined. */ 4562 /* PORT_OPC0_bm Predefined. */ 4563 /* PORT_OPC0_bp Predefined. */ 4564 /* PORT_OPC1_bm Predefined. */ 4565 /* PORT_OPC1_bp Predefined. */ 4566 /* PORT_OPC2_bm Predefined. */ 4567 /* PORT_OPC2_bp Predefined. */ 4568 4569 /* PORT_ISC_gm Predefined. */ 4570 /* PORT_ISC_gp Predefined. */ 4571 /* PORT_ISC0_bm Predefined. */ 4572 /* PORT_ISC0_bp Predefined. */ 4573 /* PORT_ISC1_bm Predefined. */ 4574 /* PORT_ISC1_bp Predefined. */ 4575 /* PORT_ISC2_bm Predefined. */ 4576 /* PORT_ISC2_bp Predefined. */ 4577 4578 4579 /* PORT.PIN4CTRL bit masks and bit positions */ 4580 /* PORT_SRLEN_bm Predefined. */ 4581 /* PORT_SRLEN_bp Predefined. */ 4582 4583 /* PORT_INVEN_bm Predefined. */ 4584 /* PORT_INVEN_bp Predefined. */ 4585 4586 /* PORT_OPC_gm Predefined. */ 4587 /* PORT_OPC_gp Predefined. */ 4588 /* PORT_OPC0_bm Predefined. */ 4589 /* PORT_OPC0_bp Predefined. */ 4590 /* PORT_OPC1_bm Predefined. */ 4591 /* PORT_OPC1_bp Predefined. */ 4592 /* PORT_OPC2_bm Predefined. */ 4593 /* PORT_OPC2_bp Predefined. */ 4594 4595 /* PORT_ISC_gm Predefined. */ 4596 /* PORT_ISC_gp Predefined. */ 4597 /* PORT_ISC0_bm Predefined. */ 4598 /* PORT_ISC0_bp Predefined. */ 4599 /* PORT_ISC1_bm Predefined. */ 4600 /* PORT_ISC1_bp Predefined. */ 4601 /* PORT_ISC2_bm Predefined. */ 4602 /* PORT_ISC2_bp Predefined. */ 4603 4604 4605 /* PORT.PIN5CTRL bit masks and bit positions */ 4606 /* PORT_SRLEN_bm Predefined. */ 4607 /* PORT_SRLEN_bp Predefined. */ 4608 4609 /* PORT_INVEN_bm Predefined. */ 4610 /* PORT_INVEN_bp Predefined. */ 4611 4612 /* PORT_OPC_gm Predefined. */ 4613 /* PORT_OPC_gp Predefined. */ 4614 /* PORT_OPC0_bm Predefined. */ 4615 /* PORT_OPC0_bp Predefined. */ 4616 /* PORT_OPC1_bm Predefined. */ 4617 /* PORT_OPC1_bp Predefined. */ 4618 /* PORT_OPC2_bm Predefined. */ 4619 /* PORT_OPC2_bp Predefined. */ 4620 4621 /* PORT_ISC_gm Predefined. */ 4622 /* PORT_ISC_gp Predefined. */ 4623 /* PORT_ISC0_bm Predefined. */ 4624 /* PORT_ISC0_bp Predefined. */ 4625 /* PORT_ISC1_bm Predefined. */ 4626 /* PORT_ISC1_bp Predefined. */ 4627 /* PORT_ISC2_bm Predefined. */ 4628 /* PORT_ISC2_bp Predefined. */ 4629 4630 4631 /* PORT.PIN6CTRL bit masks and bit positions */ 4632 /* PORT_SRLEN_bm Predefined. */ 4633 /* PORT_SRLEN_bp Predefined. */ 4634 4635 /* PORT_INVEN_bm Predefined. */ 4636 /* PORT_INVEN_bp Predefined. */ 4637 4638 /* PORT_OPC_gm Predefined. */ 4639 /* PORT_OPC_gp Predefined. */ 4640 /* PORT_OPC0_bm Predefined. */ 4641 /* PORT_OPC0_bp Predefined. */ 4642 /* PORT_OPC1_bm Predefined. */ 4643 /* PORT_OPC1_bp Predefined. */ 4644 /* PORT_OPC2_bm Predefined. */ 4645 /* PORT_OPC2_bp Predefined. */ 4646 4647 /* PORT_ISC_gm Predefined. */ 4648 /* PORT_ISC_gp Predefined. */ 4649 /* PORT_ISC0_bm Predefined. */ 4650 /* PORT_ISC0_bp Predefined. */ 4651 /* PORT_ISC1_bm Predefined. */ 4652 /* PORT_ISC1_bp Predefined. */ 4653 /* PORT_ISC2_bm Predefined. */ 4654 /* PORT_ISC2_bp Predefined. */ 4655 4656 4657 /* PORT.PIN7CTRL bit masks and bit positions */ 4658 /* PORT_SRLEN_bm Predefined. */ 4659 /* PORT_SRLEN_bp Predefined. */ 4660 4661 /* PORT_INVEN_bm Predefined. */ 4662 /* PORT_INVEN_bp Predefined. */ 4663 4664 /* PORT_OPC_gm Predefined. */ 4665 /* PORT_OPC_gp Predefined. */ 4666 /* PORT_OPC0_bm Predefined. */ 4667 /* PORT_OPC0_bp Predefined. */ 4668 /* PORT_OPC1_bm Predefined. */ 4669 /* PORT_OPC1_bp Predefined. */ 4670 /* PORT_OPC2_bm Predefined. */ 4671 /* PORT_OPC2_bp Predefined. */ 4672 4673 /* PORT_ISC_gm Predefined. */ 4674 /* PORT_ISC_gp Predefined. */ 4675 /* PORT_ISC0_bm Predefined. */ 4676 /* PORT_ISC0_bp Predefined. */ 4677 /* PORT_ISC1_bm Predefined. */ 4678 /* PORT_ISC1_bp Predefined. */ 4679 /* PORT_ISC2_bm Predefined. */ 4680 /* PORT_ISC2_bp Predefined. */ 4681 4682 4683 /* TC - 16-bit Timer/Counter With PWM */ 4684 /* TC0.CTRLA bit masks and bit positions */ 4685 #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 4686 #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ 4687 #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 4688 #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 4689 #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 4690 #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 4691 #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 4692 #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 4693 #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 4694 #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 4695 4696 4697 /* TC0.CTRLB bit masks and bit positions */ 4698 #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ 4699 #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ 4700 4701 #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ 4702 #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ 4703 4704 #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ 4705 #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ 4706 4707 #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ 4708 #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ 4709 4710 #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ 4711 #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ 4712 #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ 4713 #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ 4714 #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ 4715 #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ 4716 #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ 4717 #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ 4718 4719 4720 /* TC0.CTRLC bit masks and bit positions */ 4721 #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ 4722 #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ 4723 4724 #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ 4725 #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ 4726 4727 #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ 4728 #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ 4729 4730 #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ 4731 #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ 4732 4733 4734 /* TC0.CTRLD bit masks and bit positions */ 4735 #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ 4736 #define TC0_EVACT_gp 5 /* Event Action group position. */ 4737 #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ 4738 #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ 4739 #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ 4740 #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ 4741 #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ 4742 #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ 4743 4744 #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ 4745 #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ 4746 4747 #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ 4748 #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ 4749 #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ 4750 #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ 4751 #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ 4752 #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ 4753 #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ 4754 #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ 4755 #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ 4756 #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ 4757 4758 4759 /* TC0.CTRLE bit masks and bit positions */ 4760 #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ 4761 #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ 4762 4763 4764 /* TC0.INTCTRLA bit masks and bit positions */ 4765 #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ 4766 #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ 4767 #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ 4768 #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ 4769 #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ 4770 #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ 4771 4772 #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ 4773 #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ 4774 #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ 4775 #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ 4776 #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ 4777 #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ 4778 4779 4780 /* TC0.INTCTRLB bit masks and bit positions */ 4781 #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ 4782 #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ 4783 #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ 4784 #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ 4785 #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ 4786 #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ 4787 4788 #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ 4789 #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ 4790 #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ 4791 #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ 4792 #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ 4793 #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ 4794 4795 #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ 4796 #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ 4797 #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ 4798 #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ 4799 #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ 4800 #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ 4801 4802 #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ 4803 #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ 4804 #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ 4805 #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ 4806 #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ 4807 #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ 4808 4809 4810 /* TC0.CTRLFCLR bit masks and bit positions */ 4811 #define TC0_CMD_gm 0x0C /* Command group mask. */ 4812 #define TC0_CMD_gp 2 /* Command group position. */ 4813 #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ 4814 #define TC0_CMD0_bp 2 /* Command bit 0 position. */ 4815 #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ 4816 #define TC0_CMD1_bp 3 /* Command bit 1 position. */ 4817 4818 #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ 4819 #define TC0_LUPD_bp 1 /* Lock Update bit position. */ 4820 4821 #define TC0_DIR_bm 0x01 /* Direction bit mask. */ 4822 #define TC0_DIR_bp 0 /* Direction bit position. */ 4823 4824 4825 /* TC0.CTRLFSET bit masks and bit positions */ 4826 /* TC0_CMD_gm Predefined. */ 4827 /* TC0_CMD_gp Predefined. */ 4828 /* TC0_CMD0_bm Predefined. */ 4829 /* TC0_CMD0_bp Predefined. */ 4830 /* TC0_CMD1_bm Predefined. */ 4831 /* TC0_CMD1_bp Predefined. */ 4832 4833 /* TC0_LUPD_bm Predefined. */ 4834 /* TC0_LUPD_bp Predefined. */ 4835 4836 /* TC0_DIR_bm Predefined. */ 4837 /* TC0_DIR_bp Predefined. */ 4838 4839 4840 /* TC0.CTRLGCLR bit masks and bit positions */ 4841 #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ 4842 #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ 4843 4844 #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ 4845 #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ 4846 4847 #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ 4848 #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ 4849 4850 #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ 4851 #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ 4852 4853 #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ 4854 #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ 4855 4856 4857 /* TC0.CTRLGSET bit masks and bit positions */ 4858 /* TC0_CCDBV_bm Predefined. */ 4859 /* TC0_CCDBV_bp Predefined. */ 4860 4861 /* TC0_CCCBV_bm Predefined. */ 4862 /* TC0_CCCBV_bp Predefined. */ 4863 4864 /* TC0_CCBBV_bm Predefined. */ 4865 /* TC0_CCBBV_bp Predefined. */ 4866 4867 /* TC0_CCABV_bm Predefined. */ 4868 /* TC0_CCABV_bp Predefined. */ 4869 4870 /* TC0_PERBV_bm Predefined. */ 4871 /* TC0_PERBV_bp Predefined. */ 4872 4873 4874 /* TC0.INTFLAGS bit masks and bit positions */ 4875 #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ 4876 #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ 4877 4878 #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ 4879 #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ 4880 4881 #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ 4882 #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ 4883 4884 #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ 4885 #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ 4886 4887 #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ 4888 #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ 4889 4890 #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 4891 #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 4892 4893 4894 /* TC1.CTRLA bit masks and bit positions */ 4895 #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 4896 #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ 4897 #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 4898 #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 4899 #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 4900 #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 4901 #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 4902 #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 4903 #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 4904 #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 4905 4906 4907 /* TC1.CTRLB bit masks and bit positions */ 4908 #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ 4909 #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ 4910 4911 #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ 4912 #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ 4913 4914 #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ 4915 #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ 4916 #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ 4917 #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ 4918 #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ 4919 #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ 4920 #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ 4921 #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ 4922 4923 4924 /* TC1.CTRLC bit masks and bit positions */ 4925 #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ 4926 #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ 4927 4928 #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ 4929 #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ 4930 4931 4932 /* TC1.CTRLD bit masks and bit positions */ 4933 #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ 4934 #define TC1_EVACT_gp 5 /* Event Action group position. */ 4935 #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ 4936 #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ 4937 #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ 4938 #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ 4939 #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ 4940 #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ 4941 4942 #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ 4943 #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ 4944 4945 #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ 4946 #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ 4947 #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ 4948 #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ 4949 #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ 4950 #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ 4951 #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ 4952 #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ 4953 #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ 4954 #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ 4955 4956 4957 /* TC1.CTRLE bit masks and bit positions */ 4958 #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ 4959 #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ 4960 4961 4962 /* TC1.INTCTRLA bit masks and bit positions */ 4963 #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ 4964 #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ 4965 #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ 4966 #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ 4967 #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ 4968 #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ 4969 4970 #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ 4971 #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ 4972 #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ 4973 #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ 4974 #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ 4975 #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ 4976 4977 4978 /* TC1.INTCTRLB bit masks and bit positions */ 4979 #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ 4980 #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ 4981 #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ 4982 #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ 4983 #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ 4984 #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ 4985 4986 #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ 4987 #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ 4988 #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ 4989 #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ 4990 #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ 4991 #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ 4992 4993 4994 /* TC1.CTRLFCLR bit masks and bit positions */ 4995 #define TC1_CMD_gm 0x0C /* Command group mask. */ 4996 #define TC1_CMD_gp 2 /* Command group position. */ 4997 #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ 4998 #define TC1_CMD0_bp 2 /* Command bit 0 position. */ 4999 #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ 5000 #define TC1_CMD1_bp 3 /* Command bit 1 position. */ 5001 5002 #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ 5003 #define TC1_LUPD_bp 1 /* Lock Update bit position. */ 5004 5005 #define TC1_DIR_bm 0x01 /* Direction bit mask. */ 5006 #define TC1_DIR_bp 0 /* Direction bit position. */ 5007 5008 5009 /* TC1.CTRLFSET bit masks and bit positions */ 5010 /* TC1_CMD_gm Predefined. */ 5011 /* TC1_CMD_gp Predefined. */ 5012 /* TC1_CMD0_bm Predefined. */ 5013 /* TC1_CMD0_bp Predefined. */ 5014 /* TC1_CMD1_bm Predefined. */ 5015 /* TC1_CMD1_bp Predefined. */ 5016 5017 /* TC1_LUPD_bm Predefined. */ 5018 /* TC1_LUPD_bp Predefined. */ 5019 5020 /* TC1_DIR_bm Predefined. */ 5021 /* TC1_DIR_bp Predefined. */ 5022 5023 5024 /* TC1.CTRLGCLR bit masks and bit positions */ 5025 #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ 5026 #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ 5027 5028 #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ 5029 #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ 5030 5031 #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ 5032 #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ 5033 5034 5035 /* TC1.CTRLGSET bit masks and bit positions */ 5036 /* TC1_CCBBV_bm Predefined. */ 5037 /* TC1_CCBBV_bp Predefined. */ 5038 5039 /* TC1_CCABV_bm Predefined. */ 5040 /* TC1_CCABV_bp Predefined. */ 5041 5042 /* TC1_PERBV_bm Predefined. */ 5043 /* TC1_PERBV_bp Predefined. */ 5044 5045 5046 /* TC1.INTFLAGS bit masks and bit positions */ 5047 #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ 5048 #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ 5049 5050 #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ 5051 #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ 5052 5053 #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ 5054 #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ 5055 5056 #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 5057 #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 5058 5059 5060 /* AWEX.CTRL bit masks and bit positions */ 5061 #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ 5062 #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ 5063 5064 #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ 5065 #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ 5066 5067 #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ 5068 #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ 5069 5070 #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ 5071 #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ 5072 5073 #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ 5074 #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ 5075 5076 #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ 5077 #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ 5078 5079 5080 /* AWEX.FDCTRL bit masks and bit positions */ 5081 #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ 5082 #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ 5083 5084 #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ 5085 #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ 5086 5087 #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ 5088 #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ 5089 #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ 5090 #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ 5091 #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ 5092 #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ 5093 5094 5095 /* AWEX.STATUS bit masks and bit positions */ 5096 #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ 5097 #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ 5098 5099 #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ 5100 #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ 5101 5102 #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ 5103 #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ 5104 5105 5106 /* HIRES.CTRLA bit masks and bit positions */ 5107 #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ 5108 #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ 5109 #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ 5110 #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ 5111 #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ 5112 #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ 5113 5114 5115 /* USART - Universal Asynchronous Receiver-Transmitter */ 5116 /* USART.STATUS bit masks and bit positions */ 5117 #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ 5118 #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ 5119 5120 #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ 5121 #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ 5122 5123 #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ 5124 #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ 5125 5126 #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ 5127 #define USART_FERR_bp 4 /* Frame Error bit position. */ 5128 5129 #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ 5130 #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ 5131 5132 #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ 5133 #define USART_PERR_bp 2 /* Parity Error bit position. */ 5134 5135 #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ 5136 #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ 5137 5138 5139 /* USART.CTRLA bit masks and bit positions */ 5140 #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ 5141 #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ 5142 #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ 5143 #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ 5144 #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ 5145 #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ 5146 5147 #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ 5148 #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ 5149 #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ 5150 #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ 5151 #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ 5152 #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ 5153 5154 #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ 5155 #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ 5156 #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ 5157 #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ 5158 #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ 5159 #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ 5160 5161 5162 /* USART.CTRLB bit masks and bit positions */ 5163 #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ 5164 #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ 5165 5166 #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ 5167 #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ 5168 5169 #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ 5170 #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ 5171 5172 #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ 5173 #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ 5174 5175 #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ 5176 #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ 5177 5178 5179 /* USART.CTRLC bit masks and bit positions */ 5180 #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ 5181 #define USART_CMODE_gp 6 /* Communication Mode group position. */ 5182 #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ 5183 #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ 5184 #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ 5185 #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ 5186 5187 #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ 5188 #define USART_PMODE_gp 4 /* Parity Mode group position. */ 5189 #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ 5190 #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ 5191 #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ 5192 #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ 5193 5194 #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ 5195 #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ 5196 5197 #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ 5198 #define USART_CHSIZE_gp 0 /* Character Size group position. */ 5199 #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ 5200 #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ 5201 #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ 5202 #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ 5203 #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ 5204 #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ 5205 5206 5207 /* USART.BAUDCTRLA bit masks and bit positions */ 5208 #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ 5209 #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ 5210 #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ 5211 #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ 5212 #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ 5213 #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ 5214 #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ 5215 #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ 5216 #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ 5217 #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ 5218 #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ 5219 #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ 5220 #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ 5221 #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ 5222 #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ 5223 #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ 5224 #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ 5225 #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ 5226 5227 5228 /* USART.BAUDCTRLB bit masks and bit positions */ 5229 #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ 5230 #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ 5231 #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ 5232 #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ 5233 #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ 5234 #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ 5235 #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ 5236 #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ 5237 #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ 5238 #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ 5239 5240 /* USART_BSEL_gm Predefined. */ 5241 /* USART_BSEL_gp Predefined. */ 5242 /* USART_BSEL0_bm Predefined. */ 5243 /* USART_BSEL0_bp Predefined. */ 5244 /* USART_BSEL1_bm Predefined. */ 5245 /* USART_BSEL1_bp Predefined. */ 5246 /* USART_BSEL2_bm Predefined. */ 5247 /* USART_BSEL2_bp Predefined. */ 5248 /* USART_BSEL3_bm Predefined. */ 5249 /* USART_BSEL3_bp Predefined. */ 5250 5251 5252 /* SPI - Serial Peripheral Interface */ 5253 /* SPI.CTRL bit masks and bit positions */ 5254 #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ 5255 #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ 5256 5257 #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ 5258 #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ 5259 5260 #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ 5261 #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ 5262 5263 #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ 5264 #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ 5265 5266 #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ 5267 #define SPI_MODE_gp 2 /* SPI Mode group position. */ 5268 #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ 5269 #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ 5270 #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ 5271 #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ 5272 5273 #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ 5274 #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ 5275 #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ 5276 #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ 5277 #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ 5278 #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ 5279 5280 5281 /* SPI.INTCTRL bit masks and bit positions */ 5282 #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ 5283 #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ 5284 #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ 5285 #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ 5286 #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ 5287 #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ 5288 5289 5290 /* SPI.STATUS bit masks and bit positions */ 5291 #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ 5292 #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ 5293 5294 #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ 5295 #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ 5296 5297 5298 /* IRCOM - IR Communication Module */ 5299 /* IRCOM.CTRL bit masks and bit positions */ 5300 #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ 5301 #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ 5302 #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ 5303 #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ 5304 #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ 5305 #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ 5306 #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ 5307 #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ 5308 #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ 5309 #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ 5310 5311 5312 5313 // Generic Port Pins 5314 5315 #define PIN0_bm 0x01 5316 #define PIN0_bp 0 5317 #define PIN1_bm 0x02 5318 #define PIN1_bp 1 5319 #define PIN2_bm 0x04 5320 #define PIN2_bp 2 5321 #define PIN3_bm 0x08 5322 #define PIN3_bp 3 5323 #define PIN4_bm 0x10 5324 #define PIN4_bp 4 5325 #define PIN5_bm 0x20 5326 #define PIN5_bp 5 5327 #define PIN6_bm 0x40 5328 #define PIN6_bp 6 5329 #define PIN7_bm 0x80 5330 #define PIN7_bp 7 5331 5332 5333 /* ========== Interrupt Vector Definitions ========== */ 5334 /* Vector 0 is the reset vector */ 5335 5336 /* OSC interrupt vectors */ 5337 #define OSC_XOSCF_vect_num 1 5338 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ 5339 5340 /* PORTC interrupt vectors */ 5341 #define PORTC_INT0_vect_num 2 5342 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ 5343 #define PORTC_INT1_vect_num 3 5344 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ 5345 5346 /* PORTR interrupt vectors */ 5347 #define PORTR_INT0_vect_num 4 5348 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ 5349 #define PORTR_INT1_vect_num 5 5350 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ 5351 5352 /* RTC interrupt vectors */ 5353 #define RTC_OVF_vect_num 10 5354 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ 5355 #define RTC_COMP_vect_num 11 5356 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ 5357 5358 /* TWIC interrupt vectors */ 5359 #define TWIC_TWIS_vect_num 12 5360 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ 5361 #define TWIC_TWIM_vect_num 13 5362 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ 5363 5364 /* TCC0 interrupt vectors */ 5365 #define TCC0_OVF_vect_num 14 5366 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ 5367 #define TCC0_ERR_vect_num 15 5368 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ 5369 #define TCC0_CCA_vect_num 16 5370 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ 5371 #define TCC0_CCB_vect_num 17 5372 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ 5373 #define TCC0_CCC_vect_num 18 5374 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ 5375 #define TCC0_CCD_vect_num 19 5376 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ 5377 5378 /* TCC1 interrupt vectors */ 5379 #define TCC1_OVF_vect_num 20 5380 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ 5381 #define TCC1_ERR_vect_num 21 5382 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ 5383 #define TCC1_CCA_vect_num 22 5384 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ 5385 #define TCC1_CCB_vect_num 23 5386 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ 5387 5388 /* SPIC interrupt vectors */ 5389 #define SPIC_INT_vect_num 24 5390 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ 5391 5392 /* USARTC0 interrupt vectors */ 5393 #define USARTC0_RXC_vect_num 25 5394 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ 5395 #define USARTC0_DRE_vect_num 26 5396 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ 5397 #define USARTC0_TXC_vect_num 27 5398 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ 5399 5400 /* NVM interrupt vectors */ 5401 #define NVM_EE_vect_num 32 5402 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ 5403 #define NVM_SPM_vect_num 33 5404 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ 5405 5406 /* PORTB interrupt vectors */ 5407 #define PORTB_INT0_vect_num 34 5408 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ 5409 #define PORTB_INT1_vect_num 35 5410 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ 5411 5412 /* PORTE interrupt vectors */ 5413 #define PORTE_INT0_vect_num 43 5414 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ 5415 #define PORTE_INT1_vect_num 44 5416 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ 5417 5418 /* TWIE interrupt vectors */ 5419 #define TWIE_TWIS_vect_num 45 5420 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ 5421 #define TWIE_TWIM_vect_num 46 5422 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ 5423 5424 /* TCE0 interrupt vectors */ 5425 #define TCE0_OVF_vect_num 47 5426 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ 5427 #define TCE0_ERR_vect_num 48 5428 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ 5429 #define TCE0_CCA_vect_num 49 5430 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ 5431 #define TCE0_CCB_vect_num 50 5432 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ 5433 #define TCE0_CCC_vect_num 51 5434 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ 5435 #define TCE0_CCD_vect_num 52 5436 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ 5437 5438 /* USARTE0 interrupt vectors */ 5439 #define USARTE0_RXC_vect_num 58 5440 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ 5441 #define USARTE0_DRE_vect_num 59 5442 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ 5443 #define USARTE0_TXC_vect_num 60 5444 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ 5445 5446 /* PORTD interrupt vectors */ 5447 #define PORTD_INT0_vect_num 64 5448 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ 5449 #define PORTD_INT1_vect_num 65 5450 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ 5451 5452 /* PORTA interrupt vectors */ 5453 #define PORTA_INT0_vect_num 66 5454 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ 5455 #define PORTA_INT1_vect_num 67 5456 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ 5457 5458 /* ACA interrupt vectors */ 5459 #define ACA_AC0_vect_num 68 5460 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ 5461 #define ACA_AC1_vect_num 69 5462 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ 5463 #define ACA_ACW_vect_num 70 5464 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ 5465 5466 /* ADCA interrupt vectors */ 5467 #define ADCA_CH0_vect_num 71 5468 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ 5469 5470 /* TCD0 interrupt vectors */ 5471 #define TCD0_OVF_vect_num 77 5472 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ 5473 #define TCD0_ERR_vect_num 78 5474 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ 5475 #define TCD0_CCA_vect_num 79 5476 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ 5477 #define TCD0_CCB_vect_num 80 5478 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ 5479 #define TCD0_CCC_vect_num 81 5480 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ 5481 #define TCD0_CCD_vect_num 82 5482 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ 5483 5484 /* SPID interrupt vectors */ 5485 #define SPID_INT_vect_num 87 5486 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ 5487 5488 /* USARTD0 interrupt vectors */ 5489 #define USARTD0_RXC_vect_num 88 5490 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ 5491 #define USARTD0_DRE_vect_num 89 5492 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ 5493 #define USARTD0_TXC_vect_num 90 5494 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ 5495 5496 /* PORTF interrupt vectors */ 5497 #define PORTF_INT0_vect_num 104 5498 #define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ 5499 #define PORTF_INT1_vect_num 105 5500 #define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ 5501 5502 /* TCF0 interrupt vectors */ 5503 #define TCF0_OVF_vect_num 108 5504 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ 5505 #define TCF0_ERR_vect_num 109 5506 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ 5507 #define TCF0_CCA_vect_num 110 5508 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ 5509 #define TCF0_CCB_vect_num 111 5510 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ 5511 #define TCF0_CCC_vect_num 112 5512 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ 5513 #define TCF0_CCD_vect_num 113 5514 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ 5515 5516 5517 #define _VECTOR_SIZE 4 /* Size of individual vector. */ 5518 #define _VECTORS_SIZE (114 * _VECTOR_SIZE) 5519 5520 5521 /* ========== Constants ========== */ 5522 5523 #define PROGMEM_START (0x0000) 5524 #define PROGMEM_SIZE (270336) 5525 #define PROGMEM_PAGE_SIZE (512) 5526 #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) 5527 5528 #define APP_SECTION_START (0x0000) 5529 #define APP_SECTION_SIZE (262144) 5530 #define APP_SECTION_PAGE_SIZE (512) 5531 #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) 5532 5533 #define APPTABLE_SECTION_START (0x3E000) 5534 #define APPTABLE_SECTION_SIZE (8192) 5535 #define APPTABLE_SECTION_PAGE_SIZE (512) 5536 #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) 5537 5538 #define BOOT_SECTION_START (0x40000) 5539 #define BOOT_SECTION_SIZE (8192) 5540 #define BOOT_SECTION_PAGE_SIZE (512) 5541 #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) 5542 5543 #define DATAMEM_START (0x0000) 5544 #define DATAMEM_SIZE (24576) 5545 #define DATAMEM_PAGE_SIZE (0) 5546 #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) 5547 5548 #define IO_START (0x0000) 5549 #define IO_SIZE (4096) 5550 #define IO_PAGE_SIZE (0) 5551 #define IO_END (IO_START + IO_SIZE - 1) 5552 5553 #define MAPPED_EEPROM_START (0x1000) 5554 #define MAPPED_EEPROM_SIZE (4096) 5555 #define MAPPED_EEPROM_PAGE_SIZE (0) 5556 #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) 5557 5558 #define INTERNAL_SRAM_START (0x2000) 5559 #define INTERNAL_SRAM_SIZE (16384) 5560 #define INTERNAL_SRAM_PAGE_SIZE (0) 5561 #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) 5562 5563 #define EEPROM_START (0x0000) 5564 #define EEPROM_SIZE (4096) 5565 #define EEPROM_PAGE_SIZE (32) 5566 #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) 5567 5568 #define FUSE_START (0x0000) 5569 #define FUSE_SIZE (6) 5570 #define FUSE_PAGE_SIZE (0) 5571 #define FUSE_END (FUSE_START + FUSE_SIZE - 1) 5572 5573 #define LOCKBIT_START (0x0000) 5574 #define LOCKBIT_SIZE (1) 5575 #define LOCKBIT_PAGE_SIZE (0) 5576 #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) 5577 5578 #define SIGNATURES_START (0x0000) 5579 #define SIGNATURES_SIZE (3) 5580 #define SIGNATURES_PAGE_SIZE (0) 5581 #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) 5582 5583 #define USER_SIGNATURES_START (0x0000) 5584 #define USER_SIGNATURES_SIZE (512) 5585 #define USER_SIGNATURES_PAGE_SIZE (0) 5586 #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) 5587 5588 #define PROD_SIGNATURES_START (0x0000) 5589 #define PROD_SIGNATURES_SIZE (52) 5590 #define PROD_SIGNATURES_PAGE_SIZE (0) 5591 #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) 5592 5593 #define FLASHEND PROGMEM_END 5594 #define SPM_PAGESIZE PROGMEM_PAGE_SIZE 5595 #define RAMSTART INTERNAL_SRAM_START 5596 #define RAMSIZE INTERNAL_SRAM_SIZE 5597 #define RAMEND INTERNAL_SRAM_END 5598 #define XRAMSTART EXTERNAL_SRAM_START 5599 #define XRAMSIZE EXTERNAL_SRAM_SIZE 5600 #define XRAMEND INTERNAL_SRAM_END 5601 #define E2END EEPROM_END 5602 #define E2PAGESIZE EEPROM_PAGE_SIZE 5603 5604 5605 /* ========== Fuses ========== */ 5606 #define FUSE_MEMORY_SIZE 6 5607 5608 /* Fuse Byte 0 */ 5609 #define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ 5610 #define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ 5611 #define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ 5612 #define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ 5613 #define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ 5614 #define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ 5615 #define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ 5616 #define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ 5617 #define FUSE0_DEFAULT (0xFF) 5618 5619 /* Fuse Byte 1 */ 5620 #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ 5621 #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ 5622 #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ 5623 #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ 5624 #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ 5625 #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ 5626 #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ 5627 #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ 5628 #define FUSE1_DEFAULT (0xFF) 5629 5630 /* Fuse Byte 2 */ 5631 #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ 5632 #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ 5633 #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ 5634 #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ 5635 #define FUSE2_DEFAULT (0xFF) 5636 5637 /* Fuse Byte 3 Reserved */ 5638 5639 /* Fuse Byte 4 */ 5640 #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ 5641 #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ 5642 #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ 5643 #define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ 5644 #define FUSE4_DEFAULT (0xFF) 5645 5646 /* Fuse Byte 5 */ 5647 #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ 5648 #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ 5649 #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ 5650 #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ 5651 #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ 5652 #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ 5653 #define FUSE5_DEFAULT (0xFF) 5654 5655 5656 /* ========== Lock Bits ========== */ 5657 #define __LOCK_BITS_EXIST 5658 #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST 5659 #define __BOOT_LOCK_APPLICATION_BITS_EXIST 5660 #define __BOOT_LOCK_BOOT_BITS_EXIST 5661 5662 5663 /* ========== Signature ========== */ 5664 #define SIGNATURE_0 0x1E 5665 #define SIGNATURE_1 0x98 5666 #define SIGNATURE_2 0x44 5667 5668 /* ========== Power Reduction Condition Definitions ========== */ 5669 5670 /* PR.PRGEN */ 5671 #define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) 5672 #define __AVR_HAVE_PRGEN_RTC 5673 #define __AVR_HAVE_PRGEN_EVSYS 5674 5675 /* PR.PRPA */ 5676 #define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) 5677 #define __AVR_HAVE_PRPA_ADC 5678 #define __AVR_HAVE_PRPA_AC 5679 5680 /* PR.PRPC */ 5681 #define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) 5682 #define __AVR_HAVE_PRPC_TWI 5683 #define __AVR_HAVE_PRPC_USART0 5684 #define __AVR_HAVE_PRPC_SPI 5685 #define __AVR_HAVE_PRPC_HIRES 5686 #define __AVR_HAVE_PRPC_TC1 5687 #define __AVR_HAVE_PRPC_TC0 5688 5689 /* PR.PRPD */ 5690 #define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) 5691 #define __AVR_HAVE_PRPD_USART0 5692 #define __AVR_HAVE_PRPD_SPI 5693 #define __AVR_HAVE_PRPD_TC0 5694 5695 /* PR.PRPE */ 5696 #define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) 5697 #define __AVR_HAVE_PRPE_TWI 5698 #define __AVR_HAVE_PRPE_USART0 5699 #define __AVR_HAVE_PRPE_TC0 5700 5701 /* PR.PRPF */ 5702 #define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) 5703 #define __AVR_HAVE_PRPF_USART0 5704 #define __AVR_HAVE_PRPF_TC0 5705 5706 5707 #endif /* _AVR_ATxmega256D3_H_ */ 5708 5709