1 /* Copyright (c) 2009-2010 Atmel Corporation 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: iox32a4.h 2482 2015-08-06 08:54:17Z pitchumani $ */ 32 33 /* avr/iox32a4.h - definitions for ATxmega32A4 */ 34 35 /* This file should only be included from <avr/io.h>, never directly. */ 36 37 #ifndef _AVR_IO_H_ 38 # error "Include <avr/io.h> instead of this file." 39 #endif 40 41 #ifndef _AVR_IOXXX_H_ 42 # define _AVR_IOXXX_H_ "iox32a4.h" 43 #else 44 # error "Attempt to include more than one <avr/ioXXX.h> file." 45 #endif 46 47 48 #ifndef _AVR_ATxmega32A4_H_ 49 #define _AVR_ATxmega32A4_H_ 1 50 51 52 /* Ungrouped common registers */ 53 #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ 54 #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ 55 #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ 56 #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ 57 #define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ 58 #define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ 59 #define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ 60 #define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ 61 #define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ 62 #define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ 63 #define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ 64 #define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ 65 #define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ 66 #define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ 67 #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ 68 #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ 69 70 /* Deprecated */ 71 #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ 72 #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ 73 #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ 74 #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ 75 #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ 76 #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ 77 #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ 78 #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ 79 #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ 80 #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ 81 #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ 82 #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ 83 #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ 84 #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ 85 #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ 86 #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ 87 88 #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ 89 #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ 90 #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ 91 #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ 92 #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ 93 #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ 94 #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ 95 #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ 96 #define SREG _SFR_MEM8(0x003F) /* Status Register */ 97 98 99 /* C Language Only */ 100 #if !defined (__ASSEMBLER__) 101 102 #include <stdint.h> 103 104 typedef volatile uint8_t register8_t; 105 typedef volatile uint16_t register16_t; 106 typedef volatile uint32_t register32_t; 107 108 109 #ifdef _WORDREGISTER 110 #undef _WORDREGISTER 111 #endif 112 #define _WORDREGISTER(regname) \ 113 __extension__ union \ 114 { \ 115 register16_t regname; \ 116 struct \ 117 { \ 118 register8_t regname ## L; \ 119 register8_t regname ## H; \ 120 }; \ 121 } 122 123 #ifdef _DWORDREGISTER 124 #undef _DWORDREGISTER 125 #endif 126 #define _DWORDREGISTER(regname) \ 127 __extension__ union \ 128 { \ 129 register32_t regname; \ 130 struct \ 131 { \ 132 register8_t regname ## 0; \ 133 register8_t regname ## 1; \ 134 register8_t regname ## 2; \ 135 register8_t regname ## 3; \ 136 }; \ 137 } 138 139 140 /* 141 ========================================================================== 142 IO Module Structures 143 ========================================================================== 144 */ 145 146 147 /* 148 -------------------------------------------------------------------------- 149 XOCD - On-Chip Debug System 150 -------------------------------------------------------------------------- 151 */ 152 153 /* On-Chip Debug System */ 154 typedef struct OCD_struct 155 { 156 register8_t OCDR0; /* OCD Register 0 */ 157 register8_t OCDR1; /* OCD Register 1 */ 158 } OCD_t; 159 160 161 /* CCP signatures */ 162 typedef enum CCP_enum 163 { 164 CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ 165 CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ 166 } CCP_t; 167 168 169 /* 170 -------------------------------------------------------------------------- 171 CLK - Clock System 172 -------------------------------------------------------------------------- 173 */ 174 175 /* Clock System */ 176 typedef struct CLK_struct 177 { 178 register8_t CTRL; /* Control Register */ 179 register8_t PSCTRL; /* Prescaler Control Register */ 180 register8_t LOCK; /* Lock register */ 181 register8_t RTCCTRL; /* RTC Control Register */ 182 } CLK_t; 183 184 /* 185 -------------------------------------------------------------------------- 186 CLK - Clock System 187 -------------------------------------------------------------------------- 188 */ 189 190 /* Power Reduction */ 191 typedef struct PR_struct 192 { 193 register8_t PRGEN; /* General Power Reduction */ 194 register8_t PRPA; /* Power Reduction Port A */ 195 register8_t PRPB; /* Power Reduction Port B */ 196 register8_t PRPC; /* Power Reduction Port C */ 197 register8_t PRPD; /* Power Reduction Port D */ 198 register8_t PRPE; /* Power Reduction Port E */ 199 register8_t PRPF; /* Power Reduction Port F */ 200 } PR_t; 201 202 /* System Clock Selection */ 203 typedef enum CLK_SCLKSEL_enum 204 { 205 CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ 206 CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ 207 CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ 208 CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ 209 CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ 210 } CLK_SCLKSEL_t; 211 212 /* Prescaler A Division Factor */ 213 typedef enum CLK_PSADIV_enum 214 { 215 CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ 216 CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ 217 CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ 218 CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ 219 CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ 220 CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ 221 CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ 222 CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ 223 CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ 224 CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ 225 } CLK_PSADIV_t; 226 227 /* Prescaler B and C Division Factor */ 228 typedef enum CLK_PSBCDIV_enum 229 { 230 CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ 231 CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ 232 CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ 233 CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ 234 } CLK_PSBCDIV_t; 235 236 /* RTC Clock Source */ 237 typedef enum CLK_RTCSRC_enum 238 { 239 CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ 240 CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ 241 CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ 242 CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ 243 } CLK_RTCSRC_t; 244 245 246 /* 247 -------------------------------------------------------------------------- 248 SLEEP - Sleep Controller 249 -------------------------------------------------------------------------- 250 */ 251 252 /* Sleep Controller */ 253 typedef struct SLEEP_struct 254 { 255 register8_t CTRL; /* Control Register */ 256 } SLEEP_t; 257 258 /* Sleep Mode */ 259 typedef enum SLEEP_SMODE_enum 260 { 261 SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ 262 SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ 263 SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ 264 SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ 265 SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ 266 } SLEEP_SMODE_t; 267 268 269 #define SLEEP_MODE_IDLE (0x00<<1) 270 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 271 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 272 #define SLEEP_MODE_STANDBY (0x06<<1) 273 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 274 275 /* 276 -------------------------------------------------------------------------- 277 OSC - Oscillator 278 -------------------------------------------------------------------------- 279 */ 280 281 /* Oscillator */ 282 typedef struct OSC_struct 283 { 284 register8_t CTRL; /* Control Register */ 285 register8_t STATUS; /* Status Register */ 286 register8_t XOSCCTRL; /* External Oscillator Control Register */ 287 register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ 288 register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ 289 register8_t PLLCTRL; /* PLL Control REgister */ 290 register8_t DFLLCTRL; /* DFLL Control Register */ 291 } OSC_t; 292 293 /* Oscillator Frequency Range */ 294 typedef enum OSC_FRQRANGE_enum 295 { 296 OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ 297 OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ 298 OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ 299 OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ 300 } OSC_FRQRANGE_t; 301 302 /* External Oscillator Selection and Startup Time */ 303 typedef enum OSC_XOSCSEL_enum 304 { 305 OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ 306 OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ 307 OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ 308 OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ 309 OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ 310 } OSC_XOSCSEL_t; 311 312 /* PLL Clock Source */ 313 typedef enum OSC_PLLSRC_enum 314 { 315 OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ 316 OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ 317 OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ 318 } OSC_PLLSRC_t; 319 320 321 /* 322 -------------------------------------------------------------------------- 323 DFLL - DFLL 324 -------------------------------------------------------------------------- 325 */ 326 327 /* DFLL */ 328 typedef struct DFLL_struct 329 { 330 register8_t CTRL; /* Control Register */ 331 register8_t reserved_0x01; 332 register8_t CALA; /* Calibration Register A */ 333 register8_t CALB; /* Calibration Register B */ 334 register8_t COMP0; /* Oscillator Compare Register 0 */ 335 register8_t COMP1; /* Oscillator Compare Register 1 */ 336 register8_t COMP2; /* Oscillator Compare Register 2 */ 337 register8_t reserved_0x07; 338 } DFLL_t; 339 340 341 /* 342 -------------------------------------------------------------------------- 343 RST - Reset 344 -------------------------------------------------------------------------- 345 */ 346 347 /* Reset */ 348 typedef struct RST_struct 349 { 350 register8_t STATUS; /* Status Register */ 351 register8_t CTRL; /* Control Register */ 352 } RST_t; 353 354 355 /* 356 -------------------------------------------------------------------------- 357 WDT - Watch-Dog Timer 358 -------------------------------------------------------------------------- 359 */ 360 361 /* Watch-Dog Timer */ 362 typedef struct WDT_struct 363 { 364 register8_t CTRL; /* Control */ 365 register8_t WINCTRL; /* Windowed Mode Control */ 366 register8_t STATUS; /* Status */ 367 } WDT_t; 368 369 /* Period setting */ 370 typedef enum WDT_PER_enum 371 { 372 WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ 373 WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ 374 WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ 375 WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ 376 WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ 377 WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ 378 WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ 379 WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ 380 WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ 381 WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ 382 WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ 383 } WDT_PER_t; 384 385 /* Closed window period */ 386 typedef enum WDT_WPER_enum 387 { 388 WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ 389 WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ 390 WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ 391 WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ 392 WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ 393 WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ 394 WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ 395 WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ 396 WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ 397 WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ 398 WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ 399 } WDT_WPER_t; 400 401 402 /* 403 -------------------------------------------------------------------------- 404 MCU - MCU Control 405 -------------------------------------------------------------------------- 406 */ 407 408 /* MCU Control */ 409 typedef struct MCU_struct 410 { 411 register8_t DEVID0; /* Device ID byte 0 */ 412 register8_t DEVID1; /* Device ID byte 1 */ 413 register8_t DEVID2; /* Device ID byte 2 */ 414 register8_t REVID; /* Revision ID */ 415 register8_t JTAGUID; /* JTAG User ID */ 416 register8_t reserved_0x05; 417 register8_t MCUCR; /* MCU Control */ 418 register8_t reserved_0x07; 419 register8_t EVSYSLOCK; /* Event System Lock */ 420 register8_t AWEXLOCK; /* AWEX Lock */ 421 register8_t reserved_0x0A; 422 register8_t reserved_0x0B; 423 } MCU_t; 424 425 426 /* 427 -------------------------------------------------------------------------- 428 PMIC - Programmable Multi-level Interrupt Controller 429 -------------------------------------------------------------------------- 430 */ 431 432 /* Programmable Multi-level Interrupt Controller */ 433 typedef struct PMIC_struct 434 { 435 register8_t STATUS; /* Status Register */ 436 register8_t INTPRI; /* Interrupt Priority */ 437 register8_t CTRL; /* Control Register */ 438 } PMIC_t; 439 440 441 /* 442 -------------------------------------------------------------------------- 443 DMA - DMA Controller 444 -------------------------------------------------------------------------- 445 */ 446 447 /* DMA Channel */ 448 typedef struct DMA_CH_struct 449 { 450 register8_t CTRLA; /* Channel Control */ 451 register8_t CTRLB; /* Channel Control */ 452 register8_t ADDRCTRL; /* Address Control */ 453 register8_t TRIGSRC; /* Channel Trigger Source */ 454 _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ 455 register8_t REPCNT; /* Channel Repeat Count */ 456 register8_t reserved_0x07; 457 register8_t SRCADDR0; /* Channel Source Address 0 */ 458 register8_t SRCADDR1; /* Channel Source Address 1 */ 459 register8_t SRCADDR2; /* Channel Source Address 2 */ 460 register8_t reserved_0x0B; 461 register8_t DESTADDR0; /* Channel Destination Address 0 */ 462 register8_t DESTADDR1; /* Channel Destination Address 1 */ 463 register8_t DESTADDR2; /* Channel Destination Address 2 */ 464 register8_t reserved_0x0F; 465 } DMA_CH_t; 466 467 /* 468 -------------------------------------------------------------------------- 469 DMA - DMA Controller 470 -------------------------------------------------------------------------- 471 */ 472 473 /* DMA Controller */ 474 typedef struct DMA_struct 475 { 476 register8_t CTRL; /* Control */ 477 register8_t reserved_0x01; 478 register8_t reserved_0x02; 479 register8_t INTFLAGS; /* Transfer Interrupt Status */ 480 register8_t STATUS; /* Status */ 481 register8_t reserved_0x05; 482 _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ 483 register8_t reserved_0x08; 484 register8_t reserved_0x09; 485 register8_t reserved_0x0A; 486 register8_t reserved_0x0B; 487 register8_t reserved_0x0C; 488 register8_t reserved_0x0D; 489 register8_t reserved_0x0E; 490 register8_t reserved_0x0F; 491 DMA_CH_t CH0; /* DMA Channel 0 */ 492 DMA_CH_t CH1; /* DMA Channel 1 */ 493 DMA_CH_t CH2; /* DMA Channel 2 */ 494 DMA_CH_t CH3; /* DMA Channel 3 */ 495 } DMA_t; 496 497 /* Burst mode */ 498 typedef enum DMA_CH_BURSTLEN_enum 499 { 500 DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ 501 DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ 502 DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ 503 DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ 504 } DMA_CH_BURSTLEN_t; 505 506 /* Source address reload mode */ 507 typedef enum DMA_CH_SRCRELOAD_enum 508 { 509 DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ 510 DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ 511 DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ 512 DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ 513 } DMA_CH_SRCRELOAD_t; 514 515 /* Source addressing mode */ 516 typedef enum DMA_CH_SRCDIR_enum 517 { 518 DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ 519 DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ 520 DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ 521 } DMA_CH_SRCDIR_t; 522 523 /* Destination adress reload mode */ 524 typedef enum DMA_CH_DESTRELOAD_enum 525 { 526 DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ 527 DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ 528 DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ 529 DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ 530 } DMA_CH_DESTRELOAD_t; 531 532 /* Destination adressing mode */ 533 typedef enum DMA_CH_DESTDIR_enum 534 { 535 DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ 536 DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ 537 DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ 538 } DMA_CH_DESTDIR_t; 539 540 /* Transfer trigger source */ 541 typedef enum DMA_CH_TRIGSRC_enum 542 { 543 DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ 544 DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ 545 DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ 546 DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ 547 DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ 548 DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ 549 DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ 550 DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ 551 DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ 552 DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ 553 DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ 554 DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ 555 DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ 556 DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ 557 DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ 558 DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ 559 DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ 560 DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ 561 DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ 562 DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ 563 DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ 564 DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ 565 DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ 566 DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ 567 DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ 568 DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ 569 DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ 570 DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ 571 DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ 572 DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ 573 DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ 574 DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ 575 DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ 576 DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ 577 DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ 578 DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ 579 DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ 580 DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ 581 DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ 582 DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ 583 DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ 584 DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ 585 DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ 586 DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ 587 DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ 588 DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ 589 DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ 590 DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ 591 DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ 592 DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ 593 DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ 594 DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ 595 DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ 596 DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ 597 DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ 598 DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ 599 DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ 600 DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ 601 DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ 602 DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ 603 DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ 604 DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ 605 DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ 606 DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ 607 DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ 608 DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ 609 DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ 610 DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ 611 DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ 612 DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ 613 DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ 614 DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ 615 DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ 616 DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ 617 DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ 618 DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ 619 DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ 620 DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ 621 } DMA_CH_TRIGSRC_t; 622 623 /* Double buffering mode */ 624 typedef enum DMA_DBUFMODE_enum 625 { 626 DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ 627 DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ 628 DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ 629 DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ 630 } DMA_DBUFMODE_t; 631 632 /* Priority mode */ 633 typedef enum DMA_PRIMODE_enum 634 { 635 DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ 636 DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ 637 DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ 638 DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ 639 } DMA_PRIMODE_t; 640 641 /* Interrupt level */ 642 typedef enum DMA_CH_ERRINTLVL_enum 643 { 644 DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ 645 DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ 646 DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ 647 DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ 648 } DMA_CH_ERRINTLVL_t; 649 650 /* Interrupt level */ 651 typedef enum DMA_CH_TRNINTLVL_enum 652 { 653 DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 654 DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ 655 DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ 656 DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ 657 } DMA_CH_TRNINTLVL_t; 658 659 660 /* 661 -------------------------------------------------------------------------- 662 EVSYS - Event System 663 -------------------------------------------------------------------------- 664 */ 665 666 /* Event System */ 667 typedef struct EVSYS_struct 668 { 669 register8_t CH0MUX; /* Event Channel 0 Multiplexer */ 670 register8_t CH1MUX; /* Event Channel 1 Multiplexer */ 671 register8_t CH2MUX; /* Event Channel 2 Multiplexer */ 672 register8_t CH3MUX; /* Event Channel 3 Multiplexer */ 673 register8_t CH4MUX; /* Event Channel 4 Multiplexer */ 674 register8_t CH5MUX; /* Event Channel 5 Multiplexer */ 675 register8_t CH6MUX; /* Event Channel 6 Multiplexer */ 676 register8_t CH7MUX; /* Event Channel 7 Multiplexer */ 677 register8_t CH0CTRL; /* Channel 0 Control Register */ 678 register8_t CH1CTRL; /* Channel 1 Control Register */ 679 register8_t CH2CTRL; /* Channel 2 Control Register */ 680 register8_t CH3CTRL; /* Channel 3 Control Register */ 681 register8_t CH4CTRL; /* Channel 4 Control Register */ 682 register8_t CH5CTRL; /* Channel 5 Control Register */ 683 register8_t CH6CTRL; /* Channel 6 Control Register */ 684 register8_t CH7CTRL; /* Channel 7 Control Register */ 685 register8_t STROBE; /* Event Strobe */ 686 register8_t DATA; /* Event Data */ 687 } EVSYS_t; 688 689 /* Quadrature Decoder Index Recognition Mode */ 690 typedef enum EVSYS_QDIRM_enum 691 { 692 EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ 693 EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ 694 EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ 695 EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ 696 } EVSYS_QDIRM_t; 697 698 /* Digital filter coefficient */ 699 typedef enum EVSYS_DIGFILT_enum 700 { 701 EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ 702 EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ 703 EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ 704 EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ 705 EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ 706 EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ 707 EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ 708 EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ 709 } EVSYS_DIGFILT_t; 710 711 /* Event Channel multiplexer input selection */ 712 typedef enum EVSYS_CHMUX_enum 713 { 714 EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ 715 EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ 716 EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ 717 EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ 718 EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ 719 EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ 720 EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ 721 EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ 722 EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ 723 EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ 724 EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ 725 EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ 726 EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ 727 EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ 728 EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ 729 EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ 730 EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ 731 EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ 732 EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ 733 EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ 734 EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ 735 EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ 736 EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ 737 EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ 738 EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ 739 EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ 740 EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ 741 EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ 742 EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ 743 EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ 744 EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ 745 EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ 746 EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ 747 EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ 748 EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ 749 EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ 750 EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ 751 EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ 752 EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ 753 EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ 754 EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ 755 EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ 756 EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ 757 EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ 758 EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ 759 EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ 760 EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ 761 EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ 762 EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ 763 EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ 764 EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ 765 EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ 766 EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ 767 EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ 768 EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ 769 EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ 770 EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ 771 EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ 772 EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ 773 EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ 774 EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ 775 EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ 776 EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ 777 EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ 778 EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ 779 EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ 780 EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ 781 EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ 782 EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ 783 EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ 784 EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ 785 EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ 786 EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ 787 EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ 788 EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ 789 EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ 790 EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ 791 EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ 792 EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ 793 EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ 794 EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ 795 EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ 796 EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ 797 EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ 798 EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ 799 EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ 800 EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ 801 EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ 802 EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ 803 EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ 804 EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ 805 EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ 806 EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ 807 EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ 808 EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ 809 EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ 810 EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ 811 EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ 812 EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ 813 EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ 814 EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ 815 EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ 816 EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ 817 EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ 818 EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ 819 EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ 820 EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ 821 EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ 822 EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ 823 EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ 824 EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ 825 EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ 826 EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ 827 EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ 828 EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ 829 EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ 830 EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ 831 EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ 832 EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ 833 EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ 834 EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ 835 } EVSYS_CHMUX_t; 836 837 838 /* 839 -------------------------------------------------------------------------- 840 NVM - Non Volatile Memory Controller 841 -------------------------------------------------------------------------- 842 */ 843 844 /* Non-volatile Memory Controller */ 845 typedef struct NVM_struct 846 { 847 register8_t ADDR0; /* Address Register 0 */ 848 register8_t ADDR1; /* Address Register 1 */ 849 register8_t ADDR2; /* Address Register 2 */ 850 register8_t reserved_0x03; 851 register8_t DATA0; /* Data Register 0 */ 852 register8_t DATA1; /* Data Register 1 */ 853 register8_t DATA2; /* Data Register 2 */ 854 register8_t reserved_0x07; 855 register8_t reserved_0x08; 856 register8_t reserved_0x09; 857 register8_t CMD; /* Command */ 858 register8_t CTRLA; /* Control Register A */ 859 register8_t CTRLB; /* Control Register B */ 860 register8_t INTCTRL; /* Interrupt Control */ 861 register8_t reserved_0x0E; 862 register8_t STATUS; /* Status */ 863 register8_t LOCK_BITS; /* Lock Bits */ 864 } NVM_t; 865 866 /* 867 -------------------------------------------------------------------------- 868 NVM - Non Volatile Memory Controller 869 -------------------------------------------------------------------------- 870 */ 871 872 /* Lock Bits */ 873 typedef struct NVM_LOCKBITS_struct 874 { 875 register8_t LOCKBITS; /* Lock Bits */ 876 } NVM_LOCKBITS_t; 877 878 /* 879 -------------------------------------------------------------------------- 880 NVM - Non Volatile Memory Controller 881 -------------------------------------------------------------------------- 882 */ 883 884 /* Fuses */ 885 typedef struct NVM_FUSES_struct 886 { 887 register8_t FUSEBYTE0; /* User ID */ 888 register8_t FUSEBYTE1; /* Watchdog Configuration */ 889 register8_t FUSEBYTE2; /* Reset Configuration */ 890 register8_t reserved_0x03; 891 register8_t FUSEBYTE4; /* Start-up Configuration */ 892 register8_t FUSEBYTE5; /* EESAVE and BOD Level */ 893 } NVM_FUSES_t; 894 895 /* 896 -------------------------------------------------------------------------- 897 NVM - Non Volatile Memory Controller 898 -------------------------------------------------------------------------- 899 */ 900 901 /* Production Signatures */ 902 typedef struct NVM_PROD_SIGNATURES_struct 903 { 904 register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ 905 register8_t reserved_0x01; 906 register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ 907 register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ 908 register8_t reserved_0x04; 909 register8_t reserved_0x05; 910 register8_t reserved_0x06; 911 register8_t reserved_0x07; 912 register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ 913 register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ 914 register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ 915 register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ 916 register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ 917 register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ 918 register8_t reserved_0x0E; 919 register8_t reserved_0x0F; 920 register8_t WAFNUM; /* Wafer Number */ 921 register8_t reserved_0x11; 922 register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ 923 register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ 924 register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ 925 register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ 926 register8_t reserved_0x16; 927 register8_t reserved_0x17; 928 register8_t reserved_0x18; 929 register8_t reserved_0x19; 930 register8_t reserved_0x1A; 931 register8_t reserved_0x1B; 932 register8_t reserved_0x1C; 933 register8_t reserved_0x1D; 934 register8_t reserved_0x1E; 935 register8_t reserved_0x1F; 936 register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ 937 register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ 938 register8_t reserved_0x22; 939 register8_t reserved_0x23; 940 register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ 941 register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ 942 register8_t reserved_0x26; 943 register8_t reserved_0x27; 944 register8_t reserved_0x28; 945 register8_t reserved_0x29; 946 register8_t reserved_0x2A; 947 register8_t reserved_0x2B; 948 register8_t reserved_0x2C; 949 register8_t reserved_0x2D; 950 register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ 951 register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ 952 register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ 953 register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ 954 register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ 955 register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ 956 register8_t reserved_0x34; 957 register8_t reserved_0x35; 958 register8_t reserved_0x36; 959 register8_t reserved_0x37; 960 register8_t reserved_0x38; 961 register8_t reserved_0x39; 962 register8_t reserved_0x3A; 963 register8_t reserved_0x3B; 964 register8_t reserved_0x3C; 965 register8_t reserved_0x3D; 966 register8_t reserved_0x3E; 967 } NVM_PROD_SIGNATURES_t; 968 969 /* NVM Command */ 970 typedef enum NVM_CMD_enum 971 { 972 NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ 973 NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ 974 NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ 975 NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ 976 NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ 977 NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ 978 NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ 979 NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ 980 NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ 981 NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ 982 NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ 983 NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ 984 NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ 985 NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ 986 NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ 987 NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ 988 NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ 989 NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ 990 NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ 991 NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ 992 NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ 993 NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ 994 NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ 995 NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ 996 NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ 997 NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ 998 } NVM_CMD_t; 999 1000 /* SPM ready interrupt level */ 1001 typedef enum NVM_SPMLVL_enum 1002 { 1003 NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ 1004 NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ 1005 NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ 1006 NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ 1007 } NVM_SPMLVL_t; 1008 1009 /* EEPROM ready interrupt level */ 1010 typedef enum NVM_EELVL_enum 1011 { 1012 NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1013 NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ 1014 NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ 1015 NVM_EELVL_HI_gc = (0x03<<0), /* High level */ 1016 } NVM_EELVL_t; 1017 1018 /* Boot lock bits - boot setcion */ 1019 typedef enum NVM_BLBB_enum 1020 { 1021 NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ 1022 NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ 1023 NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ 1024 NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ 1025 } NVM_BLBB_t; 1026 1027 /* Boot lock bits - application section */ 1028 typedef enum NVM_BLBA_enum 1029 { 1030 NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ 1031 NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ 1032 NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ 1033 NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ 1034 } NVM_BLBA_t; 1035 1036 /* Boot lock bits - application table section */ 1037 typedef enum NVM_BLBAT_enum 1038 { 1039 NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ 1040 NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ 1041 NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ 1042 NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ 1043 } NVM_BLBAT_t; 1044 1045 /* Lock bits */ 1046 typedef enum NVM_LB_enum 1047 { 1048 NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ 1049 NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ 1050 NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ 1051 } NVM_LB_t; 1052 1053 /* Boot Loader Section Reset Vector */ 1054 typedef enum BOOTRST_enum 1055 { 1056 BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ 1057 BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ 1058 } BOOTRST_t; 1059 1060 /* BOD operation */ 1061 typedef enum BOD_enum 1062 { 1063 BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ 1064 BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ 1065 BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ 1066 } BOD_t; 1067 1068 /* Watchdog (Window) Timeout Period */ 1069 typedef enum WD_enum 1070 { 1071 WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ 1072 WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ 1073 WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ 1074 WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ 1075 WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ 1076 WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ 1077 WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ 1078 WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ 1079 WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ 1080 WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ 1081 WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ 1082 } WD_t; 1083 1084 /* Start-up Time */ 1085 typedef enum SUT_enum 1086 { 1087 SUT_0MS_gc = (0x03<<2), /* 0 ms */ 1088 SUT_4MS_gc = (0x01<<2), /* 4 ms */ 1089 SUT_64MS_gc = (0x00<<2), /* 64 ms */ 1090 } SUT_t; 1091 1092 /* Brown Out Detection Voltage Level */ 1093 typedef enum BODLVL_enum 1094 { 1095 BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ 1096 BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ 1097 BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ 1098 BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ 1099 BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ 1100 BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ 1101 BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ 1102 } BODLVL_t; 1103 1104 1105 /* 1106 -------------------------------------------------------------------------- 1107 AC - Analog Comparator 1108 -------------------------------------------------------------------------- 1109 */ 1110 1111 /* Analog Comparator */ 1112 typedef struct AC_struct 1113 { 1114 register8_t AC0CTRL; /* Comparator 0 Control */ 1115 register8_t AC1CTRL; /* Comparator 1 Control */ 1116 register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ 1117 register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ 1118 register8_t CTRLA; /* Control Register A */ 1119 register8_t CTRLB; /* Control Register B */ 1120 register8_t WINCTRL; /* Window Mode Control */ 1121 register8_t STATUS; /* Status */ 1122 } AC_t; 1123 1124 /* Interrupt mode */ 1125 typedef enum AC_INTMODE_enum 1126 { 1127 AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ 1128 AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ 1129 AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ 1130 } AC_INTMODE_t; 1131 1132 /* Interrupt level */ 1133 typedef enum AC_INTLVL_enum 1134 { 1135 AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ 1136 AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ 1137 AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ 1138 AC_INTLVL_HI_gc = (0x03<<4), /* High level */ 1139 } AC_INTLVL_t; 1140 1141 /* Hysteresis mode selection */ 1142 typedef enum AC_HYSMODE_enum 1143 { 1144 AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ 1145 AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ 1146 AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ 1147 } AC_HYSMODE_t; 1148 1149 /* Positive input multiplexer selection */ 1150 typedef enum AC_MUXPOS_enum 1151 { 1152 AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ 1153 AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ 1154 AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ 1155 AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ 1156 AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ 1157 AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ 1158 AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ 1159 AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ 1160 } AC_MUXPOS_t; 1161 1162 /* Negative input multiplexer selection */ 1163 typedef enum AC_MUXNEG_enum 1164 { 1165 AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ 1166 AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ 1167 AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ 1168 AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ 1169 AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ 1170 AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ 1171 AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ 1172 AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ 1173 } AC_MUXNEG_t; 1174 1175 /* Windows interrupt mode */ 1176 typedef enum AC_WINTMODE_enum 1177 { 1178 AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ 1179 AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ 1180 AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ 1181 AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ 1182 } AC_WINTMODE_t; 1183 1184 /* Window interrupt level */ 1185 typedef enum AC_WINTLVL_enum 1186 { 1187 AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1188 AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ 1189 AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ 1190 AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ 1191 } AC_WINTLVL_t; 1192 1193 /* Window mode state */ 1194 typedef enum AC_WSTATE_enum 1195 { 1196 AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ 1197 AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ 1198 AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ 1199 } AC_WSTATE_t; 1200 1201 1202 /* 1203 -------------------------------------------------------------------------- 1204 ADC - Analog/Digital Converter 1205 -------------------------------------------------------------------------- 1206 */ 1207 1208 /* ADC Channel */ 1209 typedef struct ADC_CH_struct 1210 { 1211 register8_t CTRL; /* Control Register */ 1212 register8_t MUXCTRL; /* MUX Control */ 1213 register8_t INTCTRL; /* Channel Interrupt Control */ 1214 register8_t INTFLAGS; /* Interrupt Flags */ 1215 _WORDREGISTER(RES); /* Channel Result */ 1216 register8_t reserved_0x6; 1217 register8_t reserved_0x7; 1218 } ADC_CH_t; 1219 1220 /* 1221 -------------------------------------------------------------------------- 1222 ADC - Analog/Digital Converter 1223 -------------------------------------------------------------------------- 1224 */ 1225 1226 /* Analog-to-Digital Converter */ 1227 typedef struct ADC_struct 1228 { 1229 register8_t CTRLA; /* Control Register A */ 1230 register8_t CTRLB; /* Control Register B */ 1231 register8_t REFCTRL; /* Reference Control */ 1232 register8_t EVCTRL; /* Event Control */ 1233 register8_t PRESCALER; /* Clock Prescaler */ 1234 register8_t reserved_0x05; 1235 register8_t INTFLAGS; /* Interrupt Flags */ 1236 register8_t reserved_0x07; 1237 register8_t reserved_0x08; 1238 register8_t reserved_0x09; 1239 register8_t reserved_0x0A; 1240 register8_t reserved_0x0B; 1241 _WORDREGISTER(CAL); /* Calibration Value */ 1242 register8_t reserved_0x0E; 1243 register8_t reserved_0x0F; 1244 _WORDREGISTER(CH0RES); /* Channel 0 Result */ 1245 _WORDREGISTER(CH1RES); /* Channel 1 Result */ 1246 _WORDREGISTER(CH2RES); /* Channel 2 Result */ 1247 _WORDREGISTER(CH3RES); /* Channel 3 Result */ 1248 _WORDREGISTER(CMP); /* Compare Value */ 1249 register8_t reserved_0x1A; 1250 register8_t reserved_0x1B; 1251 register8_t reserved_0x1C; 1252 register8_t reserved_0x1D; 1253 register8_t reserved_0x1E; 1254 register8_t reserved_0x1F; 1255 ADC_CH_t CH0; /* ADC Channel 0 */ 1256 ADC_CH_t CH1; /* ADC Channel 1 */ 1257 ADC_CH_t CH2; /* ADC Channel 2 */ 1258 ADC_CH_t CH3; /* ADC Channel 3 */ 1259 } ADC_t; 1260 1261 /* Positive input multiplexer selection */ 1262 typedef enum ADC_CH_MUXPOS_enum 1263 { 1264 ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ 1265 ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ 1266 ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ 1267 ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ 1268 ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ 1269 ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ 1270 ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ 1271 ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ 1272 ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ 1273 ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ 1274 ADC_CH_MUXPOS_PIN10_gc = (0x10<<3), /* Input pin 10 */ 1275 ADC_CH_MUXPOS_PIN11_gc = (0x11<<3), /* Input pin 11 */ 1276 } ADC_CH_MUXPOS_t; 1277 1278 /* Internal input multiplexer selections */ 1279 typedef enum ADC_CH_MUXINT_enum 1280 { 1281 ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ 1282 ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ 1283 ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ 1284 ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ 1285 } ADC_CH_MUXINT_t; 1286 1287 /* Negative input multiplexer selection */ 1288 typedef enum ADC_CH_MUXNEG_enum 1289 { 1290 ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ 1291 ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ 1292 ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ 1293 ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ 1294 ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ 1295 ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ 1296 ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ 1297 ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ 1298 } ADC_CH_MUXNEG_t; 1299 1300 /* Input mode */ 1301 typedef enum ADC_CH_INPUTMODE_enum 1302 { 1303 ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ 1304 ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ 1305 ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ 1306 ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ 1307 } ADC_CH_INPUTMODE_t; 1308 1309 /* Gain factor */ 1310 typedef enum ADC_CH_GAIN_enum 1311 { 1312 ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ 1313 ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ 1314 ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ 1315 ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ 1316 ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ 1317 ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ 1318 ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ 1319 } ADC_CH_GAIN_t; 1320 1321 /* Conversion result resolution */ 1322 typedef enum ADC_RESOLUTION_enum 1323 { 1324 ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ 1325 ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ 1326 ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ 1327 } ADC_RESOLUTION_t; 1328 1329 /* Voltage reference selection */ 1330 typedef enum ADC_REFSEL_enum 1331 { 1332 ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ 1333 ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ 1334 ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ 1335 ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ 1336 } ADC_REFSEL_t; 1337 1338 /* Channel sweep selection */ 1339 typedef enum ADC_SWEEP_enum 1340 { 1341 ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ 1342 ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ 1343 ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ 1344 ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ 1345 } ADC_SWEEP_t; 1346 1347 /* Event channel input selection */ 1348 typedef enum ADC_EVSEL_enum 1349 { 1350 ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ 1351 ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ 1352 ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ 1353 ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ 1354 ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ 1355 ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ 1356 ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ 1357 ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ 1358 } ADC_EVSEL_t; 1359 1360 /* Event action selection */ 1361 typedef enum ADC_EVACT_enum 1362 { 1363 ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ 1364 ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ 1365 ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ 1366 ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ 1367 ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ 1368 ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ 1369 ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ 1370 } ADC_EVACT_t; 1371 1372 /* Interupt mode */ 1373 typedef enum ADC_CH_INTMODE_enum 1374 { 1375 ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ 1376 ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ 1377 ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ 1378 } ADC_CH_INTMODE_t; 1379 1380 /* Interrupt level */ 1381 typedef enum ADC_CH_INTLVL_enum 1382 { 1383 ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1384 ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ 1385 ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ 1386 ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ 1387 } ADC_CH_INTLVL_t; 1388 1389 /* DMA request selection */ 1390 typedef enum ADC_DMASEL_enum 1391 { 1392 ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ 1393 ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ 1394 ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ 1395 ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ 1396 } ADC_DMASEL_t; 1397 1398 /* Clock prescaler */ 1399 typedef enum ADC_PRESCALER_enum 1400 { 1401 ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ 1402 ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ 1403 ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ 1404 ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ 1405 ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ 1406 ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ 1407 ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ 1408 ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ 1409 } ADC_PRESCALER_t; 1410 1411 1412 /* 1413 -------------------------------------------------------------------------- 1414 DAC - Digital/Analog Converter 1415 -------------------------------------------------------------------------- 1416 */ 1417 1418 /* Digital-to-Analog Converter */ 1419 typedef struct DAC_struct 1420 { 1421 register8_t CTRLA; /* Control Register A */ 1422 register8_t CTRLB; /* Control Register B */ 1423 register8_t CTRLC; /* Control Register C */ 1424 register8_t EVCTRL; /* Event Input Control */ 1425 register8_t TIMCTRL; /* Timing Control */ 1426 register8_t STATUS; /* Status */ 1427 register8_t reserved_0x06; 1428 register8_t reserved_0x07; 1429 register8_t GAINCAL; /* Gain Calibration */ 1430 register8_t OFFSETCAL; /* Offset Calibration */ 1431 register8_t reserved_0x0A; 1432 register8_t reserved_0x0B; 1433 register8_t reserved_0x0C; 1434 register8_t reserved_0x0D; 1435 register8_t reserved_0x0E; 1436 register8_t reserved_0x0F; 1437 register8_t reserved_0x10; 1438 register8_t reserved_0x11; 1439 register8_t reserved_0x12; 1440 register8_t reserved_0x13; 1441 register8_t reserved_0x14; 1442 register8_t reserved_0x15; 1443 register8_t reserved_0x16; 1444 register8_t reserved_0x17; 1445 _WORDREGISTER(CH0DATA); /* Channel 0 Data */ 1446 _WORDREGISTER(CH1DATA); /* Channel 1 Data */ 1447 } DAC_t; 1448 1449 /* Output channel selection */ 1450 typedef enum DAC_CHSEL_enum 1451 { 1452 DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ 1453 DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ 1454 } DAC_CHSEL_t; 1455 1456 /* Reference voltage selection */ 1457 typedef enum DAC_REFSEL_enum 1458 { 1459 DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ 1460 DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ 1461 DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ 1462 DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ 1463 } DAC_REFSEL_t; 1464 1465 /* Event channel selection */ 1466 typedef enum DAC_EVSEL_enum 1467 { 1468 DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ 1469 DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ 1470 DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ 1471 DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ 1472 DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ 1473 DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ 1474 DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ 1475 DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ 1476 } DAC_EVSEL_t; 1477 1478 /* Conversion interval */ 1479 typedef enum DAC_CONINTVAL_enum 1480 { 1481 DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ 1482 DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ 1483 DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ 1484 DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ 1485 DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ 1486 DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ 1487 DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ 1488 DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ 1489 } DAC_CONINTVAL_t; 1490 1491 /* Refresh rate */ 1492 typedef enum DAC_REFRESH_enum 1493 { 1494 DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ 1495 DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ 1496 DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ 1497 DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ 1498 DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ 1499 DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ 1500 DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ 1501 DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ 1502 DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ 1503 DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ 1504 DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ 1505 DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ 1506 DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ 1507 DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ 1508 } DAC_REFRESH_t; 1509 1510 1511 /* 1512 -------------------------------------------------------------------------- 1513 RTC - Real-Time Clounter 1514 -------------------------------------------------------------------------- 1515 */ 1516 1517 /* Real-Time Counter */ 1518 typedef struct RTC_struct 1519 { 1520 register8_t CTRL; /* Control Register */ 1521 register8_t STATUS; /* Status Register */ 1522 register8_t INTCTRL; /* Interrupt Control Register */ 1523 register8_t INTFLAGS; /* Interrupt Flags */ 1524 register8_t TEMP; /* Temporary register */ 1525 register8_t reserved_0x05; 1526 register8_t reserved_0x06; 1527 register8_t reserved_0x07; 1528 _WORDREGISTER(CNT); /* Count Register */ 1529 _WORDREGISTER(PER); /* Period Register */ 1530 _WORDREGISTER(COMP); /* Compare Register */ 1531 } RTC_t; 1532 1533 /* Prescaler Factor */ 1534 typedef enum RTC_PRESCALER_enum 1535 { 1536 RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ 1537 RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ 1538 RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ 1539 RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ 1540 RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ 1541 RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ 1542 RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ 1543 RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ 1544 } RTC_PRESCALER_t; 1545 1546 /* Compare Interrupt level */ 1547 typedef enum RTC_COMPINTLVL_enum 1548 { 1549 RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1550 RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1551 RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1552 RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ 1553 } RTC_COMPINTLVL_t; 1554 1555 /* Overflow Interrupt level */ 1556 typedef enum RTC_OVFINTLVL_enum 1557 { 1558 RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1559 RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1560 RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1561 RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ 1562 } RTC_OVFINTLVL_t; 1563 1564 1565 /* 1566 -------------------------------------------------------------------------- 1567 EBI - External Bus Interface 1568 -------------------------------------------------------------------------- 1569 */ 1570 1571 /* EBI Chip Select Module */ 1572 typedef struct EBI_CS_struct 1573 { 1574 register8_t CTRLA; /* Chip Select Control Register A */ 1575 register8_t CTRLB; /* Chip Select Control Register B */ 1576 _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ 1577 } EBI_CS_t; 1578 1579 /* 1580 -------------------------------------------------------------------------- 1581 EBI - External Bus Interface 1582 -------------------------------------------------------------------------- 1583 */ 1584 1585 /* External Bus Interface */ 1586 typedef struct EBI_struct 1587 { 1588 register8_t CTRL; /* Control */ 1589 register8_t SDRAMCTRLA; /* SDRAM Control Register A */ 1590 register8_t reserved_0x02; 1591 register8_t reserved_0x03; 1592 _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ 1593 _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ 1594 register8_t SDRAMCTRLB; /* SDRAM Control Register B */ 1595 register8_t SDRAMCTRLC; /* SDRAM Control Register C */ 1596 register8_t reserved_0x0A; 1597 register8_t reserved_0x0B; 1598 register8_t reserved_0x0C; 1599 register8_t reserved_0x0D; 1600 register8_t reserved_0x0E; 1601 register8_t reserved_0x0F; 1602 EBI_CS_t CS0; /* Chip Select 0 */ 1603 EBI_CS_t CS1; /* Chip Select 1 */ 1604 EBI_CS_t CS2; /* Chip Select 2 */ 1605 EBI_CS_t CS3; /* Chip Select 3 */ 1606 } EBI_t; 1607 1608 /* Chip Select adress space */ 1609 typedef enum EBI_CS_ASIZE_enum 1610 { 1611 EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ 1612 EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ 1613 EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ 1614 EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ 1615 EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ 1616 EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ 1617 EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ 1618 EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ 1619 EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ 1620 EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ 1621 EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ 1622 EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ 1623 EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ 1624 EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ 1625 EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ 1626 EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ 1627 EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ 1628 } EBI_CS_ASIZE_t; 1629 1630 /* */ 1631 typedef enum EBI_CS_SRWS_enum 1632 { 1633 EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ 1634 EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ 1635 EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ 1636 EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ 1637 EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ 1638 EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ 1639 EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ 1640 EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ 1641 } EBI_CS_SRWS_t; 1642 1643 /* Chip Select address mode */ 1644 typedef enum EBI_CS_MODE_enum 1645 { 1646 EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ 1647 EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ 1648 EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ 1649 EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ 1650 } EBI_CS_MODE_t; 1651 1652 /* Chip Select SDRAM mode */ 1653 typedef enum EBI_CS_SDMODE_enum 1654 { 1655 EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ 1656 EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ 1657 } EBI_CS_SDMODE_t; 1658 1659 /* */ 1660 typedef enum EBI_SDDATAW_enum 1661 { 1662 EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ 1663 EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ 1664 } EBI_SDDATAW_t; 1665 1666 /* */ 1667 typedef enum EBI_LPCMODE_enum 1668 { 1669 EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ 1670 EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ 1671 } EBI_LPCMODE_t; 1672 1673 /* */ 1674 typedef enum EBI_SRMODE_enum 1675 { 1676 EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ 1677 EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ 1678 EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ 1679 EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ 1680 } EBI_SRMODE_t; 1681 1682 /* */ 1683 typedef enum EBI_IFMODE_enum 1684 { 1685 EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ 1686 EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ 1687 EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ 1688 EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ 1689 } EBI_IFMODE_t; 1690 1691 /* */ 1692 typedef enum EBI_SDCOL_enum 1693 { 1694 EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ 1695 EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ 1696 EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ 1697 EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ 1698 } EBI_SDCOL_t; 1699 1700 /* */ 1701 typedef enum EBI_MRDLY_enum 1702 { 1703 EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ 1704 EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ 1705 EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ 1706 EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ 1707 } EBI_MRDLY_t; 1708 1709 /* */ 1710 typedef enum EBI_ROWCYCDLY_enum 1711 { 1712 EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ 1713 EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ 1714 EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ 1715 EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ 1716 EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ 1717 EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ 1718 EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ 1719 EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ 1720 } EBI_ROWCYCDLY_t; 1721 1722 /* */ 1723 typedef enum EBI_RPDLY_enum 1724 { 1725 EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ 1726 EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ 1727 EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ 1728 EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ 1729 EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ 1730 EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ 1731 EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ 1732 EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ 1733 } EBI_RPDLY_t; 1734 1735 /* */ 1736 typedef enum EBI_WRDLY_enum 1737 { 1738 EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ 1739 EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ 1740 EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ 1741 EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ 1742 } EBI_WRDLY_t; 1743 1744 /* */ 1745 typedef enum EBI_ESRDLY_enum 1746 { 1747 EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ 1748 EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ 1749 EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ 1750 EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ 1751 EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ 1752 EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ 1753 EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ 1754 EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ 1755 } EBI_ESRDLY_t; 1756 1757 /* */ 1758 typedef enum EBI_ROWCOLDLY_enum 1759 { 1760 EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ 1761 EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ 1762 EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ 1763 EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ 1764 EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ 1765 EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ 1766 EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ 1767 EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ 1768 } EBI_ROWCOLDLY_t; 1769 1770 1771 /* 1772 -------------------------------------------------------------------------- 1773 TWI - Two-Wire Interface 1774 -------------------------------------------------------------------------- 1775 */ 1776 1777 /* */ 1778 typedef struct TWI_MASTER_struct 1779 { 1780 register8_t CTRLA; /* Control Register A */ 1781 register8_t CTRLB; /* Control Register B */ 1782 register8_t CTRLC; /* Control Register C */ 1783 register8_t STATUS; /* Status Register */ 1784 register8_t BAUD; /* Baurd Rate Control Register */ 1785 register8_t ADDR; /* Address Register */ 1786 register8_t DATA; /* Data Register */ 1787 } TWI_MASTER_t; 1788 1789 /* 1790 -------------------------------------------------------------------------- 1791 TWI - Two-Wire Interface 1792 -------------------------------------------------------------------------- 1793 */ 1794 1795 /* */ 1796 typedef struct TWI_SLAVE_struct 1797 { 1798 register8_t CTRLA; /* Control Register A */ 1799 register8_t CTRLB; /* Control Register B */ 1800 register8_t STATUS; /* Status Register */ 1801 register8_t ADDR; /* Address Register */ 1802 register8_t DATA; /* Data Register */ 1803 register8_t ADDRMASK; /* Address Mask Register */ 1804 } TWI_SLAVE_t; 1805 1806 /* 1807 -------------------------------------------------------------------------- 1808 TWI - Two-Wire Interface 1809 -------------------------------------------------------------------------- 1810 */ 1811 1812 /* Two-Wire Interface */ 1813 typedef struct TWI_struct 1814 { 1815 register8_t CTRL; /* TWI Common Control Register */ 1816 TWI_MASTER_t MASTER; /* TWI master module */ 1817 TWI_SLAVE_t SLAVE; /* TWI slave module */ 1818 } TWI_t; 1819 1820 /* Master Interrupt Level */ 1821 typedef enum TWI_MASTER_INTLVL_enum 1822 { 1823 TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1824 TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ 1825 TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1826 TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ 1827 } TWI_MASTER_INTLVL_t; 1828 1829 /* Inactive Timeout */ 1830 typedef enum TWI_MASTER_TIMEOUT_enum 1831 { 1832 TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ 1833 TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ 1834 TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ 1835 TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ 1836 } TWI_MASTER_TIMEOUT_t; 1837 1838 /* Master Command */ 1839 typedef enum TWI_MASTER_CMD_enum 1840 { 1841 TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ 1842 TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ 1843 TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ 1844 TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ 1845 } TWI_MASTER_CMD_t; 1846 1847 /* Master Bus State */ 1848 typedef enum TWI_MASTER_BUSSTATE_enum 1849 { 1850 TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ 1851 TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ 1852 TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ 1853 TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ 1854 } TWI_MASTER_BUSSTATE_t; 1855 1856 /* Slave Interrupt Level */ 1857 typedef enum TWI_SLAVE_INTLVL_enum 1858 { 1859 TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1860 TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ 1861 TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1862 TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ 1863 } TWI_SLAVE_INTLVL_t; 1864 1865 /* Slave Command */ 1866 typedef enum TWI_SLAVE_CMD_enum 1867 { 1868 TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ 1869 TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ 1870 TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ 1871 } TWI_SLAVE_CMD_t; 1872 1873 1874 /* 1875 -------------------------------------------------------------------------- 1876 PORT - Port Configuration 1877 -------------------------------------------------------------------------- 1878 */ 1879 1880 /* I/O port Configuration */ 1881 typedef struct PORTCFG_struct 1882 { 1883 register8_t MPCMASK; /* Multi-pin Configuration Mask */ 1884 register8_t reserved_0x01; 1885 register8_t VPCTRLA; /* Virtual Port Control Register A */ 1886 register8_t VPCTRLB; /* Virtual Port Control Register B */ 1887 register8_t CLKEVOUT; /* Clock and Event Out Register */ 1888 } PORTCFG_t; 1889 1890 /* 1891 -------------------------------------------------------------------------- 1892 PORT - Port Configuration 1893 -------------------------------------------------------------------------- 1894 */ 1895 1896 /* Virtual Port */ 1897 typedef struct VPORT_struct 1898 { 1899 register8_t DIR; /* I/O Port Data Direction */ 1900 register8_t OUT; /* I/O Port Output */ 1901 register8_t IN; /* I/O Port Input */ 1902 register8_t INTFLAGS; /* Interrupt Flag Register */ 1903 } VPORT_t; 1904 1905 /* 1906 -------------------------------------------------------------------------- 1907 PORT - Port Configuration 1908 -------------------------------------------------------------------------- 1909 */ 1910 1911 /* I/O Ports */ 1912 typedef struct PORT_struct 1913 { 1914 register8_t DIR; /* I/O Port Data Direction */ 1915 register8_t DIRSET; /* I/O Port Data Direction Set */ 1916 register8_t DIRCLR; /* I/O Port Data Direction Clear */ 1917 register8_t DIRTGL; /* I/O Port Data Direction Toggle */ 1918 register8_t OUT; /* I/O Port Output */ 1919 register8_t OUTSET; /* I/O Port Output Set */ 1920 register8_t OUTCLR; /* I/O Port Output Clear */ 1921 register8_t OUTTGL; /* I/O Port Output Toggle */ 1922 register8_t IN; /* I/O port Input */ 1923 register8_t INTCTRL; /* Interrupt Control Register */ 1924 register8_t INT0MASK; /* Port Interrupt 0 Mask */ 1925 register8_t INT1MASK; /* Port Interrupt 1 Mask */ 1926 register8_t INTFLAGS; /* Interrupt Flag Register */ 1927 register8_t reserved_0x0D; 1928 register8_t reserved_0x0E; 1929 register8_t reserved_0x0F; 1930 register8_t PIN0CTRL; /* Pin 0 Control Register */ 1931 register8_t PIN1CTRL; /* Pin 1 Control Register */ 1932 register8_t PIN2CTRL; /* Pin 2 Control Register */ 1933 register8_t PIN3CTRL; /* Pin 3 Control Register */ 1934 register8_t PIN4CTRL; /* Pin 4 Control Register */ 1935 register8_t PIN5CTRL; /* Pin 5 Control Register */ 1936 register8_t PIN6CTRL; /* Pin 6 Control Register */ 1937 register8_t PIN7CTRL; /* Pin 7 Control Register */ 1938 } PORT_t; 1939 1940 /* Virtual Port 0 Mapping */ 1941 typedef enum PORTCFG_VP0MAP_enum 1942 { 1943 PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ 1944 PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ 1945 PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ 1946 PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ 1947 PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ 1948 PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ 1949 PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ 1950 PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ 1951 PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ 1952 PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ 1953 PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ 1954 PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ 1955 PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ 1956 PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ 1957 PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ 1958 PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ 1959 } PORTCFG_VP0MAP_t; 1960 1961 /* Virtual Port 1 Mapping */ 1962 typedef enum PORTCFG_VP1MAP_enum 1963 { 1964 PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ 1965 PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ 1966 PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ 1967 PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ 1968 PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ 1969 PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ 1970 PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ 1971 PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ 1972 PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ 1973 PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ 1974 PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ 1975 PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ 1976 PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ 1977 PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ 1978 PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ 1979 PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ 1980 } PORTCFG_VP1MAP_t; 1981 1982 /* Virtual Port 2 Mapping */ 1983 typedef enum PORTCFG_VP2MAP_enum 1984 { 1985 PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ 1986 PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ 1987 PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ 1988 PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ 1989 PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ 1990 PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ 1991 PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ 1992 PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ 1993 PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ 1994 PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ 1995 PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ 1996 PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ 1997 PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ 1998 PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ 1999 PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ 2000 PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ 2001 } PORTCFG_VP2MAP_t; 2002 2003 /* Virtual Port 3 Mapping */ 2004 typedef enum PORTCFG_VP3MAP_enum 2005 { 2006 PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ 2007 PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ 2008 PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ 2009 PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ 2010 PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ 2011 PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ 2012 PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ 2013 PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ 2014 PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ 2015 PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ 2016 PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ 2017 PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ 2018 PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ 2019 PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ 2020 PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ 2021 PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ 2022 } PORTCFG_VP3MAP_t; 2023 2024 /* Clock Output Port */ 2025 typedef enum PORTCFG_CLKOUT_enum 2026 { 2027 PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ 2028 PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ 2029 PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ 2030 PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ 2031 } PORTCFG_CLKOUT_t; 2032 2033 /* Event Output Port */ 2034 typedef enum PORTCFG_EVOUT_enum 2035 { 2036 PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ 2037 PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ 2038 PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ 2039 PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ 2040 } PORTCFG_EVOUT_t; 2041 2042 /* Port Interrupt 0 Level */ 2043 typedef enum PORT_INT0LVL_enum 2044 { 2045 PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2046 PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ 2047 PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ 2048 PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ 2049 } PORT_INT0LVL_t; 2050 2051 /* Port Interrupt 1 Level */ 2052 typedef enum PORT_INT1LVL_enum 2053 { 2054 PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 2055 PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ 2056 PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ 2057 PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ 2058 } PORT_INT1LVL_t; 2059 2060 /* Output/Pull Configuration */ 2061 typedef enum PORT_OPC_enum 2062 { 2063 PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ 2064 PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ 2065 PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ 2066 PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ 2067 PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ 2068 PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ 2069 PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ 2070 PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ 2071 } PORT_OPC_t; 2072 2073 /* Input/Sense Configuration */ 2074 typedef enum PORT_ISC_enum 2075 { 2076 PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ 2077 PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ 2078 PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ 2079 PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ 2080 PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ 2081 } PORT_ISC_t; 2082 2083 2084 /* 2085 -------------------------------------------------------------------------- 2086 TC - 16-bit Timer/Counter With PWM 2087 -------------------------------------------------------------------------- 2088 */ 2089 2090 /* 16-bit Timer/Counter 0 */ 2091 typedef struct TC0_struct 2092 { 2093 register8_t CTRLA; /* Control Register A */ 2094 register8_t CTRLB; /* Control Register B */ 2095 register8_t CTRLC; /* Control register C */ 2096 register8_t CTRLD; /* Control Register D */ 2097 register8_t CTRLE; /* Control Register E */ 2098 register8_t reserved_0x05; 2099 register8_t INTCTRLA; /* Interrupt Control Register A */ 2100 register8_t INTCTRLB; /* Interrupt Control Register B */ 2101 register8_t CTRLFCLR; /* Control Register F Clear */ 2102 register8_t CTRLFSET; /* Control Register F Set */ 2103 register8_t CTRLGCLR; /* Control Register G Clear */ 2104 register8_t CTRLGSET; /* Control Register G Set */ 2105 register8_t INTFLAGS; /* Interrupt Flag Register */ 2106 register8_t reserved_0x0D; 2107 register8_t reserved_0x0E; 2108 register8_t TEMP; /* Temporary Register For 16-bit Access */ 2109 register8_t reserved_0x10; 2110 register8_t reserved_0x11; 2111 register8_t reserved_0x12; 2112 register8_t reserved_0x13; 2113 register8_t reserved_0x14; 2114 register8_t reserved_0x15; 2115 register8_t reserved_0x16; 2116 register8_t reserved_0x17; 2117 register8_t reserved_0x18; 2118 register8_t reserved_0x19; 2119 register8_t reserved_0x1A; 2120 register8_t reserved_0x1B; 2121 register8_t reserved_0x1C; 2122 register8_t reserved_0x1D; 2123 register8_t reserved_0x1E; 2124 register8_t reserved_0x1F; 2125 _WORDREGISTER(CNT); /* Count */ 2126 register8_t reserved_0x22; 2127 register8_t reserved_0x23; 2128 register8_t reserved_0x24; 2129 register8_t reserved_0x25; 2130 _WORDREGISTER(PER); /* Period */ 2131 _WORDREGISTER(CCA); /* Compare or Capture A */ 2132 _WORDREGISTER(CCB); /* Compare or Capture B */ 2133 _WORDREGISTER(CCC); /* Compare or Capture C */ 2134 _WORDREGISTER(CCD); /* Compare or Capture D */ 2135 register8_t reserved_0x30; 2136 register8_t reserved_0x31; 2137 register8_t reserved_0x32; 2138 register8_t reserved_0x33; 2139 register8_t reserved_0x34; 2140 register8_t reserved_0x35; 2141 _WORDREGISTER(PERBUF); /* Period Buffer */ 2142 _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ 2143 _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ 2144 _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ 2145 _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ 2146 } TC0_t; 2147 2148 /* 2149 -------------------------------------------------------------------------- 2150 TC - 16-bit Timer/Counter With PWM 2151 -------------------------------------------------------------------------- 2152 */ 2153 2154 /* 16-bit Timer/Counter 1 */ 2155 typedef struct TC1_struct 2156 { 2157 register8_t CTRLA; /* Control Register A */ 2158 register8_t CTRLB; /* Control Register B */ 2159 register8_t CTRLC; /* Control register C */ 2160 register8_t CTRLD; /* Control Register D */ 2161 register8_t CTRLE; /* Control Register E */ 2162 register8_t reserved_0x05; 2163 register8_t INTCTRLA; /* Interrupt Control Register A */ 2164 register8_t INTCTRLB; /* Interrupt Control Register B */ 2165 register8_t CTRLFCLR; /* Control Register F Clear */ 2166 register8_t CTRLFSET; /* Control Register F Set */ 2167 register8_t CTRLGCLR; /* Control Register G Clear */ 2168 register8_t CTRLGSET; /* Control Register G Set */ 2169 register8_t INTFLAGS; /* Interrupt Flag Register */ 2170 register8_t reserved_0x0D; 2171 register8_t reserved_0x0E; 2172 register8_t TEMP; /* Temporary Register For 16-bit Access */ 2173 register8_t reserved_0x10; 2174 register8_t reserved_0x11; 2175 register8_t reserved_0x12; 2176 register8_t reserved_0x13; 2177 register8_t reserved_0x14; 2178 register8_t reserved_0x15; 2179 register8_t reserved_0x16; 2180 register8_t reserved_0x17; 2181 register8_t reserved_0x18; 2182 register8_t reserved_0x19; 2183 register8_t reserved_0x1A; 2184 register8_t reserved_0x1B; 2185 register8_t reserved_0x1C; 2186 register8_t reserved_0x1D; 2187 register8_t reserved_0x1E; 2188 register8_t reserved_0x1F; 2189 _WORDREGISTER(CNT); /* Count */ 2190 register8_t reserved_0x22; 2191 register8_t reserved_0x23; 2192 register8_t reserved_0x24; 2193 register8_t reserved_0x25; 2194 _WORDREGISTER(PER); /* Period */ 2195 _WORDREGISTER(CCA); /* Compare or Capture A */ 2196 _WORDREGISTER(CCB); /* Compare or Capture B */ 2197 register8_t reserved_0x2C; 2198 register8_t reserved_0x2D; 2199 register8_t reserved_0x2E; 2200 register8_t reserved_0x2F; 2201 register8_t reserved_0x30; 2202 register8_t reserved_0x31; 2203 register8_t reserved_0x32; 2204 register8_t reserved_0x33; 2205 register8_t reserved_0x34; 2206 register8_t reserved_0x35; 2207 _WORDREGISTER(PERBUF); /* Period Buffer */ 2208 _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ 2209 _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ 2210 } TC1_t; 2211 2212 /* 2213 -------------------------------------------------------------------------- 2214 TC - 16-bit Timer/Counter With PWM 2215 -------------------------------------------------------------------------- 2216 */ 2217 2218 /* Advanced Waveform Extension */ 2219 typedef struct AWEX_struct 2220 { 2221 register8_t CTRL; /* Control Register */ 2222 register8_t reserved_0x01; 2223 register8_t FDEMASK; /* Fault Detection Event Mask */ 2224 register8_t FDCTRL; /* Fault Detection Control Register */ 2225 register8_t STATUS; /* Status Register */ 2226 register8_t reserved_0x05; 2227 register8_t DTBOTH; /* Dead Time Both Sides */ 2228 register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ 2229 register8_t DTLS; /* Dead Time Low Side */ 2230 register8_t DTHS; /* Dead Time High Side */ 2231 register8_t DTLSBUF; /* Dead Time Low Side Buffer */ 2232 register8_t DTHSBUF; /* Dead Time High Side Buffer */ 2233 register8_t OUTOVEN; /* Output Override Enable */ 2234 } AWEX_t; 2235 2236 /* 2237 -------------------------------------------------------------------------- 2238 TC - 16-bit Timer/Counter With PWM 2239 -------------------------------------------------------------------------- 2240 */ 2241 2242 /* High-Resolution Extension */ 2243 typedef struct HIRES_struct 2244 { 2245 register8_t CTRLA; /* Control Register */ 2246 } HIRES_t; 2247 2248 /* Clock Selection */ 2249 typedef enum TC_CLKSEL_enum 2250 { 2251 TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ 2252 TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ 2253 TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ 2254 TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ 2255 TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ 2256 TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ 2257 TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ 2258 TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ 2259 TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ 2260 TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ 2261 TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ 2262 TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ 2263 TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ 2264 TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ 2265 TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ 2266 TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ 2267 } TC_CLKSEL_t; 2268 2269 /* Waveform Generation Mode */ 2270 typedef enum TC_WGMODE_enum 2271 { 2272 TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ 2273 TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ 2274 TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ 2275 TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ 2276 TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ 2277 TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ 2278 } TC_WGMODE_t; 2279 2280 /* Event Action */ 2281 typedef enum TC_EVACT_enum 2282 { 2283 TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ 2284 TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ 2285 TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ 2286 TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ 2287 TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ 2288 TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ 2289 TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ 2290 TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ 2291 } TC_EVACT_t; 2292 2293 /* Event Selection */ 2294 typedef enum TC_EVSEL_enum 2295 { 2296 TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ 2297 TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ 2298 TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ 2299 TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ 2300 TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ 2301 TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ 2302 TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ 2303 TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ 2304 TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ 2305 } TC_EVSEL_t; 2306 2307 /* Error Interrupt Level */ 2308 typedef enum TC_ERRINTLVL_enum 2309 { 2310 TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 2311 TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ 2312 TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 2313 TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ 2314 } TC_ERRINTLVL_t; 2315 2316 /* Overflow Interrupt Level */ 2317 typedef enum TC_OVFINTLVL_enum 2318 { 2319 TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2320 TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 2321 TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2322 TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ 2323 } TC_OVFINTLVL_t; 2324 2325 /* Compare or Capture D Interrupt Level */ 2326 typedef enum TC_CCDINTLVL_enum 2327 { 2328 TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 2329 TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ 2330 TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ 2331 TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ 2332 } TC_CCDINTLVL_t; 2333 2334 /* Compare or Capture C Interrupt Level */ 2335 typedef enum TC_CCCINTLVL_enum 2336 { 2337 TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 2338 TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 2339 TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 2340 TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ 2341 } TC_CCCINTLVL_t; 2342 2343 /* Compare or Capture B Interrupt Level */ 2344 typedef enum TC_CCBINTLVL_enum 2345 { 2346 TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 2347 TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ 2348 TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 2349 TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ 2350 } TC_CCBINTLVL_t; 2351 2352 /* Compare or Capture A Interrupt Level */ 2353 typedef enum TC_CCAINTLVL_enum 2354 { 2355 TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2356 TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ 2357 TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2358 TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ 2359 } TC_CCAINTLVL_t; 2360 2361 /* Timer/Counter Command */ 2362 typedef enum TC_CMD_enum 2363 { 2364 TC_CMD_NONE_gc = (0x00<<2), /* No Command */ 2365 TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ 2366 TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ 2367 TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ 2368 } TC_CMD_t; 2369 2370 /* Fault Detect Action */ 2371 typedef enum AWEX_FDACT_enum 2372 { 2373 AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ 2374 AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ 2375 AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ 2376 } AWEX_FDACT_t; 2377 2378 /* High Resolution Enable */ 2379 typedef enum HIRES_HREN_enum 2380 { 2381 HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ 2382 HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ 2383 HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ 2384 HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ 2385 } HIRES_HREN_t; 2386 2387 2388 /* 2389 -------------------------------------------------------------------------- 2390 USART - Universal Asynchronous Receiver-Transmitter 2391 -------------------------------------------------------------------------- 2392 */ 2393 2394 /* Universal Synchronous/Asynchronous Receiver/Transmitter */ 2395 typedef struct USART_struct 2396 { 2397 register8_t DATA; /* Data Register */ 2398 register8_t STATUS; /* Status Register */ 2399 register8_t reserved_0x02; 2400 register8_t CTRLA; /* Control Register A */ 2401 register8_t CTRLB; /* Control Register B */ 2402 register8_t CTRLC; /* Control Register C */ 2403 register8_t BAUDCTRLA; /* Baud Rate Control Register A */ 2404 register8_t BAUDCTRLB; /* Baud Rate Control Register B */ 2405 } USART_t; 2406 2407 /* Receive Complete Interrupt level */ 2408 typedef enum USART_RXCINTLVL_enum 2409 { 2410 USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 2411 USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 2412 USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 2413 USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ 2414 } USART_RXCINTLVL_t; 2415 2416 /* Transmit Complete Interrupt level */ 2417 typedef enum USART_TXCINTLVL_enum 2418 { 2419 USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 2420 USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ 2421 USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 2422 USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ 2423 } USART_TXCINTLVL_t; 2424 2425 /* Data Register Empty Interrupt level */ 2426 typedef enum USART_DREINTLVL_enum 2427 { 2428 USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2429 USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ 2430 USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2431 USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ 2432 } USART_DREINTLVL_t; 2433 2434 /* Character Size */ 2435 typedef enum USART_CHSIZE_enum 2436 { 2437 USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ 2438 USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ 2439 USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ 2440 USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ 2441 USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ 2442 } USART_CHSIZE_t; 2443 2444 /* Communication Mode */ 2445 typedef enum USART_CMODE_enum 2446 { 2447 USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ 2448 USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ 2449 USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ 2450 USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ 2451 } USART_CMODE_t; 2452 2453 /* Parity Mode */ 2454 typedef enum USART_PMODE_enum 2455 { 2456 USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ 2457 USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ 2458 USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ 2459 } USART_PMODE_t; 2460 2461 2462 /* 2463 -------------------------------------------------------------------------- 2464 SPI - Serial Peripheral Interface 2465 -------------------------------------------------------------------------- 2466 */ 2467 2468 /* Serial Peripheral Interface */ 2469 typedef struct SPI_struct 2470 { 2471 register8_t CTRL; /* Control Register */ 2472 register8_t INTCTRL; /* Interrupt Control Register */ 2473 register8_t STATUS; /* Status Register */ 2474 register8_t DATA; /* Data Register */ 2475 } SPI_t; 2476 2477 /* SPI Mode */ 2478 typedef enum SPI_MODE_enum 2479 { 2480 SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ 2481 SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ 2482 SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ 2483 SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ 2484 } SPI_MODE_t; 2485 2486 /* Prescaler setting */ 2487 typedef enum SPI_PRESCALER_enum 2488 { 2489 SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ 2490 SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ 2491 SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ 2492 SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ 2493 } SPI_PRESCALER_t; 2494 2495 /* Interrupt level */ 2496 typedef enum SPI_INTLVL_enum 2497 { 2498 SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2499 SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ 2500 SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2501 SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ 2502 } SPI_INTLVL_t; 2503 2504 2505 /* 2506 -------------------------------------------------------------------------- 2507 IRCOM - IR Communication Module 2508 -------------------------------------------------------------------------- 2509 */ 2510 2511 /* IR Communication Module */ 2512 typedef struct IRCOM_struct 2513 { 2514 register8_t CTRL; /* Control Register */ 2515 register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ 2516 register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ 2517 } IRCOM_t; 2518 2519 /* Event channel selection */ 2520 typedef enum IRDA_EVSEL_enum 2521 { 2522 IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ 2523 IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ 2524 IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ 2525 IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ 2526 IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ 2527 IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ 2528 IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ 2529 IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ 2530 IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ 2531 } IRDA_EVSEL_t; 2532 2533 2534 /* 2535 -------------------------------------------------------------------------- 2536 AES - AES Module 2537 -------------------------------------------------------------------------- 2538 */ 2539 2540 /* AES Module */ 2541 typedef struct AES_struct 2542 { 2543 register8_t CTRL; /* AES Control Register */ 2544 register8_t STATUS; /* AES Status Register */ 2545 register8_t STATE; /* AES State Register */ 2546 register8_t KEY; /* AES Key Register */ 2547 register8_t INTCTRL; /* AES Interrupt Control Register */ 2548 } AES_t; 2549 2550 /* Interrupt level */ 2551 typedef enum AES_INTLVL_enum 2552 { 2553 AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2554 AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ 2555 AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2556 AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ 2557 } AES_INTLVL_t; 2558 2559 2560 2561 /* 2562 ========================================================================== 2563 IO Module Instances. Mapped to memory. 2564 ========================================================================== 2565 */ 2566 2567 #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ 2568 #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ 2569 #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ 2570 #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ 2571 #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ 2572 #define CLK (*(CLK_t *) 0x0040) /* Clock System */ 2573 #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ 2574 #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ 2575 #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ 2576 #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ 2577 #define PR (*(PR_t *) 0x0070) /* Power Reduction */ 2578 #define RST (*(RST_t *) 0x0078) /* Reset Controller */ 2579 #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ 2580 #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ 2581 #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ 2582 #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ 2583 #define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ 2584 #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ 2585 #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ 2586 #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ 2587 #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ 2588 #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ 2589 #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ 2590 #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ 2591 #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ 2592 #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ 2593 #define PORTA (*(PORT_t *) 0x0600) /* Port A */ 2594 #define PORTB (*(PORT_t *) 0x0620) /* Port B */ 2595 #define PORTC (*(PORT_t *) 0x0640) /* Port C */ 2596 #define PORTD (*(PORT_t *) 0x0660) /* Port D */ 2597 #define PORTE (*(PORT_t *) 0x0680) /* Port E */ 2598 #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ 2599 #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ 2600 #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ 2601 #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ 2602 #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ 2603 #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ 2604 #define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ 2605 #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ 2606 #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ 2607 #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ 2608 #define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ 2609 #define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ 2610 #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ 2611 #define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ 2612 #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ 2613 #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ 2614 #define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ 2615 #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ 2616 2617 2618 #endif /* !defined (__ASSEMBLER__) */ 2619 2620 2621 /* ========== Flattened fully qualified IO register names ========== */ 2622 2623 /* GPIO - General Purpose IO Registers */ 2624 #define GPIO_GPIOR0 _SFR_MEM8(0x0000) 2625 #define GPIO_GPIOR1 _SFR_MEM8(0x0001) 2626 #define GPIO_GPIOR2 _SFR_MEM8(0x0002) 2627 #define GPIO_GPIOR3 _SFR_MEM8(0x0003) 2628 #define GPIO_GPIOR4 _SFR_MEM8(0x0004) 2629 #define GPIO_GPIOR5 _SFR_MEM8(0x0005) 2630 #define GPIO_GPIOR6 _SFR_MEM8(0x0006) 2631 #define GPIO_GPIOR7 _SFR_MEM8(0x0007) 2632 #define GPIO_GPIOR8 _SFR_MEM8(0x0008) 2633 #define GPIO_GPIOR9 _SFR_MEM8(0x0009) 2634 #define GPIO_GPIORA _SFR_MEM8(0x000A) 2635 #define GPIO_GPIORB _SFR_MEM8(0x000B) 2636 #define GPIO_GPIORC _SFR_MEM8(0x000C) 2637 #define GPIO_GPIORD _SFR_MEM8(0x000D) 2638 #define GPIO_GPIORE _SFR_MEM8(0x000E) 2639 #define GPIO_GPIORF _SFR_MEM8(0x000F) 2640 2641 /* Deprecated */ 2642 #define GPIO_GPIO0 _SFR_MEM8(0x0000) 2643 #define GPIO_GPIO1 _SFR_MEM8(0x0001) 2644 #define GPIO_GPIO2 _SFR_MEM8(0x0002) 2645 #define GPIO_GPIO3 _SFR_MEM8(0x0003) 2646 #define GPIO_GPIO4 _SFR_MEM8(0x0004) 2647 #define GPIO_GPIO5 _SFR_MEM8(0x0005) 2648 #define GPIO_GPIO6 _SFR_MEM8(0x0006) 2649 #define GPIO_GPIO7 _SFR_MEM8(0x0007) 2650 #define GPIO_GPIO8 _SFR_MEM8(0x0008) 2651 #define GPIO_GPIO9 _SFR_MEM8(0x0009) 2652 #define GPIO_GPIOA _SFR_MEM8(0x000A) 2653 #define GPIO_GPIOB _SFR_MEM8(0x000B) 2654 #define GPIO_GPIOC _SFR_MEM8(0x000C) 2655 #define GPIO_GPIOD _SFR_MEM8(0x000D) 2656 #define GPIO_GPIOE _SFR_MEM8(0x000E) 2657 #define GPIO_GPIOF _SFR_MEM8(0x000F) 2658 2659 /* VPORT0 - Virtual Port 0 */ 2660 #define VPORT0_DIR _SFR_MEM8(0x0010) 2661 #define VPORT0_OUT _SFR_MEM8(0x0011) 2662 #define VPORT0_IN _SFR_MEM8(0x0012) 2663 #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) 2664 2665 /* VPORT1 - Virtual Port 1 */ 2666 #define VPORT1_DIR _SFR_MEM8(0x0014) 2667 #define VPORT1_OUT _SFR_MEM8(0x0015) 2668 #define VPORT1_IN _SFR_MEM8(0x0016) 2669 #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) 2670 2671 /* VPORT2 - Virtual Port 2 */ 2672 #define VPORT2_DIR _SFR_MEM8(0x0018) 2673 #define VPORT2_OUT _SFR_MEM8(0x0019) 2674 #define VPORT2_IN _SFR_MEM8(0x001A) 2675 #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) 2676 2677 /* VPORT3 - Virtual Port 3 */ 2678 #define VPORT3_DIR _SFR_MEM8(0x001C) 2679 #define VPORT3_OUT _SFR_MEM8(0x001D) 2680 #define VPORT3_IN _SFR_MEM8(0x001E) 2681 #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) 2682 2683 /* OCD - On-Chip Debug System */ 2684 #define OCD_OCDR0 _SFR_MEM8(0x002E) 2685 #define OCD_OCDR1 _SFR_MEM8(0x002F) 2686 2687 /* CPU - CPU Registers */ 2688 #define CPU_CCP _SFR_MEM8(0x0034) 2689 #define CPU_RAMPD _SFR_MEM8(0x0038) 2690 #define CPU_RAMPX _SFR_MEM8(0x0039) 2691 #define CPU_RAMPY _SFR_MEM8(0x003A) 2692 #define CPU_RAMPZ _SFR_MEM8(0x003B) 2693 #define CPU_EIND _SFR_MEM8(0x003C) 2694 #define CPU_SPL _SFR_MEM8(0x003D) 2695 #define CPU_SPH _SFR_MEM8(0x003E) 2696 #define CPU_SREG _SFR_MEM8(0x003F) 2697 2698 /* CLK - Clock System */ 2699 #define CLK_CTRL _SFR_MEM8(0x0040) 2700 #define CLK_PSCTRL _SFR_MEM8(0x0041) 2701 #define CLK_LOCK _SFR_MEM8(0x0042) 2702 #define CLK_RTCCTRL _SFR_MEM8(0x0043) 2703 2704 /* SLEEP - Sleep Controller */ 2705 #define SLEEP_CTRL _SFR_MEM8(0x0048) 2706 2707 /* OSC - Oscillator Control */ 2708 #define OSC_CTRL _SFR_MEM8(0x0050) 2709 #define OSC_STATUS _SFR_MEM8(0x0051) 2710 #define OSC_XOSCCTRL _SFR_MEM8(0x0052) 2711 #define OSC_XOSCFAIL _SFR_MEM8(0x0053) 2712 #define OSC_RC32KCAL _SFR_MEM8(0x0054) 2713 #define OSC_PLLCTRL _SFR_MEM8(0x0055) 2714 #define OSC_DFLLCTRL _SFR_MEM8(0x0056) 2715 2716 /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ 2717 #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) 2718 #define DFLLRC32M_CALA _SFR_MEM8(0x0062) 2719 #define DFLLRC32M_CALB _SFR_MEM8(0x0063) 2720 #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) 2721 #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) 2722 #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) 2723 2724 /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ 2725 #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) 2726 #define DFLLRC2M_CALA _SFR_MEM8(0x006A) 2727 #define DFLLRC2M_CALB _SFR_MEM8(0x006B) 2728 #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) 2729 #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) 2730 #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) 2731 2732 /* PR - Power Reduction */ 2733 #define PR_PRGEN _SFR_MEM8(0x0070) 2734 #define PR_PRPA _SFR_MEM8(0x0071) 2735 #define PR_PRPB _SFR_MEM8(0x0072) 2736 #define PR_PRPC _SFR_MEM8(0x0073) 2737 #define PR_PRPD _SFR_MEM8(0x0074) 2738 #define PR_PRPE _SFR_MEM8(0x0075) 2739 #define PR_PRPF _SFR_MEM8(0x0076) 2740 2741 /* RST - Reset Controller */ 2742 #define RST_STATUS _SFR_MEM8(0x0078) 2743 #define RST_CTRL _SFR_MEM8(0x0079) 2744 2745 /* WDT - Watch-Dog Timer */ 2746 #define WDT_CTRL _SFR_MEM8(0x0080) 2747 #define WDT_WINCTRL _SFR_MEM8(0x0081) 2748 #define WDT_STATUS _SFR_MEM8(0x0082) 2749 2750 /* MCU - MCU Control */ 2751 #define MCU_DEVID0 _SFR_MEM8(0x0090) 2752 #define MCU_DEVID1 _SFR_MEM8(0x0091) 2753 #define MCU_DEVID2 _SFR_MEM8(0x0092) 2754 #define MCU_REVID _SFR_MEM8(0x0093) 2755 #define MCU_JTAGUID _SFR_MEM8(0x0094) 2756 #define MCU_MCUCR _SFR_MEM8(0x0096) 2757 #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) 2758 #define MCU_AWEXLOCK _SFR_MEM8(0x0099) 2759 2760 /* PMIC - Programmable Interrupt Controller */ 2761 #define PMIC_STATUS _SFR_MEM8(0x00A0) 2762 #define PMIC_INTPRI _SFR_MEM8(0x00A1) 2763 #define PMIC_CTRL _SFR_MEM8(0x00A2) 2764 2765 /* PORTCFG - Port Configuration */ 2766 #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) 2767 #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) 2768 #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) 2769 #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) 2770 2771 /* AES - AES Crypto Module */ 2772 #define AES_CTRL _SFR_MEM8(0x00C0) 2773 #define AES_STATUS _SFR_MEM8(0x00C1) 2774 #define AES_STATE _SFR_MEM8(0x00C2) 2775 #define AES_KEY _SFR_MEM8(0x00C3) 2776 #define AES_INTCTRL _SFR_MEM8(0x00C4) 2777 2778 /* DMA - DMA Controller */ 2779 #define DMA_CTRL _SFR_MEM8(0x0100) 2780 #define DMA_INTFLAGS _SFR_MEM8(0x0103) 2781 #define DMA_STATUS _SFR_MEM8(0x0104) 2782 #define DMA_TEMP _SFR_MEM16(0x0106) 2783 #define DMA_CH0_CTRLA _SFR_MEM8(0x0110) 2784 #define DMA_CH0_CTRLB _SFR_MEM8(0x0111) 2785 #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) 2786 #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) 2787 #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) 2788 #define DMA_CH0_REPCNT _SFR_MEM8(0x0116) 2789 #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) 2790 #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) 2791 #define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) 2792 #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) 2793 #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) 2794 #define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) 2795 #define DMA_CH1_CTRLA _SFR_MEM8(0x0120) 2796 #define DMA_CH1_CTRLB _SFR_MEM8(0x0121) 2797 #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) 2798 #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) 2799 #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) 2800 #define DMA_CH1_REPCNT _SFR_MEM8(0x0126) 2801 #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) 2802 #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) 2803 #define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) 2804 #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) 2805 #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) 2806 #define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) 2807 #define DMA_CH2_CTRLA _SFR_MEM8(0x0130) 2808 #define DMA_CH2_CTRLB _SFR_MEM8(0x0131) 2809 #define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) 2810 #define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) 2811 #define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) 2812 #define DMA_CH2_REPCNT _SFR_MEM8(0x0136) 2813 #define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) 2814 #define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) 2815 #define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) 2816 #define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) 2817 #define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) 2818 #define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) 2819 #define DMA_CH3_CTRLA _SFR_MEM8(0x0140) 2820 #define DMA_CH3_CTRLB _SFR_MEM8(0x0141) 2821 #define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) 2822 #define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) 2823 #define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) 2824 #define DMA_CH3_REPCNT _SFR_MEM8(0x0146) 2825 #define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) 2826 #define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) 2827 #define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) 2828 #define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) 2829 #define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) 2830 #define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) 2831 2832 /* EVSYS - Event System */ 2833 #define EVSYS_CH0MUX _SFR_MEM8(0x0180) 2834 #define EVSYS_CH1MUX _SFR_MEM8(0x0181) 2835 #define EVSYS_CH2MUX _SFR_MEM8(0x0182) 2836 #define EVSYS_CH3MUX _SFR_MEM8(0x0183) 2837 #define EVSYS_CH4MUX _SFR_MEM8(0x0184) 2838 #define EVSYS_CH5MUX _SFR_MEM8(0x0185) 2839 #define EVSYS_CH6MUX _SFR_MEM8(0x0186) 2840 #define EVSYS_CH7MUX _SFR_MEM8(0x0187) 2841 #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) 2842 #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) 2843 #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) 2844 #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) 2845 #define EVSYS_CH4CTRL _SFR_MEM8(0x018C) 2846 #define EVSYS_CH5CTRL _SFR_MEM8(0x018D) 2847 #define EVSYS_CH6CTRL _SFR_MEM8(0x018E) 2848 #define EVSYS_CH7CTRL _SFR_MEM8(0x018F) 2849 #define EVSYS_STROBE _SFR_MEM8(0x0190) 2850 #define EVSYS_DATA _SFR_MEM8(0x0191) 2851 2852 /* NVM - Non Volatile Memory Controller */ 2853 #define NVM_ADDR0 _SFR_MEM8(0x01C0) 2854 #define NVM_ADDR1 _SFR_MEM8(0x01C1) 2855 #define NVM_ADDR2 _SFR_MEM8(0x01C2) 2856 #define NVM_DATA0 _SFR_MEM8(0x01C4) 2857 #define NVM_DATA1 _SFR_MEM8(0x01C5) 2858 #define NVM_DATA2 _SFR_MEM8(0x01C6) 2859 #define NVM_CMD _SFR_MEM8(0x01CA) 2860 #define NVM_CTRLA _SFR_MEM8(0x01CB) 2861 #define NVM_CTRLB _SFR_MEM8(0x01CC) 2862 #define NVM_INTCTRL _SFR_MEM8(0x01CD) 2863 #define NVM_STATUS _SFR_MEM8(0x01CF) 2864 #define NVM_LOCKBITS _SFR_MEM8(0x01D0) 2865 2866 /* ADCA - Analog to Digital Converter A */ 2867 #define ADCA_CTRLA _SFR_MEM8(0x0200) 2868 #define ADCA_CTRLB _SFR_MEM8(0x0201) 2869 #define ADCA_REFCTRL _SFR_MEM8(0x0202) 2870 #define ADCA_EVCTRL _SFR_MEM8(0x0203) 2871 #define ADCA_PRESCALER _SFR_MEM8(0x0204) 2872 #define ADCA_INTFLAGS _SFR_MEM8(0x0206) 2873 #define ADCA_CAL _SFR_MEM16(0x020C) 2874 #define ADCA_CH0RES _SFR_MEM16(0x0210) 2875 #define ADCA_CH1RES _SFR_MEM16(0x0212) 2876 #define ADCA_CH2RES _SFR_MEM16(0x0214) 2877 #define ADCA_CH3RES _SFR_MEM16(0x0216) 2878 #define ADCA_CMP _SFR_MEM16(0x0218) 2879 #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) 2880 #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) 2881 #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) 2882 #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) 2883 #define ADCA_CH0_RES _SFR_MEM16(0x0224) 2884 #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) 2885 #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) 2886 #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) 2887 #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) 2888 #define ADCA_CH1_RES _SFR_MEM16(0x022C) 2889 #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) 2890 #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) 2891 #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) 2892 #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) 2893 #define ADCA_CH2_RES _SFR_MEM16(0x0234) 2894 #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) 2895 #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) 2896 #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) 2897 #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) 2898 #define ADCA_CH3_RES _SFR_MEM16(0x023C) 2899 2900 /* DACB - Digital to Analog Converter B */ 2901 #define DACB_CTRLA _SFR_MEM8(0x0320) 2902 #define DACB_CTRLB _SFR_MEM8(0x0321) 2903 #define DACB_CTRLC _SFR_MEM8(0x0322) 2904 #define DACB_EVCTRL _SFR_MEM8(0x0323) 2905 #define DACB_TIMCTRL _SFR_MEM8(0x0324) 2906 #define DACB_STATUS _SFR_MEM8(0x0325) 2907 #define DACB_GAINCAL _SFR_MEM8(0x0328) 2908 #define DACB_OFFSETCAL _SFR_MEM8(0x0329) 2909 #define DACB_CH0DATA _SFR_MEM16(0x0338) 2910 #define DACB_CH1DATA _SFR_MEM16(0x033A) 2911 2912 /* ACA - Analog Comparator A */ 2913 #define ACA_AC0CTRL _SFR_MEM8(0x0380) 2914 #define ACA_AC1CTRL _SFR_MEM8(0x0381) 2915 #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) 2916 #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) 2917 #define ACA_CTRLA _SFR_MEM8(0x0384) 2918 #define ACA_CTRLB _SFR_MEM8(0x0385) 2919 #define ACA_WINCTRL _SFR_MEM8(0x0386) 2920 #define ACA_STATUS _SFR_MEM8(0x0387) 2921 2922 /* RTC - Real-Time Counter */ 2923 #define RTC_CTRL _SFR_MEM8(0x0400) 2924 #define RTC_STATUS _SFR_MEM8(0x0401) 2925 #define RTC_INTCTRL _SFR_MEM8(0x0402) 2926 #define RTC_INTFLAGS _SFR_MEM8(0x0403) 2927 #define RTC_TEMP _SFR_MEM8(0x0404) 2928 #define RTC_CNT _SFR_MEM16(0x0408) 2929 #define RTC_PER _SFR_MEM16(0x040A) 2930 #define RTC_COMP _SFR_MEM16(0x040C) 2931 2932 /* TWIC - Two-Wire Interface C */ 2933 #define TWIC_CTRL _SFR_MEM8(0x0480) 2934 #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) 2935 #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) 2936 #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) 2937 #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) 2938 #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) 2939 #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) 2940 #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) 2941 #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) 2942 #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) 2943 #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) 2944 #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) 2945 #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) 2946 #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) 2947 2948 /* TWIE - Two-Wire Interface E */ 2949 #define TWIE_CTRL _SFR_MEM8(0x04A0) 2950 #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) 2951 #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) 2952 #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) 2953 #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) 2954 #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) 2955 #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) 2956 #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) 2957 #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) 2958 #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) 2959 #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) 2960 #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) 2961 #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) 2962 #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) 2963 2964 /* PORTA - Port A */ 2965 #define PORTA_DIR _SFR_MEM8(0x0600) 2966 #define PORTA_DIRSET _SFR_MEM8(0x0601) 2967 #define PORTA_DIRCLR _SFR_MEM8(0x0602) 2968 #define PORTA_DIRTGL _SFR_MEM8(0x0603) 2969 #define PORTA_OUT _SFR_MEM8(0x0604) 2970 #define PORTA_OUTSET _SFR_MEM8(0x0605) 2971 #define PORTA_OUTCLR _SFR_MEM8(0x0606) 2972 #define PORTA_OUTTGL _SFR_MEM8(0x0607) 2973 #define PORTA_IN _SFR_MEM8(0x0608) 2974 #define PORTA_INTCTRL _SFR_MEM8(0x0609) 2975 #define PORTA_INT0MASK _SFR_MEM8(0x060A) 2976 #define PORTA_INT1MASK _SFR_MEM8(0x060B) 2977 #define PORTA_INTFLAGS _SFR_MEM8(0x060C) 2978 #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) 2979 #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) 2980 #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) 2981 #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) 2982 #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) 2983 #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) 2984 #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) 2985 #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) 2986 2987 /* PORTB - Port B */ 2988 #define PORTB_DIR _SFR_MEM8(0x0620) 2989 #define PORTB_DIRSET _SFR_MEM8(0x0621) 2990 #define PORTB_DIRCLR _SFR_MEM8(0x0622) 2991 #define PORTB_DIRTGL _SFR_MEM8(0x0623) 2992 #define PORTB_OUT _SFR_MEM8(0x0624) 2993 #define PORTB_OUTSET _SFR_MEM8(0x0625) 2994 #define PORTB_OUTCLR _SFR_MEM8(0x0626) 2995 #define PORTB_OUTTGL _SFR_MEM8(0x0627) 2996 #define PORTB_IN _SFR_MEM8(0x0628) 2997 #define PORTB_INTCTRL _SFR_MEM8(0x0629) 2998 #define PORTB_INT0MASK _SFR_MEM8(0x062A) 2999 #define PORTB_INT1MASK _SFR_MEM8(0x062B) 3000 #define PORTB_INTFLAGS _SFR_MEM8(0x062C) 3001 #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) 3002 #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) 3003 #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) 3004 #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) 3005 #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) 3006 #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) 3007 #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) 3008 #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) 3009 3010 /* PORTC - Port C */ 3011 #define PORTC_DIR _SFR_MEM8(0x0640) 3012 #define PORTC_DIRSET _SFR_MEM8(0x0641) 3013 #define PORTC_DIRCLR _SFR_MEM8(0x0642) 3014 #define PORTC_DIRTGL _SFR_MEM8(0x0643) 3015 #define PORTC_OUT _SFR_MEM8(0x0644) 3016 #define PORTC_OUTSET _SFR_MEM8(0x0645) 3017 #define PORTC_OUTCLR _SFR_MEM8(0x0646) 3018 #define PORTC_OUTTGL _SFR_MEM8(0x0647) 3019 #define PORTC_IN _SFR_MEM8(0x0648) 3020 #define PORTC_INTCTRL _SFR_MEM8(0x0649) 3021 #define PORTC_INT0MASK _SFR_MEM8(0x064A) 3022 #define PORTC_INT1MASK _SFR_MEM8(0x064B) 3023 #define PORTC_INTFLAGS _SFR_MEM8(0x064C) 3024 #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) 3025 #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) 3026 #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) 3027 #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) 3028 #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) 3029 #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) 3030 #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) 3031 #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) 3032 3033 /* PORTD - Port D */ 3034 #define PORTD_DIR _SFR_MEM8(0x0660) 3035 #define PORTD_DIRSET _SFR_MEM8(0x0661) 3036 #define PORTD_DIRCLR _SFR_MEM8(0x0662) 3037 #define PORTD_DIRTGL _SFR_MEM8(0x0663) 3038 #define PORTD_OUT _SFR_MEM8(0x0664) 3039 #define PORTD_OUTSET _SFR_MEM8(0x0665) 3040 #define PORTD_OUTCLR _SFR_MEM8(0x0666) 3041 #define PORTD_OUTTGL _SFR_MEM8(0x0667) 3042 #define PORTD_IN _SFR_MEM8(0x0668) 3043 #define PORTD_INTCTRL _SFR_MEM8(0x0669) 3044 #define PORTD_INT0MASK _SFR_MEM8(0x066A) 3045 #define PORTD_INT1MASK _SFR_MEM8(0x066B) 3046 #define PORTD_INTFLAGS _SFR_MEM8(0x066C) 3047 #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) 3048 #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) 3049 #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) 3050 #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) 3051 #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) 3052 #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) 3053 #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) 3054 #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) 3055 3056 /* PORTE - Port E */ 3057 #define PORTE_DIR _SFR_MEM8(0x0680) 3058 #define PORTE_DIRSET _SFR_MEM8(0x0681) 3059 #define PORTE_DIRCLR _SFR_MEM8(0x0682) 3060 #define PORTE_DIRTGL _SFR_MEM8(0x0683) 3061 #define PORTE_OUT _SFR_MEM8(0x0684) 3062 #define PORTE_OUTSET _SFR_MEM8(0x0685) 3063 #define PORTE_OUTCLR _SFR_MEM8(0x0686) 3064 #define PORTE_OUTTGL _SFR_MEM8(0x0687) 3065 #define PORTE_IN _SFR_MEM8(0x0688) 3066 #define PORTE_INTCTRL _SFR_MEM8(0x0689) 3067 #define PORTE_INT0MASK _SFR_MEM8(0x068A) 3068 #define PORTE_INT1MASK _SFR_MEM8(0x068B) 3069 #define PORTE_INTFLAGS _SFR_MEM8(0x068C) 3070 #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) 3071 #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) 3072 #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) 3073 #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) 3074 #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) 3075 #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) 3076 #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) 3077 #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) 3078 3079 /* PORTR - Port R */ 3080 #define PORTR_DIR _SFR_MEM8(0x07E0) 3081 #define PORTR_DIRSET _SFR_MEM8(0x07E1) 3082 #define PORTR_DIRCLR _SFR_MEM8(0x07E2) 3083 #define PORTR_DIRTGL _SFR_MEM8(0x07E3) 3084 #define PORTR_OUT _SFR_MEM8(0x07E4) 3085 #define PORTR_OUTSET _SFR_MEM8(0x07E5) 3086 #define PORTR_OUTCLR _SFR_MEM8(0x07E6) 3087 #define PORTR_OUTTGL _SFR_MEM8(0x07E7) 3088 #define PORTR_IN _SFR_MEM8(0x07E8) 3089 #define PORTR_INTCTRL _SFR_MEM8(0x07E9) 3090 #define PORTR_INT0MASK _SFR_MEM8(0x07EA) 3091 #define PORTR_INT1MASK _SFR_MEM8(0x07EB) 3092 #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) 3093 #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) 3094 #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) 3095 #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) 3096 #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) 3097 #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) 3098 #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) 3099 #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) 3100 #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) 3101 3102 /* TCC0 - Timer/Counter C0 */ 3103 #define TCC0_CTRLA _SFR_MEM8(0x0800) 3104 #define TCC0_CTRLB _SFR_MEM8(0x0801) 3105 #define TCC0_CTRLC _SFR_MEM8(0x0802) 3106 #define TCC0_CTRLD _SFR_MEM8(0x0803) 3107 #define TCC0_CTRLE _SFR_MEM8(0x0804) 3108 #define TCC0_INTCTRLA _SFR_MEM8(0x0806) 3109 #define TCC0_INTCTRLB _SFR_MEM8(0x0807) 3110 #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) 3111 #define TCC0_CTRLFSET _SFR_MEM8(0x0809) 3112 #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) 3113 #define TCC0_CTRLGSET _SFR_MEM8(0x080B) 3114 #define TCC0_INTFLAGS _SFR_MEM8(0x080C) 3115 #define TCC0_TEMP _SFR_MEM8(0x080F) 3116 #define TCC0_CNT _SFR_MEM16(0x0820) 3117 #define TCC0_PER _SFR_MEM16(0x0826) 3118 #define TCC0_CCA _SFR_MEM16(0x0828) 3119 #define TCC0_CCB _SFR_MEM16(0x082A) 3120 #define TCC0_CCC _SFR_MEM16(0x082C) 3121 #define TCC0_CCD _SFR_MEM16(0x082E) 3122 #define TCC0_PERBUF _SFR_MEM16(0x0836) 3123 #define TCC0_CCABUF _SFR_MEM16(0x0838) 3124 #define TCC0_CCBBUF _SFR_MEM16(0x083A) 3125 #define TCC0_CCCBUF _SFR_MEM16(0x083C) 3126 #define TCC0_CCDBUF _SFR_MEM16(0x083E) 3127 3128 /* TCC1 - Timer/Counter C1 */ 3129 #define TCC1_CTRLA _SFR_MEM8(0x0840) 3130 #define TCC1_CTRLB _SFR_MEM8(0x0841) 3131 #define TCC1_CTRLC _SFR_MEM8(0x0842) 3132 #define TCC1_CTRLD _SFR_MEM8(0x0843) 3133 #define TCC1_CTRLE _SFR_MEM8(0x0844) 3134 #define TCC1_INTCTRLA _SFR_MEM8(0x0846) 3135 #define TCC1_INTCTRLB _SFR_MEM8(0x0847) 3136 #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) 3137 #define TCC1_CTRLFSET _SFR_MEM8(0x0849) 3138 #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) 3139 #define TCC1_CTRLGSET _SFR_MEM8(0x084B) 3140 #define TCC1_INTFLAGS _SFR_MEM8(0x084C) 3141 #define TCC1_TEMP _SFR_MEM8(0x084F) 3142 #define TCC1_CNT _SFR_MEM16(0x0860) 3143 #define TCC1_PER _SFR_MEM16(0x0866) 3144 #define TCC1_CCA _SFR_MEM16(0x0868) 3145 #define TCC1_CCB _SFR_MEM16(0x086A) 3146 #define TCC1_PERBUF _SFR_MEM16(0x0876) 3147 #define TCC1_CCABUF _SFR_MEM16(0x0878) 3148 #define TCC1_CCBBUF _SFR_MEM16(0x087A) 3149 3150 /* AWEXC - Advanced Waveform Extension C */ 3151 #define AWEXC_CTRL _SFR_MEM8(0x0880) 3152 #define AWEXC_FDEMASK _SFR_MEM8(0x0882) 3153 #define AWEXC_FDCTRL _SFR_MEM8(0x0883) 3154 #define AWEXC_STATUS _SFR_MEM8(0x0884) 3155 #define AWEXC_DTBOTH _SFR_MEM8(0x0886) 3156 #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) 3157 #define AWEXC_DTLS _SFR_MEM8(0x0888) 3158 #define AWEXC_DTHS _SFR_MEM8(0x0889) 3159 #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) 3160 #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) 3161 #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) 3162 3163 /* HIRESC - High-Resolution Extension C */ 3164 #define HIRESC_CTRLA _SFR_MEM8(0x0890) 3165 3166 /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ 3167 #define USARTC0_DATA _SFR_MEM8(0x08A0) 3168 #define USARTC0_STATUS _SFR_MEM8(0x08A1) 3169 #define USARTC0_CTRLA _SFR_MEM8(0x08A3) 3170 #define USARTC0_CTRLB _SFR_MEM8(0x08A4) 3171 #define USARTC0_CTRLC _SFR_MEM8(0x08A5) 3172 #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) 3173 #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) 3174 3175 /* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ 3176 #define USARTC1_DATA _SFR_MEM8(0x08B0) 3177 #define USARTC1_STATUS _SFR_MEM8(0x08B1) 3178 #define USARTC1_CTRLA _SFR_MEM8(0x08B3) 3179 #define USARTC1_CTRLB _SFR_MEM8(0x08B4) 3180 #define USARTC1_CTRLC _SFR_MEM8(0x08B5) 3181 #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) 3182 #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) 3183 3184 /* SPIC - Serial Peripheral Interface C */ 3185 #define SPIC_CTRL _SFR_MEM8(0x08C0) 3186 #define SPIC_INTCTRL _SFR_MEM8(0x08C1) 3187 #define SPIC_STATUS _SFR_MEM8(0x08C2) 3188 #define SPIC_DATA _SFR_MEM8(0x08C3) 3189 3190 /* IRCOM - IR Communication Module */ 3191 #define IRCOM_CTRL _SFR_MEM8(0x08F8) 3192 #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) 3193 #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) 3194 3195 /* TCD0 - Timer/Counter D0 */ 3196 #define TCD0_CTRLA _SFR_MEM8(0x0900) 3197 #define TCD0_CTRLB _SFR_MEM8(0x0901) 3198 #define TCD0_CTRLC _SFR_MEM8(0x0902) 3199 #define TCD0_CTRLD _SFR_MEM8(0x0903) 3200 #define TCD0_CTRLE _SFR_MEM8(0x0904) 3201 #define TCD0_INTCTRLA _SFR_MEM8(0x0906) 3202 #define TCD0_INTCTRLB _SFR_MEM8(0x0907) 3203 #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) 3204 #define TCD0_CTRLFSET _SFR_MEM8(0x0909) 3205 #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) 3206 #define TCD0_CTRLGSET _SFR_MEM8(0x090B) 3207 #define TCD0_INTFLAGS _SFR_MEM8(0x090C) 3208 #define TCD0_TEMP _SFR_MEM8(0x090F) 3209 #define TCD0_CNT _SFR_MEM16(0x0920) 3210 #define TCD0_PER _SFR_MEM16(0x0926) 3211 #define TCD0_CCA _SFR_MEM16(0x0928) 3212 #define TCD0_CCB _SFR_MEM16(0x092A) 3213 #define TCD0_CCC _SFR_MEM16(0x092C) 3214 #define TCD0_CCD _SFR_MEM16(0x092E) 3215 #define TCD0_PERBUF _SFR_MEM16(0x0936) 3216 #define TCD0_CCABUF _SFR_MEM16(0x0938) 3217 #define TCD0_CCBBUF _SFR_MEM16(0x093A) 3218 #define TCD0_CCCBUF _SFR_MEM16(0x093C) 3219 #define TCD0_CCDBUF _SFR_MEM16(0x093E) 3220 3221 /* TCD1 - Timer/Counter D1 */ 3222 #define TCD1_CTRLA _SFR_MEM8(0x0940) 3223 #define TCD1_CTRLB _SFR_MEM8(0x0941) 3224 #define TCD1_CTRLC _SFR_MEM8(0x0942) 3225 #define TCD1_CTRLD _SFR_MEM8(0x0943) 3226 #define TCD1_CTRLE _SFR_MEM8(0x0944) 3227 #define TCD1_INTCTRLA _SFR_MEM8(0x0946) 3228 #define TCD1_INTCTRLB _SFR_MEM8(0x0947) 3229 #define TCD1_CTRLFCLR _SFR_MEM8(0x0948) 3230 #define TCD1_CTRLFSET _SFR_MEM8(0x0949) 3231 #define TCD1_CTRLGCLR _SFR_MEM8(0x094A) 3232 #define TCD1_CTRLGSET _SFR_MEM8(0x094B) 3233 #define TCD1_INTFLAGS _SFR_MEM8(0x094C) 3234 #define TCD1_TEMP _SFR_MEM8(0x094F) 3235 #define TCD1_CNT _SFR_MEM16(0x0960) 3236 #define TCD1_PER _SFR_MEM16(0x0966) 3237 #define TCD1_CCA _SFR_MEM16(0x0968) 3238 #define TCD1_CCB _SFR_MEM16(0x096A) 3239 #define TCD1_PERBUF _SFR_MEM16(0x0976) 3240 #define TCD1_CCABUF _SFR_MEM16(0x0978) 3241 #define TCD1_CCBBUF _SFR_MEM16(0x097A) 3242 3243 /* HIRESD - High-Resolution Extension D */ 3244 #define HIRESD_CTRLA _SFR_MEM8(0x0990) 3245 3246 /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ 3247 #define USARTD0_DATA _SFR_MEM8(0x09A0) 3248 #define USARTD0_STATUS _SFR_MEM8(0x09A1) 3249 #define USARTD0_CTRLA _SFR_MEM8(0x09A3) 3250 #define USARTD0_CTRLB _SFR_MEM8(0x09A4) 3251 #define USARTD0_CTRLC _SFR_MEM8(0x09A5) 3252 #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) 3253 #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) 3254 3255 /* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ 3256 #define USARTD1_DATA _SFR_MEM8(0x09B0) 3257 #define USARTD1_STATUS _SFR_MEM8(0x09B1) 3258 #define USARTD1_CTRLA _SFR_MEM8(0x09B3) 3259 #define USARTD1_CTRLB _SFR_MEM8(0x09B4) 3260 #define USARTD1_CTRLC _SFR_MEM8(0x09B5) 3261 #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) 3262 #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) 3263 3264 /* SPID - Serial Peripheral Interface D */ 3265 #define SPID_CTRL _SFR_MEM8(0x09C0) 3266 #define SPID_INTCTRL _SFR_MEM8(0x09C1) 3267 #define SPID_STATUS _SFR_MEM8(0x09C2) 3268 #define SPID_DATA _SFR_MEM8(0x09C3) 3269 3270 /* TCE0 - Timer/Counter E0 */ 3271 #define TCE0_CTRLA _SFR_MEM8(0x0A00) 3272 #define TCE0_CTRLB _SFR_MEM8(0x0A01) 3273 #define TCE0_CTRLC _SFR_MEM8(0x0A02) 3274 #define TCE0_CTRLD _SFR_MEM8(0x0A03) 3275 #define TCE0_CTRLE _SFR_MEM8(0x0A04) 3276 #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) 3277 #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) 3278 #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) 3279 #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) 3280 #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) 3281 #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) 3282 #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) 3283 #define TCE0_TEMP _SFR_MEM8(0x0A0F) 3284 #define TCE0_CNT _SFR_MEM16(0x0A20) 3285 #define TCE0_PER _SFR_MEM16(0x0A26) 3286 #define TCE0_CCA _SFR_MEM16(0x0A28) 3287 #define TCE0_CCB _SFR_MEM16(0x0A2A) 3288 #define TCE0_CCC _SFR_MEM16(0x0A2C) 3289 #define TCE0_CCD _SFR_MEM16(0x0A2E) 3290 #define TCE0_PERBUF _SFR_MEM16(0x0A36) 3291 #define TCE0_CCABUF _SFR_MEM16(0x0A38) 3292 #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) 3293 #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) 3294 #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) 3295 3296 /* HIRESE - High-Resolution Extension E */ 3297 #define HIRESE_CTRLA _SFR_MEM8(0x0A90) 3298 3299 /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ 3300 #define USARTE0_DATA _SFR_MEM8(0x0AA0) 3301 #define USARTE0_STATUS _SFR_MEM8(0x0AA1) 3302 #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) 3303 #define USARTE0_CTRLB _SFR_MEM8(0x0AA4) 3304 #define USARTE0_CTRLC _SFR_MEM8(0x0AA5) 3305 #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) 3306 #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) 3307 3308 3309 3310 /*================== Bitfield Definitions ================== */ 3311 3312 /* XOCD - On-Chip Debug System */ 3313 /* OCD.OCDR1 bit masks and bit positions */ 3314 #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ 3315 #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ 3316 3317 3318 /* CPU - CPU */ 3319 /* CPU.CCP bit masks and bit positions */ 3320 #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ 3321 #define CPU_CCP_gp 0 /* CCP signature group position. */ 3322 #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ 3323 #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ 3324 #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ 3325 #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ 3326 #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ 3327 #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ 3328 #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ 3329 #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ 3330 #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ 3331 #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ 3332 #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ 3333 #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ 3334 #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ 3335 #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ 3336 #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ 3337 #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ 3338 3339 3340 /* CPU.SREG bit masks and bit positions */ 3341 #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ 3342 #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ 3343 3344 #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ 3345 #define CPU_T_bp 6 /* Transfer Bit bit position. */ 3346 3347 #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ 3348 #define CPU_H_bp 5 /* Half Carry Flag bit position. */ 3349 3350 #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ 3351 #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ 3352 3353 #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ 3354 #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ 3355 3356 #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ 3357 #define CPU_N_bp 2 /* Negative Flag bit position. */ 3358 3359 #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ 3360 #define CPU_Z_bp 1 /* Zero Flag bit position. */ 3361 3362 #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ 3363 #define CPU_C_bp 0 /* Carry Flag bit position. */ 3364 3365 3366 /* CLK - Clock System */ 3367 /* CLK.CTRL bit masks and bit positions */ 3368 #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ 3369 #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ 3370 #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ 3371 #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ 3372 #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ 3373 #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ 3374 #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ 3375 #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ 3376 3377 3378 /* CLK.PSCTRL bit masks and bit positions */ 3379 #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ 3380 #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ 3381 #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ 3382 #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ 3383 #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ 3384 #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ 3385 #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ 3386 #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ 3387 #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ 3388 #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ 3389 #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ 3390 #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ 3391 3392 #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ 3393 #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ 3394 #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ 3395 #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ 3396 #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ 3397 #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ 3398 3399 3400 /* CLK.LOCK bit masks and bit positions */ 3401 #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ 3402 #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ 3403 3404 3405 /* CLK.RTCCTRL bit masks and bit positions */ 3406 #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ 3407 #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ 3408 #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ 3409 #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ 3410 #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ 3411 #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ 3412 #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ 3413 #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ 3414 3415 #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ 3416 #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ 3417 3418 3419 /* PR.PRGEN bit masks and bit positions */ 3420 #define PR_AES_bm 0x10 /* AES bit mask. */ 3421 #define PR_AES_bp 4 /* AES bit position. */ 3422 3423 #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ 3424 #define PR_EBI_bp 3 /* External Bus Interface bit position. */ 3425 3426 #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ 3427 #define PR_RTC_bp 2 /* Real-time Counter bit position. */ 3428 3429 #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ 3430 #define PR_EVSYS_bp 1 /* Event System bit position. */ 3431 3432 #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ 3433 #define PR_DMA_bp 0 /* DMA-Controller bit position. */ 3434 3435 3436 /* PR.PRPA bit masks and bit positions */ 3437 #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ 3438 #define PR_DAC_bp 2 /* Port A DAC bit position. */ 3439 3440 #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ 3441 #define PR_ADC_bp 1 /* Port A ADC bit position. */ 3442 3443 #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ 3444 #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ 3445 3446 3447 /* PR.PRPB bit masks and bit positions */ 3448 /* PR_DAC_bm Predefined. */ 3449 /* PR_DAC_bp Predefined. */ 3450 3451 /* PR_ADC_bm Predefined. */ 3452 /* PR_ADC_bp Predefined. */ 3453 3454 /* PR_AC_bm Predefined. */ 3455 /* PR_AC_bp Predefined. */ 3456 3457 3458 /* PR.PRPC bit masks and bit positions */ 3459 #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ 3460 #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ 3461 3462 #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ 3463 #define PR_USART1_bp 5 /* Port C USART1 bit position. */ 3464 3465 #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ 3466 #define PR_USART0_bp 4 /* Port C USART0 bit position. */ 3467 3468 #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ 3469 #define PR_SPI_bp 3 /* Port C SPI bit position. */ 3470 3471 #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ 3472 #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ 3473 3474 #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ 3475 #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ 3476 3477 #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ 3478 #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ 3479 3480 3481 /* PR.PRPD bit masks and bit positions */ 3482 /* PR_TWI_bm Predefined. */ 3483 /* PR_TWI_bp Predefined. */ 3484 3485 /* PR_USART1_bm Predefined. */ 3486 /* PR_USART1_bp Predefined. */ 3487 3488 /* PR_USART0_bm Predefined. */ 3489 /* PR_USART0_bp Predefined. */ 3490 3491 /* PR_SPI_bm Predefined. */ 3492 /* PR_SPI_bp Predefined. */ 3493 3494 /* PR_HIRES_bm Predefined. */ 3495 /* PR_HIRES_bp Predefined. */ 3496 3497 /* PR_TC1_bm Predefined. */ 3498 /* PR_TC1_bp Predefined. */ 3499 3500 /* PR_TC0_bm Predefined. */ 3501 /* PR_TC0_bp Predefined. */ 3502 3503 3504 /* PR.PRPE bit masks and bit positions */ 3505 /* PR_TWI_bm Predefined. */ 3506 /* PR_TWI_bp Predefined. */ 3507 3508 /* PR_USART1_bm Predefined. */ 3509 /* PR_USART1_bp Predefined. */ 3510 3511 /* PR_USART0_bm Predefined. */ 3512 /* PR_USART0_bp Predefined. */ 3513 3514 /* PR_SPI_bm Predefined. */ 3515 /* PR_SPI_bp Predefined. */ 3516 3517 /* PR_HIRES_bm Predefined. */ 3518 /* PR_HIRES_bp Predefined. */ 3519 3520 /* PR_TC1_bm Predefined. */ 3521 /* PR_TC1_bp Predefined. */ 3522 3523 /* PR_TC0_bm Predefined. */ 3524 /* PR_TC0_bp Predefined. */ 3525 3526 3527 /* PR.PRPF bit masks and bit positions */ 3528 /* PR_TWI_bm Predefined. */ 3529 /* PR_TWI_bp Predefined. */ 3530 3531 /* PR_USART1_bm Predefined. */ 3532 /* PR_USART1_bp Predefined. */ 3533 3534 /* PR_USART0_bm Predefined. */ 3535 /* PR_USART0_bp Predefined. */ 3536 3537 /* PR_SPI_bm Predefined. */ 3538 /* PR_SPI_bp Predefined. */ 3539 3540 /* PR_HIRES_bm Predefined. */ 3541 /* PR_HIRES_bp Predefined. */ 3542 3543 /* PR_TC1_bm Predefined. */ 3544 /* PR_TC1_bp Predefined. */ 3545 3546 /* PR_TC0_bm Predefined. */ 3547 /* PR_TC0_bp Predefined. */ 3548 3549 3550 /* SLEEP - Sleep Controller */ 3551 /* SLEEP.CTRL bit masks and bit positions */ 3552 #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ 3553 #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ 3554 #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ 3555 #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ 3556 #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ 3557 #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ 3558 #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ 3559 #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ 3560 3561 #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ 3562 #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ 3563 3564 3565 /* OSC - Oscillator */ 3566 /* OSC.CTRL bit masks and bit positions */ 3567 #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ 3568 #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ 3569 3570 #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ 3571 #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ 3572 3573 #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ 3574 #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ 3575 3576 #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ 3577 #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ 3578 3579 #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ 3580 #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ 3581 3582 3583 /* OSC.STATUS bit masks and bit positions */ 3584 #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ 3585 #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ 3586 3587 #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ 3588 #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ 3589 3590 #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ 3591 #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ 3592 3593 #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ 3594 #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ 3595 3596 #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ 3597 #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ 3598 3599 3600 /* OSC.XOSCCTRL bit masks and bit positions */ 3601 #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ 3602 #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ 3603 #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ 3604 #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ 3605 #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ 3606 #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ 3607 3608 #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ 3609 #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ 3610 3611 #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ 3612 #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ 3613 #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ 3614 #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ 3615 #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ 3616 #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ 3617 #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ 3618 #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ 3619 #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ 3620 #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ 3621 3622 3623 /* OSC.XOSCFAIL bit masks and bit positions */ 3624 #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ 3625 #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ 3626 3627 #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ 3628 #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ 3629 3630 3631 /* OSC.PLLCTRL bit masks and bit positions */ 3632 #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ 3633 #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ 3634 #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ 3635 #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ 3636 #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ 3637 #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ 3638 3639 #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ 3640 #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ 3641 #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ 3642 #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ 3643 #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ 3644 #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ 3645 #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ 3646 #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ 3647 #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ 3648 #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ 3649 #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ 3650 #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ 3651 3652 3653 /* OSC.DFLLCTRL bit masks and bit positions */ 3654 #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ 3655 #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ 3656 3657 #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ 3658 #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ 3659 3660 3661 /* DFLL - DFLL */ 3662 /* DFLL.CTRL bit masks and bit positions */ 3663 #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ 3664 #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ 3665 3666 3667 /* DFLL.CALA bit masks and bit positions */ 3668 #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ 3669 #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ 3670 #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ 3671 #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ 3672 #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ 3673 #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ 3674 #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ 3675 #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ 3676 #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ 3677 #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ 3678 #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ 3679 #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ 3680 #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ 3681 #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ 3682 #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ 3683 #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ 3684 3685 3686 /* DFLL.CALB bit masks and bit positions */ 3687 #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ 3688 #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ 3689 #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ 3690 #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ 3691 #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ 3692 #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ 3693 #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ 3694 #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ 3695 #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ 3696 #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ 3697 #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ 3698 #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ 3699 #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ 3700 #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ 3701 3702 3703 /* RST - Reset */ 3704 /* RST.STATUS bit masks and bit positions */ 3705 #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ 3706 #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ 3707 3708 #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ 3709 #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ 3710 3711 #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ 3712 #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ 3713 3714 #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ 3715 #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ 3716 3717 #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ 3718 #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ 3719 3720 #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ 3721 #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ 3722 3723 #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ 3724 #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ 3725 3726 3727 /* RST.CTRL bit masks and bit positions */ 3728 #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ 3729 #define RST_SWRST_bp 0 /* Software Reset bit position. */ 3730 3731 3732 /* WDT - Watch-Dog Timer */ 3733 /* WDT.CTRL bit masks and bit positions */ 3734 #define WDT_PER_gm 0x3C /* Period group mask. */ 3735 #define WDT_PER_gp 2 /* Period group position. */ 3736 #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ 3737 #define WDT_PER0_bp 2 /* Period bit 0 position. */ 3738 #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ 3739 #define WDT_PER1_bp 3 /* Period bit 1 position. */ 3740 #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ 3741 #define WDT_PER2_bp 4 /* Period bit 2 position. */ 3742 #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ 3743 #define WDT_PER3_bp 5 /* Period bit 3 position. */ 3744 3745 #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ 3746 #define WDT_ENABLE_bp 1 /* Enable bit position. */ 3747 3748 #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ 3749 #define WDT_CEN_bp 0 /* Change Enable bit position. */ 3750 3751 3752 /* WDT.WINCTRL bit masks and bit positions */ 3753 #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ 3754 #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ 3755 #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ 3756 #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ 3757 #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ 3758 #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ 3759 #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ 3760 #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ 3761 #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ 3762 #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ 3763 3764 #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ 3765 #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ 3766 3767 #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ 3768 #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ 3769 3770 3771 /* WDT.STATUS bit masks and bit positions */ 3772 #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ 3773 #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ 3774 3775 3776 /* MCU - MCU Control */ 3777 /* MCU.MCUCR bit masks and bit positions */ 3778 #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ 3779 #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ 3780 3781 3782 /* MCU.EVSYSLOCK bit masks and bit positions */ 3783 #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ 3784 #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ 3785 3786 #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ 3787 #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ 3788 3789 3790 /* MCU.AWEXLOCK bit masks and bit positions */ 3791 #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ 3792 #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ 3793 3794 #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ 3795 #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ 3796 3797 3798 /* PMIC - Programmable Multi-level Interrupt Controller */ 3799 /* PMIC.STATUS bit masks and bit positions */ 3800 #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ 3801 #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ 3802 3803 #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ 3804 #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ 3805 3806 #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ 3807 #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ 3808 3809 #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ 3810 #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ 3811 3812 3813 /* PMIC.CTRL bit masks and bit positions */ 3814 #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ 3815 #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ 3816 3817 #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ 3818 #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ 3819 3820 #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ 3821 #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ 3822 3823 #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ 3824 #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ 3825 3826 #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ 3827 #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ 3828 3829 3830 /* DMA - DMA Controller */ 3831 /* DMA_CH.CTRLA bit masks and bit positions */ 3832 #define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ 3833 #define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ 3834 3835 #define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ 3836 #define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ 3837 3838 #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ 3839 #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ 3840 3841 #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ 3842 #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ 3843 3844 #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ 3845 #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ 3846 3847 #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ 3848 #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ 3849 #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ 3850 #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ 3851 #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ 3852 #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ 3853 3854 3855 /* DMA_CH.CTRLB bit masks and bit positions */ 3856 #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ 3857 #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ 3858 3859 #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ 3860 #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ 3861 3862 #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ 3863 #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ 3864 3865 #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ 3866 #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ 3867 3868 #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ 3869 #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ 3870 #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ 3871 #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ 3872 #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ 3873 #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ 3874 3875 #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ 3876 #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ 3877 #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ 3878 #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ 3879 #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ 3880 #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ 3881 3882 3883 /* DMA_CH.ADDRCTRL bit masks and bit positions */ 3884 #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ 3885 #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ 3886 #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ 3887 #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ 3888 #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ 3889 #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ 3890 3891 #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ 3892 #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ 3893 #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ 3894 #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ 3895 #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ 3896 #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ 3897 3898 #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ 3899 #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ 3900 #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ 3901 #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ 3902 #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ 3903 #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ 3904 3905 #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ 3906 #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ 3907 #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ 3908 #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ 3909 #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ 3910 #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ 3911 3912 3913 /* DMA_CH.TRIGSRC bit masks and bit positions */ 3914 #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ 3915 #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ 3916 #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ 3917 #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ 3918 #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ 3919 #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ 3920 #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ 3921 #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ 3922 #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ 3923 #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ 3924 #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ 3925 #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ 3926 #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ 3927 #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ 3928 #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ 3929 #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ 3930 #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ 3931 #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ 3932 3933 3934 /* DMA.CTRL bit masks and bit positions */ 3935 #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ 3936 #define DMA_ENABLE_bp 7 /* Enable bit position. */ 3937 3938 #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ 3939 #define DMA_RESET_bp 6 /* Software Reset bit position. */ 3940 3941 #define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ 3942 #define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ 3943 #define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ 3944 #define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ 3945 #define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ 3946 #define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ 3947 3948 #define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ 3949 #define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ 3950 #define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ 3951 #define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ 3952 #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ 3953 #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ 3954 3955 3956 /* DMA.INTFLAGS bit masks and bit positions */ 3957 #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ 3958 #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ 3959 3960 #define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ 3961 #define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ 3962 3963 #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ 3964 #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ 3965 3966 #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ 3967 #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ 3968 3969 #define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ 3970 #define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ 3971 3972 #define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ 3973 #define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ 3974 3975 #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ 3976 #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ 3977 3978 #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ 3979 #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ 3980 3981 3982 /* DMA.STATUS bit masks and bit positions */ 3983 #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ 3984 #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ 3985 3986 #define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ 3987 #define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ 3988 3989 #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ 3990 #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ 3991 3992 #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ 3993 #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ 3994 3995 #define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ 3996 #define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ 3997 3998 #define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ 3999 #define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ 4000 4001 #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ 4002 #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ 4003 4004 #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ 4005 #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ 4006 4007 4008 /* EVSYS - Event System */ 4009 /* EVSYS.CH0MUX bit masks and bit positions */ 4010 #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ 4011 #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ 4012 #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ 4013 #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ 4014 #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ 4015 #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ 4016 #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ 4017 #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ 4018 #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ 4019 #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ 4020 #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ 4021 #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ 4022 #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ 4023 #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ 4024 #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ 4025 #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ 4026 #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ 4027 #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ 4028 4029 4030 /* EVSYS.CH1MUX bit masks and bit positions */ 4031 /* EVSYS_CHMUX_gm Predefined. */ 4032 /* EVSYS_CHMUX_gp Predefined. */ 4033 /* EVSYS_CHMUX0_bm Predefined. */ 4034 /* EVSYS_CHMUX0_bp Predefined. */ 4035 /* EVSYS_CHMUX1_bm Predefined. */ 4036 /* EVSYS_CHMUX1_bp Predefined. */ 4037 /* EVSYS_CHMUX2_bm Predefined. */ 4038 /* EVSYS_CHMUX2_bp Predefined. */ 4039 /* EVSYS_CHMUX3_bm Predefined. */ 4040 /* EVSYS_CHMUX3_bp Predefined. */ 4041 /* EVSYS_CHMUX4_bm Predefined. */ 4042 /* EVSYS_CHMUX4_bp Predefined. */ 4043 /* EVSYS_CHMUX5_bm Predefined. */ 4044 /* EVSYS_CHMUX5_bp Predefined. */ 4045 /* EVSYS_CHMUX6_bm Predefined. */ 4046 /* EVSYS_CHMUX6_bp Predefined. */ 4047 /* EVSYS_CHMUX7_bm Predefined. */ 4048 /* EVSYS_CHMUX7_bp Predefined. */ 4049 4050 4051 /* EVSYS.CH2MUX bit masks and bit positions */ 4052 /* EVSYS_CHMUX_gm Predefined. */ 4053 /* EVSYS_CHMUX_gp Predefined. */ 4054 /* EVSYS_CHMUX0_bm Predefined. */ 4055 /* EVSYS_CHMUX0_bp Predefined. */ 4056 /* EVSYS_CHMUX1_bm Predefined. */ 4057 /* EVSYS_CHMUX1_bp Predefined. */ 4058 /* EVSYS_CHMUX2_bm Predefined. */ 4059 /* EVSYS_CHMUX2_bp Predefined. */ 4060 /* EVSYS_CHMUX3_bm Predefined. */ 4061 /* EVSYS_CHMUX3_bp Predefined. */ 4062 /* EVSYS_CHMUX4_bm Predefined. */ 4063 /* EVSYS_CHMUX4_bp Predefined. */ 4064 /* EVSYS_CHMUX5_bm Predefined. */ 4065 /* EVSYS_CHMUX5_bp Predefined. */ 4066 /* EVSYS_CHMUX6_bm Predefined. */ 4067 /* EVSYS_CHMUX6_bp Predefined. */ 4068 /* EVSYS_CHMUX7_bm Predefined. */ 4069 /* EVSYS_CHMUX7_bp Predefined. */ 4070 4071 4072 /* EVSYS.CH3MUX bit masks and bit positions */ 4073 /* EVSYS_CHMUX_gm Predefined. */ 4074 /* EVSYS_CHMUX_gp Predefined. */ 4075 /* EVSYS_CHMUX0_bm Predefined. */ 4076 /* EVSYS_CHMUX0_bp Predefined. */ 4077 /* EVSYS_CHMUX1_bm Predefined. */ 4078 /* EVSYS_CHMUX1_bp Predefined. */ 4079 /* EVSYS_CHMUX2_bm Predefined. */ 4080 /* EVSYS_CHMUX2_bp Predefined. */ 4081 /* EVSYS_CHMUX3_bm Predefined. */ 4082 /* EVSYS_CHMUX3_bp Predefined. */ 4083 /* EVSYS_CHMUX4_bm Predefined. */ 4084 /* EVSYS_CHMUX4_bp Predefined. */ 4085 /* EVSYS_CHMUX5_bm Predefined. */ 4086 /* EVSYS_CHMUX5_bp Predefined. */ 4087 /* EVSYS_CHMUX6_bm Predefined. */ 4088 /* EVSYS_CHMUX6_bp Predefined. */ 4089 /* EVSYS_CHMUX7_bm Predefined. */ 4090 /* EVSYS_CHMUX7_bp Predefined. */ 4091 4092 4093 /* EVSYS.CH4MUX bit masks and bit positions */ 4094 /* EVSYS_CHMUX_gm Predefined. */ 4095 /* EVSYS_CHMUX_gp Predefined. */ 4096 /* EVSYS_CHMUX0_bm Predefined. */ 4097 /* EVSYS_CHMUX0_bp Predefined. */ 4098 /* EVSYS_CHMUX1_bm Predefined. */ 4099 /* EVSYS_CHMUX1_bp Predefined. */ 4100 /* EVSYS_CHMUX2_bm Predefined. */ 4101 /* EVSYS_CHMUX2_bp Predefined. */ 4102 /* EVSYS_CHMUX3_bm Predefined. */ 4103 /* EVSYS_CHMUX3_bp Predefined. */ 4104 /* EVSYS_CHMUX4_bm Predefined. */ 4105 /* EVSYS_CHMUX4_bp Predefined. */ 4106 /* EVSYS_CHMUX5_bm Predefined. */ 4107 /* EVSYS_CHMUX5_bp Predefined. */ 4108 /* EVSYS_CHMUX6_bm Predefined. */ 4109 /* EVSYS_CHMUX6_bp Predefined. */ 4110 /* EVSYS_CHMUX7_bm Predefined. */ 4111 /* EVSYS_CHMUX7_bp Predefined. */ 4112 4113 4114 /* EVSYS.CH5MUX bit masks and bit positions */ 4115 /* EVSYS_CHMUX_gm Predefined. */ 4116 /* EVSYS_CHMUX_gp Predefined. */ 4117 /* EVSYS_CHMUX0_bm Predefined. */ 4118 /* EVSYS_CHMUX0_bp Predefined. */ 4119 /* EVSYS_CHMUX1_bm Predefined. */ 4120 /* EVSYS_CHMUX1_bp Predefined. */ 4121 /* EVSYS_CHMUX2_bm Predefined. */ 4122 /* EVSYS_CHMUX2_bp Predefined. */ 4123 /* EVSYS_CHMUX3_bm Predefined. */ 4124 /* EVSYS_CHMUX3_bp Predefined. */ 4125 /* EVSYS_CHMUX4_bm Predefined. */ 4126 /* EVSYS_CHMUX4_bp Predefined. */ 4127 /* EVSYS_CHMUX5_bm Predefined. */ 4128 /* EVSYS_CHMUX5_bp Predefined. */ 4129 /* EVSYS_CHMUX6_bm Predefined. */ 4130 /* EVSYS_CHMUX6_bp Predefined. */ 4131 /* EVSYS_CHMUX7_bm Predefined. */ 4132 /* EVSYS_CHMUX7_bp Predefined. */ 4133 4134 4135 /* EVSYS.CH6MUX bit masks and bit positions */ 4136 /* EVSYS_CHMUX_gm Predefined. */ 4137 /* EVSYS_CHMUX_gp Predefined. */ 4138 /* EVSYS_CHMUX0_bm Predefined. */ 4139 /* EVSYS_CHMUX0_bp Predefined. */ 4140 /* EVSYS_CHMUX1_bm Predefined. */ 4141 /* EVSYS_CHMUX1_bp Predefined. */ 4142 /* EVSYS_CHMUX2_bm Predefined. */ 4143 /* EVSYS_CHMUX2_bp Predefined. */ 4144 /* EVSYS_CHMUX3_bm Predefined. */ 4145 /* EVSYS_CHMUX3_bp Predefined. */ 4146 /* EVSYS_CHMUX4_bm Predefined. */ 4147 /* EVSYS_CHMUX4_bp Predefined. */ 4148 /* EVSYS_CHMUX5_bm Predefined. */ 4149 /* EVSYS_CHMUX5_bp Predefined. */ 4150 /* EVSYS_CHMUX6_bm Predefined. */ 4151 /* EVSYS_CHMUX6_bp Predefined. */ 4152 /* EVSYS_CHMUX7_bm Predefined. */ 4153 /* EVSYS_CHMUX7_bp Predefined. */ 4154 4155 4156 /* EVSYS.CH7MUX bit masks and bit positions */ 4157 /* EVSYS_CHMUX_gm Predefined. */ 4158 /* EVSYS_CHMUX_gp Predefined. */ 4159 /* EVSYS_CHMUX0_bm Predefined. */ 4160 /* EVSYS_CHMUX0_bp Predefined. */ 4161 /* EVSYS_CHMUX1_bm Predefined. */ 4162 /* EVSYS_CHMUX1_bp Predefined. */ 4163 /* EVSYS_CHMUX2_bm Predefined. */ 4164 /* EVSYS_CHMUX2_bp Predefined. */ 4165 /* EVSYS_CHMUX3_bm Predefined. */ 4166 /* EVSYS_CHMUX3_bp Predefined. */ 4167 /* EVSYS_CHMUX4_bm Predefined. */ 4168 /* EVSYS_CHMUX4_bp Predefined. */ 4169 /* EVSYS_CHMUX5_bm Predefined. */ 4170 /* EVSYS_CHMUX5_bp Predefined. */ 4171 /* EVSYS_CHMUX6_bm Predefined. */ 4172 /* EVSYS_CHMUX6_bp Predefined. */ 4173 /* EVSYS_CHMUX7_bm Predefined. */ 4174 /* EVSYS_CHMUX7_bp Predefined. */ 4175 4176 4177 /* EVSYS.CH0CTRL bit masks and bit positions */ 4178 #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ 4179 #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ 4180 #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ 4181 #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ 4182 #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ 4183 #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ 4184 4185 #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ 4186 #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ 4187 4188 #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ 4189 #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ 4190 4191 #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ 4192 #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ 4193 #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ 4194 #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ 4195 #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ 4196 #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ 4197 #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ 4198 #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ 4199 4200 4201 /* EVSYS.CH1CTRL bit masks and bit positions */ 4202 /* EVSYS_DIGFILT_gm Predefined. */ 4203 /* EVSYS_DIGFILT_gp Predefined. */ 4204 /* EVSYS_DIGFILT0_bm Predefined. */ 4205 /* EVSYS_DIGFILT0_bp Predefined. */ 4206 /* EVSYS_DIGFILT1_bm Predefined. */ 4207 /* EVSYS_DIGFILT1_bp Predefined. */ 4208 /* EVSYS_DIGFILT2_bm Predefined. */ 4209 /* EVSYS_DIGFILT2_bp Predefined. */ 4210 4211 4212 /* EVSYS.CH2CTRL bit masks and bit positions */ 4213 /* EVSYS_QDIRM_gm Predefined. */ 4214 /* EVSYS_QDIRM_gp Predefined. */ 4215 /* EVSYS_QDIRM0_bm Predefined. */ 4216 /* EVSYS_QDIRM0_bp Predefined. */ 4217 /* EVSYS_QDIRM1_bm Predefined. */ 4218 /* EVSYS_QDIRM1_bp Predefined. */ 4219 4220 /* EVSYS_QDIEN_bm Predefined. */ 4221 /* EVSYS_QDIEN_bp Predefined. */ 4222 4223 /* EVSYS_QDEN_bm Predefined. */ 4224 /* EVSYS_QDEN_bp Predefined. */ 4225 4226 /* EVSYS_DIGFILT_gm Predefined. */ 4227 /* EVSYS_DIGFILT_gp Predefined. */ 4228 /* EVSYS_DIGFILT0_bm Predefined. */ 4229 /* EVSYS_DIGFILT0_bp Predefined. */ 4230 /* EVSYS_DIGFILT1_bm Predefined. */ 4231 /* EVSYS_DIGFILT1_bp Predefined. */ 4232 /* EVSYS_DIGFILT2_bm Predefined. */ 4233 /* EVSYS_DIGFILT2_bp Predefined. */ 4234 4235 4236 /* EVSYS.CH3CTRL bit masks and bit positions */ 4237 /* EVSYS_DIGFILT_gm Predefined. */ 4238 /* EVSYS_DIGFILT_gp Predefined. */ 4239 /* EVSYS_DIGFILT0_bm Predefined. */ 4240 /* EVSYS_DIGFILT0_bp Predefined. */ 4241 /* EVSYS_DIGFILT1_bm Predefined. */ 4242 /* EVSYS_DIGFILT1_bp Predefined. */ 4243 /* EVSYS_DIGFILT2_bm Predefined. */ 4244 /* EVSYS_DIGFILT2_bp Predefined. */ 4245 4246 4247 /* EVSYS.CH4CTRL bit masks and bit positions */ 4248 /* EVSYS_QDIRM_gm Predefined. */ 4249 /* EVSYS_QDIRM_gp Predefined. */ 4250 /* EVSYS_QDIRM0_bm Predefined. */ 4251 /* EVSYS_QDIRM0_bp Predefined. */ 4252 /* EVSYS_QDIRM1_bm Predefined. */ 4253 /* EVSYS_QDIRM1_bp Predefined. */ 4254 4255 /* EVSYS_QDIEN_bm Predefined. */ 4256 /* EVSYS_QDIEN_bp Predefined. */ 4257 4258 /* EVSYS_QDEN_bm Predefined. */ 4259 /* EVSYS_QDEN_bp Predefined. */ 4260 4261 /* EVSYS_DIGFILT_gm Predefined. */ 4262 /* EVSYS_DIGFILT_gp Predefined. */ 4263 /* EVSYS_DIGFILT0_bm Predefined. */ 4264 /* EVSYS_DIGFILT0_bp Predefined. */ 4265 /* EVSYS_DIGFILT1_bm Predefined. */ 4266 /* EVSYS_DIGFILT1_bp Predefined. */ 4267 /* EVSYS_DIGFILT2_bm Predefined. */ 4268 /* EVSYS_DIGFILT2_bp Predefined. */ 4269 4270 4271 /* EVSYS.CH5CTRL bit masks and bit positions */ 4272 /* EVSYS_DIGFILT_gm Predefined. */ 4273 /* EVSYS_DIGFILT_gp Predefined. */ 4274 /* EVSYS_DIGFILT0_bm Predefined. */ 4275 /* EVSYS_DIGFILT0_bp Predefined. */ 4276 /* EVSYS_DIGFILT1_bm Predefined. */ 4277 /* EVSYS_DIGFILT1_bp Predefined. */ 4278 /* EVSYS_DIGFILT2_bm Predefined. */ 4279 /* EVSYS_DIGFILT2_bp Predefined. */ 4280 4281 4282 /* EVSYS.CH6CTRL bit masks and bit positions */ 4283 /* EVSYS_DIGFILT_gm Predefined. */ 4284 /* EVSYS_DIGFILT_gp Predefined. */ 4285 /* EVSYS_DIGFILT0_bm Predefined. */ 4286 /* EVSYS_DIGFILT0_bp Predefined. */ 4287 /* EVSYS_DIGFILT1_bm Predefined. */ 4288 /* EVSYS_DIGFILT1_bp Predefined. */ 4289 /* EVSYS_DIGFILT2_bm Predefined. */ 4290 /* EVSYS_DIGFILT2_bp Predefined. */ 4291 4292 4293 /* EVSYS.CH7CTRL bit masks and bit positions */ 4294 /* EVSYS_DIGFILT_gm Predefined. */ 4295 /* EVSYS_DIGFILT_gp Predefined. */ 4296 /* EVSYS_DIGFILT0_bm Predefined. */ 4297 /* EVSYS_DIGFILT0_bp Predefined. */ 4298 /* EVSYS_DIGFILT1_bm Predefined. */ 4299 /* EVSYS_DIGFILT1_bp Predefined. */ 4300 /* EVSYS_DIGFILT2_bm Predefined. */ 4301 /* EVSYS_DIGFILT2_bp Predefined. */ 4302 4303 4304 /* NVM - Non Volatile Memory Controller */ 4305 /* NVM.CMD bit masks and bit positions */ 4306 #define NVM_CMD_gm 0xFF /* Command group mask. */ 4307 #define NVM_CMD_gp 0 /* Command group position. */ 4308 #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ 4309 #define NVM_CMD0_bp 0 /* Command bit 0 position. */ 4310 #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ 4311 #define NVM_CMD1_bp 1 /* Command bit 1 position. */ 4312 #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ 4313 #define NVM_CMD2_bp 2 /* Command bit 2 position. */ 4314 #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ 4315 #define NVM_CMD3_bp 3 /* Command bit 3 position. */ 4316 #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ 4317 #define NVM_CMD4_bp 4 /* Command bit 4 position. */ 4318 #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ 4319 #define NVM_CMD5_bp 5 /* Command bit 5 position. */ 4320 #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ 4321 #define NVM_CMD6_bp 6 /* Command bit 6 position. */ 4322 #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ 4323 #define NVM_CMD7_bp 7 /* Command bit 7 position. */ 4324 4325 4326 /* NVM.CTRLA bit masks and bit positions */ 4327 #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ 4328 #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ 4329 4330 4331 /* NVM.CTRLB bit masks and bit positions */ 4332 #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ 4333 #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ 4334 4335 #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ 4336 #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ 4337 4338 #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ 4339 #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ 4340 4341 #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ 4342 #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ 4343 4344 4345 /* NVM.INTCTRL bit masks and bit positions */ 4346 #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ 4347 #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ 4348 #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ 4349 #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ 4350 #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ 4351 #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ 4352 4353 #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ 4354 #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ 4355 #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ 4356 #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ 4357 #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ 4358 #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ 4359 4360 4361 /* NVM.STATUS bit masks and bit positions */ 4362 #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ 4363 #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ 4364 4365 #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ 4366 #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ 4367 4368 #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ 4369 #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ 4370 4371 #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ 4372 #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ 4373 4374 4375 /* NVM.LOCKBITS bit masks and bit positions */ 4376 #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ 4377 #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ 4378 #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ 4379 #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ 4380 #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ 4381 #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ 4382 4383 #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ 4384 #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ 4385 #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ 4386 #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ 4387 #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ 4388 #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ 4389 4390 #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ 4391 #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ 4392 #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ 4393 #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ 4394 #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ 4395 #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ 4396 4397 #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ 4398 #define NVM_LB_gp 0 /* Lock Bits group position. */ 4399 #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ 4400 #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ 4401 #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ 4402 #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ 4403 4404 4405 /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ 4406 #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ 4407 #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ 4408 #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ 4409 #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ 4410 #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ 4411 #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ 4412 4413 #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ 4414 #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ 4415 #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ 4416 #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ 4417 #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ 4418 #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ 4419 4420 #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ 4421 #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ 4422 #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ 4423 #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ 4424 #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ 4425 #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ 4426 4427 #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ 4428 #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ 4429 #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ 4430 #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ 4431 #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ 4432 #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ 4433 4434 4435 /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ 4436 #define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ 4437 #define NVM_FUSES_USERID_gp 0 /* User ID group position. */ 4438 #define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ 4439 #define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ 4440 #define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ 4441 #define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ 4442 #define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ 4443 #define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ 4444 #define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ 4445 #define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ 4446 #define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ 4447 #define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ 4448 #define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ 4449 #define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ 4450 #define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ 4451 #define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ 4452 #define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ 4453 #define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ 4454 4455 4456 /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ 4457 #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ 4458 #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ 4459 #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ 4460 #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ 4461 #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ 4462 #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ 4463 #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ 4464 #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ 4465 #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ 4466 #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ 4467 4468 #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ 4469 #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ 4470 #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ 4471 #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ 4472 #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ 4473 #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ 4474 #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ 4475 #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ 4476 #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ 4477 #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ 4478 4479 4480 /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ 4481 #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ 4482 #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ 4483 4484 #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ 4485 #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ 4486 4487 #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ 4488 #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ 4489 #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ 4490 #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ 4491 #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ 4492 #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ 4493 4494 4495 /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ 4496 #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ 4497 #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ 4498 #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ 4499 #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ 4500 #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ 4501 #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ 4502 4503 #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ 4504 #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ 4505 4506 4507 /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ 4508 #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ 4509 #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ 4510 #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ 4511 #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ 4512 #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ 4513 #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ 4514 4515 #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ 4516 #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ 4517 4518 #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ 4519 #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ 4520 #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ 4521 #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ 4522 #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ 4523 #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ 4524 #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ 4525 #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ 4526 4527 4528 /* AC - Analog Comparator */ 4529 /* AC.AC0CTRL bit masks and bit positions */ 4530 #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ 4531 #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ 4532 #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ 4533 #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ 4534 #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ 4535 #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ 4536 4537 #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ 4538 #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ 4539 #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ 4540 #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ 4541 #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ 4542 #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ 4543 4544 #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ 4545 #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ 4546 4547 #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ 4548 #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ 4549 #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ 4550 #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ 4551 #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ 4552 #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ 4553 4554 #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ 4555 #define AC_ENABLE_bp 0 /* Enable bit position. */ 4556 4557 4558 /* AC.AC1CTRL bit masks and bit positions */ 4559 /* AC_INTMODE_gm Predefined. */ 4560 /* AC_INTMODE_gp Predefined. */ 4561 /* AC_INTMODE0_bm Predefined. */ 4562 /* AC_INTMODE0_bp Predefined. */ 4563 /* AC_INTMODE1_bm Predefined. */ 4564 /* AC_INTMODE1_bp Predefined. */ 4565 4566 /* AC_INTLVL_gm Predefined. */ 4567 /* AC_INTLVL_gp Predefined. */ 4568 /* AC_INTLVL0_bm Predefined. */ 4569 /* AC_INTLVL0_bp Predefined. */ 4570 /* AC_INTLVL1_bm Predefined. */ 4571 /* AC_INTLVL1_bp Predefined. */ 4572 4573 /* AC_HSMODE_bm Predefined. */ 4574 /* AC_HSMODE_bp Predefined. */ 4575 4576 /* AC_HYSMODE_gm Predefined. */ 4577 /* AC_HYSMODE_gp Predefined. */ 4578 /* AC_HYSMODE0_bm Predefined. */ 4579 /* AC_HYSMODE0_bp Predefined. */ 4580 /* AC_HYSMODE1_bm Predefined. */ 4581 /* AC_HYSMODE1_bp Predefined. */ 4582 4583 /* AC_ENABLE_bm Predefined. */ 4584 /* AC_ENABLE_bp Predefined. */ 4585 4586 4587 /* AC.AC0MUXCTRL bit masks and bit positions */ 4588 #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ 4589 #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ 4590 #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ 4591 #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ 4592 #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ 4593 #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ 4594 #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ 4595 #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ 4596 4597 #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ 4598 #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ 4599 #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ 4600 #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ 4601 #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ 4602 #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ 4603 #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ 4604 #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ 4605 4606 4607 /* AC.AC1MUXCTRL bit masks and bit positions */ 4608 /* AC_MUXPOS_gm Predefined. */ 4609 /* AC_MUXPOS_gp Predefined. */ 4610 /* AC_MUXPOS0_bm Predefined. */ 4611 /* AC_MUXPOS0_bp Predefined. */ 4612 /* AC_MUXPOS1_bm Predefined. */ 4613 /* AC_MUXPOS1_bp Predefined. */ 4614 /* AC_MUXPOS2_bm Predefined. */ 4615 /* AC_MUXPOS2_bp Predefined. */ 4616 4617 /* AC_MUXNEG_gm Predefined. */ 4618 /* AC_MUXNEG_gp Predefined. */ 4619 /* AC_MUXNEG0_bm Predefined. */ 4620 /* AC_MUXNEG0_bp Predefined. */ 4621 /* AC_MUXNEG1_bm Predefined. */ 4622 /* AC_MUXNEG1_bp Predefined. */ 4623 /* AC_MUXNEG2_bm Predefined. */ 4624 /* AC_MUXNEG2_bp Predefined. */ 4625 4626 4627 /* AC.CTRLA bit masks and bit positions */ 4628 #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ 4629 #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ 4630 4631 4632 /* AC.CTRLB bit masks and bit positions */ 4633 #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ 4634 #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ 4635 #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ 4636 #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ 4637 #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ 4638 #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ 4639 #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ 4640 #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ 4641 #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ 4642 #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ 4643 #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ 4644 #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ 4645 #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ 4646 #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ 4647 4648 4649 /* AC.WINCTRL bit masks and bit positions */ 4650 #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ 4651 #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ 4652 4653 #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ 4654 #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ 4655 #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ 4656 #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ 4657 #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ 4658 #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ 4659 4660 #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ 4661 #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ 4662 #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ 4663 #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ 4664 #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ 4665 #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ 4666 4667 4668 /* AC.STATUS bit masks and bit positions */ 4669 #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ 4670 #define AC_WSTATE_gp 6 /* Window Mode State group position. */ 4671 #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ 4672 #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ 4673 #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ 4674 #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ 4675 4676 #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ 4677 #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ 4678 4679 #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ 4680 #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ 4681 4682 #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ 4683 #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ 4684 4685 #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ 4686 #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ 4687 4688 #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ 4689 #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ 4690 4691 4692 /* ADC - Analog/Digital Converter */ 4693 /* ADC_CH.CTRL bit masks and bit positions */ 4694 #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ 4695 #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ 4696 4697 #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ 4698 #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ 4699 #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ 4700 #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ 4701 #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ 4702 #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ 4703 #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ 4704 #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ 4705 4706 #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ 4707 #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ 4708 #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ 4709 #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ 4710 #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ 4711 #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ 4712 4713 4714 /* ADC_CH.MUXCTRL bit masks and bit positions */ 4715 #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ 4716 #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ 4717 #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ 4718 #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ 4719 #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ 4720 #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ 4721 #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ 4722 #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ 4723 #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ 4724 #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ 4725 4726 #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ 4727 #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ 4728 #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ 4729 #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ 4730 #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ 4731 #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ 4732 #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ 4733 #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ 4734 #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ 4735 #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ 4736 4737 #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ 4738 #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ 4739 #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ 4740 #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ 4741 #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ 4742 #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ 4743 4744 4745 /* ADC_CH.INTCTRL bit masks and bit positions */ 4746 #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ 4747 #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ 4748 #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ 4749 #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ 4750 #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ 4751 #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ 4752 4753 #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ 4754 #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ 4755 #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ 4756 #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ 4757 #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ 4758 #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ 4759 4760 4761 /* ADC_CH.INTFLAGS bit masks and bit positions */ 4762 #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ 4763 #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ 4764 4765 4766 /* ADC.CTRLA bit masks and bit positions */ 4767 #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ 4768 #define ADC_DMASEL_gp 6 /* DMA Selection group position. */ 4769 #define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ 4770 #define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ 4771 #define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ 4772 #define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ 4773 4774 #define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ 4775 #define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ 4776 4777 #define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ 4778 #define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ 4779 4780 #define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ 4781 #define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ 4782 4783 #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ 4784 #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ 4785 4786 #define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ 4787 #define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ 4788 4789 #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ 4790 #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ 4791 4792 4793 /* ADC.CTRLB bit masks and bit positions */ 4794 #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ 4795 #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ 4796 4797 #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ 4798 #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ 4799 4800 #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ 4801 #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ 4802 #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ 4803 #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ 4804 #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ 4805 #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ 4806 4807 4808 /* ADC.REFCTRL bit masks and bit positions */ 4809 #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ 4810 #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ 4811 #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ 4812 #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ 4813 #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ 4814 #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ 4815 4816 #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ 4817 #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ 4818 4819 #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ 4820 #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ 4821 4822 4823 /* ADC.EVCTRL bit masks and bit positions */ 4824 #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ 4825 #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ 4826 #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ 4827 #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ 4828 #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ 4829 #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ 4830 4831 #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ 4832 #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ 4833 #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ 4834 #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ 4835 #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ 4836 #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ 4837 #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ 4838 #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ 4839 4840 #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ 4841 #define ADC_EVACT_gp 0 /* Event Action Select group position. */ 4842 #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ 4843 #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ 4844 #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ 4845 #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ 4846 #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ 4847 #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ 4848 4849 4850 /* ADC.PRESCALER bit masks and bit positions */ 4851 #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ 4852 #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ 4853 #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ 4854 #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ 4855 #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ 4856 #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ 4857 #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ 4858 #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ 4859 4860 4861 /* ADC.INTFLAGS bit masks and bit positions */ 4862 #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ 4863 #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ 4864 4865 #define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ 4866 #define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ 4867 4868 #define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ 4869 #define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ 4870 4871 #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ 4872 #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ 4873 4874 4875 /* DAC - Digital/Analog Converter */ 4876 /* DAC.CTRLA bit masks and bit positions */ 4877 #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ 4878 #define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ 4879 4880 #define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ 4881 #define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ 4882 4883 #define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ 4884 #define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ 4885 4886 #define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ 4887 #define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ 4888 4889 #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ 4890 #define DAC_ENABLE_bp 0 /* Enable bit position. */ 4891 4892 4893 /* DAC.CTRLB bit masks and bit positions */ 4894 #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ 4895 #define DAC_CHSEL_gp 5 /* Channel Select group position. */ 4896 #define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ 4897 #define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ 4898 #define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ 4899 #define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ 4900 4901 #define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ 4902 #define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ 4903 4904 #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ 4905 #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ 4906 4907 4908 /* DAC.CTRLC bit masks and bit positions */ 4909 #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ 4910 #define DAC_REFSEL_gp 3 /* Reference Select group position. */ 4911 #define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ 4912 #define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ 4913 #define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ 4914 #define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ 4915 4916 #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ 4917 #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ 4918 4919 4920 /* DAC.EVCTRL bit masks and bit positions */ 4921 #define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ 4922 #define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ 4923 #define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ 4924 #define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ 4925 #define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ 4926 #define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ 4927 #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ 4928 #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ 4929 4930 4931 /* DAC.TIMCTRL bit masks and bit positions */ 4932 #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ 4933 #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ 4934 #define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ 4935 #define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ 4936 #define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ 4937 #define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ 4938 #define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ 4939 #define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ 4940 4941 #define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ 4942 #define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ 4943 #define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ 4944 #define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ 4945 #define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ 4946 #define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ 4947 #define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ 4948 #define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ 4949 #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ 4950 #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ 4951 4952 4953 /* DAC.STATUS bit masks and bit positions */ 4954 #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ 4955 #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ 4956 4957 #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ 4958 #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ 4959 4960 4961 /* RTC - Real-Time Clounter */ 4962 /* RTC.CTRL bit masks and bit positions */ 4963 #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ 4964 #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ 4965 #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ 4966 #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ 4967 #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ 4968 #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ 4969 #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ 4970 #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ 4971 4972 4973 /* RTC.STATUS bit masks and bit positions */ 4974 #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ 4975 #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ 4976 4977 4978 /* RTC.INTCTRL bit masks and bit positions */ 4979 #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ 4980 #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ 4981 #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ 4982 #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ 4983 #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ 4984 #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ 4985 4986 #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ 4987 #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ 4988 #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ 4989 #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ 4990 #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ 4991 #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ 4992 4993 4994 /* RTC.INTFLAGS bit masks and bit positions */ 4995 #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ 4996 #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ 4997 4998 #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 4999 #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 5000 5001 5002 /* EBI - External Bus Interface */ 5003 /* EBI_CS.CTRLA bit masks and bit positions */ 5004 #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ 5005 #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ 5006 #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ 5007 #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ 5008 #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ 5009 #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ 5010 #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ 5011 #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ 5012 #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ 5013 #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ 5014 #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ 5015 #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ 5016 5017 #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ 5018 #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ 5019 #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ 5020 #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ 5021 #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ 5022 #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ 5023 5024 5025 /* EBI_CS.CTRLB bit masks and bit positions */ 5026 #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ 5027 #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ 5028 #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ 5029 #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ 5030 #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ 5031 #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ 5032 #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ 5033 #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ 5034 5035 #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ 5036 #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ 5037 5038 #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ 5039 #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ 5040 5041 #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ 5042 #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ 5043 #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ 5044 #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ 5045 #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ 5046 #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ 5047 5048 5049 /* EBI.CTRL bit masks and bit positions */ 5050 #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ 5051 #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ 5052 #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ 5053 #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ 5054 #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ 5055 #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ 5056 5057 #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ 5058 #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ 5059 #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ 5060 #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ 5061 #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ 5062 #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ 5063 5064 #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ 5065 #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ 5066 #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ 5067 #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ 5068 #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ 5069 #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ 5070 5071 #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ 5072 #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ 5073 #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ 5074 #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ 5075 #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ 5076 #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ 5077 5078 5079 /* EBI.SDRAMCTRLA bit masks and bit positions */ 5080 #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ 5081 #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ 5082 5083 #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ 5084 #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ 5085 5086 #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ 5087 #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ 5088 #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ 5089 #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ 5090 #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ 5091 #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ 5092 5093 5094 /* EBI.SDRAMCTRLB bit masks and bit positions */ 5095 #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ 5096 #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ 5097 #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ 5098 #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ 5099 #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ 5100 #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ 5101 5102 #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ 5103 #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ 5104 #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ 5105 #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ 5106 #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ 5107 #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ 5108 #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ 5109 #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ 5110 5111 #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ 5112 #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ 5113 #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ 5114 #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ 5115 #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ 5116 #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ 5117 #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ 5118 #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ 5119 5120 5121 /* EBI.SDRAMCTRLC bit masks and bit positions */ 5122 #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ 5123 #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ 5124 #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ 5125 #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ 5126 #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ 5127 #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ 5128 5129 #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ 5130 #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ 5131 #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ 5132 #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ 5133 #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ 5134 #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ 5135 #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ 5136 #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ 5137 5138 #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ 5139 #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ 5140 #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ 5141 #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ 5142 #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ 5143 #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ 5144 #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ 5145 #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ 5146 5147 5148 /* TWI - Two-Wire Interface */ 5149 /* TWI_MASTER.CTRLA bit masks and bit positions */ 5150 #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ 5151 #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ 5152 #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ 5153 #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ 5154 #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ 5155 #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ 5156 5157 #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ 5158 #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ 5159 5160 #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ 5161 #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ 5162 5163 #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ 5164 #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ 5165 5166 5167 /* TWI_MASTER.CTRLB bit masks and bit positions */ 5168 #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ 5169 #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ 5170 #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ 5171 #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ 5172 #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ 5173 #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ 5174 5175 #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ 5176 #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ 5177 5178 #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ 5179 #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ 5180 5181 5182 /* TWI_MASTER.CTRLC bit masks and bit positions */ 5183 #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ 5184 #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ 5185 5186 #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ 5187 #define TWI_MASTER_CMD_gp 0 /* Command group position. */ 5188 #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ 5189 #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ 5190 #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ 5191 #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ 5192 5193 5194 /* TWI_MASTER.STATUS bit masks and bit positions */ 5195 #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ 5196 #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ 5197 5198 #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ 5199 #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ 5200 5201 #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ 5202 #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ 5203 5204 #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ 5205 #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ 5206 5207 #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ 5208 #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ 5209 5210 #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ 5211 #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ 5212 5213 #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ 5214 #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ 5215 #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ 5216 #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ 5217 #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ 5218 #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ 5219 5220 5221 /* TWI_SLAVE.CTRLA bit masks and bit positions */ 5222 #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ 5223 #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ 5224 #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ 5225 #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ 5226 #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ 5227 #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ 5228 5229 #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ 5230 #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ 5231 5232 #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ 5233 #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ 5234 5235 #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ 5236 #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ 5237 5238 #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ 5239 #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ 5240 5241 #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ 5242 #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ 5243 5244 #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ 5245 #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ 5246 5247 5248 /* TWI_SLAVE.CTRLB bit masks and bit positions */ 5249 #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ 5250 #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ 5251 5252 #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ 5253 #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ 5254 #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ 5255 #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ 5256 #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ 5257 #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ 5258 5259 5260 /* TWI_SLAVE.STATUS bit masks and bit positions */ 5261 #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ 5262 #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ 5263 5264 #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ 5265 #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ 5266 5267 #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ 5268 #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ 5269 5270 #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ 5271 #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ 5272 5273 #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ 5274 #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ 5275 5276 #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ 5277 #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ 5278 5279 #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ 5280 #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ 5281 5282 #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ 5283 #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ 5284 5285 5286 /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ 5287 #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ 5288 #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ 5289 #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ 5290 #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ 5291 #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ 5292 #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ 5293 #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ 5294 #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ 5295 #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ 5296 #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ 5297 #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ 5298 #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ 5299 #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ 5300 #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ 5301 #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ 5302 #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ 5303 5304 #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ 5305 #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ 5306 5307 5308 /* TWI.CTRL bit masks and bit positions */ 5309 #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ 5310 #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ 5311 5312 #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ 5313 #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ 5314 5315 5316 /* PORT - Port Configuration */ 5317 /* PORTCFG.VPCTRLA bit masks and bit positions */ 5318 #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ 5319 #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ 5320 #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ 5321 #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ 5322 #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ 5323 #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ 5324 #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ 5325 #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ 5326 #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ 5327 #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ 5328 5329 #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ 5330 #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ 5331 #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ 5332 #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ 5333 #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ 5334 #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ 5335 #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ 5336 #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ 5337 #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ 5338 #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ 5339 5340 5341 /* PORTCFG.VPCTRLB bit masks and bit positions */ 5342 #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ 5343 #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ 5344 #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ 5345 #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ 5346 #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ 5347 #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ 5348 #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ 5349 #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ 5350 #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ 5351 #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ 5352 5353 #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ 5354 #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ 5355 #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ 5356 #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ 5357 #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ 5358 #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ 5359 #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ 5360 #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ 5361 #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ 5362 #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ 5363 5364 5365 /* PORTCFG.CLKEVOUT bit masks and bit positions */ 5366 #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ 5367 #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ 5368 #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ 5369 #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ 5370 #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ 5371 #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ 5372 5373 #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ 5374 #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ 5375 #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ 5376 #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ 5377 #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ 5378 #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ 5379 5380 5381 /* VPORT.INTFLAGS bit masks and bit positions */ 5382 #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ 5383 #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ 5384 5385 #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ 5386 #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ 5387 5388 5389 /* PORT.INTCTRL bit masks and bit positions */ 5390 #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ 5391 #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ 5392 #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ 5393 #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ 5394 #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ 5395 #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ 5396 5397 #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ 5398 #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ 5399 #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ 5400 #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ 5401 #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ 5402 #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ 5403 5404 5405 /* PORT.INTFLAGS bit masks and bit positions */ 5406 #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ 5407 #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ 5408 5409 #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ 5410 #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ 5411 5412 5413 /* PORT.PIN0CTRL bit masks and bit positions */ 5414 #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ 5415 #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ 5416 5417 #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ 5418 #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ 5419 5420 #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ 5421 #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ 5422 #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ 5423 #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ 5424 #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ 5425 #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ 5426 #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ 5427 #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ 5428 5429 #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ 5430 #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ 5431 #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ 5432 #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ 5433 #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ 5434 #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ 5435 #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ 5436 #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ 5437 5438 5439 /* PORT.PIN1CTRL bit masks and bit positions */ 5440 /* PORT_SRLEN_bm Predefined. */ 5441 /* PORT_SRLEN_bp Predefined. */ 5442 5443 /* PORT_INVEN_bm Predefined. */ 5444 /* PORT_INVEN_bp Predefined. */ 5445 5446 /* PORT_OPC_gm Predefined. */ 5447 /* PORT_OPC_gp Predefined. */ 5448 /* PORT_OPC0_bm Predefined. */ 5449 /* PORT_OPC0_bp Predefined. */ 5450 /* PORT_OPC1_bm Predefined. */ 5451 /* PORT_OPC1_bp Predefined. */ 5452 /* PORT_OPC2_bm Predefined. */ 5453 /* PORT_OPC2_bp Predefined. */ 5454 5455 /* PORT_ISC_gm Predefined. */ 5456 /* PORT_ISC_gp Predefined. */ 5457 /* PORT_ISC0_bm Predefined. */ 5458 /* PORT_ISC0_bp Predefined. */ 5459 /* PORT_ISC1_bm Predefined. */ 5460 /* PORT_ISC1_bp Predefined. */ 5461 /* PORT_ISC2_bm Predefined. */ 5462 /* PORT_ISC2_bp Predefined. */ 5463 5464 5465 /* PORT.PIN2CTRL bit masks and bit positions */ 5466 /* PORT_SRLEN_bm Predefined. */ 5467 /* PORT_SRLEN_bp Predefined. */ 5468 5469 /* PORT_INVEN_bm Predefined. */ 5470 /* PORT_INVEN_bp Predefined. */ 5471 5472 /* PORT_OPC_gm Predefined. */ 5473 /* PORT_OPC_gp Predefined. */ 5474 /* PORT_OPC0_bm Predefined. */ 5475 /* PORT_OPC0_bp Predefined. */ 5476 /* PORT_OPC1_bm Predefined. */ 5477 /* PORT_OPC1_bp Predefined. */ 5478 /* PORT_OPC2_bm Predefined. */ 5479 /* PORT_OPC2_bp Predefined. */ 5480 5481 /* PORT_ISC_gm Predefined. */ 5482 /* PORT_ISC_gp Predefined. */ 5483 /* PORT_ISC0_bm Predefined. */ 5484 /* PORT_ISC0_bp Predefined. */ 5485 /* PORT_ISC1_bm Predefined. */ 5486 /* PORT_ISC1_bp Predefined. */ 5487 /* PORT_ISC2_bm Predefined. */ 5488 /* PORT_ISC2_bp Predefined. */ 5489 5490 5491 /* PORT.PIN3CTRL bit masks and bit positions */ 5492 /* PORT_SRLEN_bm Predefined. */ 5493 /* PORT_SRLEN_bp Predefined. */ 5494 5495 /* PORT_INVEN_bm Predefined. */ 5496 /* PORT_INVEN_bp Predefined. */ 5497 5498 /* PORT_OPC_gm Predefined. */ 5499 /* PORT_OPC_gp Predefined. */ 5500 /* PORT_OPC0_bm Predefined. */ 5501 /* PORT_OPC0_bp Predefined. */ 5502 /* PORT_OPC1_bm Predefined. */ 5503 /* PORT_OPC1_bp Predefined. */ 5504 /* PORT_OPC2_bm Predefined. */ 5505 /* PORT_OPC2_bp Predefined. */ 5506 5507 /* PORT_ISC_gm Predefined. */ 5508 /* PORT_ISC_gp Predefined. */ 5509 /* PORT_ISC0_bm Predefined. */ 5510 /* PORT_ISC0_bp Predefined. */ 5511 /* PORT_ISC1_bm Predefined. */ 5512 /* PORT_ISC1_bp Predefined. */ 5513 /* PORT_ISC2_bm Predefined. */ 5514 /* PORT_ISC2_bp Predefined. */ 5515 5516 5517 /* PORT.PIN4CTRL bit masks and bit positions */ 5518 /* PORT_SRLEN_bm Predefined. */ 5519 /* PORT_SRLEN_bp Predefined. */ 5520 5521 /* PORT_INVEN_bm Predefined. */ 5522 /* PORT_INVEN_bp Predefined. */ 5523 5524 /* PORT_OPC_gm Predefined. */ 5525 /* PORT_OPC_gp Predefined. */ 5526 /* PORT_OPC0_bm Predefined. */ 5527 /* PORT_OPC0_bp Predefined. */ 5528 /* PORT_OPC1_bm Predefined. */ 5529 /* PORT_OPC1_bp Predefined. */ 5530 /* PORT_OPC2_bm Predefined. */ 5531 /* PORT_OPC2_bp Predefined. */ 5532 5533 /* PORT_ISC_gm Predefined. */ 5534 /* PORT_ISC_gp Predefined. */ 5535 /* PORT_ISC0_bm Predefined. */ 5536 /* PORT_ISC0_bp Predefined. */ 5537 /* PORT_ISC1_bm Predefined. */ 5538 /* PORT_ISC1_bp Predefined. */ 5539 /* PORT_ISC2_bm Predefined. */ 5540 /* PORT_ISC2_bp Predefined. */ 5541 5542 5543 /* PORT.PIN5CTRL bit masks and bit positions */ 5544 /* PORT_SRLEN_bm Predefined. */ 5545 /* PORT_SRLEN_bp Predefined. */ 5546 5547 /* PORT_INVEN_bm Predefined. */ 5548 /* PORT_INVEN_bp Predefined. */ 5549 5550 /* PORT_OPC_gm Predefined. */ 5551 /* PORT_OPC_gp Predefined. */ 5552 /* PORT_OPC0_bm Predefined. */ 5553 /* PORT_OPC0_bp Predefined. */ 5554 /* PORT_OPC1_bm Predefined. */ 5555 /* PORT_OPC1_bp Predefined. */ 5556 /* PORT_OPC2_bm Predefined. */ 5557 /* PORT_OPC2_bp Predefined. */ 5558 5559 /* PORT_ISC_gm Predefined. */ 5560 /* PORT_ISC_gp Predefined. */ 5561 /* PORT_ISC0_bm Predefined. */ 5562 /* PORT_ISC0_bp Predefined. */ 5563 /* PORT_ISC1_bm Predefined. */ 5564 /* PORT_ISC1_bp Predefined. */ 5565 /* PORT_ISC2_bm Predefined. */ 5566 /* PORT_ISC2_bp Predefined. */ 5567 5568 5569 /* PORT.PIN6CTRL bit masks and bit positions */ 5570 /* PORT_SRLEN_bm Predefined. */ 5571 /* PORT_SRLEN_bp Predefined. */ 5572 5573 /* PORT_INVEN_bm Predefined. */ 5574 /* PORT_INVEN_bp Predefined. */ 5575 5576 /* PORT_OPC_gm Predefined. */ 5577 /* PORT_OPC_gp Predefined. */ 5578 /* PORT_OPC0_bm Predefined. */ 5579 /* PORT_OPC0_bp Predefined. */ 5580 /* PORT_OPC1_bm Predefined. */ 5581 /* PORT_OPC1_bp Predefined. */ 5582 /* PORT_OPC2_bm Predefined. */ 5583 /* PORT_OPC2_bp Predefined. */ 5584 5585 /* PORT_ISC_gm Predefined. */ 5586 /* PORT_ISC_gp Predefined. */ 5587 /* PORT_ISC0_bm Predefined. */ 5588 /* PORT_ISC0_bp Predefined. */ 5589 /* PORT_ISC1_bm Predefined. */ 5590 /* PORT_ISC1_bp Predefined. */ 5591 /* PORT_ISC2_bm Predefined. */ 5592 /* PORT_ISC2_bp Predefined. */ 5593 5594 5595 /* PORT.PIN7CTRL bit masks and bit positions */ 5596 /* PORT_SRLEN_bm Predefined. */ 5597 /* PORT_SRLEN_bp Predefined. */ 5598 5599 /* PORT_INVEN_bm Predefined. */ 5600 /* PORT_INVEN_bp Predefined. */ 5601 5602 /* PORT_OPC_gm Predefined. */ 5603 /* PORT_OPC_gp Predefined. */ 5604 /* PORT_OPC0_bm Predefined. */ 5605 /* PORT_OPC0_bp Predefined. */ 5606 /* PORT_OPC1_bm Predefined. */ 5607 /* PORT_OPC1_bp Predefined. */ 5608 /* PORT_OPC2_bm Predefined. */ 5609 /* PORT_OPC2_bp Predefined. */ 5610 5611 /* PORT_ISC_gm Predefined. */ 5612 /* PORT_ISC_gp Predefined. */ 5613 /* PORT_ISC0_bm Predefined. */ 5614 /* PORT_ISC0_bp Predefined. */ 5615 /* PORT_ISC1_bm Predefined. */ 5616 /* PORT_ISC1_bp Predefined. */ 5617 /* PORT_ISC2_bm Predefined. */ 5618 /* PORT_ISC2_bp Predefined. */ 5619 5620 5621 /* TC - 16-bit Timer/Counter With PWM */ 5622 /* TC0.CTRLA bit masks and bit positions */ 5623 #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 5624 #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ 5625 #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 5626 #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 5627 #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 5628 #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 5629 #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 5630 #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 5631 #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 5632 #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 5633 5634 5635 /* TC0.CTRLB bit masks and bit positions */ 5636 #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ 5637 #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ 5638 5639 #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ 5640 #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ 5641 5642 #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ 5643 #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ 5644 5645 #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ 5646 #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ 5647 5648 #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ 5649 #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ 5650 #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ 5651 #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ 5652 #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ 5653 #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ 5654 #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ 5655 #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ 5656 5657 5658 /* TC0.CTRLC bit masks and bit positions */ 5659 #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ 5660 #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ 5661 5662 #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ 5663 #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ 5664 5665 #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ 5666 #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ 5667 5668 #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ 5669 #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ 5670 5671 5672 /* TC0.CTRLD bit masks and bit positions */ 5673 #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ 5674 #define TC0_EVACT_gp 5 /* Event Action group position. */ 5675 #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ 5676 #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ 5677 #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ 5678 #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ 5679 #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ 5680 #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ 5681 5682 #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ 5683 #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ 5684 5685 #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ 5686 #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ 5687 #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ 5688 #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ 5689 #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ 5690 #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ 5691 #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ 5692 #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ 5693 #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ 5694 #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ 5695 5696 5697 /* TC0.CTRLE bit masks and bit positions */ 5698 #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ 5699 #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ 5700 5701 #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ 5702 #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ 5703 5704 5705 /* TC0.INTCTRLA bit masks and bit positions */ 5706 #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ 5707 #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ 5708 #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ 5709 #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ 5710 #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ 5711 #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ 5712 5713 #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ 5714 #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ 5715 #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ 5716 #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ 5717 #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ 5718 #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ 5719 5720 5721 /* TC0.INTCTRLB bit masks and bit positions */ 5722 #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ 5723 #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ 5724 #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ 5725 #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ 5726 #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ 5727 #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ 5728 5729 #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ 5730 #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ 5731 #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ 5732 #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ 5733 #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ 5734 #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ 5735 5736 #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ 5737 #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ 5738 #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ 5739 #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ 5740 #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ 5741 #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ 5742 5743 #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ 5744 #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ 5745 #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ 5746 #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ 5747 #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ 5748 #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ 5749 5750 5751 /* TC0.CTRLFCLR bit masks and bit positions */ 5752 #define TC0_CMD_gm 0x0C /* Command group mask. */ 5753 #define TC0_CMD_gp 2 /* Command group position. */ 5754 #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ 5755 #define TC0_CMD0_bp 2 /* Command bit 0 position. */ 5756 #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ 5757 #define TC0_CMD1_bp 3 /* Command bit 1 position. */ 5758 5759 #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ 5760 #define TC0_LUPD_bp 1 /* Lock Update bit position. */ 5761 5762 #define TC0_DIR_bm 0x01 /* Direction bit mask. */ 5763 #define TC0_DIR_bp 0 /* Direction bit position. */ 5764 5765 5766 /* TC0.CTRLFSET bit masks and bit positions */ 5767 /* TC0_CMD_gm Predefined. */ 5768 /* TC0_CMD_gp Predefined. */ 5769 /* TC0_CMD0_bm Predefined. */ 5770 /* TC0_CMD0_bp Predefined. */ 5771 /* TC0_CMD1_bm Predefined. */ 5772 /* TC0_CMD1_bp Predefined. */ 5773 5774 /* TC0_LUPD_bm Predefined. */ 5775 /* TC0_LUPD_bp Predefined. */ 5776 5777 /* TC0_DIR_bm Predefined. */ 5778 /* TC0_DIR_bp Predefined. */ 5779 5780 5781 /* TC0.CTRLGCLR bit masks and bit positions */ 5782 #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ 5783 #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ 5784 5785 #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ 5786 #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ 5787 5788 #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ 5789 #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ 5790 5791 #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ 5792 #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ 5793 5794 #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ 5795 #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ 5796 5797 5798 /* TC0.CTRLGSET bit masks and bit positions */ 5799 /* TC0_CCDBV_bm Predefined. */ 5800 /* TC0_CCDBV_bp Predefined. */ 5801 5802 /* TC0_CCCBV_bm Predefined. */ 5803 /* TC0_CCCBV_bp Predefined. */ 5804 5805 /* TC0_CCBBV_bm Predefined. */ 5806 /* TC0_CCBBV_bp Predefined. */ 5807 5808 /* TC0_CCABV_bm Predefined. */ 5809 /* TC0_CCABV_bp Predefined. */ 5810 5811 /* TC0_PERBV_bm Predefined. */ 5812 /* TC0_PERBV_bp Predefined. */ 5813 5814 5815 /* TC0.INTFLAGS bit masks and bit positions */ 5816 #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ 5817 #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ 5818 5819 #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ 5820 #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ 5821 5822 #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ 5823 #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ 5824 5825 #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ 5826 #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ 5827 5828 #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ 5829 #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ 5830 5831 #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 5832 #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 5833 5834 5835 /* TC1.CTRLA bit masks and bit positions */ 5836 #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 5837 #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ 5838 #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 5839 #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 5840 #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 5841 #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 5842 #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 5843 #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 5844 #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 5845 #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 5846 5847 5848 /* TC1.CTRLB bit masks and bit positions */ 5849 #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ 5850 #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ 5851 5852 #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ 5853 #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ 5854 5855 #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ 5856 #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ 5857 #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ 5858 #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ 5859 #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ 5860 #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ 5861 #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ 5862 #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ 5863 5864 5865 /* TC1.CTRLC bit masks and bit positions */ 5866 #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ 5867 #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ 5868 5869 #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ 5870 #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ 5871 5872 5873 /* TC1.CTRLD bit masks and bit positions */ 5874 #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ 5875 #define TC1_EVACT_gp 5 /* Event Action group position. */ 5876 #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ 5877 #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ 5878 #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ 5879 #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ 5880 #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ 5881 #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ 5882 5883 #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ 5884 #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ 5885 5886 #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ 5887 #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ 5888 #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ 5889 #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ 5890 #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ 5891 #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ 5892 #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ 5893 #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ 5894 #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ 5895 #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ 5896 5897 5898 /* TC1.CTRLE bit masks and bit positions */ 5899 #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ 5900 #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ 5901 5902 #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ 5903 #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ 5904 5905 5906 /* TC1.INTCTRLA bit masks and bit positions */ 5907 #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ 5908 #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ 5909 #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ 5910 #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ 5911 #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ 5912 #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ 5913 5914 #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ 5915 #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ 5916 #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ 5917 #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ 5918 #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ 5919 #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ 5920 5921 5922 /* TC1.INTCTRLB bit masks and bit positions */ 5923 #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ 5924 #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ 5925 #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ 5926 #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ 5927 #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ 5928 #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ 5929 5930 #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ 5931 #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ 5932 #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ 5933 #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ 5934 #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ 5935 #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ 5936 5937 5938 /* TC1.CTRLFCLR bit masks and bit positions */ 5939 #define TC1_CMD_gm 0x0C /* Command group mask. */ 5940 #define TC1_CMD_gp 2 /* Command group position. */ 5941 #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ 5942 #define TC1_CMD0_bp 2 /* Command bit 0 position. */ 5943 #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ 5944 #define TC1_CMD1_bp 3 /* Command bit 1 position. */ 5945 5946 #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ 5947 #define TC1_LUPD_bp 1 /* Lock Update bit position. */ 5948 5949 #define TC1_DIR_bm 0x01 /* Direction bit mask. */ 5950 #define TC1_DIR_bp 0 /* Direction bit position. */ 5951 5952 5953 /* TC1.CTRLFSET bit masks and bit positions */ 5954 /* TC1_CMD_gm Predefined. */ 5955 /* TC1_CMD_gp Predefined. */ 5956 /* TC1_CMD0_bm Predefined. */ 5957 /* TC1_CMD0_bp Predefined. */ 5958 /* TC1_CMD1_bm Predefined. */ 5959 /* TC1_CMD1_bp Predefined. */ 5960 5961 /* TC1_LUPD_bm Predefined. */ 5962 /* TC1_LUPD_bp Predefined. */ 5963 5964 /* TC1_DIR_bm Predefined. */ 5965 /* TC1_DIR_bp Predefined. */ 5966 5967 5968 /* TC1.CTRLGCLR bit masks and bit positions */ 5969 #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ 5970 #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ 5971 5972 #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ 5973 #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ 5974 5975 #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ 5976 #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ 5977 5978 5979 /* TC1.CTRLGSET bit masks and bit positions */ 5980 /* TC1_CCBBV_bm Predefined. */ 5981 /* TC1_CCBBV_bp Predefined. */ 5982 5983 /* TC1_CCABV_bm Predefined. */ 5984 /* TC1_CCABV_bp Predefined. */ 5985 5986 /* TC1_PERBV_bm Predefined. */ 5987 /* TC1_PERBV_bp Predefined. */ 5988 5989 5990 /* TC1.INTFLAGS bit masks and bit positions */ 5991 #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ 5992 #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ 5993 5994 #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ 5995 #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ 5996 5997 #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ 5998 #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ 5999 6000 #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 6001 #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 6002 6003 6004 /* AWEX.CTRL bit masks and bit positions */ 6005 #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ 6006 #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ 6007 6008 #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ 6009 #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ 6010 6011 #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ 6012 #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ 6013 6014 #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ 6015 #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ 6016 6017 #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ 6018 #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ 6019 6020 #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ 6021 #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ 6022 6023 6024 /* AWEX.FDCTRL bit masks and bit positions */ 6025 #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ 6026 #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ 6027 6028 #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ 6029 #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ 6030 6031 #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ 6032 #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ 6033 #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ 6034 #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ 6035 #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ 6036 #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ 6037 6038 6039 /* AWEX.STATUS bit masks and bit positions */ 6040 #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ 6041 #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ 6042 6043 #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ 6044 #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ 6045 6046 #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ 6047 #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ 6048 6049 6050 /* HIRES.CTRL bit masks and bit positions */ 6051 #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ 6052 #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ 6053 #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ 6054 #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ 6055 #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ 6056 #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ 6057 6058 6059 /* USART - Universal Asynchronous Receiver-Transmitter */ 6060 /* USART.STATUS bit masks and bit positions */ 6061 #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ 6062 #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ 6063 6064 #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ 6065 #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ 6066 6067 #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ 6068 #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ 6069 6070 #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ 6071 #define USART_FERR_bp 4 /* Frame Error bit position. */ 6072 6073 #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ 6074 #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ 6075 6076 #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ 6077 #define USART_PERR_bp 2 /* Parity Error bit position. */ 6078 6079 #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ 6080 #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ 6081 6082 6083 /* USART.CTRLA bit masks and bit positions */ 6084 #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ 6085 #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ 6086 #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ 6087 #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ 6088 #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ 6089 #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ 6090 6091 #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ 6092 #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ 6093 #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ 6094 #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ 6095 #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ 6096 #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ 6097 6098 #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ 6099 #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ 6100 #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ 6101 #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ 6102 #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ 6103 #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ 6104 6105 6106 /* USART.CTRLB bit masks and bit positions */ 6107 #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ 6108 #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ 6109 6110 #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ 6111 #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ 6112 6113 #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ 6114 #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ 6115 6116 #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ 6117 #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ 6118 6119 #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ 6120 #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ 6121 6122 6123 /* USART.CTRLC bit masks and bit positions */ 6124 #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ 6125 #define USART_CMODE_gp 6 /* Communication Mode group position. */ 6126 #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ 6127 #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ 6128 #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ 6129 #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ 6130 6131 #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ 6132 #define USART_PMODE_gp 4 /* Parity Mode group position. */ 6133 #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ 6134 #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ 6135 #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ 6136 #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ 6137 6138 #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ 6139 #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ 6140 6141 #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ 6142 #define USART_CHSIZE_gp 0 /* Character Size group position. */ 6143 #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ 6144 #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ 6145 #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ 6146 #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ 6147 #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ 6148 #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ 6149 6150 6151 /* USART.BAUDCTRLA bit masks and bit positions */ 6152 #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ 6153 #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ 6154 #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ 6155 #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ 6156 #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ 6157 #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ 6158 #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ 6159 #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ 6160 #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ 6161 #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ 6162 #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ 6163 #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ 6164 #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ 6165 #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ 6166 #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ 6167 #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ 6168 #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ 6169 #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ 6170 6171 6172 /* USART.BAUDCTRLB bit masks and bit positions */ 6173 #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ 6174 #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ 6175 #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ 6176 #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ 6177 #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ 6178 #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ 6179 #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ 6180 #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ 6181 #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ 6182 #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ 6183 6184 /* USART_BSEL_gm Predefined. */ 6185 /* USART_BSEL_gp Predefined. */ 6186 /* USART_BSEL0_bm Predefined. */ 6187 /* USART_BSEL0_bp Predefined. */ 6188 /* USART_BSEL1_bm Predefined. */ 6189 /* USART_BSEL1_bp Predefined. */ 6190 /* USART_BSEL2_bm Predefined. */ 6191 /* USART_BSEL2_bp Predefined. */ 6192 /* USART_BSEL3_bm Predefined. */ 6193 /* USART_BSEL3_bp Predefined. */ 6194 6195 6196 /* SPI - Serial Peripheral Interface */ 6197 /* SPI.CTRL bit masks and bit positions */ 6198 #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ 6199 #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ 6200 6201 #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ 6202 #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ 6203 6204 #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ 6205 #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ 6206 6207 #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ 6208 #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ 6209 6210 #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ 6211 #define SPI_MODE_gp 2 /* SPI Mode group position. */ 6212 #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ 6213 #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ 6214 #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ 6215 #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ 6216 6217 #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ 6218 #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ 6219 #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ 6220 #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ 6221 #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ 6222 #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ 6223 6224 6225 /* SPI.INTCTRL bit masks and bit positions */ 6226 #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ 6227 #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ 6228 #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ 6229 #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ 6230 #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ 6231 #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ 6232 6233 6234 /* SPI.STATUS bit masks and bit positions */ 6235 #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ 6236 #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ 6237 6238 #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ 6239 #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ 6240 6241 6242 /* IRCOM - IR Communication Module */ 6243 /* IRCOM.CTRL bit masks and bit positions */ 6244 #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ 6245 #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ 6246 #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ 6247 #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ 6248 #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ 6249 #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ 6250 #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ 6251 #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ 6252 #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ 6253 #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ 6254 6255 6256 /* AES - AES Module */ 6257 /* AES.CTRL bit masks and bit positions */ 6258 #define AES_START_bm 0x80 /* Start/Run bit mask. */ 6259 #define AES_START_bp 7 /* Start/Run bit position. */ 6260 6261 #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ 6262 #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ 6263 6264 #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ 6265 #define AES_RESET_bp 5 /* AES Software Reset bit position. */ 6266 6267 #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ 6268 #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ 6269 6270 #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ 6271 #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ 6272 6273 6274 /* AES.STATUS bit masks and bit positions */ 6275 #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ 6276 #define AES_ERROR_bp 7 /* AES Error bit position. */ 6277 6278 #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ 6279 #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ 6280 6281 6282 /* AES.INTCTRL bit masks and bit positions */ 6283 #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ 6284 #define AES_INTLVL_gp 0 /* Interrupt level group position. */ 6285 #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ 6286 #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ 6287 #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ 6288 #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ 6289 6290 6291 6292 // Generic Port Pins 6293 6294 #define PIN0_bm 0x01 6295 #define PIN0_bp 0 6296 #define PIN1_bm 0x02 6297 #define PIN1_bp 1 6298 #define PIN2_bm 0x04 6299 #define PIN2_bp 2 6300 #define PIN3_bm 0x08 6301 #define PIN3_bp 3 6302 #define PIN4_bm 0x10 6303 #define PIN4_bp 4 6304 #define PIN5_bm 0x20 6305 #define PIN5_bp 5 6306 #define PIN6_bm 0x40 6307 #define PIN6_bp 6 6308 #define PIN7_bm 0x80 6309 #define PIN7_bp 7 6310 6311 6312 /* ========== Interrupt Vector Definitions ========== */ 6313 /* Vector 0 is the reset vector */ 6314 6315 /* OSC interrupt vectors */ 6316 #define OSC_XOSCF_vect_num 1 6317 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ 6318 6319 /* PORTC interrupt vectors */ 6320 #define PORTC_INT0_vect_num 2 6321 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ 6322 #define PORTC_INT1_vect_num 3 6323 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ 6324 6325 /* PORTR interrupt vectors */ 6326 #define PORTR_INT0_vect_num 4 6327 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ 6328 #define PORTR_INT1_vect_num 5 6329 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ 6330 6331 /* DMA interrupt vectors */ 6332 #define DMA_CH0_vect_num 6 6333 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ 6334 #define DMA_CH1_vect_num 7 6335 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ 6336 #define DMA_CH2_vect_num 8 6337 #define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ 6338 #define DMA_CH3_vect_num 9 6339 #define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ 6340 6341 /* RTC interrupt vectors */ 6342 #define RTC_OVF_vect_num 10 6343 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ 6344 #define RTC_COMP_vect_num 11 6345 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ 6346 6347 /* TWIC interrupt vectors */ 6348 #define TWIC_TWIS_vect_num 12 6349 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ 6350 #define TWIC_TWIM_vect_num 13 6351 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ 6352 6353 /* TCC0 interrupt vectors */ 6354 #define TCC0_OVF_vect_num 14 6355 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ 6356 #define TCC0_ERR_vect_num 15 6357 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ 6358 #define TCC0_CCA_vect_num 16 6359 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ 6360 #define TCC0_CCB_vect_num 17 6361 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ 6362 #define TCC0_CCC_vect_num 18 6363 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ 6364 #define TCC0_CCD_vect_num 19 6365 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ 6366 6367 /* TCC1 interrupt vectors */ 6368 #define TCC1_OVF_vect_num 20 6369 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ 6370 #define TCC1_ERR_vect_num 21 6371 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ 6372 #define TCC1_CCA_vect_num 22 6373 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ 6374 #define TCC1_CCB_vect_num 23 6375 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ 6376 6377 /* SPIC interrupt vectors */ 6378 #define SPIC_INT_vect_num 24 6379 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ 6380 6381 /* USARTC0 interrupt vectors */ 6382 #define USARTC0_RXC_vect_num 25 6383 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ 6384 #define USARTC0_DRE_vect_num 26 6385 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ 6386 #define USARTC0_TXC_vect_num 27 6387 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ 6388 6389 /* USARTC1 interrupt vectors */ 6390 #define USARTC1_RXC_vect_num 28 6391 #define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ 6392 #define USARTC1_DRE_vect_num 29 6393 #define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ 6394 #define USARTC1_TXC_vect_num 30 6395 #define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ 6396 6397 /* AES interrupt vectors */ 6398 #define AES_INT_vect_num 31 6399 #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ 6400 6401 /* NVM interrupt vectors */ 6402 #define NVM_EE_vect_num 32 6403 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ 6404 #define NVM_SPM_vect_num 33 6405 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ 6406 6407 /* PORTB interrupt vectors */ 6408 #define PORTB_INT0_vect_num 34 6409 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ 6410 #define PORTB_INT1_vect_num 35 6411 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ 6412 6413 /* PORTE interrupt vectors */ 6414 #define PORTE_INT0_vect_num 43 6415 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ 6416 #define PORTE_INT1_vect_num 44 6417 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ 6418 6419 /* TWIE interrupt vectors */ 6420 #define TWIE_TWIS_vect_num 45 6421 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ 6422 #define TWIE_TWIM_vect_num 46 6423 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ 6424 6425 /* TCE0 interrupt vectors */ 6426 #define TCE0_OVF_vect_num 47 6427 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ 6428 #define TCE0_ERR_vect_num 48 6429 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ 6430 #define TCE0_CCA_vect_num 49 6431 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ 6432 #define TCE0_CCB_vect_num 50 6433 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ 6434 #define TCE0_CCC_vect_num 51 6435 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ 6436 #define TCE0_CCD_vect_num 52 6437 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ 6438 6439 /* TCE1 interrupt vectors */ 6440 #define TCE1_OVF_vect_num 53 6441 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ 6442 #define TCE1_ERR_vect_num 54 6443 #define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ 6444 #define TCE1_CCA_vect_num 55 6445 #define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ 6446 #define TCE1_CCB_vect_num 56 6447 #define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ 6448 6449 /* USARTE0 interrupt vectors */ 6450 #define USARTE0_RXC_vect_num 58 6451 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ 6452 #define USARTE0_DRE_vect_num 59 6453 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ 6454 #define USARTE0_TXC_vect_num 60 6455 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ 6456 6457 /* PORTD interrupt vectors */ 6458 #define PORTD_INT0_vect_num 64 6459 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ 6460 #define PORTD_INT1_vect_num 65 6461 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ 6462 6463 /* PORTA interrupt vectors */ 6464 #define PORTA_INT0_vect_num 66 6465 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ 6466 #define PORTA_INT1_vect_num 67 6467 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ 6468 6469 /* ACA interrupt vectors */ 6470 #define ACA_AC0_vect_num 68 6471 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ 6472 #define ACA_AC1_vect_num 69 6473 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ 6474 #define ACA_ACW_vect_num 70 6475 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ 6476 6477 /* ADCA interrupt vectors */ 6478 #define ADCA_CH0_vect_num 71 6479 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ 6480 #define ADCA_CH1_vect_num 72 6481 #define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ 6482 #define ADCA_CH2_vect_num 73 6483 #define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ 6484 #define ADCA_CH3_vect_num 74 6485 #define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ 6486 6487 /* TCD0 interrupt vectors */ 6488 #define TCD0_OVF_vect_num 77 6489 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ 6490 #define TCD0_ERR_vect_num 78 6491 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ 6492 #define TCD0_CCA_vect_num 79 6493 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ 6494 #define TCD0_CCB_vect_num 80 6495 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ 6496 #define TCD0_CCC_vect_num 81 6497 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ 6498 #define TCD0_CCD_vect_num 82 6499 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ 6500 6501 /* TCD1 interrupt vectors */ 6502 #define TCD1_OVF_vect_num 83 6503 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ 6504 #define TCD1_ERR_vect_num 84 6505 #define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ 6506 #define TCD1_CCA_vect_num 85 6507 #define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ 6508 #define TCD1_CCB_vect_num 86 6509 #define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ 6510 6511 /* SPID interrupt vectors */ 6512 #define SPID_INT_vect_num 87 6513 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ 6514 6515 /* USARTD0 interrupt vectors */ 6516 #define USARTD0_RXC_vect_num 88 6517 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ 6518 #define USARTD0_DRE_vect_num 89 6519 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ 6520 #define USARTD0_TXC_vect_num 90 6521 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ 6522 6523 /* USARTD1 interrupt vectors */ 6524 #define USARTD1_RXC_vect_num 91 6525 #define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ 6526 #define USARTD1_DRE_vect_num 92 6527 #define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ 6528 #define USARTD1_TXC_vect_num 93 6529 #define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ 6530 6531 6532 #define _VECTOR_SIZE 4 /* Size of individual vector. */ 6533 #define _VECTORS_SIZE (94 * _VECTOR_SIZE) 6534 6535 6536 /* ========== Constants ========== */ 6537 6538 #define PROGMEM_START (0x0000) 6539 #define PROGMEM_SIZE (36864) 6540 #define PROGMEM_PAGE_SIZE (256) 6541 #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) 6542 6543 #define APP_SECTION_START (0x0000) 6544 #define APP_SECTION_SIZE (32768) 6545 #define APP_SECTION_PAGE_SIZE (256) 6546 #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) 6547 6548 #define APPTABLE_SECTION_START (0x07000) 6549 #define APPTABLE_SECTION_SIZE (4096) 6550 #define APPTABLE_SECTION_PAGE_SIZE (256) 6551 #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) 6552 6553 #define BOOT_SECTION_START (0x8000) 6554 #define BOOT_SECTION_SIZE (4096) 6555 #define BOOT_SECTION_PAGE_SIZE (256) 6556 #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) 6557 6558 #define DATAMEM_START (0x0000) 6559 #define DATAMEM_SIZE (12288) 6560 #define DATAMEM_PAGE_SIZE (0) 6561 #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) 6562 6563 #define IO_START (0x0000) 6564 #define IO_SIZE (4096) 6565 #define IO_PAGE_SIZE (0) 6566 #define IO_END (IO_START + IO_SIZE - 1) 6567 6568 #define MAPPED_EEPROM_START (0x1000) 6569 #define MAPPED_EEPROM_SIZE (1024) 6570 #define MAPPED_EEPROM_PAGE_SIZE (0) 6571 #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) 6572 6573 #define INTERNAL_SRAM_START (0x2000) 6574 #define INTERNAL_SRAM_SIZE (4096) 6575 #define INTERNAL_SRAM_PAGE_SIZE (0) 6576 #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) 6577 6578 #define EEPROM_START (0x0000) 6579 #define EEPROM_SIZE (1024) 6580 #define EEPROM_PAGE_SIZE (32) 6581 #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) 6582 6583 #define FUSE_START (0x0000) 6584 #define FUSE_SIZE (6) 6585 #define FUSE_PAGE_SIZE (0) 6586 #define FUSE_END (FUSE_START + FUSE_SIZE - 1) 6587 6588 #define LOCKBIT_START (0x0000) 6589 #define LOCKBIT_SIZE (1) 6590 #define LOCKBIT_PAGE_SIZE (0) 6591 #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) 6592 6593 #define SIGNATURES_START (0x0000) 6594 #define SIGNATURES_SIZE (3) 6595 #define SIGNATURES_PAGE_SIZE (0) 6596 #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) 6597 6598 #define USER_SIGNATURES_START (0x0000) 6599 #define USER_SIGNATURES_SIZE (256) 6600 #define USER_SIGNATURES_PAGE_SIZE (0) 6601 #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) 6602 6603 #define PROD_SIGNATURES_START (0x0000) 6604 #define PROD_SIGNATURES_SIZE (52) 6605 #define PROD_SIGNATURES_PAGE_SIZE (0) 6606 #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) 6607 6608 #define FLASHEND PROGMEM_END 6609 #define SPM_PAGESIZE PROGMEM_PAGE_SIZE 6610 #define RAMSTART INTERNAL_SRAM_START 6611 #define RAMSIZE INTERNAL_SRAM_SIZE 6612 #define RAMEND INTERNAL_SRAM_END 6613 #define XRAMSTART EXTERNAL_SRAM_START 6614 #define XRAMSIZE EXTERNAL_SRAM_SIZE 6615 #define XRAMEND INTERNAL_SRAM_END 6616 #define E2END EEPROM_END 6617 #define E2PAGESIZE EEPROM_PAGE_SIZE 6618 6619 6620 /* ========== Fuses ========== */ 6621 #define FUSE_MEMORY_SIZE 6 6622 6623 /* Fuse Byte 0 */ 6624 #define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ 6625 #define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ 6626 #define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ 6627 #define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ 6628 #define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ 6629 #define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ 6630 #define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ 6631 #define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ 6632 #define FUSE0_DEFAULT (0xFF) 6633 6634 /* Fuse Byte 1 */ 6635 #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ 6636 #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ 6637 #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ 6638 #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ 6639 #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ 6640 #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ 6641 #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ 6642 #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ 6643 #define FUSE1_DEFAULT (0xFF) 6644 6645 /* Fuse Byte 2 */ 6646 #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ 6647 #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ 6648 #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ 6649 #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ 6650 #define FUSE2_DEFAULT (0xFF) 6651 6652 /* Fuse Byte 3 Reserved */ 6653 6654 /* Fuse Byte 4 */ 6655 #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ 6656 #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ 6657 #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ 6658 #define FUSE4_DEFAULT (0xFF) 6659 6660 /* Fuse Byte 5 */ 6661 #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ 6662 #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ 6663 #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ 6664 #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ 6665 #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ 6666 #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ 6667 #define FUSE5_DEFAULT (0xFF) 6668 6669 6670 /* ========== Lock Bits ========== */ 6671 #define __LOCK_BITS_EXIST 6672 #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST 6673 #define __BOOT_LOCK_APPLICATION_BITS_EXIST 6674 #define __BOOT_LOCK_BOOT_BITS_EXIST 6675 6676 6677 /* ========== Signature ========== */ 6678 #define SIGNATURE_0 0x1E 6679 #define SIGNATURE_1 0x95 6680 #define SIGNATURE_2 0x41 6681 6682 /* ========== Power Reduction Condition Definitions ========== */ 6683 6684 /* PR.PRGEN */ 6685 #define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) 6686 #define __AVR_HAVE_PRGEN_AES 6687 #define __AVR_HAVE_PRGEN_EBI 6688 #define __AVR_HAVE_PRGEN_RTC 6689 #define __AVR_HAVE_PRGEN_EVSYS 6690 #define __AVR_HAVE_PRGEN_DMA 6691 6692 /* PR.PRPA */ 6693 #define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) 6694 #define __AVR_HAVE_PRPA_DAC 6695 #define __AVR_HAVE_PRPA_ADC 6696 #define __AVR_HAVE_PRPA_AC 6697 6698 /* PR.PRPB */ 6699 #define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) 6700 #define __AVR_HAVE_PRPB_DAC 6701 #define __AVR_HAVE_PRPB_ADC 6702 #define __AVR_HAVE_PRPB_AC 6703 6704 /* PR.PRPC */ 6705 #define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) 6706 #define __AVR_HAVE_PRPC_TWI 6707 #define __AVR_HAVE_PRPC_USART1 6708 #define __AVR_HAVE_PRPC_USART0 6709 #define __AVR_HAVE_PRPC_SPI 6710 #define __AVR_HAVE_PRPC_HIRES 6711 #define __AVR_HAVE_PRPC_TC1 6712 #define __AVR_HAVE_PRPC_TC0 6713 6714 /* PR.PRPD */ 6715 #define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) 6716 #define __AVR_HAVE_PRPD_TWI 6717 #define __AVR_HAVE_PRPD_USART1 6718 #define __AVR_HAVE_PRPD_USART0 6719 #define __AVR_HAVE_PRPD_SPI 6720 #define __AVR_HAVE_PRPD_HIRES 6721 #define __AVR_HAVE_PRPD_TC1 6722 #define __AVR_HAVE_PRPD_TC0 6723 6724 /* PR.PRPE */ 6725 #define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) 6726 #define __AVR_HAVE_PRPE_TWI 6727 #define __AVR_HAVE_PRPE_USART1 6728 #define __AVR_HAVE_PRPE_USART0 6729 #define __AVR_HAVE_PRPE_SPI 6730 #define __AVR_HAVE_PRPE_HIRES 6731 #define __AVR_HAVE_PRPE_TC1 6732 #define __AVR_HAVE_PRPE_TC0 6733 6734 /* PR.PRPF */ 6735 #define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) 6736 #define __AVR_HAVE_PRPF_TWI 6737 #define __AVR_HAVE_PRPF_USART1 6738 #define __AVR_HAVE_PRPF_USART0 6739 #define __AVR_HAVE_PRPF_SPI 6740 #define __AVR_HAVE_PRPF_HIRES 6741 #define __AVR_HAVE_PRPF_TC1 6742 #define __AVR_HAVE_PRPF_TC0 6743 6744 6745 #endif /* _AVR_ATxmega32A4_H_ */ 6746 6747