1 /* 2 (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) 3 (c) Copyright 2000-2004 Convergence (integrated media) GmbH 4 5 All rights reserved. 6 7 Written by Antonino Daplas <adaplas@pol.net> 8 9 This library is free software; you can redistribute it and/or 10 modify it under the terms of the GNU Lesser General Public 11 License as published by the Free Software Foundation; either 12 version 2 of the License, or (at your option) any later version. 13 14 This library is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 Lesser General Public License for more details. 18 19 You should have received a copy of the GNU Lesser General Public 20 License along with this library; if not, write to the 21 Free Software Foundation, Inc., 59 Temple Place - Suite 330, 22 Boston, MA 02111-1307, USA. 23 */ 24 25 /* 26 * Intel 810 Chipset Family PRM 15 3.1 27 * GC Register Memory Address Map 28 * 29 * Based on: 30 * Intel (R) 810 Chipset Family 31 * Programmer s Reference Manual 32 * November 1999 33 * Revision 1.0 34 * Order Number: 298026-001 R 35 * 36 * All GC registers are memory-mapped. In addition, the VGA and extended VGA registers 37 * are I/O mapped. 38 */ 39 40 #ifndef __I810_H__ 41 #define __I810_H__ 42 43 #include <dfb_types.h> 44 #include <sys/io.h> 45 #include <linux/agpgart.h> 46 47 #include <core/gfxcard.h> 48 #include <core/layers.h> 49 50 51 #define LP_RING 0x2030 52 #define HP_RING 0x2040 53 54 #define RING_TAIL 0x00 55 #define RING_HEAD 0x04 56 #define RING_START 0x08 57 #define RING_LEN 0x0C 58 59 60 /* Instruction and Interrupt Control Registers (01000h 02FFFh) */ 61 #define FENCE 0x02000 62 #define PGTBL_CTL 0x02020 63 #define PGTBL_ER 0x02024 64 #define RINGBUFFER 0x02030 65 #define LRING 0x02030 66 #define IRING 0x02040 67 #define HWS_PGA 0x02080 68 #define IPEIR 0x02088 69 #define IPEHR 0x0208C 70 #define INSTDONE 0x02090 71 #define NOPID 0x02094 72 #define HWSTAM 0x02098 73 #define IER 0x020A0 74 #define IIR 0x020A4 75 #define IMR 0x020A8 76 #define ISR 0x020AC 77 #define EIR 0x020B0 78 #define EMR 0x020B4 79 #define ESR 0x020B8 80 #define INSTPM 0x020C0 81 #define INSTPS 0x020C4 82 #define BBP_PTR 0x020C8 83 #define ABB_SRT 0x020CC 84 #define ABB_END 0x020D0 85 #define DMA_FADD 0x020D4 86 #define FW_BLC 0x020D8 87 #define MEM_MODE 0x020DC 88 89 /* Memory Control Registers (03000h 03FFFh) */ 90 #define DRT 0x03000 91 #define DRAMCL 0x03001 92 #define DRAMCH 0x03002 93 94 95 /* Span Cursor Registers (04000h 04FFFh) */ 96 #define UI_SC_CTL 0x04008 97 98 /* I/O Control Registers (05000h 05FFFh) */ 99 #define HVSYNC 0x05000 100 #define GPIOA 0x05010 101 #define GPIOB 0x05014 102 103 /* Clock Control and Power Management Registers (06000h 06FFFh) */ 104 #define DCLK_0D 0x06000 105 #define DCLK_1D 0x06004 106 #define DCLK_2D 0x06008 107 #define LCD_CLKD 0x0600C 108 #define DCLK_0DS 0x06010 109 #define PWR_CLKC 0x06014 110 111 /* Graphics Translation Table Range Definition (10000h 1FFFFh) */ 112 #define GTT 0x10000 113 114 /* Overlay Registers (30000h 03FFFFh) */ 115 #define OV0ADDR 0x30000 116 #define DOV0STA 0x30008 117 #define GAMMA 0x30010 118 #define OBUF_0Y 0x30100 119 #define OBUF_1Y 0x30104 120 #define OBUF_0U 0x30108 121 #define OBUF_0V 0x3010C 122 #define OBUF_1U 0x30110 123 #define OBUF_1V 0x30114 124 #define OV0STRIDE 0x30118 125 #define YRGB_VPH 0x3011C 126 #define UV_VPH 0x30120 127 #define HORZ_PH 0x30124 128 #define INIT_PH 0x30128 129 #define DWINPOS 0x3012C 130 #define DWINSZ 0x30130 131 #define SWID 0x30134 132 #define SWIDQW 0x30138 133 #define SHEIGHT 0x3013C 134 #define YRGBSCALE 0x30140 135 #define UVSCALE 0x30144 136 #define OV0CLRCO 0x30148 137 #define OV0CLRC1 0x3014C 138 #define DCLRKV 0x30150 139 #define DLCRKM 0x30154 140 #define SCLRKVH 0x30158 141 #define SCLRKVL 0x3015C 142 #define SCLRKM 0x30160 143 #define OV0CONF 0x30164 144 #define OV0CMD 0x30168 145 #define AWINPOS 0x30170 146 #define AWINZ 0x30174 147 148 /* BLT Engine Status (40000h 4FFFFh) (Software Debug) */ 149 #define BR00 0x40000 150 #define BRO1 0x40004 151 #define BR02 0x40008 152 #define BR03 0x4000C 153 #define BR04 0x40010 154 #define BR05 0x40014 155 #define BR06 0x40018 156 #define BR07 0x4001C 157 #define BR08 0x40020 158 #define BR09 0x40024 159 #define BR10 0x40028 160 #define BR11 0x4002C 161 #define BR12 0x40030 162 #define BR13 0x40034 163 #define BR14 0x40038 164 #define BR15 0x4003C 165 #define BR16 0x40040 166 #define BR17 0x40044 167 #define BR18 0x40048 168 #define BR19 0x4004C 169 #define SSLADD 0x40074 170 #define DSLH 0x40078 171 #define DSLRADD 0x4007C 172 173 174 /* LCD/TV-Out and HW DVD Registers (60000h 6FFFFh) */ 175 /* LCD/TV-Out */ 176 #define HTOTAL 0x60000 177 #define HBLANK 0x60004 178 #define HSYNC 0x60008 179 #define VTOTAL 0x6000C 180 #define VBLANK 0x60010 181 #define VSYNC 0x60014 182 #define LCDTV_C 0x60018 183 #define OVRACT 0x6001C 184 #define BCLRPAT 0x60020 185 186 /* Display and Cursor Control Registers (70000h 7FFFFh) */ 187 #define DISP_SL 0x70000 188 #define DISP_SLC 0x70004 189 #define PIXCONF 0x70008 190 #define PIXCONF1 0x70009 191 #define BLTCNTL 0x7000C 192 #define SWF 0x70014 193 #define DPLYBASE 0x70020 194 #define DPLYSTAS 0x70024 195 #define CURCNTR 0x70080 196 #define CURBASE 0x70084 197 #define CURPOS 0x70088 198 199 200 /* VGA Registers */ 201 202 /* SMRAM Registers */ 203 #define SMRAM 0x10 204 205 /* Graphics Control Registers */ 206 #define GR_INDEX 0x3CE 207 #define GR_DATA 0x3CF 208 209 #define GR10 0x10 210 #define GR11 0x11 211 212 /* CRT Controller Registers */ 213 #define CR_INDEX_MDA 0x3B4 214 #define CR_INDEX_CGA 0x3D4 215 #define CR_DATA_MDA 0x3B5 216 #define CR_DATA_CGA 0x3D5 217 218 #define CR30 0x30 219 #define CR31 0x31 220 #define CR32 0x32 221 #define CR33 0x33 222 #define CR35 0x35 223 #define CR39 0x39 224 #define CR40 0x40 225 #define CR41 0x41 226 #define CR42 0x42 227 #define CR70 0x70 228 #define CR80 0x80 229 #define CR81 0x82 230 231 /* Extended VGA Registers */ 232 233 /* General Control and Status Registers */ 234 #define ST00 0x3C2 235 #define ST01_MDA 0x3BA 236 #define ST01_CGA 0x3DA 237 #define FRC_READ 0x3CA 238 #define FRC_WRITE_MDA 0x3BA 239 #define FRC_WRITE_CGA 0x3DA 240 #define MSR_READ 0x3CC 241 #define MSR_WRITE 0x3C2 242 243 /* Sequencer Registers */ 244 #define SR_INDEX 0x3C4 245 #define SR_DATA 0x3C5 246 247 #define SR01 0x01 248 #define SR02 0x02 249 #define SR03 0x03 250 #define SR04 0x04 251 #define SR07 0x07 252 253 /* Graphics Controller Registers */ 254 #define GR00 0x00 255 #define GR01 0x01 256 #define GR02 0x02 257 #define GR03 0x03 258 #define GR04 0x04 259 #define GR05 0x05 260 #define GR06 0x06 261 #define GR07 0x07 262 #define GR08 0x08 263 264 /* Attribute Controller Registers */ 265 #define ATTR_WRITE 0x3C0 266 #define ATTR_READ 0x3C1 267 268 /* VGA Color Palette Registers */ 269 270 /* CLUT */ 271 #define CLUT_DATA 0x3C9 /* DACDATA */ 272 #define CLUT_INDEX_READ 0x3C7 /* DACRX */ 273 #define CLUT_INDEX_WRITE 0x3C8 /* DACWX */ 274 #define DACMASK 0x3C6 275 276 /* CRT Controller Registers */ 277 #define CR00 0x00 278 #define CR01 0x01 279 #define CR02 0x02 280 #define CR03 0x03 281 #define CR04 0x04 282 #define CR05 0x05 283 #define CR06 0x06 284 #define CR07 0x07 285 #define CR08 0x08 286 #define CR09 0x09 287 #define CR0A 0x0A 288 #define CR0B 0x0B 289 #define CR0C 0x0C 290 #define CR0D 0x0D 291 #define CR0E 0x0E 292 #define CR0F 0x0F 293 #define CR10 0x10 294 #define CR11 0x11 295 #define CR12 0x12 296 #define CR13 0x13 297 #define CR14 0x14 298 #define CR15 0x15 299 #define CR16 0x16 300 #define CR17 0x17 301 #define CR18 0x18 302 303 304 /* Raster ops */ 305 #define COLOR_COPY_ROP 0xF0 306 #define PAT_COPY_ROP 0xCC 307 #define CLEAR_ROP 0x00 308 #define WHITE_ROP 0xFF 309 #define INVERT_ROP 0x55 310 311 /* 2D Engine definitions */ 312 #define SOLIDPATTERN 0x80000000 313 #define NONSOLID 0x00000000 314 #define BPP8 0x00000000 315 #define BPP16 0x01 << 24 316 #define BPP24 0x02 << 24 317 #define DYN_COLOR_EN 0x00400000 318 #define DYN_COLOR_DIS 0x00000000 319 #define INCREMENT 0x00000000 320 #define DECREMENT 0x01 << 30 321 #define ARB_ON 0x00000001 322 #define ARB_OFF 0x00000000 323 #define SYNC_FLIP 0x00000000 324 #define ASYNC_FLIP 0x00000040 325 #define OPTYPE_MASK 0xE0000000 326 #define PARSER_MASK 0x001F8000 327 #define D2_MASK 0x001FC000 /* 2D mask */ 328 329 /* Instruction type */ 330 /* There are more but pertains to 3D */ 331 #define PARSER 0x00000000 332 #define BLIT 0x02 << 29 333 #define RENDER 0x03 << 29 334 335 /* Parser */ 336 #define NOP 0x00 /* No operation, padding */ 337 #define BP_INT 0x01 << 23 /* Breakpoint interrupt */ 338 #define USR_INT 0x02 << 23 /* User interrupt */ 339 #define WAIT_FOR_EVNT 0x03 << 23 /* Wait for event */ 340 #define FLUSH 0x04 << 23 341 #define CONTEXT_SEL 0x05 << 23 342 #define REPORT_HEAD 0x07 << 23 343 #define ARB_ON_OFF 0x08 << 23 344 #define OVERLAY_FLIP 0x11 << 23 345 #define LOAD_SCAN_INC 0x12 << 23 346 #define LOAD_SCAN_EX 0x13 << 23 347 #define FRONT_BUFFER 0x14 << 23 348 #define DEST_BUFFER 0x15 << 23 349 #define Z_BUFFER 0x16 << 23 /* we won't need this */ 350 #define STORE_DWORD_IMM 0x20 << 23 351 #define STORE_DWORD_IDX 0x21 << 23 352 #define BATCH_BUFFER 0x30 << 23 353 354 /* Blit */ 355 #define SETUP_BLIT 0x00 356 #define SETUP_MONO_PATTERN_SL_BLT 0x10 << 22 357 #define PIXEL_BLT 0x20 << 22 358 #define SCANLINE_BLT 0x21 << 22 359 #define TEXT_BLT 0x22 << 22 360 #define TEXT_IMM_BLT 0x30 << 22 361 #define COLOR_BLT 0x40 << 22 362 #define MONO_PAT_BLIT 0x42 << 22 363 #define SOURCE_COPY_BLIT 0x43 << 22 364 #define FULL_BLIT 0x45 << 22 365 366 /* Primitive */ 367 #define TRILIST 0 368 #define TRISTRIP 1 << 18 369 #define TRISTRIP_REV 2 << 18 370 #define TRIFAN 3 << 18 371 #define POLYGON 4 << 18 372 #define LINELIST 5 << 18 373 #define LINESTRIP 6 << 18 374 #define RECTANGLE 7 << 18 375 #define V0_ENABLE 1 376 #define V1_ENABLE 2 377 #define V2_ENABLE 4 378 379 /* Vertex Flags */ 380 #define COORD_1 0 381 #define COORD_2 1 << 8 382 #define COORD_3 2 << 8 383 #define FOG_ENABLE 1 << 7 384 #define ARGB_ENABLE 1 << 6 385 #define Z_OFFSET_PRESENT 1 << 5 386 #define XYZ 0x01 << 1 387 #define XYZW 0x02 << 1 388 #define XY 0x03 << 1 389 #define XYW 0x04 << 1 390 391 /* Antialiasing */ 392 #define AA_UPDATE_EDGEFLAG (1<<13) 393 #define AA_ENABLE_EDGEFLAG (1<<12) 394 #define AA_UPDATE_POLYWIDTH (1<<11) 395 #define AA_POLYWIDTH_05 (1<<9) 396 #define AA_POLYWIDTH_10 (2<<9) 397 #define AA_POLYWIDTH_20 (3<<9) 398 #define AA_POLYWIDTH_40 (4<<9) 399 #define AA_UPDATE_LINEWIDTH (1<<8) 400 #define AA_LINEWIDTH_05 (1<<6) 401 #define AA_LINEWIDTH_10 (2<<6) 402 #define AA_LINEWIDTH_20 (3<<6) 403 #define AA_LINEWIDTH_40 (4<<6) 404 #define AA_UPDATE_BB_EXPANSION (1<<5) 405 #define AA_BB_EXPANSION_SHIFT 2 406 #define AA_UPDATE_AA_ENABLE (1<<1) 407 #define AA_ENABLE (1<<0) 408 409 /* Pixelization Rule */ 410 #define PVK_SMALL_TRI_UPDATE 1 << 12 411 #define PVK_SMALL_TRI 1 << 11 412 #define PVK_PIX_RULE_UPDATE 1 << 10 413 #define PVK_PIX_RULE 1 << 9 414 #define PVK_LINE_UPDATE 1 << 8 415 #define PVK_LINE_V0 0 416 #define PVK_LINE_V1 1 << 6 417 #define PVK_TRIFAN_UPDATE 1 << 5 418 #define PVK_TRIFAN_V0 0 419 #define PVK_TRIFAN_V1 1 << 3 420 #define PVK_TRIFAN_V2 2 << 3 421 #define PVK_TRISTRIP_UPDATE 1 << 2 422 #define PVK_TRISTRIP_V0 0 423 #define PVK_TRISTRIP_V1 1 424 #define PVK_TRISTRIP_V2 2 425 426 /* Boolean Enable 1 */ 427 #define B1_ALPHA_SETUP_ENABLE_UPDATE 1 << 17 428 #define B1_ALPHA_SETUP_ENABLE 1 << 16 429 #define B1_FOG_ENABLE_UPDATE 1 << 7 430 #define B1_FOG_ENABLE 1 << 6 431 #define B1_ALPHA_STATE_ENABLE_UPDATE 1 << 5 432 #define B1_ALPHA_STATE_ENABLE 1 << 4 433 #define B1_BLEND_ENABLE_UPDATE 1 << 3 434 #define B1_BLEND_ENABLE 1 << 2 435 #define B1_Z_ENABLE_UPDATE 1 << 1 436 #define B1_Z_ENABLE 1 437 438 /* Boolean Enable 2 */ 439 #define B2_MCE_UPDATE 1 << 17 440 #define B2_MCE 1 << 16 441 #define B2_ALPHA_DITHER_UPDATE 1 << 15 442 #define B2_ALPHA_DITHER 1 << 14 443 #define B2_FOG_DITHER_UPDATE 1 << 13 444 #define B2_FOG_DITHER 1 << 12 445 #define B2_SPEC_DITHER_UPDATE 1 << 11 446 #define B2_SPEC_DITHER 1 << 10 447 #define B2_COLOR_DITHER_UPDATE 1 << 9 448 #define B2_COLOR_DITHER 1 << 8 449 #define B2_FB_WRITE_UPDATE 1 << 3 450 #define B2_FB_WRITE 1 << 2 451 #define B2_ZB_WRITE_UPDATE 1 << 1 452 #define B2_ZB_WRITE 1 453 454 /* Cull Shade Mode */ 455 #define CULL_Z_UPDATE 1 << 20 456 #define CULL_Z_ALWAYS 0 457 #define CULL_Z_NEVER 1 << 16 458 #define CULL_Z_LESS 2 << 16 459 #define CULL_Z_EQUAL 3 << 16 460 #define CULL_Z_LEQUAL 4 << 16 461 #define CULL_Z_GREATER 5 << 16 462 #define CULL_Z_NOTEQUAL 6 << 16 463 #define CULL_Z_GEQUAL 7 << 16 464 #define CULL_LINE_WIDTH_UPDATE 1 << 15 465 #define CULL_LINE_WIDTH_MASK 7 << 12 466 #define CULL_ALPHA_SHADE_UPDATE 1 << 11 467 #define CULL_ALPHA_SHADE 1 << 10 468 #define CULL_FOG_SHADE_UPDATE 1 << 9 469 #define CULL_FOG_SHADE 1 << 8 470 #define CULL_SPEC_SHADE_UPDATE 1 << 7 471 #define CULL_SPEC_SHADE 1 << 6 472 #define CULL_COLOR_SHADE_UPDATE 1 << 5 473 #define CULL_COLOR_SHADE 1 << 4 474 #define CULL_MODE_UPDATE 1 << 3 475 #define CULL_NONE 1 << 2 476 #define CULL_CW 2 << 2 477 #define CULL_CCW 3 << 2 478 #define CULL_BOTH 4 << 2 479 480 /* texel map */ 481 #define UPDATE_TEXEL1 1 << 15 482 #define UPDATE_TEXEL0 1 << 7 483 #define ENABLE_TEXEL1 1 << 14 484 #define ENABLE_TEXEL0 1 << 6 485 #define TEXEL1_COORD_IDX 1 << 11 486 #define TEXEL0_COORD_IDX 1 << 3 487 #define TEXEL1_MAP_IDX 1 << 8 488 #define TEXEL0_MAP_IDX 1 489 490 /* color blend stage */ 491 #define COLOR_STAGE0 0 492 #define COLOR_STAGE1 1 << 20 493 #define COLOR_STAGE2 2 << 20 494 #define UPDATE_COLOR_SELECT_MASK 1 << 19 495 #define SELECT_COLOR_ACC 1 << 18 496 #define SELECT_COLOR_CURRENT 0 497 #define UPDATE_COLOR_ARG1 1 << 17 498 #define ARG1_COLOR_FACTOR 1 << 14 499 #define ARG1_COLOR_ACC 2 << 14 500 #define ARG1_COLOR_ITERATED 3 << 14 501 #define ARG1_COLOR_SPEC 4 << 14 502 #define ARG1_COLOR_CURRENT 5 << 14 503 #define ARG1_COLOR_TEXEL0 6 << 14 504 #define ARG1_COLOR_TEXEL1 7 << 14 505 #define ARG1_REPLICATE_ALPHA_TO_COLOR 1 << 13 506 #define ARG1_COLOR_INVERT 1 << 12 507 #define UPDATE_COLOR_ARG2 1 << 11 508 #define ARG2_COLOR_FACTOR 1 << 8 509 #define ARG2_COLOR_ACC 2 << 8 510 #define ARG2_COLOR_ITERATED 3 << 8 511 #define ARG2_COLOR_SPEC 4 << 8 512 #define ARG2_COLOR_CURRENT 5 << 8 513 #define ARG2_COLOR_TEXEL0 6 << 8 514 #define ARG2_COLOR_TEXEL1 7 << 8 515 #define ARG2_REPLICATE_ALPHA_TO_COLOR 1 << 7 516 #define ARG2_COLORINVERT 1 << 6 517 #define UPDATE_COLOR_OP 1 << 5 518 #define DISABLE_COLOR_OP 0 519 #define SELECT_COLOR_ARG1_OP 1 520 #define SELECT_COLOR_ARG2_OP 2 521 #define MODULATE_COLOR_OP 3 522 #define MODULATE2X_COLOR_OP 4 523 #define MODULATE4X_COLOR_OP 5 524 #define ADD_COLOR_OP 6 525 #define ADD_SIGNED_COLOR_OP 7 526 #define LINEAR_ALPHA_ITER_OP 8 527 #define LINEAR_ALPHA_FACTOR_OP 0x0a 528 #define LINEAR_TEXEL0_ALPHA_OP 0x10 529 #define LINEAR_TEXEL1_ALPHA_OP 0x11 530 #define LINEAR_TEXEL0_COLOR_OP 0x12 531 #define LINEAR_TEXEL1_COLOR_OP 0x13 532 #define SUBTRACT_COLOR_OP 0x14 533 534 /* alpha blend stage */ 535 #define ALPHA_STAGE0 0 536 #define ALPHA_STAGE1 1 << 20 537 #define ALPHA_STAGE2 2 << 20 538 #define UPDATE_ALPHA_SELECT_MASK 1 << 19 539 #define UPDATE_ALPHA_ARG1 1 << 18 540 #define ARG1_ALPHA_FACTOR 1 << 15 541 #define ARG1_ALPHA_ITERATED 3 << 15 542 #define ARG1_ALPHA_CURRENT 5 << 15 543 #define ARG1_ALPHA_TEXEL0 6 << 15 544 #define ARG1_ALPHA_TEXEL1 7 << 15 545 #define ARG1_ALPHA_INVERT 1 << 13 546 #define UPDATE_ALPHA_ARG2 1 << 12 547 #define ARG2_ALPHA_FACTOR 1 << 8 548 #define ARG2_ALPHA_ITERATED 3 << 8 549 #define ARG2_ALPHA_CURRENT 5 << 8 550 #define ARG2_ALPHA_TEXEL0 6 << 8 551 #define ARG2_ALPHA_TEXEL1 7 << 8 552 #define ARG2_ALPHAINVERT 1 << 6 553 #define UPDATE_ALPHA_OP 1 << 5 554 #define DISABLE_ALPHA_OP 0 555 #define SELECT_ALPHA_ARG1_OP 1 556 #define SELECT_ALPHA_ARG2_OP 2 557 #define MODULATE_ALPHA_OP 3 558 #define MODULATE2X_ALPHA_OP 4 559 #define MODULATE4X_ALPHA_OP 5 560 #define ADD_ALPHA_OP 6 561 #define ADD_SIGNED_ALPHA_OP 7 562 #define LINEAR_ALPHA_ITER_OP 8 563 #define LINEAR_ALPHA_FACTOR_OP 0x0a 564 #define LINEAR_TEXEL0_ALPHA_OP 0x10 565 #define LINEAR_TEXEL1_ALPHA_OP 0x11 566 567 /* Source-Dest Blend Mono */ 568 #define UPDATE_MONO 1 << 13 569 #define ENABLE_MONO 1 << 12 570 #define DISABLE_MONO 0 571 #define UPDATE_SRC_MONO_BLEND 1 << 11 572 #define UPDATE_DEST_MONO_BLEND 1 << 5 573 574 #define SRC_ZERO 1 >>6 575 #define SRC_ONE 2 << 6 576 #define SRC_SRC_COLOR 3 << 6 577 #define SRC_INV_SRC_COLOR 4 << 6 578 #define SRC_SRC_ALPHA 5 << 6 579 #define SRC_INV_SRC_ALPHA 6 << 6 580 #define SRC_DST_COLOR 9 << 6 581 #define SRC_INV_DST_COLOR 0x0a << 6 582 #define SRC_BOTH_SRC_ALPHA 0x0c << 6 583 #define SRC_BOTH_INV_SRC_ALPHA 0x0d << 6 584 585 #define DEST_ZERO 1 586 #define DEST_ONE 2 587 #define DEST_SRC_COLOR 3 588 #define DEST_INV_SRC_COLOR 4 589 #define DEST_SRC_ALPHA 5 590 #define DEST_INV_SRC_ALPHA 6 591 #define DEST_DST_COLOR 9 592 #define DEST_INV_DST_COLOR 0x0a 593 #define DEST_BOTH_SRC_ALPHA 0x0c 594 #define DEST_BOTH_INV_SRC_ALPHA 0x0d 595 596 /* Destination Render Buffer */ 597 #define RENDER_RGB8 0 598 #define RENDER_RGB15 1 << 8 599 #define RENDER_RGB16 2 << 8 600 #define YUV_YSWAP 4 << 8 601 #define YUV_NORMAL 5 << 8 602 #define YUV_UVSWAP 6 << 8 603 #define YUV_YUVSWAP 7 << 8 604 605 #define ORG_XBIASMASK 0x0F << 20 606 #define ORG_YBIASMASK 0x0F << 16 607 #define VSTRIDE 2 608 #define VSTRIDE_OFFSET 1 609 610 /* Alpha Z-bias */ 611 #define UPDATE_ZBIAS 1 << 22 612 #define UPDATE_ALPHA_FX 1 << 13 613 #define UPDATE_ALPHA_REFERENCE 1 << 8 614 615 #define ALPHAFX_NEVER 1 << 9 616 #define ALPHAFX_LESS 2 << 9 617 #define ALPHAFX_EQUAL 3 << 9 618 #define ALPHAFX_LEQUAL 4 << 9 619 #define ALPHAFX_GREATER 5 << 9 620 #define ALPHAFX_NOTEQUAL 6 << 9 621 #define ALPHAFX_GEQUAL 7 << 9 622 #define ALPHAFX_ALWAYS 8 << 9 623 624 /* Scissor */ 625 #define SCISSOR_ENABLE_UPDATE 1 << 1 626 #define SCISSOR_ENABLE 1 627 628 /* Stipple */ 629 #define STIPPLE_ENABLE 1 << 16 630 631 /* Rendering Packets */ 632 /* state pipelined */ 633 #define COLOR_BLEND_STAGE RENDER | 0x00 << 24 634 #define ALPHA_BLEND_STAGE RENDER | 0x01 << 24 635 #define LINE_WIDTH_CULL_SHADE RENDER | 0x02 << 24 636 #define BOOL_ENABLE_1 RENDER | 0x03 << 24 637 #define BOOL_ENABLE_2 RENDER | 0x04 << 24 638 #define VERTEX_FORMAT RENDER | 0x05 << 24 639 #define ANTIALIAS RENDER | 0x06 << 24 640 #define PVK_PIXEL_RULE RENDER | 0x07 << 24 641 #define SRC_DEST_BLEND_MONO RENDER | 0x08 << 24 642 #define MAP_TEXEL RENDER | 0x1C << 24 643 #define PRIMITIVE RENDER | 0x1F << 24 644 645 /* multiple dwords */ 646 #define COLOR_FACTOR RENDER | 0x1D << 24 | 0x01 << 16 | 0 647 #define COLOR_CHROMA_KEY RENDER | 0x1D << 24 | 0x02 << 16 | 1 648 #define DRAWING_RECT_INFO RENDER | 0x1D << 24 | 0x80 << 16 | 3 649 #define RENDER_BUF_DEST RENDER | 0x1D << 24 | 0x85 << 16 | 0 650 #define SCISSOR_INFO RENDER | 0x1D << 24 | 0x81 << 16 | 1 651 #define STIPPLE RENDER | 0x1D << 24 | 0x83 << 16 | 0 652 653 /* non-pipelined */ 654 #define ALPHA_Z_BIAS RENDER | 0x14 << 24 655 #define FOG_COLOR RENDER | 0x15 << 24 656 #define SCISSOR RENDER | 0x1C << 24 | 0x10 << 19 657 658 659 #define RBUFFER_START_MASK 0xFFFFF000 660 #define RBUFFER_SIZE_MASK 0x001FF000 661 #define RBUFFER_HEAD_MASK 0x001FFFFC 662 #define RBUFFER_TAIL_MASK 0x001FFFF8 663 #define RINGBUFFER_SIZE (128 * 1024) 664 #define RING_SIZE_MASK (RINGBUFFER_SIZE - 1) 665 666 #define I810RES_GART 1 667 #define I810RES_LRING_ACQ 2 668 #define I810RES_LRING_BIND 4 669 #define I810RES_OVL_ACQ 8 670 #define I810RES_OVL_BIND 16 671 #define I810RES_GART_ACQ 32 672 #define I810RES_MMAP 64 673 #define I810RES_STATE_SAVE 128 674 675 #ifndef AGP_NORMAL_MEMORY 676 #define AGP_NORMAL_MEMORY 0 677 #endif 678 679 #ifndef AGP_PHYSICAL_MEMORY 680 #define AGP_PHYSICAL_MEMORY 2 681 #endif 682 683 struct i810_ovl_regs { 684 u32 obuf_0y; 685 u32 obuf_1y; 686 u32 obuf_0u; 687 u32 obuf_0v; 688 u32 obuf_1u; 689 u32 obuf_1v; 690 u32 ov0stride; 691 u32 yrgb_vph; 692 u32 uv_vph; 693 u32 horz_ph; 694 u32 init_ph; 695 u32 dwinpos; 696 u32 dwinsz; 697 u32 swid; 698 u32 swidqw; 699 u32 sheight; 700 u32 yrgbscale; 701 u32 uvscale; 702 u32 ov0clrc0; 703 u32 ov0clrc1; 704 u32 dclrkv; 705 u32 dclrkm; 706 u32 sclrkvh; 707 u32 sclrkvl; 708 u32 sclrkm; 709 u32 ov0conf; 710 u32 ov0cmd; 711 u32 reserved; 712 u32 awinpos; 713 u32 awinsz; 714 }; 715 716 typedef struct { 717 CoreLayerRegionConfig config; 718 int planar_bug; 719 } I810OverlayLayerData; 720 721 722 typedef struct { 723 unsigned int tail_mask; 724 725 int size; 726 int head; 727 int tail; 728 int space; 729 } I810RingBuffer; 730 731 typedef struct { 732 volatile void *virt; 733 unsigned int tail_mask; 734 unsigned int outring; 735 } I810RingBlock; 736 737 738 typedef struct { 739 bool initialized; 740 741 I810RingBuffer lp_ring; 742 743 bool overlayOn; 744 I810OverlayLayerData *iovl; 745 746 agp_info info; 747 agp_allocate lring_mem; 748 agp_allocate ovl_mem; 749 agp_bind lring_bind; 750 agp_bind ovl_bind; 751 752 u32 pattern; 753 u32 lring1; 754 u32 lring2; 755 u32 lring3; 756 u32 lring4; 757 758 u32 i810fb_version; 759 u32 cur_tail; 760 int srcaddr, destaddr, srcpitch, destpitch; 761 int color_value, color_value3d, pixeldepth, blit_color; 762 int colorkey_bit, colorkey, render_color; 763 int clip_x1, clip_x2, clip_y1, clip_y2; 764 765 /* state validation */ 766 int i_src; 767 int i_dst; 768 int i_color; 769 int i_colorkey; 770 int i_clip; 771 /* benchmarking */ 772 u32 waitfifo_sum; 773 u32 waitfifo_calls; 774 u32 idle_calls; 775 u32 fifo_waitcycles; 776 u32 idle_waitcycles; 777 u32 fifo_cache_hits; 778 u32 fifo_timeoutsum; 779 u32 idle_timeoutsum; 780 } I810DeviceData; 781 782 typedef struct { 783 I810DeviceData *idev; 784 785 volatile struct i810_ovl_regs *oregs; 786 787 u32 flags; 788 int agpgart; 789 agp_info info; 790 volatile u8 *aper_base; 791 volatile u8 *lring_base; 792 volatile u8 *ovl_base; 793 volatile u8 *mmio_base; 794 volatile u8 *pattern_base; 795 } I810DriverData; 796 797 extern DisplayLayerFuncs i810OverlayFuncs; 798 799 void i810ovlOnOff( I810DriverData *idrv, 800 I810DeviceData *idev, 801 bool on ); 802 803 804 #define i810_readb(mmio_base, where) \ 805 *((volatile u8 *) (mmio_base + where)) \ 806 807 #define i810_readw(mmio_base, where) \ 808 *((volatile u16 *) (mmio_base + where)) \ 809 810 #define i810_readl(mmio_base, where) \ 811 *((volatile u32 *) (mmio_base + where)) \ 812 813 #define i810_writeb(mmio_base, where, val) \ 814 *((volatile u8 *) (mmio_base + where)) = (volatile u8) val \ 815 816 #define i810_writew(mmio_base, where, val) \ 817 *((volatile u16 *) (mmio_base + where)) = (volatile u16) val \ 818 819 #define i810_writel(mmio_base, where, val) \ 820 *((volatile u32 *) (mmio_base + where)) = (volatile u32) val \ 821 822 #define PUT_LRING(val) { \ 823 i810_writel(i810drv->lring_base, i810dev->cur_tail, val); \ 824 i810dev->cur_tail += 4; \ 825 i810dev->cur_tail &= RING_SIZE_MASK; \ 826 } 827 828 #define BEGIN_LRING i810_wait_for_space 829 830 #define END_LRING(i810drv) i810_writel(LRING, i810drv->mmio_base, i810dev->cur_tail) 831 832 #endif /* __I810_H__ */ 833