1 #objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp0-names=mips64r2 2 #name: MIPS CP0 register disassembly (mips64r2) 3 #source: cp0-names.s 4 5 # Check objdump's handling of -M cp0-names=foo options. 6 7 .*: +file format .*mips.* 8 9 Disassembly of section .text: 10 0+0000 <[^>]*> 40800000 mtc0 \$0,c0_index 11 0+0004 <[^>]*> 40800800 mtc0 \$0,c0_random 12 0+0008 <[^>]*> 40801000 mtc0 \$0,c0_entrylo0 13 0+000c <[^>]*> 40801800 mtc0 \$0,c0_entrylo1 14 0+0010 <[^>]*> 40802000 mtc0 \$0,c0_context 15 0+0014 <[^>]*> 40802800 mtc0 \$0,c0_pagemask 16 0+0018 <[^>]*> 40803000 mtc0 \$0,c0_wired 17 0+001c <[^>]*> 40803800 mtc0 \$0,c0_hwrena 18 0+0020 <[^>]*> 40804000 mtc0 \$0,c0_badvaddr 19 0+0024 <[^>]*> 40804800 mtc0 \$0,c0_count 20 0+0028 <[^>]*> 40805000 mtc0 \$0,c0_entryhi 21 0+002c <[^>]*> 40805800 mtc0 \$0,c0_compare 22 0+0030 <[^>]*> 40806000 mtc0 \$0,c0_status 23 0+0034 <[^>]*> 40806800 mtc0 \$0,c0_cause 24 0+0038 <[^>]*> 40807000 mtc0 \$0,c0_epc 25 0+003c <[^>]*> 40807800 mtc0 \$0,c0_prid 26 0+0040 <[^>]*> 40808000 mtc0 \$0,c0_config 27 0+0044 <[^>]*> 40808800 mtc0 \$0,c0_lladdr 28 0+0048 <[^>]*> 40809000 mtc0 \$0,c0_watchlo 29 0+004c <[^>]*> 40809800 mtc0 \$0,c0_watchhi 30 0+0050 <[^>]*> 4080a000 mtc0 \$0,c0_xcontext 31 0+0054 <[^>]*> 4080a800 mtc0 \$0,\$21 32 0+0058 <[^>]*> 4080b000 mtc0 \$0,\$22 33 0+005c <[^>]*> 4080b800 mtc0 \$0,c0_debug 34 0+0060 <[^>]*> 4080c000 mtc0 \$0,c0_depc 35 0+0064 <[^>]*> 4080c800 mtc0 \$0,c0_perfcnt 36 0+0068 <[^>]*> 4080d000 mtc0 \$0,c0_errctl 37 0+006c <[^>]*> 4080d800 mtc0 \$0,c0_cacheerr 38 0+0070 <[^>]*> 4080e000 mtc0 \$0,c0_taglo 39 0+0074 <[^>]*> 4080e800 mtc0 \$0,c0_taghi 40 0+0078 <[^>]*> 4080f000 mtc0 \$0,c0_errorepc 41 0+007c <[^>]*> 4080f800 mtc0 \$0,c0_desave 42 \.\.\. 43