1 /*\ 2 * dxa v0.1.1 -- symbolic 65xx disassembler 3 * 4 * Copyright (C) 1993, 1994 Marko M\"akel\"a 5 * Changes for dxa (C) 2006 Cameron Kaiser 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * 21 * Marko does not maintain dxa, so questions specific to dxa should be 22 * sent to me at ckaiser@floodgap.com . Otherwise, 23 * 24 * Contacting the author: 25 * 26 * Via Internet E-mail: 27 * <Marko.Makela@FTP.FUNET.FI> 28 * 29 * Via Snail Mail: 30 * Marko M\"akel\"a 31 * Sillitie 10 A 32 * FIN-01480 VANTAA 33 * Finland 34 \*/ 35 36 /* opcodes.h - opcodes for different microprocessors */ 37 38 #ifndef _OPCODES_H_ 39 #define _OPCODES_H_ 40 41 #ifdef _DUMP_C_ 42 43 static char *mne[] = { "???", "lda", "ldx", "ldy", "sta", "stx", "sty", 44 "stz", "adc", "sbc", "dec", "dex", "dey", "inc", "inx", "iny", "cmp", 45 "cpx", "cpy", "bit", "and", "ora", "eor", "asl", "lsr", "rol", "ror", 46 "tax", "tay", "tsx", "txs", "tya", "tad", "tas", "tda", "tsa", "txy", 47 "tyx", "pha", "phx", "phy", "php", "pea", "pei", "per", "phb", "phd", 48 "phk", "plb", "pld", "pla", "plx", "ply", "plp", "clc", "cld", "cli", 49 "clv", "sec", "sed", "sei", "rep", "sep", "xba", "xce", "bcc", "bcs", 50 "bne", "beq", "bra", "brl", "bpl", "bmi", "bvc", "bvs", "jmp", "jml", 51 "jsr", "jsl", "rts", "rtl", "rti", "brk", "nop", "trb", "tsb", "wai", 52 "bbr0", "bbr1", "bbr2", "bbr3", "bbr4", "bbr5", "bbr6", "bbr7", 53 "bbs0", "bbs1", "bbs2", "bbs3", "bbs4", "bbs5", "bbs6", "bbs7", 54 "rmb0", "rmb1", "rmb2", "rmb3", "rmb4", "rmb5", "rmb6", "rmb7", 55 "smb0", "smb1", "smb2", "smb3", "smb4", "smb5", "smb6", "smb7", "cop", 56 "mvn", "mvp", "laxs", "stax", "sha", "shx", "shy", "ane", "lxa", "lae", 57 "shs", "sbx", "usbc", "dcmp", "isbc", "rlan", "rrad", "slor", "sreo", 58 "arr", "asr", "anc", "noop", "stp", "txa", "ldax" }; 59 60 #endif /* _DUMP_C_ */ 61 62 enum 63 { 64 S_ILLEGAL = 0, S_LDA, S_LDX, S_LDY, S_STA, S_STX, S_STY, S_STZ, S_ADC, 65 S_SBC, S_DEC, S_DEX, S_DEY, S_INC, S_INX, S_INY, S_CMP, S_CPX, S_CPY, 66 S_BIT, S_AND, S_ORA, S_EOR, S_ASL, S_LSR, S_ROL, S_ROR, S_TAX, S_TAY, 67 S_TSX, S_TXS, S_TYA, S_TAD, S_TAS, S_TDA, S_TSA, S_TXY, S_TYX, S_PHA, 68 S_PHX, S_PHY, S_PHP, S_PEA, S_PEI, S_PER, S_PHB, S_PHD, S_PHK, S_PLB, 69 S_PLD, S_PLA, S_PLX, S_PLY, S_PLP, S_CLC, S_CLD, S_CLI, S_CLV, S_SEC, 70 S_SED, S_SEI, S_REP, S_SEP, S_XBA, S_XCE, S_BCC, S_BCS, S_BNE, S_BEQ, 71 S_BRA, S_BRL, S_BPL, S_BMI, S_BVC, S_BVS, S_JMP, S_JML, S_JSR, S_JSL, 72 S_RTS, S_RTL, S_RTI, S_BRK, S_NOP, S_TRB, S_TSB, S_WAI, 73 S_BBR0, S_BBR1, S_BBR2, S_BBR3, S_BBR4, S_BBR5, S_BBR6, S_BBR7, 74 S_BBS0, S_BBS1, S_BBS2, S_BBS3, S_BBS4, S_BBS5, S_BBS6, S_BBS7, 75 S_RMB0, S_RMB1, S_RMB2, S_RMB3, S_RMB4, S_RMB5, S_RMB6, S_RMB7, 76 S_SMB0, S_SMB1, S_SMB2, S_SMB3, S_SMB4, S_SMB5, S_SMB6, S_SMB7, 77 S_COP, S_MVN, S_MVP, S_LAXS, S_STAX, S_SHA, S_SHX, S_SHY, S_ANE, S_LXA, 78 S_LAE, S_SHS, S_SBX, S_USBC, S_DCMP, S_ISBC, S_RLAN, S_RRAD, S_SLOR, 79 S_SREO, S_ARR, S_ASR, S_ANC, S_NOOP, S_STP, S_TXA, S_LDAX 80 }; 81 82 enum 83 { 84 accu=0, imm, abso, zp, zpx, zpy, absx, absy, 85 iabsx, impl, rel, zrel, indx, indy, iabs, ind 86 }; 87 88 #ifdef _DUMP_C_ 89 static char *prefix[] = { "", "#", "", "", "", "", "", "", 90 "(", "", "", "", "(", "(", "(", "(" }; 91 92 /* static char *postfix[] = { " A", "", "", "", ",X", ",Y", ",X", ",Y", */ 93 static char *postfix[] = { "", "", "", "", ",x", ",y", ",x", ",y", 94 ",x)", "", "", "", ",x)", "),y", ")", ")" }; 95 #endif /* _DUMP_C_ */ 96 97 /* Adressing mode types. */ 98 enum 99 { 100 absindir, /* absolute parameter (8 or 16 bits) for indirection */ 101 absolute, /* absolute parameter (8 or 16 bits), not indexed */ 102 other, /* something else (except impimm) */ 103 impimm /* implied or immediate parameter */ 104 }; 105 106 #ifndef _SCAN_C_ 107 extern unsigned int types[]; 108 #else 109 unsigned int types[] = { impimm, impimm, absolute, absolute, other, other, 110 other, other, other, impimm, other, other, 111 other, absindir, absindir, absindir }; 112 #endif 113 114 /* Number of bytes that instructions of different addressing modes occupy */ 115 #ifndef _SCAN_C_ 116 extern unsigned int sizes[]; 117 #else 118 unsigned int sizes[] = { 1, 2, 3, 2, 2, 2, 3, 3, 3, 1, 2, 3, 2, 2, 3, 2 }; 119 #endif 120 121 typedef struct opcodes 122 { 123 int mnemonic; /* index to mnemonic instruction name table */ 124 int admode; /* addressing mode */ 125 } opcodes; 126 127 #ifndef _MAIN_C_ 128 extern 129 #endif 130 opcodes *opset; 131 132 #ifdef _MAIN_C_ 133 opcodes all_nmos6502[] = 134 { 135 {S_BRK, impl}, {S_ORA, indx}, {S_STP, impl}, {S_SLOR,indx}, 136 {S_NOOP, zp}, {S_ORA, zp}, {S_ASL, zp}, {S_SLOR, zp}, 137 {S_PHP, impl}, {S_ORA, imm}, {S_ASL, accu}, {S_ANC, imm}, 138 {S_NOOP,abso}, {S_ORA, abso}, {S_ASL, abso}, {S_SLOR, abso}, 139 {S_BPL, rel}, {S_ORA, indy}, {S_STP, impl}, {S_SLOR,indy}, 140 {S_NOOP, zpx}, {S_ORA, zpx}, {S_ASL, zpx}, {S_SLOR, zpx}, 141 {S_CLC, impl}, {S_ORA, absy}, {S_NOOP,impl}, {S_SLOR,absy}, 142 {S_NOOP,absx}, {S_ORA, absx}, {S_ASL, absx}, {S_SLOR,absx}, 143 144 {S_JSR, abso}, {S_AND, indx}, {S_STP, impl}, {S_RLAN,indx}, 145 {S_BIT, zp}, {S_AND, zp}, {S_ROL, zp}, {S_RLAN, zp}, 146 {S_PLP, impl}, {S_AND, imm}, {S_ROL, accu}, {S_ANC, imm}, 147 {S_BIT, abso}, {S_AND, abso}, {S_ROL, abso}, {S_RLAN,abso}, 148 {S_BMI, rel}, {S_AND, indy}, {S_STP, impl}, {S_RLAN,indy}, 149 {S_NOOP, zpx}, {S_AND, zpx}, {S_ROL, zpx}, {S_RLAN, zpx}, 150 {S_SEC, impl}, {S_AND, absy}, {S_NOOP,impl}, {S_RLAN,absy}, 151 {S_NOOP,absx}, {S_AND, absx}, {S_ROL, absx}, {S_RLAN,absx}, 152 153 {S_RTI, impl}, {S_EOR, indx}, {S_STP, impl}, {S_SREO,indx}, 154 {S_NOOP, zp}, {S_EOR, zp}, {S_LSR, zp}, {S_SREO, zp}, 155 {S_PHA, impl}, {S_EOR, imm}, {S_LSR, accu}, {S_ASR, imm}, 156 {S_JMP, abso}, {S_EOR, abso}, {S_LSR, abso}, {S_SREO,abso}, 157 {S_BVC, rel}, {S_EOR, indy}, {S_STP, impl}, {S_SREO,indy}, 158 {S_NOOP, zpx}, {S_EOR, zpx}, {S_LSR, zpx}, {S_SREO, zpx}, 159 {S_CLI, impl}, {S_EOR, absy}, {S_NOOP,impl}, {S_SREO,absy}, 160 {S_NOOP,absx}, {S_EOR, absx}, {S_LSR, absx}, {S_SREO,absx}, 161 162 {S_RTS, impl}, {S_ADC, indx}, {S_STP, impl}, {S_RRAD,indx}, 163 {S_NOOP, zp}, {S_ADC, zp}, {S_ROR, zp}, {S_RRAD, zp}, 164 {S_PLA, impl}, {S_ADC, imm}, {S_ROR, accu}, {S_ARR, imm}, 165 {S_JMP, iabs}, {S_ADC, abso}, {S_ROR, abso}, {S_RRAD,abso}, 166 {S_BVS, rel}, {S_ADC, indy}, {S_STP, impl}, {S_RRAD,indy}, 167 {S_NOOP, zpx}, {S_ADC, zpx}, {S_ROR, zpx}, {S_RRAD, zpx}, 168 {S_SEI, impl}, {S_ADC, absy}, {S_NOOP,impl}, {S_RRAD,absy}, 169 {S_NOOP,absx}, {S_ADC, absx}, {S_ROR, absx}, {S_RRAD,absx}, 170 171 {S_NOOP, imm}, {S_STA, indx}, {S_NOOP, imm}, {S_STAX,indx}, 172 {S_STY, zp}, {S_STA, zp}, {S_STX, zp}, {S_STAX, zp}, 173 {S_DEY, impl}, {S_NOOP, imm}, {S_TXA, impl}, {S_ANE, imm}, 174 {S_STY, abso}, {S_STA, abso}, {S_STX, abso}, {S_STAX,abso}, 175 {S_BCC, rel}, {S_STA, indy}, {S_STP, impl}, {S_SHA, indy}, 176 {S_STY, zpx}, {S_STA, zpx}, {S_STX, zpy}, {S_STAX, zpy}, 177 {S_TYA, impl}, {S_STA, absy}, {S_TXS, impl}, {S_SHS, absy}, 178 {S_SHY, absx}, {S_STA, absx}, {S_SHX, absx}, {S_SHA, absx}, 179 180 {S_LDY, imm}, {S_LDA, indx}, {S_LDX, imm}, {S_LDAX,indy}, 181 {S_LDY, zp}, {S_LDA, zp}, {S_LDX, zp}, {S_LDAX, zp}, 182 {S_TAY, impl}, {S_LDA, imm}, {S_TAX, impl}, {S_LXA, imm}, 183 {S_LDY, abso}, {S_LDA, abso}, {S_LDX, abso}, {S_LDAX,abso}, 184 {S_BCS, rel}, {S_LDA, indy}, {S_STP, impl}, {S_LDAX,indy}, 185 {S_LDY, zpx}, {S_LDA, zpx}, {S_LDX, zpy}, {S_LDAX, zpy}, 186 {S_CLV, impl}, {S_LDA, absy}, {S_TSX, impl}, {S_LAXS,absy}, 187 {S_LDY, absx}, {S_LDA, absx}, {S_LDX, absy}, {S_LDAX,absy}, 188 189 {S_CPY, imm}, {S_CMP, indx}, {S_NOOP, imm}, {S_DCMP,indx}, 190 {S_CPY, zp}, {S_CMP, zp}, {S_DEC, zp}, {S_DCMP, zp}, 191 {S_INY, impl}, {S_CMP, imm}, {S_DEX, impl}, {S_SBX, imm}, 192 {S_CPY, abso}, {S_CMP, abso}, {S_DEC, abso}, {S_DCMP,abso}, 193 {S_BNE, rel}, {S_CMP, indy}, {S_STP, impl}, {S_DCMP,indy}, 194 {S_NOOP, zpx}, {S_CMP, zpx}, {S_DEC, zpx}, {S_DCMP, zpx}, 195 {S_CLD, impl}, {S_CMP, absy}, {S_NOOP,impl}, {S_DCMP,absy}, 196 {S_NOOP,absx}, {S_CMP, absx}, {S_DEC, absx}, {S_DCMP,absx}, 197 198 {S_CPX, imm}, {S_SBC, indx}, {S_NOOP, imm}, {S_ISBC,indx}, 199 {S_CPX, zp}, {S_SBC, zp}, {S_INC, zp}, {S_ISBC, zp}, 200 {S_INX, impl}, {S_SBC, imm}, {S_NOP, impl}, {S_USBC, imm}, 201 {S_CPX, abso}, {S_SBC, abso}, {S_INC, abso}, {S_ISBC,abso}, 202 {S_BEQ, rel}, {S_SBC, indy}, {S_STP, impl}, {S_ISBC,indy}, 203 {S_NOOP, zpx}, {S_SBC, zpx}, {S_INC, zpx}, {S_ISBC, zpx}, 204 {S_SED, impl}, {S_SBC, absy}, {S_NOOP,impl}, {S_ISBC,absy}, 205 {S_NOOP,absx}, {S_SBC, absx}, {S_INC, absx}, {S_ISBC,absx}, 206 }; 207 208 /*\ 209 * The following NMOS 6502 instructions are missing from the 210 * rational_nmos6502 map: 211 * 212 * ANE SHA SHS SHY SHX LXA LAXS 213 \*/ 214 215 opcodes rational_nmos6502[] = 216 { 217 {S_BRK, impl}, {S_ORA, indx}, {S_STP, impl}, {S_SLOR,indx}, 218 {S_NOOP, zp}, {S_ORA, zp}, {S_ASL, zp}, {S_SLOR, zp}, 219 {S_PHP, impl}, {S_ORA, imm}, {S_ASL, accu}, {S_ANC, imm}, 220 {S_NOOP,abso}, {S_ORA, abso}, {S_ASL, abso}, {S_SLOR, abso}, 221 {S_BPL, rel}, {S_ORA, indy}, {S_STP, impl}, {S_SLOR,indy}, 222 {S_NOOP, zpx}, {S_ORA, zpx}, {S_ASL, zpx}, {S_SLOR, zpx}, 223 {S_CLC, impl}, {S_ORA, absy}, {S_NOOP,impl}, {S_SLOR,absy}, 224 {S_NOOP,absx}, {S_ORA, absx}, {S_ASL, absx}, {S_SLOR,absx}, 225 226 {S_JSR, abso}, {S_AND, indx}, {S_STP, impl}, {S_RLAN,indx}, 227 {S_BIT, zp}, {S_AND, zp}, {S_ROL, zp}, {S_RLAN, zp}, 228 {S_PLP, impl}, {S_AND, imm}, {S_ROL, accu}, {S_ANC, imm}, 229 {S_BIT, abso}, {S_AND, abso}, {S_ROL, abso}, {S_RLAN,abso}, 230 {S_BMI, rel}, {S_AND, indy}, {S_STP, impl}, {S_RLAN,indy}, 231 {S_NOOP, zpx}, {S_AND, zpx}, {S_ROL, zpx}, {S_RLAN, zpx}, 232 {S_SEC, impl}, {S_AND, absy}, {S_NOOP,impl}, {S_RLAN,absy}, 233 {S_NOOP,absx}, {S_AND, absx}, {S_ROL, absx}, {S_RLAN,absx}, 234 235 {S_RTI, impl}, {S_EOR, indx}, {S_STP, impl}, {S_SREO,indx}, 236 {S_NOOP, zp}, {S_EOR, zp}, {S_LSR, zp}, {S_SREO, zp}, 237 {S_PHA, impl}, {S_EOR, imm}, {S_LSR, accu}, {S_ASR, imm}, 238 {S_JMP, abso}, {S_EOR, abso}, {S_LSR, abso}, {S_SREO,abso}, 239 {S_BVC, rel}, {S_EOR, indy}, {S_STP, impl}, {S_SREO,indy}, 240 {S_NOOP, zpx}, {S_EOR, zpx}, {S_LSR, zpx}, {S_SREO, zpx}, 241 {S_CLI, impl}, {S_EOR, absy}, {S_NOOP,impl}, {S_SREO,absy}, 242 {S_NOOP,absx}, {S_EOR, absx}, {S_LSR, absx}, {S_SREO,absx}, 243 244 {S_RTS, impl}, {S_ADC, indx}, {S_STP, impl}, {S_RRAD,indx}, 245 {S_NOOP, zp}, {S_ADC, zp}, {S_ROR, zp}, {S_RRAD, zp}, 246 {S_PLA, impl}, {S_ADC, imm}, {S_ROR, accu}, {S_ARR, imm}, 247 {S_JMP, iabs}, {S_ADC, abso}, {S_ROR, abso}, {S_RRAD,abso}, 248 {S_BVS, rel}, {S_ADC, indy}, {S_STP, impl}, {S_RRAD,indy}, 249 {S_NOOP, zpx}, {S_ADC, zpx}, {S_ROR, zpx}, {S_RRAD, zpx}, 250 {S_SEI, impl}, {S_ADC, absy}, {S_NOOP,impl}, {S_RRAD,absy}, 251 {S_NOOP,absx}, {S_ADC, absx}, {S_ROR, absx}, {S_RRAD,absx}, 252 253 {S_NOOP, imm}, {S_STA, indx}, {S_NOOP, imm}, {S_STAX,indx}, 254 {S_STY, zp}, {S_STA, zp}, {S_STX, zp}, {S_STAX, zp}, 255 {S_DEY, impl}, {S_NOOP, imm}, {S_TXA, impl}, {S_ILLEGAL,0}, 256 {S_STY, abso}, {S_STA, abso}, {S_STX, abso}, {S_STAX,abso}, 257 {S_BCC, rel}, {S_STA, indy}, {S_STP, impl}, {S_ILLEGAL,0}, 258 {S_STY, zpx}, {S_STA, zpx}, {S_STX, zpy}, {S_STAX, zpy}, 259 {S_TYA, impl}, {S_STA, absy}, {S_TXS, impl}, {S_ILLEGAL,0}, 260 {S_ILLEGAL,0}, {S_STA, absx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 261 262 {S_LDY, imm}, {S_LDA, indx}, {S_LDX, imm}, {S_LDAX,indy}, 263 {S_LDY, zp}, {S_LDA, zp}, {S_LDX, zp}, {S_LDAX, zp}, 264 {S_TAY, impl}, {S_LDA, imm}, {S_TAX, impl}, {S_ILLEGAL,0}, 265 {S_LDY, abso}, {S_LDA, abso}, {S_LDX, abso}, {S_LDAX,abso}, 266 {S_BCS, rel}, {S_LDA, indy}, {S_STP, impl}, {S_LDAX,indy}, 267 {S_LDY, zpx}, {S_LDA, zpx}, {S_LDX, zpy}, {S_LDAX, zpy}, 268 {S_CLV, impl}, {S_LDA, absy}, {S_TSX, impl}, {S_ILLEGAL,0}, 269 {S_LDY, absx}, {S_LDA, absx}, {S_LDX, absy}, {S_LDAX,absy}, 270 271 {S_CPY, imm}, {S_CMP, indx}, {S_NOOP, imm}, {S_DCMP,indx}, 272 {S_CPY, zp}, {S_CMP, zp}, {S_DEC, zp}, {S_DCMP, zp}, 273 {S_INY, impl}, {S_CMP, imm}, {S_DEX, impl}, {S_SBX, imm}, 274 {S_CPY, abso}, {S_CMP, abso}, {S_DEC, abso}, {S_DCMP,abso}, 275 {S_BNE, rel}, {S_CMP, indy}, {S_STP, impl}, {S_DCMP,indy}, 276 {S_NOOP, zpx}, {S_CMP, zpx}, {S_DEC, zpx}, {S_DCMP, zpx}, 277 {S_CLD, impl}, {S_CMP, absy}, {S_NOOP,impl}, {S_DCMP,absy}, 278 {S_NOOP,absx}, {S_CMP, absx}, {S_DEC, absx}, {S_DCMP,absx}, 279 280 {S_CPX, imm}, {S_SBC, indx}, {S_NOOP, imm}, {S_ISBC,indx}, 281 {S_CPX, zp}, {S_SBC, zp}, {S_INC, zp}, {S_ISBC, zp}, 282 {S_INX, impl}, {S_SBC, imm}, {S_NOP, impl}, {S_USBC, imm}, 283 {S_CPX, abso}, {S_SBC, abso}, {S_INC, abso}, {S_ISBC,abso}, 284 {S_BEQ, rel}, {S_SBC, indy}, {S_STP, impl}, {S_ISBC,indy}, 285 {S_NOOP, zpx}, {S_SBC, zpx}, {S_INC, zpx}, {S_ISBC, zpx}, 286 {S_SED, impl}, {S_SBC, absy}, {S_NOOP,impl}, {S_ISBC,absy}, 287 {S_NOOP,absx}, {S_SBC, absx}, {S_INC, absx}, {S_ISBC,absx}, 288 }; 289 290 /*\ 291 * The following NMOS 6502 instructions are missing from the 292 * useful_nmos6502 map: 293 * 294 * ANE SHA SHS SHY SHX LXA LAXS NOOP STP 295 \*/ 296 297 opcodes useful_nmos6502[] = 298 { 299 {S_BRK, impl}, {S_ORA, indx}, {S_ILLEGAL,0}, {S_SLOR,indx}, 300 {S_ILLEGAL,0}, {S_ORA, zp}, {S_ASL, zp}, {S_SLOR, zp}, 301 {S_PHP, impl}, {S_ORA, imm}, {S_ASL, accu}, {S_ANC, imm}, 302 {S_ILLEGAL,0}, {S_ORA, abso}, {S_ASL, abso}, {S_SLOR,abso}, 303 {S_BPL, rel}, {S_ORA, indy}, {S_ILLEGAL,0}, {S_SLOR,indy}, 304 {S_ILLEGAL,0}, {S_ORA, zpx}, {S_ASL, zpx}, {S_SLOR, zpx}, 305 {S_CLC, impl}, {S_ORA, absy}, {S_ILLEGAL,0}, {S_SLOR,absy}, 306 {S_ILLEGAL,0}, {S_ORA, absx}, {S_ASL, absx}, {S_SLOR,absx}, 307 308 {S_JSR, abso}, {S_AND, indx}, {S_ILLEGAL,0}, {S_RLAN,indx}, 309 {S_BIT, zp}, {S_AND, zp}, {S_ROL, zp}, {S_RLAN, zp}, 310 {S_PLP, impl}, {S_AND, imm}, {S_ROL, accu}, {S_ANC, imm}, 311 {S_BIT, abso}, {S_AND, abso}, {S_ROL, abso}, {S_RLAN,abso}, 312 {S_BMI, rel}, {S_AND, indy}, {S_ILLEGAL,0}, {S_RLAN,indy}, 313 {S_ILLEGAL,0}, {S_AND, zpx}, {S_ROL, zpx}, {S_RLAN, zpx}, 314 {S_SEC, impl}, {S_AND, absy}, {S_ILLEGAL,0}, {S_RLAN,absy}, 315 {S_ILLEGAL,0}, {S_AND, absx}, {S_ROL, absx}, {S_RLAN,absx}, 316 317 {S_RTI, impl}, {S_EOR, indx}, {S_ILLEGAL,0}, {S_SREO,indx}, 318 {S_ILLEGAL,0}, {S_EOR, zp}, {S_LSR, zp}, {S_SREO, zp}, 319 {S_PHA, impl}, {S_EOR, imm}, {S_LSR, accu}, {S_ASR, imm}, 320 {S_JMP, abso}, {S_EOR, abso}, {S_LSR, abso}, {S_SREO,abso}, 321 {S_BVC, rel}, {S_EOR, indy}, {S_ILLEGAL,0}, {S_SREO,indy}, 322 {S_ILLEGAL,0}, {S_EOR, zpx}, {S_LSR, zpx}, {S_SREO, zpx}, 323 {S_CLI, impl}, {S_EOR, absy}, {S_ILLEGAL,0}, {S_SREO,absy}, 324 {S_ILLEGAL,0}, {S_EOR, absx}, {S_LSR, absx}, {S_SREO,absx}, 325 326 {S_RTS, impl}, {S_ADC, indx}, {S_ILLEGAL,0}, {S_RRAD,indx}, 327 {S_ILLEGAL,0}, {S_ADC, zp}, {S_ROR, zp}, {S_RRAD, zp}, 328 {S_PLA, impl}, {S_ADC, imm}, {S_ROR, accu}, {S_ARR, imm}, 329 {S_JMP, iabs}, {S_ADC, abso}, {S_ROR, abso}, {S_RRAD,abso}, 330 {S_BVS, rel}, {S_ADC, indy}, {S_ILLEGAL,0}, {S_RRAD,indy}, 331 {S_ILLEGAL,0}, {S_ADC, zpx}, {S_ROR, zpx}, {S_RRAD, zpx}, 332 {S_SEI, impl}, {S_ADC, absy}, {S_ILLEGAL,0}, {S_RRAD,absy}, 333 {S_ILLEGAL,0}, {S_ADC, absx}, {S_ROR, absx}, {S_RRAD,absx}, 334 335 {S_ILLEGAL,0}, {S_STA, indx}, {S_ILLEGAL,0}, {S_STAX,indx}, 336 {S_STY, zp}, {S_STA, zp}, {S_STX, zp}, {S_STAX, zp}, 337 {S_DEY, impl}, {S_ILLEGAL,0}, {S_TXA, impl}, {S_ILLEGAL,0}, 338 {S_STY, abso}, {S_STA, abso}, {S_STX, abso}, {S_STAX,abso}, 339 {S_BCC, rel}, {S_STA, indy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 340 {S_STY, zpx}, {S_STA, zpx}, {S_STX, zpy}, {S_STAX, zpy}, 341 {S_TYA, impl}, {S_STA, absy}, {S_TXS, impl}, {S_ILLEGAL,0}, 342 {S_ILLEGAL,0}, {S_STA, absx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 343 344 {S_LDY, imm}, {S_LDA, indx}, {S_LDX, imm}, {S_LDAX,indy}, 345 {S_LDY, zp}, {S_LDA, zp}, {S_LDX, zp}, {S_LDAX, zp}, 346 {S_TAY, impl}, {S_LDA, imm}, {S_TAX, impl}, {S_ILLEGAL,0}, 347 {S_LDY, abso}, {S_LDA, abso}, {S_LDX, abso}, {S_LDAX,abso}, 348 {S_BCS, rel}, {S_LDA, indy}, {S_ILLEGAL,0}, {S_LDAX,indy}, 349 {S_LDY, zpx}, {S_LDA, zpx}, {S_LDX, zpy}, {S_LDAX, zpy}, 350 {S_CLV, impl}, {S_LDA, absy}, {S_TSX, impl}, {S_ILLEGAL,0}, 351 {S_LDY, absx}, {S_LDA, absx}, {S_LDX, absy}, {S_LDAX,absy}, 352 353 {S_CPY, imm}, {S_CMP, indx}, {S_ILLEGAL,0}, {S_DCMP,indx}, 354 {S_CPY, zp}, {S_CMP, zp}, {S_DEC, zp}, {S_DCMP, zp}, 355 {S_INY, impl}, {S_CMP, imm}, {S_DEX, impl}, {S_SBX, imm}, 356 {S_CPY, abso}, {S_CMP, abso}, {S_DEC, abso}, {S_DCMP,abso}, 357 {S_BNE, rel}, {S_CMP, indy}, {S_ILLEGAL,0}, {S_DCMP,indy}, 358 {S_ILLEGAL,0}, {S_CMP, zpx}, {S_DEC, zpx}, {S_DCMP, zpx}, 359 {S_CLD, impl}, {S_CMP, absy}, {S_ILLEGAL,0}, {S_DCMP,absy}, 360 {S_ILLEGAL,0}, {S_CMP, absx}, {S_DEC, absx}, {S_DCMP,absx}, 361 362 {S_CPX, imm}, {S_SBC, indx}, {S_ILLEGAL,0}, {S_ISBC,indx}, 363 {S_CPX, zp}, {S_SBC, zp}, {S_INC, zp}, {S_ISBC, zp}, 364 {S_INX, impl}, {S_SBC, imm}, {S_NOP, impl}, {S_USBC, imm}, 365 {S_CPX, abso}, {S_SBC, abso}, {S_INC, abso}, {S_ISBC,abso}, 366 {S_BEQ, rel}, {S_SBC, indy}, {S_ILLEGAL,0}, {S_ISBC,indy}, 367 {S_ILLEGAL,0}, {S_SBC, zpx}, {S_INC, zpx}, {S_ISBC, zpx}, 368 {S_SED, impl}, {S_SBC, absy}, {S_ILLEGAL,0}, {S_ISBC,absy}, 369 {S_ILLEGAL,0}, {S_SBC, absx}, {S_INC, absx}, {S_ISBC,absx}, 370 }; 371 372 /*\ 373 * The following NMOS 6502 instructions are missing from the 374 * traditional_nmos6502 map: 375 * 376 * ANE SHA SHS SHY SHX LXA LAXS NOOP STP 377 * ARR ASR ANC SBX USBC 378 \*/ 379 380 opcodes traditional_nmos6502[] = 381 { 382 {S_BRK, impl}, {S_ORA, indx}, {S_ILLEGAL,0}, {S_SLOR,indx}, 383 {S_ILLEGAL,0}, {S_ORA, zp}, {S_ASL, zp}, {S_SLOR, zp}, 384 {S_PHP, impl}, {S_ORA, imm}, {S_ASL, accu}, {S_ILLEGAL,0}, 385 {S_ILLEGAL,0}, {S_ORA, abso}, {S_ASL, abso}, {S_SLOR,abso}, 386 {S_BPL, rel}, {S_ORA, indy}, {S_ILLEGAL,0}, {S_SLOR,indy}, 387 {S_ILLEGAL,0}, {S_ORA, zpx}, {S_ASL, zpx}, {S_SLOR, zpx}, 388 {S_CLC, impl}, {S_ORA, absy}, {S_ILLEGAL,0}, {S_SLOR,absy}, 389 {S_ILLEGAL,0}, {S_ORA, absx}, {S_ASL, absx}, {S_SLOR,absx}, 390 391 {S_JSR, abso}, {S_AND, indx}, {S_ILLEGAL,0}, {S_RLAN,indx}, 392 {S_BIT, zp}, {S_AND, zp}, {S_ROL, zp}, {S_RLAN, zp}, 393 {S_PLP, impl}, {S_AND, imm}, {S_ROL, accu}, {S_ILLEGAL,0}, 394 {S_BIT, abso}, {S_AND, abso}, {S_ROL, abso}, {S_RLAN,abso}, 395 {S_BMI, rel}, {S_AND, indy}, {S_ILLEGAL,0}, {S_RLAN,indy}, 396 {S_ILLEGAL,0}, {S_AND, zpx}, {S_ROL, zpx}, {S_RLAN, zpx}, 397 {S_SEC, impl}, {S_AND, absy}, {S_ILLEGAL,0}, {S_RLAN,absy}, 398 {S_ILLEGAL,0}, {S_AND, absx}, {S_ROL, absx}, {S_RLAN,absx}, 399 400 {S_RTI, impl}, {S_EOR, indx}, {S_ILLEGAL,0}, {S_SREO,indx}, 401 {S_ILLEGAL,0}, {S_EOR, zp}, {S_LSR, zp}, {S_SREO, zp}, 402 {S_PHA, impl}, {S_EOR, imm}, {S_LSR, accu}, {S_ILLEGAL,0}, 403 {S_JMP, abso}, {S_EOR, abso}, {S_LSR, abso}, {S_SREO,abso}, 404 {S_BVC, rel}, {S_EOR, indy}, {S_ILLEGAL,0}, {S_SREO,indy}, 405 {S_ILLEGAL,0}, {S_EOR, zpx}, {S_LSR, zpx}, {S_SREO, zpx}, 406 {S_CLI, impl}, {S_EOR, absy}, {S_ILLEGAL,0}, {S_SREO,absy}, 407 {S_ILLEGAL,0}, {S_EOR, absx}, {S_LSR, absx}, {S_SREO,absx}, 408 409 {S_RTS, impl}, {S_ADC, indx}, {S_ILLEGAL,0}, {S_RRAD,indx}, 410 {S_ILLEGAL,0}, {S_ADC, zp}, {S_ROR, zp}, {S_RRAD, zp}, 411 {S_PLA, impl}, {S_ADC, imm}, {S_ROR, accu}, {S_ILLEGAL,0}, 412 {S_JMP, iabs}, {S_ADC, abso}, {S_ROR, abso}, {S_RRAD,abso}, 413 {S_BVS, rel}, {S_ADC, indy}, {S_ILLEGAL,0}, {S_RRAD,indy}, 414 {S_ILLEGAL,0}, {S_ADC, zpx}, {S_ROR, zpx}, {S_RRAD, zpx}, 415 {S_SEI, impl}, {S_ADC, absy}, {S_ILLEGAL,0}, {S_RRAD,absy}, 416 {S_ILLEGAL,0}, {S_ADC, absx}, {S_ROR, absx}, {S_RRAD,absx}, 417 418 {S_ILLEGAL,0}, {S_STA, indx}, {S_ILLEGAL,0}, {S_STAX,indx}, 419 {S_STY, zp}, {S_STA, zp}, {S_STX, zp}, {S_STAX, zp}, 420 {S_DEY, impl}, {S_ILLEGAL,0}, {S_TXA, impl}, {S_ILLEGAL,0}, 421 {S_STY, abso}, {S_STA, abso}, {S_STX, abso}, {S_STAX,abso}, 422 {S_BCC, rel}, {S_STA, indy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 423 {S_STY, zpx}, {S_STA, zpx}, {S_STX, zpy}, {S_STAX, zpy}, 424 {S_TYA, impl}, {S_STA, absy}, {S_TXS, impl}, {S_ILLEGAL,0}, 425 {S_ILLEGAL,0}, {S_STA, absx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 426 427 {S_LDY, imm}, {S_LDA, indx}, {S_LDX, imm}, {S_LDAX,indy}, 428 {S_LDY, zp}, {S_LDA, zp}, {S_LDX, zp}, {S_LDAX, zp}, 429 {S_TAY, impl}, {S_LDA, imm}, {S_TAX, impl}, {S_ILLEGAL,0}, 430 {S_LDY, abso}, {S_LDA, abso}, {S_LDX, abso}, {S_LDAX,abso}, 431 {S_BCS, rel}, {S_LDA, indy}, {S_ILLEGAL,0}, {S_LDAX,indy}, 432 {S_LDY, zpx}, {S_LDA, zpx}, {S_LDX, zpy}, {S_LDAX, zpy}, 433 {S_CLV, impl}, {S_LDA, absy}, {S_TSX, impl}, {S_ILLEGAL,0}, 434 {S_LDY, absx}, {S_LDA, absx}, {S_LDX, absy}, {S_LDAX,absy}, 435 436 {S_CPY, imm}, {S_CMP, indx}, {S_ILLEGAL,0}, {S_DCMP,indx}, 437 {S_CPY, zp}, {S_CMP, zp}, {S_DEC, zp}, {S_DCMP, zp}, 438 {S_INY, impl}, {S_CMP, imm}, {S_DEX, impl}, {S_ILLEGAL,0}, 439 {S_CPY, abso}, {S_CMP, abso}, {S_DEC, abso}, {S_DCMP,abso}, 440 {S_BNE, rel}, {S_CMP, indy}, {S_ILLEGAL,0}, {S_DCMP,indy}, 441 {S_ILLEGAL,0}, {S_CMP, zpx}, {S_DEC, zpx}, {S_DCMP, zpx}, 442 {S_CLD, impl}, {S_CMP, absy}, {S_ILLEGAL,0}, {S_DCMP,absy}, 443 {S_ILLEGAL,0}, {S_CMP, absx}, {S_DEC, absx}, {S_DCMP,absx}, 444 445 {S_CPX, imm}, {S_SBC, indx}, {S_ILLEGAL,0}, {S_ISBC,indx}, 446 {S_CPX, zp}, {S_SBC, zp}, {S_INC, zp}, {S_ISBC, zp}, 447 {S_INX, impl}, {S_SBC, imm}, {S_NOP, impl}, {S_ILLEGAL,0}, 448 {S_CPX, abso}, {S_SBC, abso}, {S_INC, abso}, {S_ISBC,abso}, 449 {S_BEQ, rel}, {S_SBC, indy}, {S_ILLEGAL,0}, {S_ISBC,indy}, 450 {S_ILLEGAL,0}, {S_SBC, zpx}, {S_INC, zpx}, {S_ISBC, zpx}, 451 {S_SED, impl}, {S_SBC, absy}, {S_ILLEGAL,0}, {S_ISBC,absy}, 452 {S_ILLEGAL,0}, {S_SBC, absx}, {S_INC, absx}, {S_ISBC,absx}, 453 }; 454 455 /*\ 456 * The following is the officially documented 457 * MOS 6502 instruction set. 458 \*/ 459 460 opcodes standard_nmos6502[] = 461 { 462 {S_BRK, impl}, {S_ORA, indx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 463 {S_ILLEGAL,0}, {S_ORA, zp}, {S_ASL, zp}, {S_ILLEGAL,0}, 464 {S_PHP, impl}, {S_ORA, imm}, {S_ASL, accu}, {S_ILLEGAL,0}, 465 {S_ILLEGAL,0}, {S_ORA, abso}, {S_ASL, abso}, {S_ILLEGAL,0}, 466 {S_BPL, rel}, {S_ORA, indy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 467 {S_ILLEGAL,0}, {S_ORA, zpx}, {S_ASL, zpx}, {S_ILLEGAL,0}, 468 {S_CLC, impl}, {S_ORA, absy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 469 {S_ILLEGAL,0}, {S_ORA, absx}, {S_ASL, absx}, {S_ILLEGAL,0}, 470 471 {S_JSR, abso}, {S_AND, indx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 472 {S_BIT, zp}, {S_AND, zp}, {S_ROL, zp}, {S_ILLEGAL,0}, 473 {S_PLP, impl}, {S_AND, imm}, {S_ROL, accu}, {S_ILLEGAL,0}, 474 {S_BIT, abso}, {S_AND, abso}, {S_ROL, abso}, {S_ILLEGAL,0}, 475 {S_BMI, rel}, {S_AND, indy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 476 {S_ILLEGAL,0}, {S_AND, zpx}, {S_ROL, zpx}, {S_ILLEGAL,0}, 477 {S_SEC, impl}, {S_AND, absy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 478 {S_ILLEGAL,0}, {S_AND, absx}, {S_ROL, absx}, {S_ILLEGAL,0}, 479 480 {S_RTI, impl}, {S_EOR, indx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 481 {S_ILLEGAL,0}, {S_EOR, zp}, {S_LSR, zp}, {S_ILLEGAL,0}, 482 {S_PHA, impl}, {S_EOR, imm}, {S_LSR, accu}, {S_ILLEGAL,0}, 483 {S_JMP, abso}, {S_EOR, abso}, {S_LSR, abso}, {S_ILLEGAL,0}, 484 {S_BVC, rel}, {S_EOR, indy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 485 {S_ILLEGAL,0}, {S_EOR, zpx}, {S_LSR, zpx}, {S_ILLEGAL,0}, 486 {S_CLI, impl}, {S_EOR, absy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 487 {S_ILLEGAL,0}, {S_EOR, absx}, {S_LSR, absx}, {S_ILLEGAL,0}, 488 489 {S_RTS, impl}, {S_ADC, indx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 490 {S_ILLEGAL,0}, {S_ADC, zp}, {S_ROR, zp}, {S_ILLEGAL,0}, 491 {S_PLA, impl}, {S_ADC, imm}, {S_ROR, accu}, {S_ILLEGAL,0}, 492 {S_JMP, iabs}, {S_ADC, abso}, {S_ROR, abso}, {S_ILLEGAL,0}, 493 {S_BVS, rel}, {S_ADC, indy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 494 {S_ILLEGAL,0}, {S_ADC, zpx}, {S_ROR, zpx}, {S_ILLEGAL,0}, 495 {S_SEI, impl}, {S_ADC, absy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 496 {S_ILLEGAL,0}, {S_ADC, absx}, {S_ROR, absx}, {S_ILLEGAL,0}, 497 498 {S_ILLEGAL,0}, {S_STA, indx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 499 {S_STY, zp}, {S_STA, zp}, {S_STX, zp}, {S_ILLEGAL,0}, 500 {S_DEY, impl}, {S_ILLEGAL,0}, {S_TXA, impl}, {S_ILLEGAL,0}, 501 {S_STY, abso}, {S_STA, abso}, {S_STX, abso}, {S_ILLEGAL,0}, 502 {S_BCC, rel}, {S_STA, indy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 503 {S_STY, zpx}, {S_STA, zpx}, {S_STX, zpy}, {S_ILLEGAL,0}, 504 {S_TYA, impl}, {S_STA, absy}, {S_TXS, impl}, {S_ILLEGAL,0}, 505 {S_ILLEGAL,0}, {S_STA, absx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 506 507 {S_LDY, imm}, {S_LDA, indx}, {S_LDX, imm}, {S_ILLEGAL,0}, 508 {S_LDY, zp}, {S_LDA, zp}, {S_LDX, zp}, {S_ILLEGAL,0}, 509 {S_TAY, impl}, {S_LDA, imm}, {S_TAX, impl}, {S_ILLEGAL,0}, 510 {S_LDY, abso}, {S_LDA, abso}, {S_LDX, abso}, {S_ILLEGAL,0}, 511 {S_BCS, rel}, {S_LDA, indy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 512 {S_LDY, zpx}, {S_LDA, zpx}, {S_LDX, zpy}, {S_ILLEGAL,0}, 513 {S_CLV, impl}, {S_LDA, absy}, {S_TSX, impl}, {S_ILLEGAL,0}, 514 {S_LDY, absx}, {S_LDA, absx}, {S_LDX, absy}, {S_ILLEGAL,0}, 515 516 {S_CPY, imm}, {S_CMP, indx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 517 {S_CPY, zp}, {S_CMP, zp}, {S_DEC, zp}, {S_ILLEGAL,0}, 518 {S_INY, impl}, {S_CMP, imm}, {S_DEX, impl}, {S_ILLEGAL,0}, 519 {S_CPY, abso}, {S_CMP, abso}, {S_DEC, abso}, {S_ILLEGAL,0}, 520 {S_BNE, rel}, {S_CMP, indy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 521 {S_ILLEGAL,0}, {S_CMP, zpx}, {S_DEC, zpx}, {S_ILLEGAL,0}, 522 {S_CLD, impl}, {S_CMP, absy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 523 {S_ILLEGAL,0}, {S_CMP, absx}, {S_DEC, absx}, {S_ILLEGAL,0}, 524 525 {S_CPX, imm}, {S_SBC, indx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 526 {S_CPX, zp}, {S_SBC, zp}, {S_INC, zp}, {S_ILLEGAL,0}, 527 {S_INX, impl}, {S_SBC, imm}, {S_NOP, impl}, {S_ILLEGAL,0}, 528 {S_CPX, abso}, {S_SBC, abso}, {S_INC, abso}, {S_ILLEGAL,0}, 529 {S_BEQ, rel}, {S_SBC, indy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 530 {S_ILLEGAL,0}, {S_SBC, zpx}, {S_INC, zpx}, {S_ILLEGAL,0}, 531 {S_SED, impl}, {S_SBC, absy}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 532 {S_ILLEGAL,0}, {S_SBC, absx}, {S_INC, absx}, {S_ILLEGAL,0}, 533 }; 534 535 536 /*\ 537 * The following is the officially documented 538 * Rockwell R65C02 instruction set. 539 \*/ 540 541 opcodes r65c02[] = 542 { 543 {S_BRK, impl}, {S_ORA, indx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 544 {S_TSB, zp}, {S_ORA, zp}, {S_ASL, zp}, {S_RMB0, zp}, 545 {S_PHP, impl}, {S_ORA, imm}, {S_ASL, accu}, {S_ILLEGAL,0}, 546 {S_TSB, abso}, {S_ORA, abso}, {S_ASL, abso}, {S_BBR0,zrel}, 547 {S_BPL, rel}, {S_ORA, indy}, {S_ORA, ind}, {S_ILLEGAL,0}, 548 {S_TRB, zp}, {S_ORA, zpx}, {S_ASL, zpx}, {S_RMB1, zp}, 549 {S_CLC, impl}, {S_ORA, absy}, {S_INC, accu}, {S_ILLEGAL,0}, 550 {S_TRB, abso}, {S_ORA, absx}, {S_ASL, absx}, {S_BBR1,zrel}, 551 552 {S_JSR, abso}, {S_AND, indx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 553 {S_BIT, zp}, {S_AND, zp}, {S_ROL, zp}, {S_RMB2, zp}, 554 {S_PLP, impl}, {S_AND, imm}, {S_ROL, accu}, {S_ILLEGAL,0}, 555 {S_BIT, abso}, {S_AND, abso}, {S_ROL, abso}, {S_BBR2,zrel}, 556 {S_BMI, rel}, {S_AND, indy}, {S_AND, ind}, {S_ILLEGAL,0}, 557 {S_BIT, zpx}, {S_AND, zpx}, {S_ROL, zpx}, {S_RMB3, zp}, 558 {S_SEC, impl}, {S_AND, absy}, {S_DEC, accu}, {S_ILLEGAL,0}, 559 {S_BIT, absx}, {S_AND, absx}, {S_ROL, absx}, {S_BBR3,zrel}, 560 561 {S_RTI, impl}, {S_EOR, indx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 562 {S_ILLEGAL,0}, {S_EOR, zp}, {S_LSR, zp}, {S_RMB4, zp}, 563 {S_PHA, impl}, {S_EOR, imm}, {S_LSR, accu}, {S_ILLEGAL,0}, 564 {S_JMP, abso}, {S_EOR, abso}, {S_LSR, abso}, {S_BBR4,zrel}, 565 {S_BVC, rel}, {S_EOR, indy}, {S_EOR, ind}, {S_ILLEGAL,0}, 566 {S_ILLEGAL,0}, {S_EOR, zpx}, {S_LSR, zpx}, {S_RMB5, zp}, 567 {S_CLI, impl}, {S_EOR, absy}, {S_PHY, impl}, {S_ILLEGAL,0}, 568 {S_ILLEGAL,0}, {S_EOR, absx}, {S_LSR, absx}, {S_BBR5,zrel}, 569 570 {S_RTS, impl}, {S_ADC, indx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 571 {S_STZ, zp}, {S_ADC, zp}, {S_ROR, zp}, {S_RMB6, zp}, 572 {S_PLA, impl}, {S_ADC, imm}, {S_ROR, accu}, {S_ILLEGAL,0}, 573 {S_JMP, iabs}, {S_ADC, abso}, {S_ROR, abso}, {S_BBR6,zrel}, 574 {S_BVS, rel}, {S_ADC, indy}, {S_ADC, ind}, {S_ILLEGAL,0}, 575 {S_STZ, zpx}, {S_ADC, zpx}, {S_ROR, zpx}, {S_RMB7, zp}, 576 {S_SEI, impl}, {S_ADC, absy}, {S_PLY, impl}, {S_ILLEGAL,0}, 577 {S_JMP,iabsx}, {S_ADC, absx}, {S_ROR, absx}, {S_BBR7,zrel}, 578 579 {S_BRA, rel}, {S_STA, indx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 580 {S_STY, zp}, {S_STA, zp}, {S_STX, zp}, {S_SMB0, zp}, 581 {S_DEY, impl}, {S_BIT, imm}, {S_TXA, impl}, {S_ILLEGAL,0}, 582 {S_STY, abso}, {S_STA, abso}, {S_STX, abso}, {S_BBS0,zrel}, 583 {S_BCC, rel}, {S_STA, indy}, {S_STA, ind}, {S_ILLEGAL,0}, 584 {S_STY, zpx}, {S_STA, zpx}, {S_STX, zpy}, {S_SMB1, zp}, 585 {S_TYA, impl}, {S_STA, absy}, {S_TXS, impl}, {S_ILLEGAL,0}, 586 {S_STZ, abso}, {S_STA, absx}, {S_STZ, absx}, {S_BBS1,zrel}, 587 588 {S_LDY, imm}, {S_LDA, indx}, {S_LDX, imm}, {S_ILLEGAL,0}, 589 {S_LDY, zp}, {S_LDA, zp}, {S_LDX, zp}, {S_SMB2, zp}, 590 {S_TAY, impl}, {S_LDA, imm}, {S_TAX, impl}, {S_ILLEGAL,0}, 591 {S_LDY, abso}, {S_LDA, abso}, {S_LDX, abso}, {S_BBS2,zrel}, 592 {S_BCS, rel}, {S_LDA, indy}, {S_LDA, ind}, {S_ILLEGAL,0}, 593 {S_LDY, zpx}, {S_LDA, zpx}, {S_LDX, zpy}, {S_SMB3, zp}, 594 {S_CLV, impl}, {S_LDA, absy}, {S_TSX, impl}, {S_ILLEGAL,0}, 595 {S_LDY, absx}, {S_LDA, absx}, {S_LDX, absy}, {S_BBS3,zrel}, 596 597 {S_CPY, imm}, {S_CMP, indx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 598 {S_CPY, zp}, {S_CMP, zp}, {S_DEC, zp}, {S_SMB4, zp}, 599 {S_INY, impl}, {S_CMP, imm}, {S_DEX, impl}, {S_ILLEGAL,0}, 600 {S_CPY, abso}, {S_CMP, abso}, {S_DEC, abso}, {S_BBS4,zrel}, 601 {S_BNE, rel}, {S_CMP, indy}, {S_CMP, ind}, {S_ILLEGAL,0}, 602 {S_ILLEGAL,0}, {S_CMP, zpx}, {S_DEC, zpx}, {S_SMB5, zp}, 603 {S_CLD, impl}, {S_CMP, absy}, {S_PHX, impl}, {S_ILLEGAL,0}, 604 {S_ILLEGAL,0}, {S_CMP, absx}, {S_DEC, absx}, {S_BBS5,zrel}, 605 606 {S_CPX, imm}, {S_SBC, indx}, {S_ILLEGAL,0}, {S_ILLEGAL,0}, 607 {S_CPX, zp}, {S_SBC, zp}, {S_INC, zp}, {S_SMB6, zp}, 608 {S_INX, impl}, {S_SBC, imm}, {S_NOP, impl}, {S_ILLEGAL,0}, 609 {S_CPX, abso}, {S_SBC, abso}, {S_INC, abso}, {S_BBS6,zrel}, 610 {S_BEQ, rel}, {S_SBC, indy}, {S_SBC, ind}, {S_ILLEGAL,0}, 611 {S_ILLEGAL,0}, {S_SBC, zpx}, {S_INC, zpx}, {S_SMB7, zp}, 612 {S_SED, impl}, {S_SBC, absy}, {S_PLX, impl}, {S_ILLEGAL,0}, 613 {S_ILLEGAL,0}, {S_SBC, absx}, {S_INC, absx}, {S_BBS7,zrel}, 614 }; 615 #endif /* _MAIN_C_ */ 616 617 #endif /* _OPCODES_H_ */ 618