12013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 2 3 * arm.h (CRC_EXT_ARMV8): New constant. 4 (ARCH_CRC_ARMV8): New macro. 5 62013-02-28 Yufeng Zhang <yufeng.zhang@arm.com> 7 8 * aarch64.h (AARCH64_FEATURE_CRC): New macro. 9 102013-02-06 Sandra Loosemore <sandra@codesourcery.com> 11 Andrew Jenner <andrew@codesourcery.com> 12 13 Based on patches from Altera Corporation. 14 15 * nios2.h: New file. 16 172013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> 18 19 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2. 20 212013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com> 22 23 PR gas/15069 24 * tic6x-opcode-table.h: Fix encoding of BNOP instruction. 25 262013-01-24 Nick Clifton <nickc@redhat.com> 27 28 * v850.h: Add e3v5 support. 29 302013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> 31 32 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B. 33 342013-01-10 Peter Bergner <bergner@vnet.ibm.com> 35 36 * ppc.h (PPC_OPCODE_POWER8): New define. 37 (PPC_OPCODE_HTM): Likewise. 38 392013-01-10 Will Newton <will.newton@imgtec.com> 40 41 * metag.h: New file. 42 432013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com> 44 45 * cr16.h (make_instruction): Rename to cr16_make_instruction. 46 (match_opcode): Rename to cr16_match_opcode. 47 482013-01-04 Juergen Urban <JuergenUrban@gmx.de> 49 50 * mips.h: Add support for r5900 instructions including lq and sq. 51 522013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com> 53 54 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c 55 (make_instruction,match_opcode): Added function prototypes. 56 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern. 57 582012-11-23 Alan Modra <amodra@gmail.com> 59 60 * ppc.h (ppc_parse_cpu): Update prototype. 61 622012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 63 64 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx 65 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes. 66 672012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 68 69 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12. 70 712012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> 72 73 * ia64.h (ia64_opnd): Add new operand types. 74 752012-08-21 David S. Miller <davem@davemloft.net> 76 77 * sparc.h (F3F4): New macro. 78 792012-08-13 Ian Bolton <ian.bolton@arm.com> 80 Laurent Desnogues <laurent.desnogues@arm.com> 81 Jim MacArthur <jim.macarthur@arm.com> 82 Marcus Shawcroft <marcus.shawcroft@arm.com> 83 Nigel Stephens <nigel.stephens@arm.com> 84 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> 85 Richard Earnshaw <rearnsha@arm.com> 86 Sofiane Naci <sofiane.naci@arm.com> 87 Tejas Belagod <tejas.belagod@arm.com> 88 Yufeng Zhang <yufeng.zhang@arm.com> 89 90 * aarch64.h: New file. 91 922012-08-13 Richard Sandiford <rdsandiford@googlemail.com> 93 Maciej W. Rozycki <macro@codesourcery.com> 94 95 * mips.h (mips_opcode): Add the exclusions field. 96 (OPCODE_IS_MEMBER): Remove macro. 97 (cpu_is_member): New inline function. 98 (opcode_is_member): Likewise. 99 1002012-07-31 Chao-Ying Fu <fu@mips.com> 101 Catherine Moore <clm@codesourcery.com> 102 Maciej W. Rozycki <macro@codesourcery.com> 103 104 * mips.h: Document microMIPS DSP ASE usage. 105 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for 106 microMIPS DSP ASE support. 107 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. 108 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. 109 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. 110 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. 111 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. 112 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. 113 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. 114 1152012-07-06 Maciej W. Rozycki <macro@codesourcery.com> 116 117 * mips.h: Fix a typo in description. 118 1192012-06-07 Georg-Johann Lay <avr@gjlay.de> 120 121 * avr.h: (AVR_ISA_XCH): New define. 122 (AVR_ISA_XMEGA): Use it. 123 (XCH, LAS, LAT, LAC): New XMEGA opcodes. 124 1252012-05-15 James Murray <jsm@jsm-net.demon.co.uk> 126 127 * m68hc11.h: Add XGate definitions. 128 (struct m68hc11_opcode): Add xg_mask field. 129 1302012-05-14 Catherine Moore <clm@codesourcery.com> 131 Maciej W. Rozycki <macro@codesourcery.com> 132 Rhonda Wittels <rhonda@codesourcery.com> 133 134 * ppc.h (PPC_OPCODE_VLE): New definition. 135 (PPC_OP_SA): New macro. 136 (PPC_OP_SE_VLE): New macro. 137 (PPC_OP): Use a variable shift amount. 138 (powerpc_operand): Update comments. 139 (PPC_OPSHIFT_INV): New macro. 140 (PPC_OPERAND_CR): Replace with... 141 (PPC_OPERAND_CR_BIT): ...this and 142 (PPC_OPERAND_CR_REG): ...this. 143 144 1452012-05-03 Sean Keys <skeys@ipdatasys.com> 146 147 * xgate.h: Header file for XGATE assembler. 148 1492012-04-27 David S. Miller <davem@davemloft.net> 150 151 * sparc.h: Document new arg code' )' for crypto RS3 152 immediates. 153 154 * sparc.h (struct sparc_opcode): New field 'hwcaps'. 155 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, 156 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, 157 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete. 158 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC, 159 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF, 160 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU, 161 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES, 162 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1, 163 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE, 164 HWCAP_CBCOND, HWCAP_CRC32): New defines. 165 1662012-03-10 Edmar Wienskoski <edmar@freescale.com> 167 168 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR. 169 1702012-02-27 Alan Modra <amodra@gmail.com> 171 172 * crx.h (cst4_map): Update declaration. 173 1742012-02-25 Walter Lee <walt@tilera.com> 175 176 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS, 177 TILEGX_OPC_LD_TLS. 178 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS, 179 TILEPRO_OPC_LW_TLS_SN. 180 1812012-02-08 H.J. Lu <hongjiu.lu@intel.com> 182 183 * i386.h (XACQUIRE_PREFIX_OPCODE): New. 184 (XRELEASE_PREFIX_OPCODE): Likewise. 185 1862011-12-08 Andrew Pinski <apinski@cavium.com> 187 Adam Nemet <anemet@caviumnetworks.com> 188 189 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2. 190 (INSN_OCTEON2): New macro. 191 (CPU_OCTEON2): New macro. 192 (OPCODE_IS_MEMBER): Add Octeon2. 193 1942011-11-29 Andrew Pinski <apinski@cavium.com> 195 196 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP. 197 (INSN_OCTEONP): New macro. 198 (CPU_OCTEONP): New macro. 199 (OPCODE_IS_MEMBER): Add Octeon+. 200 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values. 201 2022011-11-01 DJ Delorie <dj@redhat.com> 203 204 * rl78.h: New file. 205 2062011-10-24 Maciej W. Rozycki <macro@codesourcery.com> 207 208 * mips.h: Fix a typo in description. 209 2102011-09-21 David S. Miller <davem@davemloft.net> 211 212 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int. 213 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, 214 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, 215 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits. 216 2172011-08-09 Chao-ying Fu <fu@mips.com> 218 Maciej W. Rozycki <macro@codesourcery.com> 219 220 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. 221 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. 222 (INSN_ASE_MASK): Add the MCU bit. 223 (INSN_MCU): New macro. 224 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values. 225 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros. 226 2272011-08-09 Maciej W. Rozycki <macro@codesourcery.com> 228 229 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros. 230 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise. 231 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise. 232 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise. 233 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise. 234 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise. 235 (INSN2_READ_GPR_MMN): Likewise. 236 (INSN2_READ_FPR_D): Change the bit used. 237 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise. 238 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise. 239 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise. 240 (INSN2_COND_BRANCH): Likewise. 241 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros. 242 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise. 243 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise. 244 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise. 245 (INSN2_MOD_GPR_MN): Likewise. 246 2472011-08-05 David S. Miller <davem@davemloft.net> 248 249 * sparc.h: Document new format codes '4', '5', and '('. 250 (OPF_LOW4, RS3): New macros. 251 2522011-08-03 Maciej W. Rozycki <macro@codesourcery.com> 253 254 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the 255 order of flags documented. 256 2572011-07-29 Maciej W. Rozycki <macro@codesourcery.com> 258 259 * mips.h: Clarify the description of microMIPS instruction 260 manipulation macros. 261 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros. 262 2632011-07-24 Chao-ying Fu <fu@mips.com> 264 Maciej W. Rozycki <macro@codesourcery.com> 265 266 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros. 267 (OP_MASK_STYPE, OP_SH_STYPE): Likewise. 268 (OP_MASK_CODE10, OP_SH_CODE10): Likewise. 269 (OP_MASK_TRAP, OP_SH_TRAP): Likewise. 270 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise. 271 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise. 272 (OP_MASK_RS3, OP_SH_RS3): Likewise. 273 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise. 274 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise. 275 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise. 276 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise. 277 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise. 278 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise. 279 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise. 280 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise. 281 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise. 282 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise. 283 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise. 284 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise. 285 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise. 286 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise. 287 (INSN_WRITE_GPR_S): New macro. 288 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise. 289 (INSN2_READ_FPR_D): Likewise. 290 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise. 291 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise. 292 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise. 293 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise. 294 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise. 295 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise. 296 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise. 297 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise. 298 (CPU_MICROMIPS): New macro. 299 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values. 300 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise. 301 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise. 302 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise. 303 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise. 304 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise. 305 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise. 306 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise. 307 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise. 308 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise. 309 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise. 310 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise. 311 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise. 312 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros. 313 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise. 314 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise. 315 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise. 316 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise. 317 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise. 318 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise. 319 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise. 320 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise. 321 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise. 322 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise. 323 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise. 324 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise. 325 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise. 326 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise. 327 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise. 328 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise. 329 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise. 330 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise. 331 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise. 332 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise. 333 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise. 334 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise. 335 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise. 336 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise. 337 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise. 338 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise. 339 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise. 340 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise. 341 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise. 342 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise. 343 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise. 344 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise. 345 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise. 346 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise. 347 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise. 348 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise. 349 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise. 350 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise. 351 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise. 352 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise. 353 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise. 354 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise. 355 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise. 356 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise. 357 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise. 358 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise. 359 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise. 360 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise. 361 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise. 362 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise. 363 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise. 364 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise. 365 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise. 366 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise. 367 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise. 368 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise. 369 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise. 370 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise. 371 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise. 372 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise. 373 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise. 374 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise. 375 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise. 376 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise. 377 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise. 378 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise. 379 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise. 380 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise. 381 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise. 382 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise. 383 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise. 384 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise. 385 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise. 386 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise. 387 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. 388 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise. 389 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. 390 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. 391 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. 392 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. 393 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. 394 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise. 395 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. 396 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise. 397 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise. 398 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise. 399 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise. 400 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise. 401 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise. 402 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise. 403 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise. 404 (micromips_opcodes): New declaration. 405 (bfd_micromips_num_opcodes): Likewise. 406 4072011-07-24 Maciej W. Rozycki <macro@codesourcery.com> 408 409 * mips.h (INSN_TRAP): Rename to... 410 (INSN_NO_DELAY_SLOT): ... this. 411 (INSN_SYNC): Remove macro. 412 4132011-07-01 Eric B. Weddington <eric.weddington@atmel.com> 414 415 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually 416 a duplicate of AVR_ISA_SPM. 417 4182011-07-01 Nick Clifton <nickc@redhat.com> 419 420 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX. 421 4222011-06-18 Robin Getz <robin.getz@analog.com> 423 424 * bfin.h (is_macmod_signed): New func 425 4262011-06-18 Mike Frysinger <vapier@gentoo.org> 427 428 * bfin.h (is_macmod_pmove): Add missing space before func args. 429 (is_macmod_hmove): Likewise. 430 4312011-06-13 Walter Lee <walt@tilera.com> 432 433 * tilegx.h: New file. 434 * tilepro.h: New file. 435 4362011-05-31 Paul Brook <paul@codesourcery.com> 437 438 * arm.h (ARM_ARCH_V7R_IDIV): Define. 439 4402011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 441 442 * s390.h: Replace S390_OPERAND_REG_EVEN with 443 S390_OPERAND_REG_PAIR. 444 4452011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 446 447 * s390.h: Add S390_OPCODE_REG_EVEN flag. 448 4492011-04-18 Julian Brown <julian@codesourcery.com> 450 451 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask. 452 4532011-04-11 Dan McDonald <dan@wellkeeper.com> 454 455 PR gas/12296 456 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS. 457 4582011-03-22 Eric B. Weddington <eric.weddington@atmel.com> 459 460 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA): 461 New instruction set flags. 462 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA. 463 4642011-02-28 Maciej W. Rozycki <macro@codesourcery.com> 465 466 * mips.h (M_PREF_AB): New enum value. 467 4682011-02-12 Mike Frysinger <vapier@gentoo.org> 469 470 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH, 471 M_IU): Define. 472 (is_macmod_pmove, is_macmod_hmove): New functions. 473 4742011-02-11 Mike Frysinger <vapier@gentoo.org> 475 476 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection. 477 4782011-02-04 Bernd Schmidt <bernds@codesourcery.com> 479 480 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP. 481 * tic6x.h (TIC6X_INSN_ATOMIC): Remove. 482 4832010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 484 485 PR gas/11395 486 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit 487 "bb" entries. 488 4892010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 490 491 PR gas/11395 492 * hppa.h: Clear "d" bit in "add" and "sub" patterns. 493 4942010-12-18 Richard Sandiford <rdsandiford@googlemail.com> 495 496 * mips.h: Update commentary after last commit. 497 4982010-12-18 Mingjie Xing <mingjie.xing@gmail.com> 499 500 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C) 501 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z) 502 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define. 503 5042010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 505 506 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU. 507 5082010-11-23 Richard Sandiford <rdsandiford@googlemail.com> 509 510 * mips.h: Fix previous commit. 511 5122010-11-23 Maciej W. Rozycki <macro@linux-mips.org> 513 514 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A. 515 (INSN_LOONGSON_3A): Clear bit 31. 516 5172010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 518 519 PR gas/12198 520 * arm.h (ARM_AEXT_V6M_ONLY): New define. 521 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY. 522 (ARM_ARCH_V6M_ONLY): New define. 523 5242010-11-11 Mingming Sun <mingm.sun@gmail.com> 525 526 * mips.h (INSN_LOONGSON_3A): Defined. 527 (CPU_LOONGSON_3A): Defined. 528 (OPCODE_IS_MEMBER): Add LOONGSON_3A. 529 5302010-10-09 Matt Rice <ratmice@gmail.com> 531 532 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_. 533 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise. 534 5352010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 536 537 * arm.h (ARM_EXT_VIRT): New define. 538 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename... 539 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization 540 Extensions. 541 5422010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 543 544 * arm.h (ARM_AEXT_ADIV): New define. 545 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise. 546 5472010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 548 549 * arm.h (ARM_EXT_OS): New define. 550 (ARM_AEXT_V6SM): Likewise. 551 (ARM_ARCH_V6SM): Likewise. 552 5532010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 554 555 * arm.h (ARM_EXT_MP): Add. 556 (ARM_ARCH_V7A_MP): Likewise. 557 5582010-09-22 Mike Frysinger <vapier@gentoo.org> 559 560 * bfin.h: Declare pseudoChr structs/defines. 561 5622010-09-21 Mike Frysinger <vapier@gentoo.org> 563 564 * bfin.h: Strip trailing whitespace. 565 5662010-07-29 DJ Delorie <dj@redhat.com> 567 568 * rx.h (RX_Operand_Type): Add TwoReg. 569 (RX_Opcode_ID): Remove ediv and ediv2. 570 5712010-07-27 DJ Delorie <dj@redhat.com> 572 573 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics. 574 5752010-07-23 Naveen.H.S <naveen.S@kpitcummins.com> 576 Ina Pandit <ina.pandit@kpitcummins.com> 577 578 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION, 579 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and 580 PROCESSOR_V850E2_ALL. 581 Remove PROCESSOR_V850EA support. 582 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC, 583 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI, 584 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED, 585 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP, 586 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and 587 V850_OPERAND_PERCENT. 588 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and 589 V850_NOT_R0. 590 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP 591 and V850E_PUSH_POP 592 5932010-07-06 Maciej W. Rozycki <macro@codesourcery.com> 594 595 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro. 596 (MIPS16_INSN_BRANCH): Rename to... 597 (MIPS16_INSN_COND_BRANCH): ... this. 598 5992010-07-03 Alan Modra <amodra@gmail.com> 600 601 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete. 602 Renumber other PPC_OPCODE defines. 603 6042010-07-03 Alan Modra <amodra@gmail.com> 605 606 * ppc.h (PPC_OPCODE_COMMON): Expand comment. 607 6082010-06-29 Alan Modra <amodra@gmail.com> 609 610 * maxq.h: Delete file. 611 6122010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de> 613 614 * ppc.h (PPC_OPCODE_E500): Define. 615 6162010-05-26 Catherine Moore <clm@codesourcery.com> 617 618 * opcode/mips.h (INSN_MIPS16): Remove. 619 6202010-04-21 Joseph Myers <joseph@codesourcery.com> 621 622 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask. 623 6242010-04-15 Nick Clifton <nickc@redhat.com> 625 626 * alpha.h: Update copyright notice to use GPLv3. 627 * arc.h: Likewise. 628 * arm.h: Likewise. 629 * avr.h: Likewise. 630 * bfin.h: Likewise. 631 * cgen.h: Likewise. 632 * convex.h: Likewise. 633 * cr16.h: Likewise. 634 * cris.h: Likewise. 635 * crx.h: Likewise. 636 * d10v.h: Likewise. 637 * d30v.h: Likewise. 638 * dlx.h: Likewise. 639 * h8300.h: Likewise. 640 * hppa.h: Likewise. 641 * i370.h: Likewise. 642 * i386.h: Likewise. 643 * i860.h: Likewise. 644 * i960.h: Likewise. 645 * ia64.h: Likewise. 646 * m68hc11.h: Likewise. 647 * m68k.h: Likewise. 648 * m88k.h: Likewise. 649 * maxq.h: Likewise. 650 * mips.h: Likewise. 651 * mmix.h: Likewise. 652 * mn10200.h: Likewise. 653 * mn10300.h: Likewise. 654 * msp430.h: Likewise. 655 * np1.h: Likewise. 656 * ns32k.h: Likewise. 657 * or32.h: Likewise. 658 * pdp11.h: Likewise. 659 * pj.h: Likewise. 660 * pn.h: Likewise. 661 * ppc.h: Likewise. 662 * pyr.h: Likewise. 663 * rx.h: Likewise. 664 * s390.h: Likewise. 665 * score-datadep.h: Likewise. 666 * score-inst.h: Likewise. 667 * sparc.h: Likewise. 668 * spu-insns.h: Likewise. 669 * spu.h: Likewise. 670 * tic30.h: Likewise. 671 * tic4x.h: Likewise. 672 * tic54x.h: Likewise. 673 * tic80.h: Likewise. 674 * v850.h: Likewise. 675 * vax.h: Likewise. 676 6772010-03-25 Joseph Myers <joseph@codesourcery.com> 678 679 * tic6x-control-registers.h, tic6x-insn-formats.h, 680 tic6x-opcode-table.h, tic6x.h: New. 681 6822010-02-25 Wu Zhangjin <wuzhangjin@gmail.com> 683 684 * mips.h: (LOONGSON2F_NOP_INSN): New macro. 685 6862010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 687 688 * opcode/ppc.h (PPC_OPCODE_TITAN): Define. 689 6902010-01-14 H.J. Lu <hongjiu.lu@intel.com> 691 692 * ia64.h (ia64_find_opcode): Remove argument name. 693 (ia64_find_next_opcode): Likewise. 694 (ia64_dis_opcode): Likewise. 695 (ia64_free_opcode): Likewise. 696 (ia64_find_dependency): Likewise. 697 6982009-11-22 Doug Evans <dje@sebabeach.org> 699 700 * cgen.h: Include bfd_stdint.h. 701 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types. 702 7032009-11-18 Paul Brook <paul@codesourcery.com> 704 705 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define. 706 7072009-11-17 Paul Brook <paul@codesourcery.com> 708 Daniel Jacobowitz <dan@codesourcery.com> 709 710 * arm.h (ARM_EXT_V6_DSP): Define. 711 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP. 712 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define. 713 7142009-11-04 DJ Delorie <dj@redhat.com> 715 716 * rx.h (rx_decode_opcode) (mvtipl): Add. 717 (mvtcp, mvfcp, opecp): Remove. 718 7192009-11-02 Paul Brook <paul@codesourcery.com> 720 721 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA, 722 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define. 723 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD, 724 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16, 725 FPU_ARCH_NEON_VFP_V4): Define. 726 7272009-10-23 Doug Evans <dje@sebabeach.org> 728 729 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h. 730 * cgen.h: Update. Improve multi-inclusion macro name. 731 7322009-10-02 Peter Bergner <bergner@vnet.ibm.com> 733 734 * ppc.h (PPC_OPCODE_476): Define. 735 7362009-10-01 Peter Bergner <bergner@vnet.ibm.com> 737 738 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2. 739 7402009-09-29 DJ Delorie <dj@redhat.com> 741 742 * rx.h: New file. 743 7442009-09-22 Peter Bergner <bergner@vnet.ibm.com> 745 746 * ppc.h (ppc_cpu_t): Typedef to uint64_t. 747 7482009-09-21 Ben Elliston <bje@au.ibm.com> 749 750 * ppc.h (PPC_OPCODE_PPCA2): New. 751 7522009-09-05 Martin Thuresson <martin@mtme.org> 753 754 * ia64.h (struct ia64_operand): Renamed member class to op_class. 755 7562009-08-29 Martin Thuresson <martin@mtme.org> 757 758 * tic30.h (template): Rename type template to 759 insn_template. Updated code to use new name. 760 * tic54x.h (template): Rename type template to 761 insn_template. 762 7632009-08-20 Nick Hudson <nick.hudson@gmx.co.uk> 764 765 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT. 766 7672009-06-11 Anthony Green <green@moxielogic.com> 768 769 * moxie.h (MOXIE_F3_PCREL): Define. 770 (moxie_form3_opc_info): Grow. 771 7722009-06-06 Anthony Green <green@moxielogic.com> 773 774 * moxie.h (MOXIE_F1_M): Define. 775 7762009-04-15 Anthony Green <green@moxielogic.com> 777 778 * moxie.h: Created. 779 7802009-04-06 DJ Delorie <dj@redhat.com> 781 782 * h8300.h: Add relaxation attributes to MOVA opcodes. 783 7842009-03-10 Alan Modra <amodra@bigpond.net.au> 785 786 * ppc.h (ppc_parse_cpu): Declare. 787 7882009-03-02 Qinwei <qinwei@sunnorth.com.cn> 789 790 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5 791 and _IMM11 for mbitclr and mbitset. 792 * score-datadep.h: Update dependency information. 793 7942009-02-26 Peter Bergner <bergner@vnet.ibm.com> 795 796 * ppc.h (PPC_OPCODE_POWER7): New. 797 7982009-02-06 Doug Evans <dje@google.com> 799 800 * i386.h: Add comment regarding sse* insns and prefixes. 801 8022009-02-03 Sandip Matte <sandip@rmicorp.com> 803 804 * mips.h (INSN_XLR): Define. 805 (INSN_CHIP_MASK): Update. 806 (CPU_XLR): Define. 807 (OPCODE_IS_MEMBER): Update. 808 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define. 809 8102009-01-28 Doug Evans <dje@google.com> 811 812 * opcode/i386.h: Add multiple inclusion protection. 813 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM) 814 (EDI_REG_NUM): New macros. 815 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros. 816 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros. 817 (REX_PREFIX_P): New macro. 818 8192009-01-09 Peter Bergner <bergner@vnet.ibm.com> 820 821 * ppc.h (struct powerpc_opcode): New field "deprecated". 822 (PPC_OPCODE_NOPOWER4): Delete. 823 8242008-11-28 Joshua Kinard <kumba@gentoo.org> 825 826 * mips.h: Define CPU_R14000, CPU_R16000. 827 (OPCODE_IS_MEMBER): Include R14000, R16000 in test. 828 8292008-11-18 Catherine Moore <clm@codesourcery.com> 830 831 * arm.h (FPU_NEON_FP16): New. 832 (FPU_ARCH_NEON_FP16): New. 833 8342008-11-06 Chao-ying Fu <fu@mips.com> 835 836 * mips.h: Doucument '1' for 5-bit sync type. 837 8382008-08-28 H.J. Lu <hongjiu.lu@intel.com> 839 840 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update 841 IA64_RS_CR. 842 8432008-08-01 Peter Bergner <bergner@vnet.ibm.com> 844 845 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New. 846 8472008-07-30 Michael J. Eager <eager@eagercon.com> 848 849 * ppc.h (PPC_OPCODE_405): Define. 850 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define. 851 8522008-06-13 Peter Bergner <bergner@vnet.ibm.com> 853 854 * ppc.h (ppc_cpu_t): New typedef. 855 (struct powerpc_opcode <flags>): Use it. 856 (struct powerpc_operand <insert, extract>): Likewise. 857 (struct powerpc_macro <flags>): Likewise. 858 8592008-06-12 Adam Nemet <anemet@caviumnetworks.com> 860 861 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S. 862 Update comment before MIPS16 field descriptors to mention MIPS16. 863 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for 864 BBIT. 865 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1): 866 New bit masks and shift counts for cins and exts. 867 868 * mips.h: Document new field descriptors +Q. 869 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI. 870 8712008-04-28 Adam Nemet <anemet@caviumnetworks.com> 872 873 * mips.h (INSN_MACRO): Move it up to the the pinfo macros. 874 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros. 875 8762008-04-14 Edmar Wienskoski <edmar@freescale.com> 877 878 * ppc.h: (PPC_OPCODE_E500MC): New. 879 8802008-04-03 H.J. Lu <hongjiu.lu@intel.com> 881 882 * i386.h (MAX_OPERANDS): Set to 5. 883 (MAX_MNEM_SIZE): Changed to 20. 884 8852008-03-28 Eric B. Weddington <eric.weddington@atmel.com> 886 887 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167. 888 8892008-03-09 Paul Brook <paul@codesourcery.com> 890 891 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define. 892 8932008-03-04 Paul Brook <paul@codesourcery.com> 894 895 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define. 896 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags. 897 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define. 898 8992008-02-27 Denis Vlasenko <vda.linux@googlemail.com> 900 Nick Clifton <nickc@redhat.com> 901 902 PR 3134 903 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction 904 with a 32-bit displacement but without the top bit of the 4th byte 905 set. 906 9072008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com> 908 909 * cr16.h (cr16_num_optab): Declared. 910 9112008-02-14 Hakan Ardo <hakan@debian.org> 912 913 PR gas/2626 914 * avr.h (AVR_ISA_2xxe): Define. 915 9162008-02-04 Adam Nemet <anemet@caviumnetworks.com> 917 918 * mips.h: Update copyright. 919 (INSN_CHIP_MASK): New macro. 920 (INSN_OCTEON): New macro. 921 (CPU_OCTEON): New macro. 922 (OPCODE_IS_MEMBER): Handle Octeon instructions. 923 9242008-01-23 Eric B. Weddington <eric.weddington@atmel.com> 925 926 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401. 927 9282008-01-03 Eric B. Weddington <eric.weddington@atmel.com> 929 930 * avr.h (AVR_ISA_USB162): Add new opcode set. 931 (AVR_ISA_AVR3): Likewise. 932 9332007-11-29 Mark Shinwell <shinwell@codesourcery.com> 934 935 * mips.h (INSN_LOONGSON_2E): New. 936 (INSN_LOONGSON_2F): New. 937 (CPU_LOONGSON_2E): New. 938 (CPU_LOONGSON_2F): New. 939 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags. 940 9412007-11-29 Mark Shinwell <shinwell@codesourcery.com> 942 943 * mips.h (INSN_ISA*): Redefine certain values as an 944 enumeration. Update comments. 945 (mips_isa_table): New. 946 (ISA_MIPS*): Redefine to match enumeration. 947 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA* 948 values. 949 9502007-08-08 Ben Elliston <bje@au.ibm.com> 951 952 * ppc.h (PPC_OPCODE_PPCPS): New. 953 9542007-07-03 Nathan Sidwell <nathan@codesourcery.com> 955 956 * m68k.h: Document j K & E. 957 9582007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> 959 960 * cr16.h: New file for CR16 target. 961 9622007-05-02 Alan Modra <amodra@bigpond.net.au> 963 964 * ppc.h (PPC_OPERAND_PLUS1): Update comment. 965 9662007-04-23 Nathan Sidwell <nathan@codesourcery.com> 967 968 * m68k.h (mcfisa_c): New. 969 (mcfusp, mcf_mask): Adjust. 970 9712007-04-20 Alan Modra <amodra@bigpond.net.au> 972 973 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm". 974 (num_powerpc_operands): Declare. 975 (PPC_OPERAND_SIGNED et al): Redefine as hex. 976 (PPC_OPERAND_PLUS1): Define. 977 9782007-03-21 H.J. Lu <hongjiu.lu@intel.com> 979 980 * i386.h (REX_MODE64): Renamed to ... 981 (REX_W): This. 982 (REX_EXTX): Renamed to ... 983 (REX_R): This. 984 (REX_EXTY): Renamed to ... 985 (REX_X): This. 986 (REX_EXTZ): Renamed to ... 987 (REX_B): This. 988 9892007-03-15 H.J. Lu <hongjiu.lu@intel.com> 990 991 * i386.h: Add entries from config/tc-i386.h and move tables 992 to opcodes/i386-opc.h. 993 9942007-03-13 H.J. Lu <hongjiu.lu@intel.com> 995 996 * i386.h (FloatDR): Removed. 997 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR. 998 9992007-03-01 Alan Modra <amodra@bigpond.net.au> 1000 1001 * spu-insns.h: Add soma double-float insns. 1002 10032007-02-20 Thiemo Seufer <ths@mips.com> 1004 Chao-Ying Fu <fu@mips.com> 1005 1006 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. 1007 (INSN_DSPR2): Add flag for DSP R2 instructions. 1008 (M_BALIGN): New macro. 1009 10102007-02-14 Alan Modra <amodra@bigpond.net.au> 1011 1012 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm 1013 and Seg3ShortFrom with Shortform. 1014 10152007-02-11 H.J. Lu <hongjiu.lu@intel.com> 1016 1017 PR gas/4027 1018 * i386.h (i386_optab): Put the real "test" before the pseudo 1019 one. 1020 10212007-01-08 Kazu Hirata <kazu@codesourcery.com> 1022 1023 * m68k.h (m68010up): OR fido_a. 1024 10252006-12-25 Kazu Hirata <kazu@codesourcery.com> 1026 1027 * m68k.h (fido_a): New. 1028 10292006-12-24 Kazu Hirata <kazu@codesourcery.com> 1030 1031 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, 1032 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined 1033 values. 1034 10352006-11-08 H.J. Lu <hongjiu.lu@intel.com> 1036 1037 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3. 1038 10392006-10-31 Mei Ligang <ligang@sunnorth.com.cn> 1040 1041 * score-inst.h (enum score_insn_type): Add Insn_internal. 1042 10432006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> 1044 Yukishige Shibata <shibata@rd.scei.sony.co.jp> 1045 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> 1046 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> 1047 Alan Modra <amodra@bigpond.net.au> 1048 1049 * spu-insns.h: New file. 1050 * spu.h: New file. 1051 10522006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> 1053 1054 * ppc.h (PPC_OPCODE_CELL): Define. 1055 10562006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 1057 1058 * i386.h : Modify opcode to support for the change in POPCNT opcode 1059 in amdfam10 architecture. 1060 10612006-09-28 H.J. Lu <hongjiu.lu@intel.com> 1062 1063 * i386.h: Replace CpuMNI with CpuSSSE3. 1064 10652006-09-26 Mark Shinwell <shinwell@codesourcery.com> 1066 Joseph Myers <joseph@codesourcery.com> 1067 Ian Lance Taylor <ian@wasabisystems.com> 1068 Ben Elliston <bje@wasabisystems.com> 1069 1070 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. 1071 10722006-09-17 Mei Ligang <ligang@sunnorth.com.cn> 1073 1074 * score-datadep.h: New file. 1075 * score-inst.h: New file. 1076 10772006-07-14 H.J. Lu <hongjiu.lu@intel.com> 1078 1079 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, 1080 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, 1081 movdq2q and movq2dq. 1082 10832006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 1084 Michael Meissner <michael.meissner@amd.com> 1085 1086 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions). 1087 10882006-06-12 H.J. Lu <hongjiu.lu@intel.com> 1089 1090 * i386.h (i386_optab): Add "nop" with memory reference. 1091 10922006-06-12 H.J. Lu <hongjiu.lu@intel.com> 1093 1094 * i386.h (i386_optab): Update comment for 64bit NOP. 1095 10962006-06-06 Ben Elliston <bje@au.ibm.com> 1097 Anton Blanchard <anton@samba.org> 1098 1099 * ppc.h (PPC_OPCODE_POWER6): Define. 1100 Adjust whitespace. 1101 11022006-06-05 Thiemo Seufer <ths@mips.com> 1103 1104 * mips.h: Improve description of MT flags. 1105 11062006-05-25 Richard Sandiford <richard@codesourcery.com> 1107 1108 * m68k.h (mcf_mask): Define. 1109 11102006-05-05 Thiemo Seufer <ths@mips.com> 1111 David Ung <davidu@mips.com> 1112 1113 * mips.h (enum): Add macro M_CACHE_AB. 1114 11152006-05-04 Thiemo Seufer <ths@mips.com> 1116 Nigel Stephens <nigel@mips.com> 1117 David Ung <davidu@mips.com> 1118 1119 * mips.h: Add INSN_SMARTMIPS define. 1120 11212006-04-30 Thiemo Seufer <ths@mips.com> 1122 David Ung <davidu@mips.com> 1123 1124 * mips.h: Defines udi bits and masks. Add description of 1125 characters which may appear in the args field of udi 1126 instructions. 1127 11282006-04-26 Thiemo Seufer <ths@networkno.de> 1129 1130 * mips.h: Improve comments describing the bitfield instruction 1131 fields. 1132 11332006-04-26 Julian Brown <julian@codesourcery.com> 1134 1135 * arm.h (FPU_VFP_EXT_V3): Define constant. 1136 (FPU_NEON_EXT_V1): Likewise. 1137 (FPU_VFP_HARD): Update. 1138 (FPU_VFP_V3): Define macro. 1139 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. 1140 11412006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> 1142 1143 * avr.h (AVR_ISA_PWMx): New. 1144 11452006-03-28 Nathan Sidwell <nathan@codesourcery.com> 1146 1147 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, 1148 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, 1149 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, 1150 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, 1151 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. 1152 11532006-03-10 Paul Brook <paul@codesourcery.com> 1154 1155 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. 1156 11572006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 1158 1159 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come 1160 first. Correct mask of bb "B" opcode. 1161 11622006-02-27 H.J. Lu <hongjiu.lu@intel.com> 1163 1164 * i386.h (i386_optab): Support Intel Merom New Instructions. 1165 11662006-02-24 Paul Brook <paul@codesourcery.com> 1167 1168 * arm.h: Add V7 feature bits. 1169 11702006-02-23 H.J. Lu <hongjiu.lu@intel.com> 1171 1172 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. 1173 11742006-01-31 Paul Brook <paul@codesourcery.com> 1175 Richard Earnshaw <rearnsha@arm.com> 1176 1177 * arm.h: Use ARM_CPU_FEATURE. 1178 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. 1179 (arm_feature_set): Change to a structure. 1180 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, 1181 ARM_FEATURE): New macros. 1182 11832005-12-07 Hans-Peter Nilsson <hp@axis.com> 1184 1185 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) 1186 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. 1187 (ADD_PC_INCR_OPCODE): Don't define. 1188 11892005-12-06 H.J. Lu <hongjiu.lu@intel.com> 1190 1191 PR gas/1874 1192 * i386.h (i386_optab): Add 64bit support for monitor and mwait. 1193 11942005-11-14 David Ung <davidu@mips.com> 1195 1196 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore 1197 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for 1198 save/restore encoding of the args field. 1199 12002005-10-28 Dave Brolley <brolley@redhat.com> 1201 1202 Contribute the following changes: 1203 2005-02-16 Dave Brolley <brolley@redhat.com> 1204 1205 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename 1206 cgen_isa_mask_* to cgen_bitset_*. 1207 * cgen.h: Likewise. 1208 1209 2003-10-21 Richard Sandiford <rsandifo@redhat.com> 1210 1211 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. 1212 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". 1213 (CGEN_CPU_TABLE): Make isas a ponter. 1214 1215 2003-09-29 Dave Brolley <brolley@redhat.com> 1216 1217 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. 1218 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. 1219 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. 1220 1221 2002-12-13 Dave Brolley <brolley@redhat.com> 1222 1223 * cgen.h (symcat.h): #include it. 1224 (cgen-bitset.h): #include it. 1225 (CGEN_ATTR_VALUE_TYPE): Now a union. 1226 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h. 1227 (CGEN_ATTR_ENTRY): 'value' now unsigned. 1228 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). 1229 * cgen-bitset.h: New file. 1230 12312005-09-30 Catherine Moore <clm@cm00re.com> 1232 1233 * bfin.h: New file. 1234 12352005-10-24 Jan Beulich <jbeulich@novell.com> 1236 1237 * ia64.h (enum ia64_opnd): Move memory operand out of set of 1238 indirect operands. 1239 12402005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 1241 1242 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. 1243 Add FLAG_STRICT to pa10 ftest opcode. 1244 12452005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 1246 1247 * hppa.h (pa_opcodes): Remove lha entries. 1248 12492005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 1250 1251 * hppa.h (FLAG_STRICT): Revise comment. 1252 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants 1253 before corresponding pa11 opcodes. Add strict pa10 register-immediate 1254 entries for "fdc". 1255 12562005-09-30 Catherine Moore <clm@cm00re.com> 1257 1258 * bfin.h: New file. 1259 12602005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 1261 1262 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. 1263 12642005-09-06 Chao-ying Fu <fu@mips.com> 1265 1266 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, 1267 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New 1268 define. 1269 Document !, $, *, &, g, +t, +T operand formats for MT instructions. 1270 (INSN_ASE_MASK): Update to include INSN_MT. 1271 (INSN_MT): New define for MT ASE. 1272 12732005-08-25 Chao-ying Fu <fu@mips.com> 1274 1275 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, 1276 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, 1277 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, 1278 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, 1279 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. 1280 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP 1281 instructions. 1282 (INSN_DSP): New define for DSP ASE. 1283 12842005-08-18 Alan Modra <amodra@bigpond.net.au> 1285 1286 * a29k.h: Delete. 1287 12882005-08-15 Daniel Jacobowitz <dan@codesourcery.com> 1289 1290 * ppc.h (PPC_OPCODE_E300): Define. 1291 12922005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> 1293 1294 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. 1295 12962005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 1297 1298 PR gas/336 1299 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb 1300 and pitlb. 1301 13022005-07-27 Jan Beulich <jbeulich@novell.com> 1303 1304 * i386.h (i386_optab): Add comment to movd. Use LongMem for all 1305 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. 1306 Add movq-s as 64-bit variants of movd-s. 1307 13082005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 1309 1310 * hppa.h: Fix punctuation in comment. 1311 1312 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for 1313 implicit space-register addressing. Set space-register bits on opcodes 1314 using implicit space-register addressing. Add various missing pa20 1315 long-immediate opcodes. Remove various opcodes using implicit 3-bit 1316 space-register addressing. Use "fE" instead of "fe" in various 1317 fstw opcodes. 1318 13192005-07-18 Jan Beulich <jbeulich@novell.com> 1320 1321 * i386.h (i386_optab): Operands of aam and aad are unsigned. 1322 13232007-07-15 H.J. Lu <hongjiu.lu@intel.com> 1324 1325 * i386.h (i386_optab): Support Intel VMX Instructions. 1326 13272005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 1328 1329 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. 1330 13312005-07-05 Jan Beulich <jbeulich@novell.com> 1332 1333 * i386.h (i386_optab): Add new insns. 1334 13352005-07-01 Nick Clifton <nickc@redhat.com> 1336 1337 * sparc.h: Add typedefs to structure declarations. 1338 13392005-06-20 H.J. Lu <hongjiu.lu@intel.com> 1340 1341 PR 1013 1342 * i386.h (i386_optab): Update comments for 64bit addressing on 1343 mov. Allow 64bit addressing for mov and movq. 1344 13452005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 1346 1347 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, 1348 respectively, in various floating-point load and store patterns. 1349 13502005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 1351 1352 * hppa.h (FLAG_STRICT): Correct comment. 1353 (pa_opcodes): Update load and store entries to allow both PA 1.X and 1354 PA 2.0 mneumonics when equivalent. Entries with cache control 1355 completers now require PA 1.1. Adjust whitespace. 1356 13572005-05-19 Anton Blanchard <anton@samba.org> 1358 1359 * ppc.h (PPC_OPCODE_POWER5): Define. 1360 13612005-05-10 Nick Clifton <nickc@redhat.com> 1362 1363 * Update the address and phone number of the FSF organization in 1364 the GPL notices in the following files: 1365 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, 1366 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, 1367 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, 1368 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, 1369 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, 1370 tic54x.h, tic80.h, v850.h, vax.h 1371 13722005-05-09 Jan Beulich <jbeulich@novell.com> 1373 1374 * i386.h (i386_optab): Add ht and hnt. 1375 13762005-04-18 Mark Kettenis <kettenis@gnu.org> 1377 1378 * i386.h: Insert hyphens into selected VIA PadLock extensions. 1379 Add xcrypt-ctr. Provide aliases without hyphens. 1380 13812005-04-13 H.J. Lu <hongjiu.lu@intel.com> 1382 1383 Moved from ../ChangeLog 1384 1385 2005-04-12 Paul Brook <paul@codesourcery.com> 1386 * m88k.h: Rename psr macros to avoid conflicts. 1387 1388 2005-03-12 Zack Weinberg <zack@codesourcery.com> 1389 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. 1390 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, 1391 and ARM_ARCH_V6ZKT2. 1392 1393 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> 1394 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. 1395 Remove redundant instruction types. 1396 (struct argument): X_op - new field. 1397 (struct cst4_entry): Remove. 1398 (no_op_insn): Declare. 1399 1400 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> 1401 * crx.h (enum argtype): Rename types, remove unused types. 1402 1403 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> 1404 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. 1405 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. 1406 (enum operand_type): Rearrange operands, edit comments. 1407 replace us<N> with ui<N> for unsigned immediate. 1408 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped 1409 displacements (respectively). 1410 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. 1411 (instruction type): Add NO_TYPE_INS. 1412 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. 1413 (operand_entry): New field - 'flags'. 1414 (operand flags): New. 1415 1416 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> 1417 * crx.h (operand_type): Remove redundant types i3, i4, 1418 i5, i8, i12. 1419 Add new unsigned immediate types us3, us4, us5, us16. 1420 14212005-04-12 Mark Kettenis <kettenis@gnu.org> 1422 1423 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and 1424 adjust them accordingly. 1425 14262005-04-01 Jan Beulich <jbeulich@novell.com> 1427 1428 * i386.h (i386_optab): Add rdtscp. 1429 14302005-03-29 H.J. Lu <hongjiu.lu@intel.com> 1431 1432 * i386.h (i386_optab): Don't allow the `l' suffix for moving 1433 between memory and segment register. Allow movq for moving between 1434 general-purpose register and segment register. 1435 14362005-02-09 Jan Beulich <jbeulich@novell.com> 1437 1438 PR gas/707 1439 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and 1440 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and 1441 fnstsw. 1442 14432006-02-07 Nathan Sidwell <nathan@codesourcery.com> 1444 1445 * m68k.h (m68008, m68ec030, m68882): Remove. 1446 (m68k_mask): New. 1447 (cpu_m68k, cpu_cf): New. 1448 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, 1449 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. 1450 14512005-01-25 Alexandre Oliva <aoliva@redhat.com> 1452 1453 2004-11-10 Alexandre Oliva <aoliva@redhat.com> 1454 * cgen.h (enum cgen_parse_operand_type): Add 1455 CGEN_PARSE_OPERAND_SYMBOLIC. 1456 14572005-01-21 Fred Fish <fnf@specifixinc.com> 1458 1459 * mips.h: Change INSN_ALIAS to INSN2_ALIAS. 1460 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. 1461 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. 1462 14632005-01-19 Fred Fish <fnf@specifixinc.com> 1464 1465 * mips.h (struct mips_opcode): Add new pinfo2 member. 1466 (INSN_ALIAS): New define for opcode table entries that are 1467 specific instances of another entry, such as 'move' for an 'or' 1468 with a zero operand. 1469 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. 1470 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. 1471 14722004-12-09 Ian Lance Taylor <ian@wasabisystems.com> 1473 1474 * mips.h (CPU_RM9000): Define. 1475 (OPCODE_IS_MEMBER): Handle CPU_RM9000. 1476 14772004-11-25 Jan Beulich <jbeulich@novell.com> 1478 1479 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves 1480 to/from test registers are illegal in 64-bit mode. Add missing 1481 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix 1482 (previously one had to explicitly encode a rex64 prefix). Re-enable 1483 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings 1484 support it there. Add cmpxchg16b as per Intel's 64-bit documentation. 1485 14862004-11-23 Jan Beulich <jbeulich@novell.com> 1487 1488 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are 1489 available only with SSE2. Change the MMX additions introduced by SSE 1490 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A 1491 instructions by their now designated identifier (since combining i686 1492 and 3DNow! does not really imply 3DNow!A). 1493 14942004-11-19 Alan Modra <amodra@bigpond.net.au> 1495 1496 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, 1497 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. 1498 14992004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> 1500 Vineet Sharma <vineets@noida.hcltech.com> 1501 1502 * maxq.h: New file: Disassembly information for the maxq port. 1503 15042004-11-05 H.J. Lu <hongjiu.lu@intel.com> 1505 1506 * i386.h (i386_optab): Put back "movzb". 1507 15082004-11-04 Hans-Peter Nilsson <hp@axis.com> 1509 1510 * cris.h (enum cris_insn_version_usage): Tweak formatting and 1511 comments. Remove member cris_ver_sim. Add members 1512 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, 1513 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. 1514 (struct cris_support_reg, struct cris_cond15): New types. 1515 (cris_conds15): Declare. 1516 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) 1517 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) 1518 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. 1519 (NOP_Z_BITS): Define in terms of NOP_OPCODE. 1520 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and 1521 SIZE_FIELD_UNSIGNED. 1522 15232004-11-04 Jan Beulich <jbeulich@novell.com> 1524 1525 * i386.h (sldx_Suf): Remove. 1526 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. 1527 (q_FP): Define, implying no REX64. 1528 (x_FP, sl_FP): Imply FloatMF. 1529 (i386_optab): Split reg and mem forms of moving from segment registers 1530 so that the memory forms can ignore the 16-/32-bit operand size 1531 distinction. Adjust a few others for Intel mode. Remove *FP uses from 1532 all non-floating-point instructions. Unite 32- and 64-bit forms of 1533 movsx, movzx, and movd. Adjust floating point operations for the above 1534 changes to the *FP macros. Add DefaultSize to floating point control 1535 insns operating on larger memory ranges. Remove left over comments 1536 hinting at certain insns being Intel-syntax ones where the ones 1537 actually meant are already gone. 1538 15392004-10-07 Tomer Levi <Tomer.Levi@nsc.com> 1540 1541 * crx.h: Add COPS_REG_INS - Coprocessor Special register 1542 instruction type. 1543 15442004-09-30 Paul Brook <paul@codesourcery.com> 1545 1546 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. 1547 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. 1548 15492004-09-11 Theodore A. Roth <troth@openavr.org> 1550 1551 * avr.h: Add support for 1552 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. 1553 15542004-09-09 Segher Boessenkool <segher@kernel.crashing.org> 1555 1556 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. 1557 15582004-08-24 Dmitry Diky <diwil@spec.ru> 1559 1560 * msp430.h (msp430_opc): Add new instructions. 1561 (msp430_rcodes): Declare new instructions. 1562 (msp430_hcodes): Likewise.. 1563 15642004-08-13 Nick Clifton <nickc@redhat.com> 1565 1566 PR/301 1567 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX 1568 processors. 1569 15702004-08-30 Michal Ludvig <mludvig@suse.cz> 1571 1572 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. 1573 15742004-07-22 H.J. Lu <hongjiu.lu@intel.com> 1575 1576 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. 1577 15782004-07-21 Jan Beulich <jbeulich@novell.com> 1579 1580 * i386.h: Adjust instruction descriptions to better match the 1581 specification. 1582 15832004-07-16 Richard Earnshaw <rearnsha@arm.com> 1584 1585 * arm.h: Remove all old content. Replace with architecture defines 1586 from gas/config/tc-arm.c. 1587 15882004-07-09 Andreas Schwab <schwab@suse.de> 1589 1590 * m68k.h: Fix comment. 1591 15922004-07-07 Tomer Levi <Tomer.Levi@nsc.com> 1593 1594 * crx.h: New file. 1595 15962004-06-24 Alan Modra <amodra@bigpond.net.au> 1597 1598 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. 1599 16002004-05-24 Peter Barada <peter@the-baradas.com> 1601 1602 * m68k.h: Add 'size' to m68k_opcode. 1603 16042004-05-05 Peter Barada <peter@the-baradas.com> 1605 1606 * m68k.h: Switch from ColdFire chip name to core variant. 1607 16082004-04-22 Peter Barada <peter@the-baradas.com> 1609 1610 * m68k.h: Add mcfmac/mcfemac definitions. Update operand 1611 descriptions for new EMAC cases. 1612 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly 1613 handle Motorola MAC syntax. 1614 Allow disassembly of ColdFire V4e object files. 1615 16162004-03-16 Alan Modra <amodra@bigpond.net.au> 1617 1618 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. 1619 16202004-03-12 Jakub Jelinek <jakub@redhat.com> 1621 1622 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. 1623 16242004-03-12 Michal Ludvig <mludvig@suse.cz> 1625 1626 * i386.h (i386_optab): Added xstore as an alias for xstorerng. 1627 16282004-03-12 Michal Ludvig <mludvig@suse.cz> 1629 1630 * i386.h (i386_optab): Added xstore/xcrypt insns. 1631 16322004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> 1633 1634 * h8300.h (32bit ldc/stc): Add relaxing support. 1635 16362004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> 1637 1638 * h8300.h (BITOP): Pass MEMRELAX flag. 1639 16402004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> 1641 1642 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 1643 except for the H8S. 1644 1645For older changes see ChangeLog-9103 1646 1647Copyright (C) 2004-2012 Free Software Foundation, Inc. 1648 1649Copying and distribution of this file, with or without modification, 1650are permitted in any medium without royalty provided the copyright 1651notice and this notice are preserved. 1652 1653Local Variables: 1654mode: change-log 1655left-margin: 8 1656fill-column: 74 1657version-control: never 1658End: 1659