1// -*- C -*- 2// 3// <insn> ::= 4// <insn-word> { "+" <insn-word> } 5// ":" <format-name> 6// ":" <filter-flags> 7// ":" <options> 8// ":" <name> 9// <nl> 10// { <insn-model> } 11// { <insn-mnemonic> } 12// <code-block> 13// 14 15 16// IGEN config - mips16 17// :option:16::insn-bit-size:16 18// :option:16::hi-bit-nr:15 19:option:16::insn-specifying-widths:true 20:option:16::gen-delayed-branch:false 21 22// IGEN config - mips32/64.. 23// :option:32::insn-bit-size:32 24// :option:32::hi-bit-nr:31 25:option:32::insn-specifying-widths:true 26:option:32::gen-delayed-branch:false 27 28 29// Generate separate simulators for each target 30// :option:::multi-sim:true 31 32 33// Models known by this simulator are defined below. 34// 35// When placing models in the instruction descriptions, please place 36// them one per line, in the order given here. 37 38// MIPS ISAs: 39// 40// Instructions and related functions for these models are included in 41// this file. 42:model:::mipsI:mips3000: 43:model:::mipsII:mips6000: 44:model:::mipsIII:mips4000: 45:model:::mipsIV:mips8000: 46:model:::mipsV:mipsisaV: 47:model:::mips32:mipsisa32: 48:model:::mips32r2:mipsisa32r2: 49:model:::mips64:mipsisa64: 50:model:::mips64r2:mipsisa64r2: 51 52// Vendor ISAs: 53// 54// Standard MIPS ISA instructions used for these models are listed here, 55// as are functions needed by those standard instructions. Instructions 56// which are model-dependent and which are not in the standard MIPS ISAs 57// (or which pre-date or use different encodings than the standard 58// instructions) are (for the most part) in separate .igen files. 59:model:::vr4100:mips4100: // vr.igen 60:model:::vr4120:mips4120: 61:model:::vr5000:mips5000: 62:model:::vr5400:mips5400: 63:model:::vr5500:mips5500: 64:model:::r3900:mips3900: // tx.igen 65 66// MIPS Application Specific Extensions (ASEs) 67// 68// Instructions for the ASEs are in separate .igen files. 69// ASEs add instructions on to a base ISA. 70:model:::mips16:mips16: // m16.igen (and m16.dc) 71:model:::mips16e:mips16e: // m16e.igen 72:model:::mips3d:mips3d: // mips3d.igen 73:model:::mdmx:mdmx: // mdmx.igen 74:model:::dsp:dsp: // dsp.igen 75:model:::dsp2:dsp2: // dsp2.igen 76:model:::smartmips:smartmips: // smartmips.igen 77 78// Vendor Extensions 79// 80// Instructions specific to these extensions are in separate .igen files. 81// Extensions add instructions on to a base ISA. 82:model:::sb1:sb1: // sb1.igen 83 84 85// Pseudo instructions known by IGEN 86:internal::::illegal: 87{ 88 SignalException (ReservedInstruction, 0); 89} 90 91 92// Pseudo instructions known by interp.c 93// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK 94000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD 95"rsvd <OP>" 96{ 97 SignalException (ReservedInstruction, instruction_0); 98} 99 100 101 102// Helper: 103// 104// Simulate a 32 bit delayslot instruction 105// 106 107:function:::address_word:delayslot32:address_word target 108{ 109 instruction_word delay_insn; 110 sim_events_slip (SD, 1); 111 DSPC = CIA; 112 CIA = CIA + 4; /* NOTE not mips16 */ 113 STATE |= simDELAYSLOT; 114 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ 115 ENGINE_ISSUE_PREFIX_HOOK(); 116 idecode_issue (CPU_, delay_insn, (CIA)); 117 STATE &= ~simDELAYSLOT; 118 return target; 119} 120 121:function:::address_word:nullify_next_insn32: 122{ 123 sim_events_slip (SD, 1); 124 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction"); 125 return CIA + 8; 126} 127 128 129// Helper: 130// 131// Calculate an effective address given a base and an offset. 132// 133 134:function:::address_word:loadstore_ea:address_word base, address_word offset 135*mipsI: 136*mipsII: 137*mipsIII: 138*mipsIV: 139*mipsV: 140*mips32: 141*mips32r2: 142*vr4100: 143*vr5000: 144*r3900: 145{ 146 return base + offset; 147} 148 149:function:::address_word:loadstore_ea:address_word base, address_word offset 150*mips64: 151*mips64r2: 152{ 153#if 0 /* XXX FIXME: enable this only after some additional testing. */ 154 /* If in user mode and UX is not set, use 32-bit compatibility effective 155 address computations as defined in the MIPS64 Architecture for 156 Programmers Volume III, Revision 0.95, section 4.9. */ 157 if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX)) 158 == (ksu_user << status_KSU_shift)) 159 return (address_word)((signed32)base + (signed32)offset); 160#endif 161 return base + offset; 162} 163 164 165// Helper: 166// 167// Check that a 32-bit register value is properly sign-extended. 168// (See NotWordValue in ISA spec.) 169// 170 171:function:::int:not_word_value:unsigned_word value 172*mipsI: 173*mipsII: 174*mipsIII: 175*mipsIV: 176*mipsV: 177*vr4100: 178*vr5000: 179*r3900: 180*mips32: 181*mips32r2: 182*mips64: 183*mips64r2: 184{ 185#if WITH_TARGET_WORD_BITSIZE == 64 186 return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); 187#else 188 return 0; 189#endif 190} 191 192// Helper: 193// 194// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent 195// theoretically portable code which invokes non-portable behaviour from 196// running with no indication of the portability issue. 197// (See definition of UNPREDICTABLE in ISA spec.) 198// 199 200:function:::void:unpredictable: 201*mipsI: 202*mipsII: 203*mipsIII: 204*mipsIV: 205*mipsV: 206*vr4100: 207*vr5000: 208*r3900: 209{ 210} 211 212:function:::void:unpredictable: 213*mips32: 214*mips32r2: 215*mips64: 216*mips64r2: 217{ 218 unpredictable_action (CPU, CIA); 219} 220 221 222// Helpers: 223// 224// Check that an access to a HI/LO register meets timing requirements 225// 226// In all MIPS ISAs, 227// 228// OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO}) 229// makes subsequent MF{HI or LO} UNPREDICTABLE. (1) 230// 231// The following restrictions exist for MIPS I - MIPS III: 232// 233// MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions 234// in between makes MF UNPREDICTABLE. (2) 235// 236// MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions 237// in between makes MF UNPREDICTABLE. (3) 238// 239// On the r3900, restriction (2) is not present, and restriction (3) is not 240// present for multiplication. 241// 242// Unfortunately, there seems to be some confusion about whether the last 243// two restrictions should apply to "MIPS IV" as well. One edition of 244// the MIPS IV ISA says they do, but references in later ISA documents 245// suggest they don't. 246// 247// In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have 248// these restrictions, while others, like the VR5500, don't. To accomodate 249// such differences, the MIPS IV and MIPS V version of these helper functions 250// use auxillary routines to determine whether the restriction applies. 251 252// check_mf_cycles: 253// 254// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo 255// to check for restrictions (2) and (3) above. 256// 257:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new 258{ 259 if (history->mf.timestamp + 3 > time) 260 { 261 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n", 262 itable[MY_INDEX].name, 263 new, (long) CIA, 264 (long) history->mf.cia); 265 return 0; 266 } 267 return 1; 268} 269 270 271// check_mt_hilo: 272// 273// Check for restriction (2) above (for ISAs/processors that have it), 274// and record timestamps for restriction (1) above. 275// 276:function:::int:check_mt_hilo:hilo_history *history 277*mipsI: 278*mipsII: 279*mipsIII: 280*vr4100: 281*vr5000: 282{ 283 signed64 time = sim_events_time (SD); 284 int ok = check_mf_cycles (SD_, history, time, "MT"); 285 history->mt.timestamp = time; 286 history->mt.cia = CIA; 287 return ok; 288} 289 290:function:::int:check_mt_hilo:hilo_history *history 291*mipsIV: 292*mipsV: 293{ 294 signed64 time = sim_events_time (SD); 295 int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD) 296 || check_mf_cycles (SD_, history, time, "MT")); 297 history->mt.timestamp = time; 298 history->mt.cia = CIA; 299 return ok; 300} 301 302:function:::int:check_mt_hilo:hilo_history *history 303*mips32: 304*mips32r2: 305*mips64: 306*mips64r2: 307*r3900: 308{ 309 signed64 time = sim_events_time (SD); 310 history->mt.timestamp = time; 311 history->mt.cia = CIA; 312 return 1; 313} 314 315 316// check_mf_hilo: 317// 318// Check for restriction (1) above, and record timestamps for 319// restriction (2) and (3) above. 320// 321:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer 322*mipsI: 323*mipsII: 324*mipsIII: 325*mipsIV: 326*mipsV: 327*mips32: 328*mips32r2: 329*mips64: 330*mips64r2: 331*vr4100: 332*vr5000: 333*r3900: 334{ 335 signed64 time = sim_events_time (SD); 336 int ok = 1; 337 if (peer != NULL 338 && peer->mt.timestamp > history->op.timestamp 339 && history->mt.timestamp < history->op.timestamp 340 && ! (history->mf.timestamp > history->op.timestamp 341 && history->mf.timestamp < peer->mt.timestamp) 342 && ! (peer->mf.timestamp > history->op.timestamp 343 && peer->mf.timestamp < peer->mt.timestamp)) 344 { 345 /* The peer has been written to since the last OP yet we have 346 not */ 347 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n", 348 itable[MY_INDEX].name, 349 (long) CIA, 350 (long) history->op.cia, 351 (long) peer->mt.cia); 352 ok = 0; 353 } 354 history->mf.timestamp = time; 355 history->mf.cia = CIA; 356 return ok; 357} 358 359 360 361// check_mult_hilo: 362// 363// Check for restriction (3) above (for ISAs/processors that have it) 364// for MULT ops, and record timestamps for restriction (1) above. 365// 366:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo 367*mipsI: 368*mipsII: 369*mipsIII: 370*vr4100: 371*vr5000: 372{ 373 signed64 time = sim_events_time (SD); 374 int ok = (check_mf_cycles (SD_, hi, time, "OP") 375 && check_mf_cycles (SD_, lo, time, "OP")); 376 hi->op.timestamp = time; 377 lo->op.timestamp = time; 378 hi->op.cia = CIA; 379 lo->op.cia = CIA; 380 return ok; 381} 382 383:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo 384*mipsIV: 385*mipsV: 386{ 387 signed64 time = sim_events_time (SD); 388 int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD) 389 || (check_mf_cycles (SD_, hi, time, "OP") 390 && check_mf_cycles (SD_, lo, time, "OP"))); 391 hi->op.timestamp = time; 392 lo->op.timestamp = time; 393 hi->op.cia = CIA; 394 lo->op.cia = CIA; 395 return ok; 396} 397 398:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo 399*mips32: 400*mips32r2: 401*mips64: 402*mips64r2: 403*r3900: 404{ 405 /* FIXME: could record the fact that a stall occured if we want */ 406 signed64 time = sim_events_time (SD); 407 hi->op.timestamp = time; 408 lo->op.timestamp = time; 409 hi->op.cia = CIA; 410 lo->op.cia = CIA; 411 return 1; 412} 413 414 415// check_div_hilo: 416// 417// Check for restriction (3) above (for ISAs/processors that have it) 418// for DIV ops, and record timestamps for restriction (1) above. 419// 420:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo 421*mipsI: 422*mipsII: 423*mipsIII: 424*vr4100: 425*vr5000: 426*r3900: 427{ 428 signed64 time = sim_events_time (SD); 429 int ok = (check_mf_cycles (SD_, hi, time, "OP") 430 && check_mf_cycles (SD_, lo, time, "OP")); 431 hi->op.timestamp = time; 432 lo->op.timestamp = time; 433 hi->op.cia = CIA; 434 lo->op.cia = CIA; 435 return ok; 436} 437 438:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo 439*mipsIV: 440*mipsV: 441{ 442 signed64 time = sim_events_time (SD); 443 int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD) 444 || (check_mf_cycles (SD_, hi, time, "OP") 445 && check_mf_cycles (SD_, lo, time, "OP"))); 446 hi->op.timestamp = time; 447 lo->op.timestamp = time; 448 hi->op.cia = CIA; 449 lo->op.cia = CIA; 450 return ok; 451} 452 453:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo 454*mips32: 455*mips32r2: 456*mips64: 457*mips64r2: 458{ 459 signed64 time = sim_events_time (SD); 460 hi->op.timestamp = time; 461 lo->op.timestamp = time; 462 hi->op.cia = CIA; 463 lo->op.cia = CIA; 464 return 1; 465} 466 467 468// Helper: 469// 470// Check that the 64-bit instruction can currently be used, and signal 471// a ReservedInstruction exception if not. 472// 473 474:function:::void:check_u64:instruction_word insn 475*mipsIII: 476*mipsIV: 477*mipsV: 478*vr4100: 479*vr5000: 480*vr5400: 481*vr5500: 482{ 483 // The check should be similar to mips64 for any with PX/UX bit equivalents. 484} 485 486:function:::void:check_u64:instruction_word insn 487*mips16e: 488*mips64: 489*mips64r2: 490{ 491#if 0 /* XXX FIXME: enable this only after some additional testing. */ 492 if (UserMode && (SR & (status_UX|status_PX)) == 0) 493 SignalException (ReservedInstruction, insn); 494#endif 495} 496 497 498 499// 500// MIPS Architecture: 501// 502// CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2) 503// 504 505 506 507000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD 508"add r<RD>, r<RS>, r<RT>" 509*mipsI: 510*mipsII: 511*mipsIII: 512*mipsIV: 513*mipsV: 514*mips32: 515*mips32r2: 516*mips64: 517*mips64r2: 518*vr4100: 519*vr5000: 520*r3900: 521{ 522 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) 523 Unpredictable (); 524 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 525 { 526 ALU32_BEGIN (GPR[RS]); 527 ALU32_ADD (GPR[RT]); 528 ALU32_END (GPR[RD]); /* This checks for overflow. */ 529 } 530 TRACE_ALU_RESULT (GPR[RD]); 531} 532 533 534 535001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI 536"addi r<RT>, r<RS>, <IMMEDIATE>" 537*mipsI: 538*mipsII: 539*mipsIII: 540*mipsIV: 541*mipsV: 542*mips32: 543*mips32r2: 544*mips64: 545*mips64r2: 546*vr4100: 547*vr5000: 548*r3900: 549{ 550 if (NotWordValue (GPR[RS])) 551 Unpredictable (); 552 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); 553 { 554 ALU32_BEGIN (GPR[RS]); 555 ALU32_ADD (EXTEND16 (IMMEDIATE)); 556 ALU32_END (GPR[RT]); /* This checks for overflow. */ 557 } 558 TRACE_ALU_RESULT (GPR[RT]); 559} 560 561 562 563:function:::void:do_addiu:int rs, int rt, unsigned16 immediate 564{ 565 if (NotWordValue (GPR[rs])) 566 Unpredictable (); 567 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); 568 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate)); 569 TRACE_ALU_RESULT (GPR[rt]); 570} 571 572001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU 573"addiu r<RT>, r<RS>, <IMMEDIATE>" 574*mipsI: 575*mipsII: 576*mipsIII: 577*mipsIV: 578*mipsV: 579*mips32: 580*mips32r2: 581*mips64: 582*mips64r2: 583*vr4100: 584*vr5000: 585*r3900: 586{ 587 do_addiu (SD_, RS, RT, IMMEDIATE); 588} 589 590 591 592:function:::void:do_addu:int rs, int rt, int rd 593{ 594 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 595 Unpredictable (); 596 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 597 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]); 598 TRACE_ALU_RESULT (GPR[rd]); 599} 600 601000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU 602"addu r<RD>, r<RS>, r<RT>" 603*mipsI: 604*mipsII: 605*mipsIII: 606*mipsIV: 607*mipsV: 608*mips32: 609*mips32r2: 610*mips64: 611*mips64r2: 612*vr4100: 613*vr5000: 614*r3900: 615{ 616 do_addu (SD_, RS, RT, RD); 617} 618 619 620 621:function:::void:do_and:int rs, int rt, int rd 622{ 623 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 624 GPR[rd] = GPR[rs] & GPR[rt]; 625 TRACE_ALU_RESULT (GPR[rd]); 626} 627 628000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND 629"and r<RD>, r<RS>, r<RT>" 630*mipsI: 631*mipsII: 632*mipsIII: 633*mipsIV: 634*mipsV: 635*mips32: 636*mips32r2: 637*mips64: 638*mips64r2: 639*vr4100: 640*vr5000: 641*r3900: 642{ 643 do_and (SD_, RS, RT, RD); 644} 645 646 647 648001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI 649"andi r<RT>, r<RS>, %#lx<IMMEDIATE>" 650*mipsI: 651*mipsII: 652*mipsIII: 653*mipsIV: 654*mipsV: 655*mips32: 656*mips32r2: 657*mips64: 658*mips64r2: 659*vr4100: 660*vr5000: 661*r3900: 662{ 663 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE); 664 GPR[RT] = GPR[RS] & IMMEDIATE; 665 TRACE_ALU_RESULT (GPR[RT]); 666} 667 668 669 670000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ 671"beq r<RS>, r<RT>, <OFFSET>" 672*mipsI: 673*mipsII: 674*mipsIII: 675*mipsIV: 676*mipsV: 677*mips32: 678*mips32r2: 679*mips64: 680*mips64r2: 681*vr4100: 682*vr5000: 683*r3900: 684{ 685 address_word offset = EXTEND16 (OFFSET) << 2; 686 if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) 687 { 688 DELAY_SLOT (NIA + offset); 689 } 690} 691 692 693 694010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL 695"beql r<RS>, r<RT>, <OFFSET>" 696*mipsII: 697*mipsIII: 698*mipsIV: 699*mipsV: 700*mips32: 701*mips32r2: 702*mips64: 703*mips64r2: 704*vr4100: 705*vr5000: 706*r3900: 707{ 708 address_word offset = EXTEND16 (OFFSET) << 2; 709 if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) 710 { 711 DELAY_SLOT (NIA + offset); 712 } 713 else 714 NULLIFY_NEXT_INSTRUCTION (); 715} 716 717 718 719000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ 720"bgez r<RS>, <OFFSET>" 721*mipsI: 722*mipsII: 723*mipsIII: 724*mipsIV: 725*mipsV: 726*mips32: 727*mips32r2: 728*mips64: 729*mips64r2: 730*vr4100: 731*vr5000: 732*r3900: 733{ 734 address_word offset = EXTEND16 (OFFSET) << 2; 735 if ((signed_word) GPR[RS] >= 0) 736 { 737 DELAY_SLOT (NIA + offset); 738 } 739} 740 741 742 743000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL 744"bgezal r<RS>, <OFFSET>" 745*mipsI: 746*mipsII: 747*mipsIII: 748*mipsIV: 749*mipsV: 750*mips32: 751*mips32r2: 752*mips64: 753*mips64r2: 754*vr4100: 755*vr5000: 756*r3900: 757{ 758 address_word offset = EXTEND16 (OFFSET) << 2; 759 if (RS == 31) 760 Unpredictable (); 761 RA = (CIA + 8); 762 if ((signed_word) GPR[RS] >= 0) 763 { 764 DELAY_SLOT (NIA + offset); 765 } 766} 767 768 769 770000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL 771"bgezall r<RS>, <OFFSET>" 772*mipsII: 773*mipsIII: 774*mipsIV: 775*mipsV: 776*mips32: 777*mips32r2: 778*mips64: 779*mips64r2: 780*vr4100: 781*vr5000: 782*r3900: 783{ 784 address_word offset = EXTEND16 (OFFSET) << 2; 785 if (RS == 31) 786 Unpredictable (); 787 RA = (CIA + 8); 788 /* NOTE: The branch occurs AFTER the next instruction has been 789 executed */ 790 if ((signed_word) GPR[RS] >= 0) 791 { 792 DELAY_SLOT (NIA + offset); 793 } 794 else 795 NULLIFY_NEXT_INSTRUCTION (); 796} 797 798 799 800000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL 801"bgezl r<RS>, <OFFSET>" 802*mipsII: 803*mipsIII: 804*mipsIV: 805*mipsV: 806*mips32: 807*mips32r2: 808*mips64: 809*mips64r2: 810*vr4100: 811*vr5000: 812*r3900: 813{ 814 address_word offset = EXTEND16 (OFFSET) << 2; 815 if ((signed_word) GPR[RS] >= 0) 816 { 817 DELAY_SLOT (NIA + offset); 818 } 819 else 820 NULLIFY_NEXT_INSTRUCTION (); 821} 822 823 824 825000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ 826"bgtz r<RS>, <OFFSET>" 827*mipsI: 828*mipsII: 829*mipsIII: 830*mipsIV: 831*mipsV: 832*mips32: 833*mips32r2: 834*mips64: 835*mips64r2: 836*vr4100: 837*vr5000: 838*r3900: 839{ 840 address_word offset = EXTEND16 (OFFSET) << 2; 841 if ((signed_word) GPR[RS] > 0) 842 { 843 DELAY_SLOT (NIA + offset); 844 } 845} 846 847 848 849010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL 850"bgtzl r<RS>, <OFFSET>" 851*mipsII: 852*mipsIII: 853*mipsIV: 854*mipsV: 855*mips32: 856*mips32r2: 857*mips64: 858*mips64r2: 859*vr4100: 860*vr5000: 861*r3900: 862{ 863 address_word offset = EXTEND16 (OFFSET) << 2; 864 /* NOTE: The branch occurs AFTER the next instruction has been 865 executed */ 866 if ((signed_word) GPR[RS] > 0) 867 { 868 DELAY_SLOT (NIA + offset); 869 } 870 else 871 NULLIFY_NEXT_INSTRUCTION (); 872} 873 874 875 876000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ 877"blez r<RS>, <OFFSET>" 878*mipsI: 879*mipsII: 880*mipsIII: 881*mipsIV: 882*mipsV: 883*mips32: 884*mips32r2: 885*mips64: 886*mips64r2: 887*vr4100: 888*vr5000: 889*r3900: 890{ 891 address_word offset = EXTEND16 (OFFSET) << 2; 892 /* NOTE: The branch occurs AFTER the next instruction has been 893 executed */ 894 if ((signed_word) GPR[RS] <= 0) 895 { 896 DELAY_SLOT (NIA + offset); 897 } 898} 899 900 901 902010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL 903"bgezl r<RS>, <OFFSET>" 904*mipsII: 905*mipsIII: 906*mipsIV: 907*mipsV: 908*mips32: 909*mips32r2: 910*mips64: 911*mips64r2: 912*vr4100: 913*vr5000: 914*r3900: 915{ 916 address_word offset = EXTEND16 (OFFSET) << 2; 917 if ((signed_word) GPR[RS] <= 0) 918 { 919 DELAY_SLOT (NIA + offset); 920 } 921 else 922 NULLIFY_NEXT_INSTRUCTION (); 923} 924 925 926 927000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ 928"bltz r<RS>, <OFFSET>" 929*mipsI: 930*mipsII: 931*mipsIII: 932*mipsIV: 933*mipsV: 934*mips32: 935*mips32r2: 936*mips64: 937*mips64r2: 938*vr4100: 939*vr5000: 940*r3900: 941{ 942 address_word offset = EXTEND16 (OFFSET) << 2; 943 if ((signed_word) GPR[RS] < 0) 944 { 945 DELAY_SLOT (NIA + offset); 946 } 947} 948 949 950 951000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL 952"bltzal r<RS>, <OFFSET>" 953*mipsI: 954*mipsII: 955*mipsIII: 956*mipsIV: 957*mipsV: 958*mips32: 959*mips32r2: 960*mips64: 961*mips64r2: 962*vr4100: 963*vr5000: 964*r3900: 965{ 966 address_word offset = EXTEND16 (OFFSET) << 2; 967 if (RS == 31) 968 Unpredictable (); 969 RA = (CIA + 8); 970 /* NOTE: The branch occurs AFTER the next instruction has been 971 executed */ 972 if ((signed_word) GPR[RS] < 0) 973 { 974 DELAY_SLOT (NIA + offset); 975 } 976} 977 978 979 980000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL 981"bltzall r<RS>, <OFFSET>" 982*mipsII: 983*mipsIII: 984*mipsIV: 985*mipsV: 986*mips32: 987*mips32r2: 988*mips64: 989*mips64r2: 990*vr4100: 991*vr5000: 992*r3900: 993{ 994 address_word offset = EXTEND16 (OFFSET) << 2; 995 if (RS == 31) 996 Unpredictable (); 997 RA = (CIA + 8); 998 if ((signed_word) GPR[RS] < 0) 999 { 1000 DELAY_SLOT (NIA + offset); 1001 } 1002 else 1003 NULLIFY_NEXT_INSTRUCTION (); 1004} 1005 1006 1007 1008000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL 1009"bltzl r<RS>, <OFFSET>" 1010*mipsII: 1011*mipsIII: 1012*mipsIV: 1013*mipsV: 1014*mips32: 1015*mips32r2: 1016*mips64: 1017*mips64r2: 1018*vr4100: 1019*vr5000: 1020*r3900: 1021{ 1022 address_word offset = EXTEND16 (OFFSET) << 2; 1023 /* NOTE: The branch occurs AFTER the next instruction has been 1024 executed */ 1025 if ((signed_word) GPR[RS] < 0) 1026 { 1027 DELAY_SLOT (NIA + offset); 1028 } 1029 else 1030 NULLIFY_NEXT_INSTRUCTION (); 1031} 1032 1033 1034 1035000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE 1036"bne r<RS>, r<RT>, <OFFSET>" 1037*mipsI: 1038*mipsII: 1039*mipsIII: 1040*mipsIV: 1041*mipsV: 1042*mips32: 1043*mips32r2: 1044*mips64: 1045*mips64r2: 1046*vr4100: 1047*vr5000: 1048*r3900: 1049{ 1050 address_word offset = EXTEND16 (OFFSET) << 2; 1051 if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) 1052 { 1053 DELAY_SLOT (NIA + offset); 1054 } 1055} 1056 1057 1058 1059010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL 1060"bnel r<RS>, r<RT>, <OFFSET>" 1061*mipsII: 1062*mipsIII: 1063*mipsIV: 1064*mipsV: 1065*mips32: 1066*mips32r2: 1067*mips64: 1068*mips64r2: 1069*vr4100: 1070*vr5000: 1071*r3900: 1072{ 1073 address_word offset = EXTEND16 (OFFSET) << 2; 1074 if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) 1075 { 1076 DELAY_SLOT (NIA + offset); 1077 } 1078 else 1079 NULLIFY_NEXT_INSTRUCTION (); 1080} 1081 1082 1083 1084000000,20.CODE,001101:SPECIAL:32::BREAK 1085"break %#lx<CODE>" 1086*mipsI: 1087*mipsII: 1088*mipsIII: 1089*mipsIV: 1090*mipsV: 1091*mips32: 1092*mips32r2: 1093*mips64: 1094*mips64r2: 1095*vr4100: 1096*vr5000: 1097*r3900: 1098{ 1099 /* Check for some break instruction which are reserved for use by the simulator. */ 1100 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK; 1101 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) || 1102 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) 1103 { 1104 sim_engine_halt (SD, CPU, NULL, cia, 1105 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); 1106 } 1107 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) || 1108 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) 1109 { 1110 if (STATE & simDELAYSLOT) 1111 PC = cia - 4; /* reference the branch instruction */ 1112 else 1113 PC = cia; 1114 SignalException (BreakPoint, instruction_0); 1115 } 1116 1117 else 1118 { 1119 /* If we get this far, we're not an instruction reserved by the sim. Raise 1120 the exception. */ 1121 SignalException (BreakPoint, instruction_0); 1122 } 1123} 1124 1125 1126 1127011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO 1128"clo r<RD>, r<RS>" 1129*mips32: 1130*mips32r2: 1131*mips64: 1132*mips64r2: 1133*vr5500: 1134{ 1135 unsigned32 temp = GPR[RS]; 1136 unsigned32 i, mask; 1137 if (RT != RD) 1138 Unpredictable (); 1139 if (NotWordValue (GPR[RS])) 1140 Unpredictable (); 1141 TRACE_ALU_INPUT1 (GPR[RS]); 1142 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i) 1143 { 1144 if ((temp & mask) == 0) 1145 break; 1146 mask >>= 1; 1147 } 1148 GPR[RD] = EXTEND32 (i); 1149 TRACE_ALU_RESULT (GPR[RD]); 1150} 1151 1152 1153 1154011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ 1155"clz r<RD>, r<RS>" 1156*mips32: 1157*mips32r2: 1158*mips64: 1159*mips64r2: 1160*vr5500: 1161{ 1162 unsigned32 temp = GPR[RS]; 1163 unsigned32 i, mask; 1164 if (RT != RD) 1165 Unpredictable (); 1166 if (NotWordValue (GPR[RS])) 1167 Unpredictable (); 1168 TRACE_ALU_INPUT1 (GPR[RS]); 1169 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i) 1170 { 1171 if ((temp & mask) != 0) 1172 break; 1173 mask >>= 1; 1174 } 1175 GPR[RD] = EXTEND32 (i); 1176 TRACE_ALU_RESULT (GPR[RD]); 1177} 1178 1179 1180 1181000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD 1182"dadd r<RD>, r<RS>, r<RT>" 1183*mipsIII: 1184*mipsIV: 1185*mipsV: 1186*mips64: 1187*mips64r2: 1188*vr4100: 1189*vr5000: 1190{ 1191 check_u64 (SD_, instruction_0); 1192 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 1193 { 1194 ALU64_BEGIN (GPR[RS]); 1195 ALU64_ADD (GPR[RT]); 1196 ALU64_END (GPR[RD]); /* This checks for overflow. */ 1197 } 1198 TRACE_ALU_RESULT (GPR[RD]); 1199} 1200 1201 1202 1203011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI 1204"daddi r<RT>, r<RS>, <IMMEDIATE>" 1205*mipsIII: 1206*mipsIV: 1207*mipsV: 1208*mips64: 1209*mips64r2: 1210*vr4100: 1211*vr5000: 1212{ 1213 check_u64 (SD_, instruction_0); 1214 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); 1215 { 1216 ALU64_BEGIN (GPR[RS]); 1217 ALU64_ADD (EXTEND16 (IMMEDIATE)); 1218 ALU64_END (GPR[RT]); /* This checks for overflow. */ 1219 } 1220 TRACE_ALU_RESULT (GPR[RT]); 1221} 1222 1223 1224 1225:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate 1226{ 1227 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); 1228 GPR[rt] = GPR[rs] + EXTEND16 (immediate); 1229 TRACE_ALU_RESULT (GPR[rt]); 1230} 1231 1232011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU 1233"daddiu r<RT>, r<RS>, <IMMEDIATE>" 1234*mipsIII: 1235*mipsIV: 1236*mipsV: 1237*mips64: 1238*mips64r2: 1239*vr4100: 1240*vr5000: 1241{ 1242 check_u64 (SD_, instruction_0); 1243 do_daddiu (SD_, RS, RT, IMMEDIATE); 1244} 1245 1246 1247 1248:function:::void:do_daddu:int rs, int rt, int rd 1249{ 1250 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1251 GPR[rd] = GPR[rs] + GPR[rt]; 1252 TRACE_ALU_RESULT (GPR[rd]); 1253} 1254 1255000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU 1256"daddu r<RD>, r<RS>, r<RT>" 1257*mipsIII: 1258*mipsIV: 1259*mipsV: 1260*mips64: 1261*mips64r2: 1262*vr4100: 1263*vr5000: 1264{ 1265 check_u64 (SD_, instruction_0); 1266 do_daddu (SD_, RS, RT, RD); 1267} 1268 1269 1270 1271011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO 1272"dclo r<RD>, r<RS>" 1273*mips64: 1274*mips64r2: 1275*vr5500: 1276{ 1277 unsigned64 temp = GPR[RS]; 1278 unsigned32 i; 1279 unsigned64 mask; 1280 check_u64 (SD_, instruction_0); 1281 if (RT != RD) 1282 Unpredictable (); 1283 TRACE_ALU_INPUT1 (GPR[RS]); 1284 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i) 1285 { 1286 if ((temp & mask) == 0) 1287 break; 1288 mask >>= 1; 1289 } 1290 GPR[RD] = EXTEND32 (i); 1291 TRACE_ALU_RESULT (GPR[RD]); 1292} 1293 1294 1295 1296011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ 1297"dclz r<RD>, r<RS>" 1298*mips64: 1299*mips64r2: 1300*vr5500: 1301{ 1302 unsigned64 temp = GPR[RS]; 1303 unsigned32 i; 1304 unsigned64 mask; 1305 check_u64 (SD_, instruction_0); 1306 if (RT != RD) 1307 Unpredictable (); 1308 TRACE_ALU_INPUT1 (GPR[RS]); 1309 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i) 1310 { 1311 if ((temp & mask) != 0) 1312 break; 1313 mask >>= 1; 1314 } 1315 GPR[RD] = EXTEND32 (i); 1316 TRACE_ALU_RESULT (GPR[RD]); 1317} 1318 1319 1320 1321:function:::void:do_ddiv:int rs, int rt 1322{ 1323 check_div_hilo (SD_, HIHISTORY, LOHISTORY); 1324 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1325 { 1326 signed64 n = GPR[rs]; 1327 signed64 d = GPR[rt]; 1328 signed64 hi; 1329 signed64 lo; 1330 if (d == 0) 1331 { 1332 lo = SIGNED64 (0x8000000000000000); 1333 hi = 0; 1334 } 1335 else if (d == -1 && n == SIGNED64 (0x8000000000000000)) 1336 { 1337 lo = SIGNED64 (0x8000000000000000); 1338 hi = 0; 1339 } 1340 else 1341 { 1342 lo = (n / d); 1343 hi = (n % d); 1344 } 1345 HI = hi; 1346 LO = lo; 1347 } 1348 TRACE_ALU_RESULT2 (HI, LO); 1349} 1350 1351000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV 1352"ddiv r<RS>, r<RT>" 1353*mipsIII: 1354*mipsIV: 1355*mipsV: 1356*mips64: 1357*mips64r2: 1358*vr4100: 1359*vr5000: 1360{ 1361 check_u64 (SD_, instruction_0); 1362 do_ddiv (SD_, RS, RT); 1363} 1364 1365 1366 1367:function:::void:do_ddivu:int rs, int rt 1368{ 1369 check_div_hilo (SD_, HIHISTORY, LOHISTORY); 1370 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1371 { 1372 unsigned64 n = GPR[rs]; 1373 unsigned64 d = GPR[rt]; 1374 unsigned64 hi; 1375 unsigned64 lo; 1376 if (d == 0) 1377 { 1378 lo = SIGNED64 (0x8000000000000000); 1379 hi = 0; 1380 } 1381 else 1382 { 1383 lo = (n / d); 1384 hi = (n % d); 1385 } 1386 HI = hi; 1387 LO = lo; 1388 } 1389 TRACE_ALU_RESULT2 (HI, LO); 1390} 1391 1392000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU 1393"ddivu r<RS>, r<RT>" 1394*mipsIII: 1395*mipsIV: 1396*mipsV: 1397*mips64: 1398*mips64r2: 1399*vr4100: 1400*vr5000: 1401{ 1402 check_u64 (SD_, instruction_0); 1403 do_ddivu (SD_, RS, RT); 1404} 1405 1406:function:::void:do_div:int rs, int rt 1407{ 1408 check_div_hilo (SD_, HIHISTORY, LOHISTORY); 1409 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1410 { 1411 signed32 n = GPR[rs]; 1412 signed32 d = GPR[rt]; 1413 if (d == 0) 1414 { 1415 LO = EXTEND32 (0x80000000); 1416 HI = EXTEND32 (0); 1417 } 1418 else if (n == SIGNED32 (0x80000000) && d == -1) 1419 { 1420 LO = EXTEND32 (0x80000000); 1421 HI = EXTEND32 (0); 1422 } 1423 else 1424 { 1425 LO = EXTEND32 (n / d); 1426 HI = EXTEND32 (n % d); 1427 } 1428 } 1429 TRACE_ALU_RESULT2 (HI, LO); 1430} 1431 1432000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV 1433"div r<RS>, r<RT>" 1434*mipsI: 1435*mipsII: 1436*mipsIII: 1437*mipsIV: 1438*mipsV: 1439*mips32: 1440*mips32r2: 1441*mips64: 1442*mips64r2: 1443*vr4100: 1444*vr5000: 1445*r3900: 1446{ 1447 do_div (SD_, RS, RT); 1448} 1449 1450 1451 1452:function:::void:do_divu:int rs, int rt 1453{ 1454 check_div_hilo (SD_, HIHISTORY, LOHISTORY); 1455 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1456 { 1457 unsigned32 n = GPR[rs]; 1458 unsigned32 d = GPR[rt]; 1459 if (d == 0) 1460 { 1461 LO = EXTEND32 (0x80000000); 1462 HI = EXTEND32 (0); 1463 } 1464 else 1465 { 1466 LO = EXTEND32 (n / d); 1467 HI = EXTEND32 (n % d); 1468 } 1469 } 1470 TRACE_ALU_RESULT2 (HI, LO); 1471} 1472 1473000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU 1474"divu r<RS>, r<RT>" 1475*mipsI: 1476*mipsII: 1477*mipsIII: 1478*mipsIV: 1479*mipsV: 1480*mips32: 1481*mips32r2: 1482*mips64: 1483*mips64r2: 1484*vr4100: 1485*vr5000: 1486*r3900: 1487{ 1488 do_divu (SD_, RS, RT); 1489} 1490 1491 1492:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p 1493{ 1494 unsigned64 lo; 1495 unsigned64 hi; 1496 unsigned64 m00; 1497 unsigned64 m01; 1498 unsigned64 m10; 1499 unsigned64 m11; 1500 unsigned64 mid; 1501 int sign; 1502 unsigned64 op1 = GPR[rs]; 1503 unsigned64 op2 = GPR[rt]; 1504 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 1505 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1506 /* make signed multiply unsigned */ 1507 sign = 0; 1508 if (signed_p) 1509 { 1510 if ((signed64) op1 < 0) 1511 { 1512 op1 = - op1; 1513 ++sign; 1514 } 1515 if ((signed64) op2 < 0) 1516 { 1517 op2 = - op2; 1518 ++sign; 1519 } 1520 } 1521 /* multiply out the 4 sub products */ 1522 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2)); 1523 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2)); 1524 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2)); 1525 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2)); 1526 /* add the products */ 1527 mid = ((unsigned64) VH4_8 (m00) 1528 + (unsigned64) VL4_8 (m10) 1529 + (unsigned64) VL4_8 (m01)); 1530 lo = U8_4 (mid, m00); 1531 hi = (m11 1532 + (unsigned64) VH4_8 (mid) 1533 + (unsigned64) VH4_8 (m01) 1534 + (unsigned64) VH4_8 (m10)); 1535 /* fix the sign */ 1536 if (sign & 1) 1537 { 1538 lo = -lo; 1539 if (lo == 0) 1540 hi = -hi; 1541 else 1542 hi = -hi - 1; 1543 } 1544 /* save the result HI/LO (and a gpr) */ 1545 LO = lo; 1546 HI = hi; 1547 if (rd != 0) 1548 GPR[rd] = lo; 1549 TRACE_ALU_RESULT2 (HI, LO); 1550} 1551 1552:function:::void:do_dmult:int rs, int rt, int rd 1553{ 1554 do_dmultx (SD_, rs, rt, rd, 1); 1555} 1556 1557000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT 1558"dmult r<RS>, r<RT>" 1559*mipsIII: 1560*mipsIV: 1561*mipsV: 1562*mips64: 1563*mips64r2: 1564*vr4100: 1565{ 1566 check_u64 (SD_, instruction_0); 1567 do_dmult (SD_, RS, RT, 0); 1568} 1569 1570000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT 1571"dmult r<RS>, r<RT>":RD == 0 1572"dmult r<RD>, r<RS>, r<RT>" 1573*vr5000: 1574{ 1575 check_u64 (SD_, instruction_0); 1576 do_dmult (SD_, RS, RT, RD); 1577} 1578 1579 1580 1581:function:::void:do_dmultu:int rs, int rt, int rd 1582{ 1583 do_dmultx (SD_, rs, rt, rd, 0); 1584} 1585 1586000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU 1587"dmultu r<RS>, r<RT>" 1588*mipsIII: 1589*mipsIV: 1590*mipsV: 1591*mips64: 1592*mips64r2: 1593*vr4100: 1594{ 1595 check_u64 (SD_, instruction_0); 1596 do_dmultu (SD_, RS, RT, 0); 1597} 1598 1599000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU 1600"dmultu r<RD>, r<RS>, r<RT>":RD == 0 1601"dmultu r<RS>, r<RT>" 1602*vr5000: 1603{ 1604 check_u64 (SD_, instruction_0); 1605 do_dmultu (SD_, RS, RT, RD); 1606} 1607 1608 1609:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y 1610{ 1611 unsigned64 result; 1612 1613 y &= 63; 1614 TRACE_ALU_INPUT2 (x, y); 1615 result = ROTR64 (x, y); 1616 TRACE_ALU_RESULT (result); 1617 return result; 1618} 1619 1620000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR 1621"dror r<RD>, r<RT>, <SHIFT>" 1622*mips64r2: 1623*vr5400: 1624*vr5500: 1625{ 1626 check_u64 (SD_, instruction_0); 1627 GPR[RD] = do_dror (SD_, GPR[RT], SHIFT); 1628} 1629 1630000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32 1631"dror32 r<RD>, r<RT>, <SHIFT>" 1632*mips64r2: 1633*vr5400: 1634*vr5500: 1635{ 1636 check_u64 (SD_, instruction_0); 1637 GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32); 1638} 1639 1640000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV 1641"drorv r<RD>, r<RT>, r<RS>" 1642*mips64r2: 1643*vr5400: 1644*vr5500: 1645{ 1646 check_u64 (SD_, instruction_0); 1647 GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]); 1648} 1649 1650 1651:function:::void:do_dsll:int rt, int rd, int shift 1652{ 1653 TRACE_ALU_INPUT2 (GPR[rt], shift); 1654 GPR[rd] = GPR[rt] << shift; 1655 TRACE_ALU_RESULT (GPR[rd]); 1656} 1657 1658000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL 1659"dsll r<RD>, r<RT>, <SHIFT>" 1660*mipsIII: 1661*mipsIV: 1662*mipsV: 1663*mips64: 1664*mips64r2: 1665*vr4100: 1666*vr5000: 1667{ 1668 check_u64 (SD_, instruction_0); 1669 do_dsll (SD_, RT, RD, SHIFT); 1670} 1671 1672 1673000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32 1674"dsll32 r<RD>, r<RT>, <SHIFT>" 1675*mipsIII: 1676*mipsIV: 1677*mipsV: 1678*mips64: 1679*mips64r2: 1680*vr4100: 1681*vr5000: 1682{ 1683 int s = 32 + SHIFT; 1684 check_u64 (SD_, instruction_0); 1685 TRACE_ALU_INPUT2 (GPR[RT], s); 1686 GPR[RD] = GPR[RT] << s; 1687 TRACE_ALU_RESULT (GPR[RD]); 1688} 1689 1690:function:::void:do_dsllv:int rs, int rt, int rd 1691{ 1692 int s = MASKED64 (GPR[rs], 5, 0); 1693 TRACE_ALU_INPUT2 (GPR[rt], s); 1694 GPR[rd] = GPR[rt] << s; 1695 TRACE_ALU_RESULT (GPR[rd]); 1696} 1697 1698000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV 1699"dsllv r<RD>, r<RT>, r<RS>" 1700*mipsIII: 1701*mipsIV: 1702*mipsV: 1703*mips64: 1704*mips64r2: 1705*vr4100: 1706*vr5000: 1707{ 1708 check_u64 (SD_, instruction_0); 1709 do_dsllv (SD_, RS, RT, RD); 1710} 1711 1712:function:::void:do_dsra:int rt, int rd, int shift 1713{ 1714 TRACE_ALU_INPUT2 (GPR[rt], shift); 1715 GPR[rd] = ((signed64) GPR[rt]) >> shift; 1716 TRACE_ALU_RESULT (GPR[rd]); 1717} 1718 1719 1720000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA 1721"dsra r<RD>, r<RT>, <SHIFT>" 1722*mipsIII: 1723*mipsIV: 1724*mipsV: 1725*mips64: 1726*mips64r2: 1727*vr4100: 1728*vr5000: 1729{ 1730 check_u64 (SD_, instruction_0); 1731 do_dsra (SD_, RT, RD, SHIFT); 1732} 1733 1734 1735000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32 1736"dsra32 r<RD>, r<RT>, <SHIFT>" 1737*mipsIII: 1738*mipsIV: 1739*mipsV: 1740*mips64: 1741*mips64r2: 1742*vr4100: 1743*vr5000: 1744{ 1745 int s = 32 + SHIFT; 1746 check_u64 (SD_, instruction_0); 1747 TRACE_ALU_INPUT2 (GPR[RT], s); 1748 GPR[RD] = ((signed64) GPR[RT]) >> s; 1749 TRACE_ALU_RESULT (GPR[RD]); 1750} 1751 1752 1753:function:::void:do_dsrav:int rs, int rt, int rd 1754{ 1755 int s = MASKED64 (GPR[rs], 5, 0); 1756 TRACE_ALU_INPUT2 (GPR[rt], s); 1757 GPR[rd] = ((signed64) GPR[rt]) >> s; 1758 TRACE_ALU_RESULT (GPR[rd]); 1759} 1760 1761000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV 1762"dsrav r<RD>, r<RT>, r<RS>" 1763*mipsIII: 1764*mipsIV: 1765*mipsV: 1766*mips64: 1767*mips64r2: 1768*vr4100: 1769*vr5000: 1770{ 1771 check_u64 (SD_, instruction_0); 1772 do_dsrav (SD_, RS, RT, RD); 1773} 1774 1775:function:::void:do_dsrl:int rt, int rd, int shift 1776{ 1777 TRACE_ALU_INPUT2 (GPR[rt], shift); 1778 GPR[rd] = (unsigned64) GPR[rt] >> shift; 1779 TRACE_ALU_RESULT (GPR[rd]); 1780} 1781 1782 1783000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL 1784"dsrl r<RD>, r<RT>, <SHIFT>" 1785*mipsIII: 1786*mipsIV: 1787*mipsV: 1788*mips64: 1789*mips64r2: 1790*vr4100: 1791*vr5000: 1792{ 1793 check_u64 (SD_, instruction_0); 1794 do_dsrl (SD_, RT, RD, SHIFT); 1795} 1796 1797 1798000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32 1799"dsrl32 r<RD>, r<RT>, <SHIFT>" 1800*mipsIII: 1801*mipsIV: 1802*mipsV: 1803*mips64: 1804*mips64r2: 1805*vr4100: 1806*vr5000: 1807{ 1808 int s = 32 + SHIFT; 1809 check_u64 (SD_, instruction_0); 1810 TRACE_ALU_INPUT2 (GPR[RT], s); 1811 GPR[RD] = (unsigned64) GPR[RT] >> s; 1812 TRACE_ALU_RESULT (GPR[RD]); 1813} 1814 1815 1816:function:::void:do_dsrlv:int rs, int rt, int rd 1817{ 1818 int s = MASKED64 (GPR[rs], 5, 0); 1819 TRACE_ALU_INPUT2 (GPR[rt], s); 1820 GPR[rd] = (unsigned64) GPR[rt] >> s; 1821 TRACE_ALU_RESULT (GPR[rd]); 1822} 1823 1824 1825 1826000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV 1827"dsrlv r<RD>, r<RT>, r<RS>" 1828*mipsIII: 1829*mipsIV: 1830*mipsV: 1831*mips64: 1832*mips64r2: 1833*vr4100: 1834*vr5000: 1835{ 1836 check_u64 (SD_, instruction_0); 1837 do_dsrlv (SD_, RS, RT, RD); 1838} 1839 1840 1841000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB 1842"dsub r<RD>, r<RS>, r<RT>" 1843*mipsIII: 1844*mipsIV: 1845*mipsV: 1846*mips64: 1847*mips64r2: 1848*vr4100: 1849*vr5000: 1850{ 1851 check_u64 (SD_, instruction_0); 1852 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 1853 { 1854 ALU64_BEGIN (GPR[RS]); 1855 ALU64_SUB (GPR[RT]); 1856 ALU64_END (GPR[RD]); /* This checks for overflow. */ 1857 } 1858 TRACE_ALU_RESULT (GPR[RD]); 1859} 1860 1861 1862:function:::void:do_dsubu:int rs, int rt, int rd 1863{ 1864 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1865 GPR[rd] = GPR[rs] - GPR[rt]; 1866 TRACE_ALU_RESULT (GPR[rd]); 1867} 1868 1869000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU 1870"dsubu r<RD>, r<RS>, r<RT>" 1871*mipsIII: 1872*mipsIV: 1873*mipsV: 1874*mips64: 1875*mips64r2: 1876*vr4100: 1877*vr5000: 1878{ 1879 check_u64 (SD_, instruction_0); 1880 do_dsubu (SD_, RS, RT, RD); 1881} 1882 1883 1884000010,26.INSTR_INDEX:NORMAL:32::J 1885"j <INSTR_INDEX>" 1886*mipsI: 1887*mipsII: 1888*mipsIII: 1889*mipsIV: 1890*mipsV: 1891*mips32: 1892*mips32r2: 1893*mips64: 1894*mips64r2: 1895*vr4100: 1896*vr5000: 1897*r3900: 1898{ 1899 /* NOTE: The region used is that of the delay slot NIA and NOT the 1900 current instruction */ 1901 address_word region = (NIA & MASK (63, 28)); 1902 DELAY_SLOT (region | (INSTR_INDEX << 2)); 1903} 1904 1905 1906000011,26.INSTR_INDEX:NORMAL:32::JAL 1907"jal <INSTR_INDEX>" 1908*mipsI: 1909*mipsII: 1910*mipsIII: 1911*mipsIV: 1912*mipsV: 1913*mips32: 1914*mips32r2: 1915*mips64: 1916*mips64r2: 1917*vr4100: 1918*vr5000: 1919*r3900: 1920{ 1921 /* NOTE: The region used is that of the delay slot and NOT the 1922 current instruction */ 1923 address_word region = (NIA & MASK (63, 28)); 1924 GPR[31] = CIA + 8; 1925 DELAY_SLOT (region | (INSTR_INDEX << 2)); 1926} 1927 1928000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR 1929"jalr r<RS>":RD == 31 1930"jalr r<RD>, r<RS>" 1931*mipsI: 1932*mipsII: 1933*mipsIII: 1934*mipsIV: 1935*mipsV: 1936*mips32: 1937*mips32r2: 1938*mips64: 1939*mips64r2: 1940*vr4100: 1941*vr5000: 1942*r3900: 1943{ 1944 address_word temp = GPR[RS]; 1945 GPR[RD] = CIA + 8; 1946 DELAY_SLOT (temp); 1947} 1948 1949000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB 1950"jalr.hb r<RS>":RD == 31 1951"jalr.hb r<RD>, r<RS>" 1952*mips32r2: 1953*mips64r2: 1954{ 1955 address_word temp = GPR[RS]; 1956 GPR[RD] = CIA + 8; 1957 DELAY_SLOT (temp); 1958} 1959 1960000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR 1961"jr r<RS>" 1962*mipsI: 1963*mipsII: 1964*mipsIII: 1965*mipsIV: 1966*mipsV: 1967*mips32: 1968*mips32r2: 1969*mips64: 1970*mips64r2: 1971*vr4100: 1972*vr5000: 1973*r3900: 1974{ 1975 DELAY_SLOT (GPR[RS]); 1976} 1977 1978000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB 1979"jr.hb r<RS>" 1980*mips32r2: 1981*mips64r2: 1982{ 1983 DELAY_SLOT (GPR[RS]); 1984} 1985 1986:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset 1987{ 1988 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 1989 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); 1990 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); 1991 unsigned int byte; 1992 address_word paddr; 1993 int uncached; 1994 unsigned64 memval; 1995 address_word vaddr; 1996 1997 vaddr = loadstore_ea (SD_, base, offset); 1998 if ((vaddr & access) != 0) 1999 { 2000 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal); 2001 } 2002 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); 2003 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); 2004 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL); 2005 byte = ((vaddr & mask) ^ bigendiancpu); 2006 return (memval >> (8 * byte)); 2007} 2008 2009:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt 2010{ 2011 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 2012 address_word reverseendian = (ReverseEndian ? -1 : 0); 2013 address_word bigendiancpu = (BigEndianCPU ? -1 : 0); 2014 unsigned int byte; 2015 unsigned int word; 2016 address_word paddr; 2017 int uncached; 2018 unsigned64 memval; 2019 address_word vaddr; 2020 int nr_lhs_bits; 2021 int nr_rhs_bits; 2022 unsigned_word lhs_mask; 2023 unsigned_word temp; 2024 2025 vaddr = loadstore_ea (SD_, base, offset); 2026 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); 2027 paddr = (paddr ^ (reverseendian & mask)); 2028 if (BigEndianMem == 0) 2029 paddr = paddr & ~access; 2030 2031 /* compute where within the word/mem we are */ 2032 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */ 2033 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */ 2034 nr_lhs_bits = 8 * byte + 8; 2035 nr_rhs_bits = 8 * access - 8 * byte; 2036 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ 2037 2038 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", 2039 (long) ((unsigned64) vaddr >> 32), (long) vaddr, 2040 (long) ((unsigned64) paddr >> 32), (long) paddr, 2041 word, byte, nr_lhs_bits, nr_rhs_bits); */ 2042 2043 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL); 2044 if (word == 0) 2045 { 2046 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */ 2047 temp = (memval << nr_rhs_bits); 2048 } 2049 else 2050 { 2051 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */ 2052 temp = (memval >> nr_lhs_bits); 2053 } 2054 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits); 2055 rt = (rt & ~lhs_mask) | (temp & lhs_mask); 2056 2057 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n", 2058 (long) ((unsigned64) memval >> 32), (long) memval, 2059 (long) ((unsigned64) temp >> 32), (long) temp, 2060 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask, 2061 (long) (rt >> 32), (long) rt); */ 2062 return rt; 2063} 2064 2065:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt 2066{ 2067 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 2068 address_word reverseendian = (ReverseEndian ? -1 : 0); 2069 address_word bigendiancpu = (BigEndianCPU ? -1 : 0); 2070 unsigned int byte; 2071 address_word paddr; 2072 int uncached; 2073 unsigned64 memval; 2074 address_word vaddr; 2075 2076 vaddr = loadstore_ea (SD_, base, offset); 2077 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); 2078 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */ 2079 paddr = (paddr ^ (reverseendian & mask)); 2080 if (BigEndianMem != 0) 2081 paddr = paddr & ~access; 2082 byte = ((vaddr & mask) ^ (bigendiancpu & mask)); 2083 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */ 2084 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL); 2085 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n", 2086 (long) paddr, byte, (long) paddr, (long) memval); */ 2087 { 2088 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0); 2089 rt &= ~screen; 2090 rt |= (memval >> (8 * byte)) & screen; 2091 } 2092 return rt; 2093} 2094 2095 2096100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB 2097"lb r<RT>, <OFFSET>(r<BASE>)" 2098*mipsI: 2099*mipsII: 2100*mipsIII: 2101*mipsIV: 2102*mipsV: 2103*mips32: 2104*mips32r2: 2105*mips64: 2106*mips64r2: 2107*vr4100: 2108*vr5000: 2109*r3900: 2110{ 2111 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET))); 2112} 2113 2114 2115100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU 2116"lbu r<RT>, <OFFSET>(r<BASE>)" 2117*mipsI: 2118*mipsII: 2119*mipsIII: 2120*mipsIV: 2121*mipsV: 2122*mips32: 2123*mips32r2: 2124*mips64: 2125*mips64r2: 2126*vr4100: 2127*vr5000: 2128*r3900: 2129{ 2130 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)); 2131} 2132 2133 2134110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD 2135"ld r<RT>, <OFFSET>(r<BASE>)" 2136*mipsIII: 2137*mipsIV: 2138*mipsV: 2139*mips64: 2140*mips64r2: 2141*vr4100: 2142*vr5000: 2143{ 2144 check_u64 (SD_, instruction_0); 2145 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); 2146} 2147 2148 21491101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz 2150"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)" 2151*mipsII: 2152*mipsIII: 2153*mipsIV: 2154*mipsV: 2155*mips32: 2156*mips32r2: 2157*mips64: 2158*mips64r2: 2159*vr4100: 2160*vr5000: 2161*r3900: 2162{ 2163 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); 2164} 2165 2166 2167 2168 2169011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL 2170"ldl r<RT>, <OFFSET>(r<BASE>)" 2171*mipsIII: 2172*mipsIV: 2173*mipsV: 2174*mips64: 2175*mips64r2: 2176*vr4100: 2177*vr5000: 2178{ 2179 check_u64 (SD_, instruction_0); 2180 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 2181} 2182 2183 2184011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR 2185"ldr r<RT>, <OFFSET>(r<BASE>)" 2186*mipsIII: 2187*mipsIV: 2188*mipsV: 2189*mips64: 2190*mips64r2: 2191*vr4100: 2192*vr5000: 2193{ 2194 check_u64 (SD_, instruction_0); 2195 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 2196} 2197 2198 2199100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH 2200"lh r<RT>, <OFFSET>(r<BASE>)" 2201*mipsI: 2202*mipsII: 2203*mipsIII: 2204*mipsIV: 2205*mipsV: 2206*mips32: 2207*mips32r2: 2208*mips64: 2209*mips64r2: 2210*vr4100: 2211*vr5000: 2212*r3900: 2213{ 2214 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET))); 2215} 2216 2217 2218100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU 2219"lhu r<RT>, <OFFSET>(r<BASE>)" 2220*mipsI: 2221*mipsII: 2222*mipsIII: 2223*mipsIV: 2224*mipsV: 2225*mips32: 2226*mips32r2: 2227*mips64: 2228*mips64r2: 2229*vr4100: 2230*vr5000: 2231*r3900: 2232{ 2233 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)); 2234} 2235 2236 2237110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL 2238"ll r<RT>, <OFFSET>(r<BASE>)" 2239*mipsII: 2240*mipsIII: 2241*mipsIV: 2242*mipsV: 2243*mips32: 2244*mips32r2: 2245*mips64: 2246*mips64r2: 2247*vr4100: 2248*vr5000: 2249{ 2250 address_word base = GPR[BASE]; 2251 address_word offset = EXTEND16 (OFFSET); 2252 { 2253 address_word vaddr = loadstore_ea (SD_, base, offset); 2254 address_word paddr; 2255 int uncached; 2256 if ((vaddr & 3) != 0) 2257 { 2258 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal); 2259 } 2260 else 2261 { 2262 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) 2263 { 2264 unsigned64 memval = 0; 2265 unsigned64 memval1 = 0; 2266 unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 2267 unsigned int shift = 2; 2268 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); 2269 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); 2270 unsigned int byte; 2271 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); 2272 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); 2273 byte = ((vaddr & mask) ^ (bigend << shift)); 2274 GPR[RT] = EXTEND32 (memval >> (8 * byte)); 2275 LLBIT = 1; 2276 } 2277 } 2278 } 2279} 2280 2281 2282110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD 2283"lld r<RT>, <OFFSET>(r<BASE>)" 2284*mipsIII: 2285*mipsIV: 2286*mipsV: 2287*mips64: 2288*mips64r2: 2289*vr4100: 2290*vr5000: 2291{ 2292 address_word base = GPR[BASE]; 2293 address_word offset = EXTEND16 (OFFSET); 2294 check_u64 (SD_, instruction_0); 2295 { 2296 address_word vaddr = loadstore_ea (SD_, base, offset); 2297 address_word paddr; 2298 int uncached; 2299 if ((vaddr & 7) != 0) 2300 { 2301 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal); 2302 } 2303 else 2304 { 2305 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) 2306 { 2307 unsigned64 memval = 0; 2308 unsigned64 memval1 = 0; 2309 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); 2310 GPR[RT] = memval; 2311 LLBIT = 1; 2312 } 2313 } 2314 } 2315} 2316 2317 2318001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI 2319"lui r<RT>, %#lx<IMMEDIATE>" 2320*mipsI: 2321*mipsII: 2322*mipsIII: 2323*mipsIV: 2324*mipsV: 2325*mips32: 2326*mips32r2: 2327*mips64: 2328*mips64r2: 2329*vr4100: 2330*vr5000: 2331*r3900: 2332{ 2333 TRACE_ALU_INPUT1 (IMMEDIATE); 2334 GPR[RT] = EXTEND32 (IMMEDIATE << 16); 2335 TRACE_ALU_RESULT (GPR[RT]); 2336} 2337 2338 2339100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW 2340"lw r<RT>, <OFFSET>(r<BASE>)" 2341*mipsI: 2342*mipsII: 2343*mipsIII: 2344*mipsIV: 2345*mipsV: 2346*mips32: 2347*mips32r2: 2348*mips64: 2349*mips64r2: 2350*vr4100: 2351*vr5000: 2352*r3900: 2353{ 2354 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); 2355} 2356 2357 23581100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz 2359"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)" 2360*mipsI: 2361*mipsII: 2362*mipsIII: 2363*mipsIV: 2364*mipsV: 2365*mips32: 2366*mips32r2: 2367*mips64: 2368*mips64r2: 2369*vr4100: 2370*vr5000: 2371*r3900: 2372{ 2373 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); 2374} 2375 2376 2377100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL 2378"lwl r<RT>, <OFFSET>(r<BASE>)" 2379*mipsI: 2380*mipsII: 2381*mipsIII: 2382*mipsIV: 2383*mipsV: 2384*mips32: 2385*mips32r2: 2386*mips64: 2387*mips64r2: 2388*vr4100: 2389*vr5000: 2390*r3900: 2391{ 2392 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); 2393} 2394 2395 2396100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR 2397"lwr r<RT>, <OFFSET>(r<BASE>)" 2398*mipsI: 2399*mipsII: 2400*mipsIII: 2401*mipsIV: 2402*mipsV: 2403*mips32: 2404*mips32r2: 2405*mips64: 2406*mips64r2: 2407*vr4100: 2408*vr5000: 2409*r3900: 2410{ 2411 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); 2412} 2413 2414 2415100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU 2416"lwu r<RT>, <OFFSET>(r<BASE>)" 2417*mipsIII: 2418*mipsIV: 2419*mipsV: 2420*mips64: 2421*mips64r2: 2422*vr4100: 2423*vr5000: 2424{ 2425 check_u64 (SD_, instruction_0); 2426 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)); 2427} 2428 2429 2430 2431011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD 2432"madd r<RS>, r<RT>" 2433*mips32: 2434*mips64: 2435*vr5500: 2436{ 2437 signed64 temp; 2438 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 2439 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) 2440 Unpredictable (); 2441 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 2442 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 2443 + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS]))); 2444 LO = EXTEND32 (temp); 2445 HI = EXTEND32 (VH4_8 (temp)); 2446 TRACE_ALU_RESULT2 (HI, LO); 2447} 2448 2449 2450011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD 2451"madd r<RS>, r<RT>":AC == 0 2452"madd ac<AC>, r<RS>, r<RT>" 2453*mips32r2: 2454*mips64r2: 2455*dsp2: 2456{ 2457 signed64 temp; 2458 if (AC == 0) 2459 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 2460 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) 2461 Unpredictable (); 2462 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 2463 temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC))) 2464 + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS]))); 2465 DSPLO(AC) = EXTEND32 (temp); 2466 DSPHI(AC) = EXTEND32 (VH4_8 (temp)); 2467 if (AC == 0) 2468 TRACE_ALU_RESULT2 (HI, LO); 2469} 2470 2471 2472011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU 2473"maddu r<RS>, r<RT>" 2474*mips32: 2475*mips64: 2476*vr5500: 2477{ 2478 unsigned64 temp; 2479 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 2480 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) 2481 Unpredictable (); 2482 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 2483 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 2484 + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); 2485 ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ 2486 LO = EXTEND32 (temp); 2487 HI = EXTEND32 (VH4_8 (temp)); 2488 TRACE_ALU_RESULT2 (HI, LO); 2489} 2490 2491 2492011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU 2493"maddu r<RS>, r<RT>":AC == 0 2494"maddu ac<AC>, r<RS>, r<RT>" 2495*mips32r2: 2496*mips64r2: 2497*dsp2: 2498{ 2499 unsigned64 temp; 2500 if (AC == 0) 2501 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 2502 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) 2503 Unpredictable (); 2504 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 2505 temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC))) 2506 + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); 2507 if (AC == 0) 2508 ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ 2509 DSPLO(AC) = EXTEND32 (temp); 2510 DSPHI(AC) = EXTEND32 (VH4_8 (temp)); 2511 if (AC == 0) 2512 TRACE_ALU_RESULT2 (HI, LO); 2513} 2514 2515 2516:function:::void:do_mfhi:int rd 2517{ 2518 check_mf_hilo (SD_, HIHISTORY, LOHISTORY); 2519 TRACE_ALU_INPUT1 (HI); 2520 GPR[rd] = HI; 2521 TRACE_ALU_RESULT (GPR[rd]); 2522} 2523 2524000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI 2525"mfhi r<RD>" 2526*mipsI: 2527*mipsII: 2528*mipsIII: 2529*mipsIV: 2530*mipsV: 2531*vr4100: 2532*vr5000: 2533*r3900: 2534*mips32: 2535*mips64: 2536{ 2537 do_mfhi (SD_, RD); 2538} 2539 2540 2541000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI 2542"mfhi r<RD>":AC == 0 2543"mfhi r<RD>, ac<AC>" 2544*mips32r2: 2545*mips64r2: 2546*dsp: 2547{ 2548 if (AC == 0) 2549 do_mfhi (SD_, RD); 2550 else 2551 GPR[RD] = DSPHI(AC); 2552} 2553 2554 2555:function:::void:do_mflo:int rd 2556{ 2557 check_mf_hilo (SD_, LOHISTORY, HIHISTORY); 2558 TRACE_ALU_INPUT1 (LO); 2559 GPR[rd] = LO; 2560 TRACE_ALU_RESULT (GPR[rd]); 2561} 2562 2563000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO 2564"mflo r<RD>" 2565*mipsI: 2566*mipsII: 2567*mipsIII: 2568*mipsIV: 2569*mipsV: 2570*vr4100: 2571*vr5000: 2572*r3900: 2573*mips32: 2574*mips64: 2575{ 2576 do_mflo (SD_, RD); 2577} 2578 2579 2580000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO 2581"mflo r<RD>":AC == 0 2582"mflo r<RD>, ac<AC>" 2583*mips32r2: 2584*mips64r2: 2585*dsp: 2586{ 2587 if (AC == 0) 2588 do_mflo (SD_, RD); 2589 else 2590 GPR[RD] = DSPLO(AC); 2591} 2592 2593 2594000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN 2595"movn r<RD>, r<RS>, r<RT>" 2596*mipsIV: 2597*mipsV: 2598*mips32: 2599*mips32r2: 2600*mips64: 2601*mips64r2: 2602*vr5000: 2603{ 2604 if (GPR[RT] != 0) 2605 { 2606 GPR[RD] = GPR[RS]; 2607 TRACE_ALU_RESULT (GPR[RD]); 2608 } 2609} 2610 2611 2612 2613000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ 2614"movz r<RD>, r<RS>, r<RT>" 2615*mipsIV: 2616*mipsV: 2617*mips32: 2618*mips32r2: 2619*mips64: 2620*mips64r2: 2621*vr5000: 2622{ 2623 if (GPR[RT] == 0) 2624 { 2625 GPR[RD] = GPR[RS]; 2626 TRACE_ALU_RESULT (GPR[RD]); 2627 } 2628} 2629 2630 2631 2632011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB 2633"msub r<RS>, r<RT>" 2634*mips32: 2635*mips64: 2636*vr5500: 2637{ 2638 signed64 temp; 2639 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 2640 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) 2641 Unpredictable (); 2642 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 2643 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 2644 - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS]))); 2645 LO = EXTEND32 (temp); 2646 HI = EXTEND32 (VH4_8 (temp)); 2647 TRACE_ALU_RESULT2 (HI, LO); 2648} 2649 2650 2651011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB 2652"msub r<RS>, r<RT>":AC == 0 2653"msub ac<AC>, r<RS>, r<RT>" 2654*mips32r2: 2655*mips64r2: 2656*dsp2: 2657{ 2658 signed64 temp; 2659 if (AC == 0) 2660 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 2661 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) 2662 Unpredictable (); 2663 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 2664 temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC))) 2665 - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS]))); 2666 DSPLO(AC) = EXTEND32 (temp); 2667 DSPHI(AC) = EXTEND32 (VH4_8 (temp)); 2668 if (AC == 0) 2669 TRACE_ALU_RESULT2 (HI, LO); 2670} 2671 2672 2673011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU 2674"msubu r<RS>, r<RT>" 2675*mips32: 2676*mips64: 2677*vr5500: 2678{ 2679 unsigned64 temp; 2680 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 2681 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) 2682 Unpredictable (); 2683 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 2684 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 2685 - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); 2686 LO = EXTEND32 (temp); 2687 HI = EXTEND32 (VH4_8 (temp)); 2688 TRACE_ALU_RESULT2 (HI, LO); 2689} 2690 2691 2692011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU 2693"msubu r<RS>, r<RT>":AC == 0 2694"msubu ac<AC>, r<RS>, r<RT>" 2695*mips32r2: 2696*mips64r2: 2697*dsp2: 2698{ 2699 unsigned64 temp; 2700 if (AC == 0) 2701 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 2702 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) 2703 Unpredictable (); 2704 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 2705 temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC))) 2706 - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); 2707 DSPLO(AC) = EXTEND32 (temp); 2708 DSPHI(AC) = EXTEND32 (VH4_8 (temp)); 2709 if (AC == 0) 2710 TRACE_ALU_RESULT2 (HI, LO); 2711} 2712 2713 2714000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI 2715"mthi r<RS>" 2716*mipsI: 2717*mipsII: 2718*mipsIII: 2719*mipsIV: 2720*mipsV: 2721*vr4100: 2722*vr5000: 2723*r3900: 2724*mips32: 2725*mips64: 2726{ 2727 check_mt_hilo (SD_, HIHISTORY); 2728 HI = GPR[RS]; 2729} 2730 2731 2732000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI 2733"mthi r<RS>":AC == 0 2734"mthi r<RS>, ac<AC>" 2735*mips32r2: 2736*mips64r2: 2737*dsp: 2738{ 2739 if (AC == 0) 2740 check_mt_hilo (SD_, HIHISTORY); 2741 DSPHI(AC) = GPR[RS]; 2742} 2743 2744 2745000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO 2746"mtlo r<RS>" 2747*mipsI: 2748*mipsII: 2749*mipsIII: 2750*mipsIV: 2751*mipsV: 2752*vr4100: 2753*vr5000: 2754*r3900: 2755*mips32: 2756*mips64: 2757{ 2758 check_mt_hilo (SD_, LOHISTORY); 2759 LO = GPR[RS]; 2760} 2761 2762 2763000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO 2764"mtlo r<RS>":AC == 0 2765"mtlo r<RS>, ac<AC>" 2766*mips32r2: 2767*mips64r2: 2768*dsp: 2769{ 2770 if (AC == 0) 2771 check_mt_hilo (SD_, LOHISTORY); 2772 DSPLO(AC) = GPR[RS]; 2773} 2774 2775 2776011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL 2777"mul r<RD>, r<RS>, r<RT>" 2778*mips32: 2779*mips32r2: 2780*mips64: 2781*mips64r2: 2782*vr5500: 2783{ 2784 signed64 prod; 2785 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) 2786 Unpredictable (); 2787 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 2788 prod = (((signed64)(signed32) GPR[RS]) 2789 * ((signed64)(signed32) GPR[RT])); 2790 GPR[RD] = EXTEND32 (VL4_8 (prod)); 2791 TRACE_ALU_RESULT (GPR[RD]); 2792} 2793 2794 2795 2796:function:::void:do_mult:int rs, int rt, int rd 2797{ 2798 signed64 prod; 2799 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 2800 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 2801 Unpredictable (); 2802 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2803 prod = (((signed64)(signed32) GPR[rs]) 2804 * ((signed64)(signed32) GPR[rt])); 2805 LO = EXTEND32 (VL4_8 (prod)); 2806 HI = EXTEND32 (VH4_8 (prod)); 2807 ACX = 0; /* SmartMIPS */ 2808 if (rd != 0) 2809 GPR[rd] = LO; 2810 TRACE_ALU_RESULT2 (HI, LO); 2811} 2812 2813000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT 2814"mult r<RS>, r<RT>" 2815*mipsI: 2816*mipsII: 2817*mipsIII: 2818*mipsIV: 2819*mipsV: 2820*mips32: 2821*mips64: 2822*vr4100: 2823{ 2824 do_mult (SD_, RS, RT, 0); 2825} 2826 2827 2828000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT 2829"mult r<RS>, r<RT>":AC == 0 2830"mult ac<AC>, r<RS>, r<RT>" 2831*mips32r2: 2832*mips64r2: 2833*dsp2: 2834{ 2835 signed64 prod; 2836 if (AC == 0) 2837 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 2838 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) 2839 Unpredictable (); 2840 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 2841 prod = ((signed64)(signed32) GPR[RS]) 2842 * ((signed64)(signed32) GPR[RT]); 2843 DSPLO(AC) = EXTEND32 (VL4_8 (prod)); 2844 DSPHI(AC) = EXTEND32 (VH4_8 (prod)); 2845 if (AC == 0) 2846 { 2847 ACX = 0; /* SmartMIPS */ 2848 TRACE_ALU_RESULT2 (HI, LO); 2849 } 2850} 2851 2852 2853000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT 2854"mult r<RS>, r<RT>":RD == 0 2855"mult r<RD>, r<RS>, r<RT>" 2856*vr5000: 2857*r3900: 2858{ 2859 do_mult (SD_, RS, RT, RD); 2860} 2861 2862 2863:function:::void:do_multu:int rs, int rt, int rd 2864{ 2865 unsigned64 prod; 2866 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 2867 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 2868 Unpredictable (); 2869 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2870 prod = (((unsigned64)(unsigned32) GPR[rs]) 2871 * ((unsigned64)(unsigned32) GPR[rt])); 2872 LO = EXTEND32 (VL4_8 (prod)); 2873 HI = EXTEND32 (VH4_8 (prod)); 2874 if (rd != 0) 2875 GPR[rd] = LO; 2876 TRACE_ALU_RESULT2 (HI, LO); 2877} 2878 2879000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU 2880"multu r<RS>, r<RT>" 2881*mipsI: 2882*mipsII: 2883*mipsIII: 2884*mipsIV: 2885*mipsV: 2886*mips32: 2887*mips64: 2888*vr4100: 2889{ 2890 do_multu (SD_, RS, RT, 0); 2891} 2892 2893 2894000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU 2895"multu r<RS>, r<RT>":AC == 0 2896"multu r<RS>, r<RT>" 2897*mips32r2: 2898*mips64r2: 2899*dsp2: 2900{ 2901 unsigned64 prod; 2902 if (AC == 0) 2903 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 2904 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) 2905 Unpredictable (); 2906 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 2907 prod = ((unsigned64)(unsigned32) GPR[RS]) 2908 * ((unsigned64)(unsigned32) GPR[RT]); 2909 DSPLO(AC) = EXTEND32 (VL4_8 (prod)); 2910 DSPHI(AC) = EXTEND32 (VH4_8 (prod)); 2911 if (AC == 0) 2912 TRACE_ALU_RESULT2 (HI, LO); 2913} 2914 2915 2916000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU 2917"multu r<RS>, r<RT>":RD == 0 2918"multu r<RD>, r<RS>, r<RT>" 2919*vr5000: 2920*r3900: 2921{ 2922 do_multu (SD_, RS, RT, RD); 2923} 2924 2925 2926:function:::void:do_nor:int rs, int rt, int rd 2927{ 2928 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2929 GPR[rd] = ~ (GPR[rs] | GPR[rt]); 2930 TRACE_ALU_RESULT (GPR[rd]); 2931} 2932 2933000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR 2934"nor r<RD>, r<RS>, r<RT>" 2935*mipsI: 2936*mipsII: 2937*mipsIII: 2938*mipsIV: 2939*mipsV: 2940*mips32: 2941*mips32r2: 2942*mips64: 2943*mips64r2: 2944*vr4100: 2945*vr5000: 2946*r3900: 2947{ 2948 do_nor (SD_, RS, RT, RD); 2949} 2950 2951 2952:function:::void:do_or:int rs, int rt, int rd 2953{ 2954 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2955 GPR[rd] = (GPR[rs] | GPR[rt]); 2956 TRACE_ALU_RESULT (GPR[rd]); 2957} 2958 2959000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR 2960"or r<RD>, r<RS>, r<RT>" 2961*mipsI: 2962*mipsII: 2963*mipsIII: 2964*mipsIV: 2965*mipsV: 2966*mips32: 2967*mips32r2: 2968*mips64: 2969*mips64r2: 2970*vr4100: 2971*vr5000: 2972*r3900: 2973{ 2974 do_or (SD_, RS, RT, RD); 2975} 2976 2977 2978 2979:function:::void:do_ori:int rs, int rt, unsigned immediate 2980{ 2981 TRACE_ALU_INPUT2 (GPR[rs], immediate); 2982 GPR[rt] = (GPR[rs] | immediate); 2983 TRACE_ALU_RESULT (GPR[rt]); 2984} 2985 2986001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI 2987"ori r<RT>, r<RS>, %#lx<IMMEDIATE>" 2988*mipsI: 2989*mipsII: 2990*mipsIII: 2991*mipsIV: 2992*mipsV: 2993*mips32: 2994*mips32r2: 2995*mips64: 2996*mips64r2: 2997*vr4100: 2998*vr5000: 2999*r3900: 3000{ 3001 do_ori (SD_, RS, RT, IMMEDIATE); 3002} 3003 3004 3005110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF 3006"pref <HINT>, <OFFSET>(r<BASE>)" 3007*mipsIV: 3008*mipsV: 3009*mips32: 3010*mips32r2: 3011*mips64: 3012*mips64r2: 3013*vr5000: 3014{ 3015 address_word base = GPR[BASE]; 3016 address_word offset = EXTEND16 (OFFSET); 3017 { 3018 address_word vaddr = loadstore_ea (SD_, base, offset); 3019 address_word paddr; 3020 int uncached; 3021 { 3022 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) 3023 Prefetch(uncached,paddr,vaddr,isDATA,HINT); 3024 } 3025 } 3026} 3027 3028 3029:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y 3030{ 3031 unsigned64 result; 3032 3033 y &= 31; 3034 TRACE_ALU_INPUT2 (x, y); 3035 result = EXTEND32 (ROTR32 (x, y)); 3036 TRACE_ALU_RESULT (result); 3037 return result; 3038} 3039 3040000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR 3041"ror r<RD>, r<RT>, <SHIFT>" 3042*mips32r2: 3043*mips64r2: 3044*smartmips: 3045*vr5400: 3046*vr5500: 3047{ 3048 GPR[RD] = do_ror (SD_, GPR[RT], SHIFT); 3049} 3050 3051000000,5.RS,5.RT,5.RD,00001,000110::32::RORV 3052"rorv r<RD>, r<RT>, r<RS>" 3053*mips32r2: 3054*mips64r2: 3055*smartmips: 3056*vr5400: 3057*vr5500: 3058{ 3059 GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]); 3060} 3061 3062 3063:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word 3064{ 3065 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 3066 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); 3067 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); 3068 unsigned int byte; 3069 address_word paddr; 3070 int uncached; 3071 unsigned64 memval; 3072 address_word vaddr; 3073 3074 vaddr = loadstore_ea (SD_, base, offset); 3075 if ((vaddr & access) != 0) 3076 { 3077 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal); 3078 } 3079 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); 3080 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); 3081 byte = ((vaddr & mask) ^ bigendiancpu); 3082 memval = (word << (8 * byte)); 3083 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL); 3084} 3085 3086:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt 3087{ 3088 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 3089 address_word reverseendian = (ReverseEndian ? -1 : 0); 3090 address_word bigendiancpu = (BigEndianCPU ? -1 : 0); 3091 unsigned int byte; 3092 unsigned int word; 3093 address_word paddr; 3094 int uncached; 3095 unsigned64 memval; 3096 address_word vaddr; 3097 int nr_lhs_bits; 3098 int nr_rhs_bits; 3099 3100 vaddr = loadstore_ea (SD_, base, offset); 3101 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); 3102 paddr = (paddr ^ (reverseendian & mask)); 3103 if (BigEndianMem == 0) 3104 paddr = paddr & ~access; 3105 3106 /* compute where within the word/mem we are */ 3107 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */ 3108 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */ 3109 nr_lhs_bits = 8 * byte + 8; 3110 nr_rhs_bits = 8 * access - 8 * byte; 3111 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ 3112 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", 3113 (long) ((unsigned64) vaddr >> 32), (long) vaddr, 3114 (long) ((unsigned64) paddr >> 32), (long) paddr, 3115 word, byte, nr_lhs_bits, nr_rhs_bits); */ 3116 3117 if (word == 0) 3118 { 3119 memval = (rt >> nr_rhs_bits); 3120 } 3121 else 3122 { 3123 memval = (rt << nr_lhs_bits); 3124 } 3125 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n", 3126 (long) ((unsigned64) rt >> 32), (long) rt, 3127 (long) ((unsigned64) memval >> 32), (long) memval); */ 3128 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL); 3129} 3130 3131:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt 3132{ 3133 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 3134 address_word reverseendian = (ReverseEndian ? -1 : 0); 3135 address_word bigendiancpu = (BigEndianCPU ? -1 : 0); 3136 unsigned int byte; 3137 address_word paddr; 3138 int uncached; 3139 unsigned64 memval; 3140 address_word vaddr; 3141 3142 vaddr = loadstore_ea (SD_, base, offset); 3143 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); 3144 paddr = (paddr ^ (reverseendian & mask)); 3145 if (BigEndianMem != 0) 3146 paddr &= ~access; 3147 byte = ((vaddr & mask) ^ (bigendiancpu & mask)); 3148 memval = (rt << (byte * 8)); 3149 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL); 3150} 3151 3152 3153101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB 3154"sb r<RT>, <OFFSET>(r<BASE>)" 3155*mipsI: 3156*mipsII: 3157*mipsIII: 3158*mipsIV: 3159*mipsV: 3160*mips32: 3161*mips32r2: 3162*mips64: 3163*mips64r2: 3164*vr4100: 3165*vr5000: 3166*r3900: 3167{ 3168 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 3169} 3170 3171 3172111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC 3173"sc r<RT>, <OFFSET>(r<BASE>)" 3174*mipsII: 3175*mipsIII: 3176*mipsIV: 3177*mipsV: 3178*mips32: 3179*mips32r2: 3180*mips64: 3181*mips64r2: 3182*vr4100: 3183*vr5000: 3184{ 3185 unsigned32 instruction = instruction_0; 3186 address_word base = GPR[BASE]; 3187 address_word offset = EXTEND16 (OFFSET); 3188 { 3189 address_word vaddr = loadstore_ea (SD_, base, offset); 3190 address_word paddr; 3191 int uncached; 3192 if ((vaddr & 3) != 0) 3193 { 3194 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal); 3195 } 3196 else 3197 { 3198 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) 3199 { 3200 unsigned64 memval = 0; 3201 unsigned64 memval1 = 0; 3202 unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 3203 address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); 3204 address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); 3205 unsigned int byte; 3206 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); 3207 byte = ((vaddr & mask) ^ bigendiancpu); 3208 memval = ((unsigned64) GPR[RT] << (8 * byte)); 3209 if (LLBIT) 3210 { 3211 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); 3212 } 3213 GPR[RT] = LLBIT; 3214 } 3215 } 3216 } 3217} 3218 3219 3220111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD 3221"scd r<RT>, <OFFSET>(r<BASE>)" 3222*mipsIII: 3223*mipsIV: 3224*mipsV: 3225*mips64: 3226*mips64r2: 3227*vr4100: 3228*vr5000: 3229{ 3230 address_word base = GPR[BASE]; 3231 address_word offset = EXTEND16 (OFFSET); 3232 check_u64 (SD_, instruction_0); 3233 { 3234 address_word vaddr = loadstore_ea (SD_, base, offset); 3235 address_word paddr; 3236 int uncached; 3237 if ((vaddr & 7) != 0) 3238 { 3239 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal); 3240 } 3241 else 3242 { 3243 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) 3244 { 3245 unsigned64 memval = 0; 3246 unsigned64 memval1 = 0; 3247 memval = GPR[RT]; 3248 if (LLBIT) 3249 { 3250 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); 3251 } 3252 GPR[RT] = LLBIT; 3253 } 3254 } 3255 } 3256} 3257 3258 3259111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD 3260"sd r<RT>, <OFFSET>(r<BASE>)" 3261*mipsIII: 3262*mipsIV: 3263*mipsV: 3264*mips64: 3265*mips64r2: 3266*vr4100: 3267*vr5000: 3268{ 3269 check_u64 (SD_, instruction_0); 3270 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 3271} 3272 3273 32741111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz 3275"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)" 3276*mipsII: 3277*mipsIII: 3278*mipsIV: 3279*mipsV: 3280*mips32: 3281*mips32r2: 3282*mips64: 3283*mips64r2: 3284*vr4100: 3285*vr5000: 3286{ 3287 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT)); 3288} 3289 3290 3291101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL 3292"sdl r<RT>, <OFFSET>(r<BASE>)" 3293*mipsIII: 3294*mipsIV: 3295*mipsV: 3296*mips64: 3297*mips64r2: 3298*vr4100: 3299*vr5000: 3300{ 3301 check_u64 (SD_, instruction_0); 3302 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 3303} 3304 3305 3306101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR 3307"sdr r<RT>, <OFFSET>(r<BASE>)" 3308*mipsIII: 3309*mipsIV: 3310*mipsV: 3311*mips64: 3312*mips64r2: 3313*vr4100: 3314*vr5000: 3315{ 3316 check_u64 (SD_, instruction_0); 3317 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 3318} 3319 3320 3321 3322101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH 3323"sh r<RT>, <OFFSET>(r<BASE>)" 3324*mipsI: 3325*mipsII: 3326*mipsIII: 3327*mipsIV: 3328*mipsV: 3329*mips32: 3330*mips32r2: 3331*mips64: 3332*mips64r2: 3333*vr4100: 3334*vr5000: 3335*r3900: 3336{ 3337 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 3338} 3339 3340 3341:function:::void:do_sll:int rt, int rd, int shift 3342{ 3343 unsigned32 temp = (GPR[rt] << shift); 3344 TRACE_ALU_INPUT2 (GPR[rt], shift); 3345 GPR[rd] = EXTEND32 (temp); 3346 TRACE_ALU_RESULT (GPR[rd]); 3347} 3348 3349000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa 3350"nop":RD == 0 && RT == 0 && SHIFT == 0 3351"sll r<RD>, r<RT>, <SHIFT>" 3352*mipsI: 3353*mipsII: 3354*mipsIII: 3355*mipsIV: 3356*mipsV: 3357*vr4100: 3358*vr5000: 3359*r3900: 3360{ 3361 /* Skip shift for NOP, so that there won't be lots of extraneous 3362 trace output. */ 3363 if (RD != 0 || RT != 0 || SHIFT != 0) 3364 do_sll (SD_, RT, RD, SHIFT); 3365} 3366 3367000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb 3368"nop":RD == 0 && RT == 0 && SHIFT == 0 3369"ssnop":RD == 0 && RT == 0 && SHIFT == 1 3370"sll r<RD>, r<RT>, <SHIFT>" 3371*mips32: 3372*mips32r2: 3373*mips64: 3374*mips64r2: 3375{ 3376 /* Skip shift for NOP and SSNOP, so that there won't be lots of 3377 extraneous trace output. */ 3378 if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1)) 3379 do_sll (SD_, RT, RD, SHIFT); 3380} 3381 3382 3383:function:::void:do_sllv:int rs, int rt, int rd 3384{ 3385 int s = MASKED (GPR[rs], 4, 0); 3386 unsigned32 temp = (GPR[rt] << s); 3387 TRACE_ALU_INPUT2 (GPR[rt], s); 3388 GPR[rd] = EXTEND32 (temp); 3389 TRACE_ALU_RESULT (GPR[rd]); 3390} 3391 3392000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV 3393"sllv r<RD>, r<RT>, r<RS>" 3394*mipsI: 3395*mipsII: 3396*mipsIII: 3397*mipsIV: 3398*mipsV: 3399*mips32: 3400*mips32r2: 3401*mips64: 3402*mips64r2: 3403*vr4100: 3404*vr5000: 3405*r3900: 3406{ 3407 do_sllv (SD_, RS, RT, RD); 3408} 3409 3410 3411:function:::void:do_slt:int rs, int rt, int rd 3412{ 3413 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 3414 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]); 3415 TRACE_ALU_RESULT (GPR[rd]); 3416} 3417 3418000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT 3419"slt r<RD>, r<RS>, r<RT>" 3420*mipsI: 3421*mipsII: 3422*mipsIII: 3423*mipsIV: 3424*mipsV: 3425*mips32: 3426*mips32r2: 3427*mips64: 3428*mips64r2: 3429*vr4100: 3430*vr5000: 3431*r3900: 3432{ 3433 do_slt (SD_, RS, RT, RD); 3434} 3435 3436 3437:function:::void:do_slti:int rs, int rt, unsigned16 immediate 3438{ 3439 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); 3440 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate)); 3441 TRACE_ALU_RESULT (GPR[rt]); 3442} 3443 3444001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI 3445"slti r<RT>, r<RS>, <IMMEDIATE>" 3446*mipsI: 3447*mipsII: 3448*mipsIII: 3449*mipsIV: 3450*mipsV: 3451*mips32: 3452*mips32r2: 3453*mips64: 3454*mips64r2: 3455*vr4100: 3456*vr5000: 3457*r3900: 3458{ 3459 do_slti (SD_, RS, RT, IMMEDIATE); 3460} 3461 3462 3463:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate 3464{ 3465 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); 3466 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate)); 3467 TRACE_ALU_RESULT (GPR[rt]); 3468} 3469 3470001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU 3471"sltiu r<RT>, r<RS>, <IMMEDIATE>" 3472*mipsI: 3473*mipsII: 3474*mipsIII: 3475*mipsIV: 3476*mipsV: 3477*mips32: 3478*mips32r2: 3479*mips64: 3480*mips64r2: 3481*vr4100: 3482*vr5000: 3483*r3900: 3484{ 3485 do_sltiu (SD_, RS, RT, IMMEDIATE); 3486} 3487 3488 3489 3490:function:::void:do_sltu:int rs, int rt, int rd 3491{ 3492 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 3493 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]); 3494 TRACE_ALU_RESULT (GPR[rd]); 3495} 3496 3497000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU 3498"sltu r<RD>, r<RS>, r<RT>" 3499*mipsI: 3500*mipsII: 3501*mipsIII: 3502*mipsIV: 3503*mipsV: 3504*mips32: 3505*mips32r2: 3506*mips64: 3507*mips64r2: 3508*vr4100: 3509*vr5000: 3510*r3900: 3511{ 3512 do_sltu (SD_, RS, RT, RD); 3513} 3514 3515 3516:function:::void:do_sra:int rt, int rd, int shift 3517{ 3518 signed32 temp = (signed32) GPR[rt] >> shift; 3519 if (NotWordValue (GPR[rt])) 3520 Unpredictable (); 3521 TRACE_ALU_INPUT2 (GPR[rt], shift); 3522 GPR[rd] = EXTEND32 (temp); 3523 TRACE_ALU_RESULT (GPR[rd]); 3524} 3525 3526000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA 3527"sra r<RD>, r<RT>, <SHIFT>" 3528*mipsI: 3529*mipsII: 3530*mipsIII: 3531*mipsIV: 3532*mipsV: 3533*mips32: 3534*mips32r2: 3535*mips64: 3536*mips64r2: 3537*vr4100: 3538*vr5000: 3539*r3900: 3540{ 3541 do_sra (SD_, RT, RD, SHIFT); 3542} 3543 3544 3545 3546:function:::void:do_srav:int rs, int rt, int rd 3547{ 3548 int s = MASKED (GPR[rs], 4, 0); 3549 signed32 temp = (signed32) GPR[rt] >> s; 3550 if (NotWordValue (GPR[rt])) 3551 Unpredictable (); 3552 TRACE_ALU_INPUT2 (GPR[rt], s); 3553 GPR[rd] = EXTEND32 (temp); 3554 TRACE_ALU_RESULT (GPR[rd]); 3555} 3556 3557000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV 3558"srav r<RD>, r<RT>, r<RS>" 3559*mipsI: 3560*mipsII: 3561*mipsIII: 3562*mipsIV: 3563*mipsV: 3564*mips32: 3565*mips32r2: 3566*mips64: 3567*mips64r2: 3568*vr4100: 3569*vr5000: 3570*r3900: 3571{ 3572 do_srav (SD_, RS, RT, RD); 3573} 3574 3575 3576 3577:function:::void:do_srl:int rt, int rd, int shift 3578{ 3579 unsigned32 temp = (unsigned32) GPR[rt] >> shift; 3580 if (NotWordValue (GPR[rt])) 3581 Unpredictable (); 3582 TRACE_ALU_INPUT2 (GPR[rt], shift); 3583 GPR[rd] = EXTEND32 (temp); 3584 TRACE_ALU_RESULT (GPR[rd]); 3585} 3586 3587000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL 3588"srl r<RD>, r<RT>, <SHIFT>" 3589*mipsI: 3590*mipsII: 3591*mipsIII: 3592*mipsIV: 3593*mipsV: 3594*mips32: 3595*mips32r2: 3596*mips64: 3597*mips64r2: 3598*vr4100: 3599*vr5000: 3600*r3900: 3601{ 3602 do_srl (SD_, RT, RD, SHIFT); 3603} 3604 3605 3606:function:::void:do_srlv:int rs, int rt, int rd 3607{ 3608 int s = MASKED (GPR[rs], 4, 0); 3609 unsigned32 temp = (unsigned32) GPR[rt] >> s; 3610 if (NotWordValue (GPR[rt])) 3611 Unpredictable (); 3612 TRACE_ALU_INPUT2 (GPR[rt], s); 3613 GPR[rd] = EXTEND32 (temp); 3614 TRACE_ALU_RESULT (GPR[rd]); 3615} 3616 3617000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV 3618"srlv r<RD>, r<RT>, r<RS>" 3619*mipsI: 3620*mipsII: 3621*mipsIII: 3622*mipsIV: 3623*mipsV: 3624*mips32: 3625*mips32r2: 3626*mips64: 3627*mips64r2: 3628*vr4100: 3629*vr5000: 3630*r3900: 3631{ 3632 do_srlv (SD_, RS, RT, RD); 3633} 3634 3635 3636000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB 3637"sub r<RD>, r<RS>, r<RT>" 3638*mipsI: 3639*mipsII: 3640*mipsIII: 3641*mipsIV: 3642*mipsV: 3643*mips32: 3644*mips32r2: 3645*mips64: 3646*mips64r2: 3647*vr4100: 3648*vr5000: 3649*r3900: 3650{ 3651 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) 3652 Unpredictable (); 3653 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 3654 { 3655 ALU32_BEGIN (GPR[RS]); 3656 ALU32_SUB (GPR[RT]); 3657 ALU32_END (GPR[RD]); /* This checks for overflow. */ 3658 } 3659 TRACE_ALU_RESULT (GPR[RD]); 3660} 3661 3662 3663:function:::void:do_subu:int rs, int rt, int rd 3664{ 3665 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 3666 Unpredictable (); 3667 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 3668 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]); 3669 TRACE_ALU_RESULT (GPR[rd]); 3670} 3671 3672000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU 3673"subu r<RD>, r<RS>, r<RT>" 3674*mipsI: 3675*mipsII: 3676*mipsIII: 3677*mipsIV: 3678*mipsV: 3679*mips32: 3680*mips32r2: 3681*mips64: 3682*mips64r2: 3683*vr4100: 3684*vr5000: 3685*r3900: 3686{ 3687 do_subu (SD_, RS, RT, RD); 3688} 3689 3690 3691101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW 3692"sw r<RT>, <OFFSET>(r<BASE>)" 3693*mipsI: 3694*mipsII: 3695*mipsIII: 3696*mipsIV: 3697*mipsV: 3698*mips32: 3699*mips32r2: 3700*mips64: 3701*mips64r2: 3702*vr4100: 3703*r3900: 3704*vr5000: 3705{ 3706 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 3707} 3708 3709 37101110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz 3711"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)" 3712*mipsI: 3713*mipsII: 3714*mipsIII: 3715*mipsIV: 3716*mipsV: 3717*mips32: 3718*mips32r2: 3719*mips64: 3720*mips64r2: 3721*vr4100: 3722*vr5000: 3723*r3900: 3724{ 3725 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT)); 3726} 3727 3728 3729101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL 3730"swl r<RT>, <OFFSET>(r<BASE>)" 3731*mipsI: 3732*mipsII: 3733*mipsIII: 3734*mipsIV: 3735*mipsV: 3736*mips32: 3737*mips32r2: 3738*mips64: 3739*mips64r2: 3740*vr4100: 3741*vr5000: 3742*r3900: 3743{ 3744 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 3745} 3746 3747 3748101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR 3749"swr r<RT>, <OFFSET>(r<BASE>)" 3750*mipsI: 3751*mipsII: 3752*mipsIII: 3753*mipsIV: 3754*mipsV: 3755*mips32: 3756*mips32r2: 3757*mips64: 3758*mips64r2: 3759*vr4100: 3760*vr5000: 3761*r3900: 3762{ 3763 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 3764} 3765 3766 3767000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC 3768"sync":STYPE == 0 3769"sync <STYPE>" 3770*mipsII: 3771*mipsIII: 3772*mipsIV: 3773*mipsV: 3774*mips32: 3775*mips32r2: 3776*mips64: 3777*mips64r2: 3778*vr4100: 3779*vr5000: 3780*r3900: 3781{ 3782 SyncOperation (STYPE); 3783} 3784 3785 3786000000,20.CODE,001100:SPECIAL:32::SYSCALL 3787"syscall %#lx<CODE>" 3788*mipsI: 3789*mipsII: 3790*mipsIII: 3791*mipsIV: 3792*mipsV: 3793*mips32: 3794*mips32r2: 3795*mips64: 3796*mips64r2: 3797*vr4100: 3798*vr5000: 3799*r3900: 3800{ 3801 SignalException (SystemCall, instruction_0); 3802} 3803 3804 3805000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ 3806"teq r<RS>, r<RT>" 3807*mipsII: 3808*mipsIII: 3809*mipsIV: 3810*mipsV: 3811*mips32: 3812*mips32r2: 3813*mips64: 3814*mips64r2: 3815*vr4100: 3816*vr5000: 3817{ 3818 if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) 3819 SignalException (Trap, instruction_0); 3820} 3821 3822 3823000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI 3824"teqi r<RS>, <IMMEDIATE>" 3825*mipsII: 3826*mipsIII: 3827*mipsIV: 3828*mipsV: 3829*mips32: 3830*mips32r2: 3831*mips64: 3832*mips64r2: 3833*vr4100: 3834*vr5000: 3835{ 3836 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE)) 3837 SignalException (Trap, instruction_0); 3838} 3839 3840 3841000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE 3842"tge r<RS>, r<RT>" 3843*mipsII: 3844*mipsIII: 3845*mipsIV: 3846*mipsV: 3847*mips32: 3848*mips32r2: 3849*mips64: 3850*mips64r2: 3851*vr4100: 3852*vr5000: 3853{ 3854 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT]) 3855 SignalException (Trap, instruction_0); 3856} 3857 3858 3859000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI 3860"tgei r<RS>, <IMMEDIATE>" 3861*mipsII: 3862*mipsIII: 3863*mipsIV: 3864*mipsV: 3865*mips32: 3866*mips32r2: 3867*mips64: 3868*mips64r2: 3869*vr4100: 3870*vr5000: 3871{ 3872 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE)) 3873 SignalException (Trap, instruction_0); 3874} 3875 3876 3877000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU 3878"tgeiu r<RS>, <IMMEDIATE>" 3879*mipsII: 3880*mipsIII: 3881*mipsIV: 3882*mipsV: 3883*mips32: 3884*mips32r2: 3885*mips64: 3886*mips64r2: 3887*vr4100: 3888*vr5000: 3889{ 3890 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE)) 3891 SignalException (Trap, instruction_0); 3892} 3893 3894 3895000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU 3896"tgeu r<RS>, r<RT>" 3897*mipsII: 3898*mipsIII: 3899*mipsIV: 3900*mipsV: 3901*mips32: 3902*mips32r2: 3903*mips64: 3904*mips64r2: 3905*vr4100: 3906*vr5000: 3907{ 3908 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT]) 3909 SignalException (Trap, instruction_0); 3910} 3911 3912 3913000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT 3914"tlt r<RS>, r<RT>" 3915*mipsII: 3916*mipsIII: 3917*mipsIV: 3918*mipsV: 3919*mips32: 3920*mips32r2: 3921*mips64: 3922*mips64r2: 3923*vr4100: 3924*vr5000: 3925{ 3926 if ((signed_word) GPR[RS] < (signed_word) GPR[RT]) 3927 SignalException (Trap, instruction_0); 3928} 3929 3930 3931000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI 3932"tlti r<RS>, <IMMEDIATE>" 3933*mipsII: 3934*mipsIII: 3935*mipsIV: 3936*mipsV: 3937*mips32: 3938*mips32r2: 3939*mips64: 3940*mips64r2: 3941*vr4100: 3942*vr5000: 3943{ 3944 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE)) 3945 SignalException (Trap, instruction_0); 3946} 3947 3948 3949000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU 3950"tltiu r<RS>, <IMMEDIATE>" 3951*mipsII: 3952*mipsIII: 3953*mipsIV: 3954*mipsV: 3955*mips32: 3956*mips32r2: 3957*mips64: 3958*mips64r2: 3959*vr4100: 3960*vr5000: 3961{ 3962 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE)) 3963 SignalException (Trap, instruction_0); 3964} 3965 3966 3967000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU 3968"tltu r<RS>, r<RT>" 3969*mipsII: 3970*mipsIII: 3971*mipsIV: 3972*mipsV: 3973*mips32: 3974*mips32r2: 3975*mips64: 3976*mips64r2: 3977*vr4100: 3978*vr5000: 3979{ 3980 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]) 3981 SignalException (Trap, instruction_0); 3982} 3983 3984 3985000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE 3986"tne r<RS>, r<RT>" 3987*mipsII: 3988*mipsIII: 3989*mipsIV: 3990*mipsV: 3991*mips32: 3992*mips32r2: 3993*mips64: 3994*mips64r2: 3995*vr4100: 3996*vr5000: 3997{ 3998 if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) 3999 SignalException (Trap, instruction_0); 4000} 4001 4002 4003000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI 4004"tnei r<RS>, <IMMEDIATE>" 4005*mipsII: 4006*mipsIII: 4007*mipsIV: 4008*mipsV: 4009*mips32: 4010*mips32r2: 4011*mips64: 4012*mips64r2: 4013*vr4100: 4014*vr5000: 4015{ 4016 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE)) 4017 SignalException (Trap, instruction_0); 4018} 4019 4020 4021:function:::void:do_xor:int rs, int rt, int rd 4022{ 4023 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 4024 GPR[rd] = GPR[rs] ^ GPR[rt]; 4025 TRACE_ALU_RESULT (GPR[rd]); 4026} 4027 4028000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR 4029"xor r<RD>, r<RS>, r<RT>" 4030*mipsI: 4031*mipsII: 4032*mipsIII: 4033*mipsIV: 4034*mipsV: 4035*mips32: 4036*mips32r2: 4037*mips64: 4038*mips64r2: 4039*vr4100: 4040*vr5000: 4041*r3900: 4042{ 4043 do_xor (SD_, RS, RT, RD); 4044} 4045 4046 4047:function:::void:do_xori:int rs, int rt, unsigned16 immediate 4048{ 4049 TRACE_ALU_INPUT2 (GPR[rs], immediate); 4050 GPR[rt] = GPR[rs] ^ immediate; 4051 TRACE_ALU_RESULT (GPR[rt]); 4052} 4053 4054001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI 4055"xori r<RT>, r<RS>, %#lx<IMMEDIATE>" 4056*mipsI: 4057*mipsII: 4058*mipsIII: 4059*mipsIV: 4060*mipsV: 4061*mips32: 4062*mips32r2: 4063*mips64: 4064*mips64r2: 4065*vr4100: 4066*vr5000: 4067*r3900: 4068{ 4069 do_xori (SD_, RS, RT, IMMEDIATE); 4070} 4071 4072 4073// 4074// MIPS Architecture: 4075// 4076// FPU Instruction Set (COP1 & COP1X) 4077// 4078 4079 4080:%s::::FMT:int fmt 4081{ 4082 switch (fmt) 4083 { 4084 case fmt_single: return "s"; 4085 case fmt_double: return "d"; 4086 case fmt_word: return "w"; 4087 case fmt_long: return "l"; 4088 case fmt_ps: return "ps"; 4089 default: return "?"; 4090 } 4091} 4092 4093:%s::::TF:int tf 4094{ 4095 if (tf) 4096 return "t"; 4097 else 4098 return "f"; 4099} 4100 4101:%s::::ND:int nd 4102{ 4103 if (nd) 4104 return "l"; 4105 else 4106 return ""; 4107} 4108 4109:%s::::COND:int cond 4110{ 4111 switch (cond) 4112 { 4113 case 00: return "f"; 4114 case 01: return "un"; 4115 case 02: return "eq"; 4116 case 03: return "ueq"; 4117 case 04: return "olt"; 4118 case 05: return "ult"; 4119 case 06: return "ole"; 4120 case 07: return "ule"; 4121 case 010: return "sf"; 4122 case 011: return "ngle"; 4123 case 012: return "seq"; 4124 case 013: return "ngl"; 4125 case 014: return "lt"; 4126 case 015: return "nge"; 4127 case 016: return "le"; 4128 case 017: return "ngt"; 4129 default: return "?"; 4130 } 4131} 4132 4133 4134// Helpers: 4135// 4136// Check that the given FPU format is usable, and signal a 4137// ReservedInstruction exception if not. 4138// 4139 4140// check_fmt_p checks that the format is single, double, or paired single. 4141:function:::void:check_fmt_p:int fmt, instruction_word insn 4142*mipsI: 4143*mipsII: 4144*mipsIII: 4145*mipsIV: 4146*mips32: 4147*vr4100: 4148*vr5000: 4149*r3900: 4150{ 4151 /* None of these ISAs support Paired Single, so just fall back to 4152 the single/double check. */ 4153 if ((fmt != fmt_single) && (fmt != fmt_double)) 4154 SignalException (ReservedInstruction, insn); 4155} 4156 4157:function:::void:check_fmt_p:int fmt, instruction_word insn 4158*mips32r2: 4159{ 4160 if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps)) 4161 SignalException (ReservedInstruction, insn); 4162} 4163 4164:function:::void:check_fmt_p:int fmt, instruction_word insn 4165*mipsV: 4166*mips64: 4167*mips64r2: 4168{ 4169 if ((fmt != fmt_single) && (fmt != fmt_double) 4170 && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0))) 4171 SignalException (ReservedInstruction, insn); 4172} 4173 4174 4175// Helper: 4176// 4177// Check that the FPU is currently usable, and signal a CoProcessorUnusable 4178// exception if not. 4179// 4180 4181:function:::void:check_fpu: 4182*mipsI: 4183*mipsII: 4184*mipsIII: 4185*mipsIV: 4186*mipsV: 4187*mips32: 4188*mips32r2: 4189*mips64: 4190*mips64r2: 4191*vr4100: 4192*vr5000: 4193*r3900: 4194{ 4195 if (! COP_Usable (1)) 4196 SignalExceptionCoProcessorUnusable (1); 4197} 4198 4199 4200// Helper: 4201// 4202// Load a double word FP value using 2 32-bit memory cycles a la MIPS II 4203// or MIPS32. do_load cannot be used instead because it returns an 4204// unsigned_word, which is limited to the size of the machine's registers. 4205// 4206 4207:function:::unsigned64:do_load_double:address_word base, address_word offset 4208*mipsII: 4209*mips32: 4210*mips32r2: 4211{ 4212 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); 4213 address_word vaddr; 4214 address_word paddr; 4215 int uncached; 4216 unsigned64 memval; 4217 unsigned64 v; 4218 4219 vaddr = loadstore_ea (SD_, base, offset); 4220 if ((vaddr & AccessLength_DOUBLEWORD) != 0) 4221 { 4222 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, 4223 AccessLength_DOUBLEWORD + 1, vaddr, read_transfer, 4224 sim_core_unaligned_signal); 4225 } 4226 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, 4227 isREAL); 4228 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr, 4229 isDATA, isREAL); 4230 v = (unsigned64)memval; 4231 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4, 4232 isDATA, isREAL); 4233 return (bigendian ? ((v << 32) | memval) : (v | (memval << 32))); 4234} 4235 4236 4237// Helper: 4238// 4239// Store a double word FP value using 2 32-bit memory cycles a la MIPS II 4240// or MIPS32. do_load cannot be used instead because it returns an 4241// unsigned_word, which is limited to the size of the machine's registers. 4242// 4243 4244:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v 4245*mipsII: 4246*mips32: 4247*mips32r2: 4248{ 4249 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); 4250 address_word vaddr; 4251 address_word paddr; 4252 int uncached; 4253 unsigned64 memval; 4254 4255 vaddr = loadstore_ea (SD_, base, offset); 4256 if ((vaddr & AccessLength_DOUBLEWORD) != 0) 4257 { 4258 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, 4259 AccessLength_DOUBLEWORD + 1, vaddr, write_transfer, 4260 sim_core_unaligned_signal); 4261 } 4262 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, 4263 isREAL); 4264 memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF)); 4265 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, 4266 isREAL); 4267 memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32)); 4268 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4, 4269 isREAL); 4270} 4271 4272 4273010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt 4274"abs.%s<FMT> f<FD>, f<FS>" 4275*mipsI: 4276*mipsII: 4277*mipsIII: 4278*mipsIV: 4279*mipsV: 4280*mips32: 4281*mips32r2: 4282*mips64: 4283*mips64r2: 4284*vr4100: 4285*vr5000: 4286*r3900: 4287{ 4288 int fmt = FMT; 4289 check_fpu (SD_); 4290 check_fmt_p (SD_, fmt, instruction_0); 4291 StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt)); 4292} 4293 4294 4295 4296010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt 4297"add.%s<FMT> f<FD>, f<FS>, f<FT>" 4298*mipsI: 4299*mipsII: 4300*mipsIII: 4301*mipsIV: 4302*mipsV: 4303*mips32: 4304*mips32r2: 4305*mips64: 4306*mips64r2: 4307*vr4100: 4308*vr5000: 4309*r3900: 4310{ 4311 int fmt = FMT; 4312 check_fpu (SD_); 4313 check_fmt_p (SD_, fmt, instruction_0); 4314 StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); 4315} 4316 4317 4318010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:32,f::ALNV.PS 4319"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>" 4320*mipsV: 4321*mips32r2: 4322*mips64: 4323*mips64r2: 4324{ 4325 unsigned64 fs; 4326 unsigned64 ft; 4327 unsigned64 fd; 4328 check_fpu (SD_); 4329 check_u64 (SD_, instruction_0); 4330 fs = ValueFPR (FS, fmt_ps); 4331 if ((GPR[RS] & 0x3) != 0) 4332 Unpredictable (); 4333 if ((GPR[RS] & 0x4) == 0) 4334 fd = fs; 4335 else 4336 { 4337 ft = ValueFPR (FT, fmt_ps); 4338 if (BigEndianCPU) 4339 fd = PackPS (PSLower (fs), PSUpper (ft)); 4340 else 4341 fd = PackPS (PSLower (ft), PSUpper (fs)); 4342 } 4343 StoreFPR (FD, fmt_ps, fd); 4344} 4345 4346 4347// BC1F 4348// BC1FL 4349// BC1T 4350// BC1TL 4351 4352010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a 4353"bc1%s<TF>%s<ND> <OFFSET>" 4354*mipsI: 4355*mipsII: 4356*mipsIII: 4357{ 4358 check_fpu (SD_); 4359 TRACE_BRANCH_INPUT (PREVCOC1()); 4360 if (PREVCOC1() == TF) 4361 { 4362 address_word dest = NIA + (EXTEND16 (OFFSET) << 2); 4363 TRACE_BRANCH_RESULT (dest); 4364 DELAY_SLOT (dest); 4365 } 4366 else if (ND) 4367 { 4368 TRACE_BRANCH_RESULT (0); 4369 NULLIFY_NEXT_INSTRUCTION (); 4370 } 4371 else 4372 { 4373 TRACE_BRANCH_RESULT (NIA); 4374 } 4375} 4376 4377010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b 4378"bc1%s<TF>%s<ND> <OFFSET>":CC == 0 4379"bc1%s<TF>%s<ND> <CC>, <OFFSET>" 4380*mipsIV: 4381*mipsV: 4382*mips32: 4383*mips32r2: 4384*mips64: 4385*mips64r2: 4386#*vr4100: 4387*vr5000: 4388*r3900: 4389{ 4390 check_fpu (SD_); 4391 if (GETFCC(CC) == TF) 4392 { 4393 address_word dest = NIA + (EXTEND16 (OFFSET) << 2); 4394 DELAY_SLOT (dest); 4395 } 4396 else if (ND) 4397 { 4398 NULLIFY_NEXT_INSTRUCTION (); 4399 } 4400} 4401 4402 4403010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta 4404"c.%s<COND>.%s<FMT> f<FS>, f<FT>" 4405*mipsI: 4406*mipsII: 4407*mipsIII: 4408{ 4409 int fmt = FMT; 4410 check_fpu (SD_); 4411 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0); 4412 TRACE_ALU_RESULT (ValueFCR (31)); 4413} 4414 4415010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb 4416"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0 4417"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>" 4418*mipsIV: 4419*mipsV: 4420*mips32: 4421*mips32r2: 4422*mips64: 4423*mips64r2: 4424*vr4100: 4425*vr5000: 4426*r3900: 4427{ 4428 int fmt = FMT; 4429 check_fpu (SD_); 4430 check_fmt_p (SD_, fmt, instruction_0); 4431 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC); 4432 TRACE_ALU_RESULT (ValueFCR (31)); 4433} 4434 4435 4436010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:32,f::CEIL.L.fmt 4437"ceil.l.%s<FMT> f<FD>, f<FS>" 4438*mipsIII: 4439*mipsIV: 4440*mipsV: 4441*mips32r2: 4442*mips64: 4443*mips64r2: 4444*vr4100: 4445*vr5000: 4446*r3900: 4447{ 4448 int fmt = FMT; 4449 check_fpu (SD_); 4450 StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt, 4451 fmt_long)); 4452} 4453 4454 4455010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W 4456"ceil.w.%s<FMT> f<FD>, f<FS>" 4457*mipsII: 4458*mipsIII: 4459*mipsIV: 4460*mipsV: 4461*mips32: 4462*mips32r2: 4463*mips64: 4464*mips64r2: 4465*vr4100: 4466*vr5000: 4467*r3900: 4468{ 4469 int fmt = FMT; 4470 check_fpu (SD_); 4471 StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt, 4472 fmt_word)); 4473} 4474 4475 4476010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a 4477"cfc1 r<RT>, f<FS>" 4478*mipsI: 4479*mipsII: 4480*mipsIII: 4481{ 4482 check_fpu (SD_); 4483 if (FS == 0) 4484 PENDING_FILL (RT, EXTEND32 (FCR0)); 4485 else if (FS == 31) 4486 PENDING_FILL (RT, EXTEND32 (FCR31)); 4487 /* else NOP */ 4488} 4489 4490010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b 4491"cfc1 r<RT>, f<FS>" 4492*mipsIV: 4493*vr4100: 4494*vr5000: 4495*r3900: 4496{ 4497 check_fpu (SD_); 4498 if (FS == 0 || FS == 31) 4499 { 4500 unsigned_word fcr = ValueFCR (FS); 4501 TRACE_ALU_INPUT1 (fcr); 4502 GPR[RT] = fcr; 4503 } 4504 /* else NOP */ 4505 TRACE_ALU_RESULT (GPR[RT]); 4506} 4507 4508010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c 4509"cfc1 r<RT>, f<FS>" 4510*mipsV: 4511*mips32: 4512*mips32r2: 4513*mips64: 4514*mips64r2: 4515{ 4516 check_fpu (SD_); 4517 if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31) 4518 { 4519 unsigned_word fcr = ValueFCR (FS); 4520 TRACE_ALU_INPUT1 (fcr); 4521 GPR[RT] = fcr; 4522 } 4523 /* else NOP */ 4524 TRACE_ALU_RESULT (GPR[RT]); 4525} 4526 4527010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a 4528"ctc1 r<RT>, f<FS>" 4529*mipsI: 4530*mipsII: 4531*mipsIII: 4532{ 4533 check_fpu (SD_); 4534 if (FS == 31) 4535 PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT])); 4536 /* else NOP */ 4537} 4538 4539010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b 4540"ctc1 r<RT>, f<FS>" 4541*mipsIV: 4542*vr4100: 4543*vr5000: 4544*r3900: 4545{ 4546 check_fpu (SD_); 4547 TRACE_ALU_INPUT1 (GPR[RT]); 4548 if (FS == 31) 4549 StoreFCR (FS, GPR[RT]); 4550 /* else NOP */ 4551} 4552 4553010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c 4554"ctc1 r<RT>, f<FS>" 4555*mipsV: 4556*mips32: 4557*mips32r2: 4558*mips64: 4559*mips64r2: 4560{ 4561 check_fpu (SD_); 4562 TRACE_ALU_INPUT1 (GPR[RT]); 4563 if (FS == 25 || FS == 26 || FS == 28 || FS == 31) 4564 StoreFCR (FS, GPR[RT]); 4565 /* else NOP */ 4566} 4567 4568 4569// 4570// FIXME: Does not correctly differentiate between mips* 4571// 4572010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt 4573"cvt.d.%s<FMT> f<FD>, f<FS>" 4574*mipsI: 4575*mipsII: 4576*mipsIII: 4577*mipsIV: 4578*mipsV: 4579*mips32: 4580*mips32r2: 4581*mips64: 4582*mips64r2: 4583*vr4100: 4584*vr5000: 4585*r3900: 4586{ 4587 int fmt = FMT; 4588 check_fpu (SD_); 4589 if ((fmt == fmt_double) | 0) 4590 SignalException (ReservedInstruction, instruction_0); 4591 StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt, 4592 fmt_double)); 4593} 4594 4595 4596010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:32,f::CVT.L.fmt 4597"cvt.l.%s<FMT> f<FD>, f<FS>" 4598*mipsIII: 4599*mipsIV: 4600*mipsV: 4601*mips32r2: 4602*mips64: 4603*mips64r2: 4604*vr4100: 4605*vr5000: 4606*r3900: 4607{ 4608 int fmt = FMT; 4609 check_fpu (SD_); 4610 if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word))) 4611 SignalException (ReservedInstruction, instruction_0); 4612 StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt, 4613 fmt_long)); 4614} 4615 4616 4617010001,10,000,5.FT,5.FS,5.FD,100110:COP1:32,f::CVT.PS.S 4618"cvt.ps.s f<FD>, f<FS>, f<FT>" 4619*mipsV: 4620*mips32r2: 4621*mips64: 4622*mips64r2: 4623{ 4624 check_fpu (SD_); 4625 check_u64 (SD_, instruction_0); 4626 StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single), 4627 ValueFPR (FT, fmt_single))); 4628} 4629 4630 4631// 4632// FIXME: Does not correctly differentiate between mips* 4633// 4634010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt 4635"cvt.s.%s<FMT> f<FD>, f<FS>" 4636*mipsI: 4637*mipsII: 4638*mipsIII: 4639*mipsIV: 4640*mipsV: 4641*mips32: 4642*mips32r2: 4643*mips64: 4644*mips64r2: 4645*vr4100: 4646*vr5000: 4647*r3900: 4648{ 4649 int fmt = FMT; 4650 check_fpu (SD_); 4651 if ((fmt == fmt_single) | 0) 4652 SignalException (ReservedInstruction, instruction_0); 4653 StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt, 4654 fmt_single)); 4655} 4656 4657 4658010001,10,110,00000,5.FS,5.FD,101000:COP1:32,f::CVT.S.PL 4659"cvt.s.pl f<FD>, f<FS>" 4660*mipsV: 4661*mips32r2: 4662*mips64: 4663*mips64r2: 4664{ 4665 check_fpu (SD_); 4666 check_u64 (SD_, instruction_0); 4667 StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps))); 4668} 4669 4670 4671010001,10,110,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.PU 4672"cvt.s.pu f<FD>, f<FS>" 4673*mipsV: 4674*mips32r2: 4675*mips64: 4676*mips64r2: 4677{ 4678 check_fpu (SD_); 4679 check_u64 (SD_, instruction_0); 4680 StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps))); 4681} 4682 4683 4684010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt 4685"cvt.w.%s<FMT> f<FD>, f<FS>" 4686*mipsI: 4687*mipsII: 4688*mipsIII: 4689*mipsIV: 4690*mipsV: 4691*mips32: 4692*mips32r2: 4693*mips64: 4694*mips64r2: 4695*vr4100: 4696*vr5000: 4697*r3900: 4698{ 4699 int fmt = FMT; 4700 check_fpu (SD_); 4701 if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word))) 4702 SignalException (ReservedInstruction, instruction_0); 4703 StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt, 4704 fmt_word)); 4705} 4706 4707 4708010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt 4709"div.%s<FMT> f<FD>, f<FS>, f<FT>" 4710*mipsI: 4711*mipsII: 4712*mipsIII: 4713*mipsIV: 4714*mipsV: 4715*mips32: 4716*mips32r2: 4717*mips64: 4718*mips64r2: 4719*vr4100: 4720*vr5000: 4721*r3900: 4722{ 4723 int fmt = FMT; 4724 check_fpu (SD_); 4725 StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); 4726} 4727 4728 4729010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a 4730"dmfc1 r<RT>, f<FS>" 4731*mipsIII: 4732{ 4733 unsigned64 v; 4734 check_fpu (SD_); 4735 check_u64 (SD_, instruction_0); 4736 if (SizeFGR () == 64) 4737 v = FGR[FS]; 4738 else if ((FS & 0x1) == 0) 4739 v = SET64HI (FGR[FS+1]) | FGR[FS]; 4740 else 4741 v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; 4742 PENDING_FILL (RT, v); 4743 TRACE_ALU_RESULT (v); 4744} 4745 4746010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b 4747"dmfc1 r<RT>, f<FS>" 4748*mipsIV: 4749*mipsV: 4750*mips64: 4751*mips64r2: 4752*vr4100: 4753*vr5000: 4754*r3900: 4755{ 4756 check_fpu (SD_); 4757 check_u64 (SD_, instruction_0); 4758 if (SizeFGR () == 64) 4759 GPR[RT] = FGR[FS]; 4760 else if ((FS & 0x1) == 0) 4761 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS]; 4762 else 4763 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; 4764 TRACE_ALU_RESULT (GPR[RT]); 4765} 4766 4767 4768010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a 4769"dmtc1 r<RT>, f<FS>" 4770*mipsIII: 4771{ 4772 unsigned64 v; 4773 check_fpu (SD_); 4774 check_u64 (SD_, instruction_0); 4775 if (SizeFGR () == 64) 4776 PENDING_FILL ((FS + FGR_BASE), GPR[RT]); 4777 else if ((FS & 0x1) == 0) 4778 { 4779 PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT])); 4780 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT])); 4781 } 4782 else 4783 Unpredictable (); 4784 TRACE_FP_RESULT (GPR[RT]); 4785} 4786 4787010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b 4788"dmtc1 r<RT>, f<FS>" 4789*mipsIV: 4790*mipsV: 4791*mips64: 4792*mips64r2: 4793*vr4100: 4794*vr5000: 4795*r3900: 4796{ 4797 check_fpu (SD_); 4798 check_u64 (SD_, instruction_0); 4799 if (SizeFGR () == 64) 4800 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]); 4801 else if ((FS & 0x1) == 0) 4802 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]); 4803 else 4804 Unpredictable (); 4805} 4806 4807 4808010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:32,f::FLOOR.L.fmt 4809"floor.l.%s<FMT> f<FD>, f<FS>" 4810*mipsIII: 4811*mipsIV: 4812*mipsV: 4813*mips32r2: 4814*mips64: 4815*mips64r2: 4816*vr4100: 4817*vr5000: 4818*r3900: 4819{ 4820 int fmt = FMT; 4821 check_fpu (SD_); 4822 StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt, 4823 fmt_long)); 4824} 4825 4826 4827010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt 4828"floor.w.%s<FMT> f<FD>, f<FS>" 4829*mipsII: 4830*mipsIII: 4831*mipsIV: 4832*mipsV: 4833*mips32: 4834*mips32r2: 4835*mips64: 4836*mips64r2: 4837*vr4100: 4838*vr5000: 4839*r3900: 4840{ 4841 int fmt = FMT; 4842 check_fpu (SD_); 4843 StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt, 4844 fmt_word)); 4845} 4846 4847 4848110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a 4849"ldc1 f<FT>, <OFFSET>(r<BASE>)" 4850*mipsII: 4851*mips32: 4852*mips32r2: 4853{ 4854 check_fpu (SD_); 4855 COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET))); 4856} 4857 4858 4859110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b 4860"ldc1 f<FT>, <OFFSET>(r<BASE>)" 4861*mipsIII: 4862*mipsIV: 4863*mipsV: 4864*mips64: 4865*mips64r2: 4866*vr4100: 4867*vr5000: 4868*r3900: 4869{ 4870 check_fpu (SD_); 4871 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); 4872} 4873 4874 4875010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:32,f::LDXC1 4876"ldxc1 f<FD>, r<INDEX>(r<BASE>)" 4877*mips32r2: 4878{ 4879 check_fpu (SD_); 4880 COP_LD (1, FD, do_load_double (SD_, GPR[BASE], GPR[INDEX])); 4881} 4882 4883 4884010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1 4885"ldxc1 f<FD>, r<INDEX>(r<BASE>)" 4886*mipsIV: 4887*mipsV: 4888*mips64: 4889*mips64r2: 4890*vr5000: 4891{ 4892 check_fpu (SD_); 4893 check_u64 (SD_, instruction_0); 4894 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX])); 4895} 4896 4897 4898010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:32,f::LUXC1 4899"luxc1 f<FD>, r<INDEX>(r<BASE>)" 4900*mips32r2: 4901{ 4902 address_word base = GPR[BASE]; 4903 address_word index = GPR[INDEX]; 4904 address_word vaddr = base + index; 4905 check_fpu (SD_); 4906 if (SizeFGR () != 64) 4907 Unpredictable (); 4908 /* Arrange for the bottom 3 bits of (base + index) to be 0. */ 4909 if ((vaddr & 0x7) != 0) 4910 index -= (vaddr & 0x7); 4911 COP_LD (1, FD, do_load_double (SD_, base, index)); 4912} 4913 4914 4915010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1 4916"luxc1 f<FD>, r<INDEX>(r<BASE>)" 4917*mipsV: 4918*mips64: 4919*mips64r2: 4920{ 4921 address_word base = GPR[BASE]; 4922 address_word index = GPR[INDEX]; 4923 address_word vaddr = base + index; 4924 check_fpu (SD_); 4925 check_u64 (SD_, instruction_0); 4926 if (SizeFGR () != 64) 4927 Unpredictable (); 4928 /* Arrange for the bottom 3 bits of (base + index) to be 0. */ 4929 if ((vaddr & 0x7) != 0) 4930 index -= (vaddr & 0x7); 4931 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index)); 4932} 4933 4934 4935110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1 4936"lwc1 f<FT>, <OFFSET>(r<BASE>)" 4937*mipsI: 4938*mipsII: 4939*mipsIII: 4940*mipsIV: 4941*mipsV: 4942*mips32: 4943*mips32r2: 4944*mips64: 4945*mips64r2: 4946*vr4100: 4947*vr5000: 4948*r3900: 4949{ 4950 check_fpu (SD_); 4951 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); 4952} 4953 4954 4955010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32,f::LWXC1 4956"lwxc1 f<FD>, r<INDEX>(r<BASE>)" 4957*mipsIV: 4958*mipsV: 4959*mips32r2: 4960*mips64: 4961*mips64r2: 4962*vr5000: 4963{ 4964 check_fpu (SD_); 4965 check_u64 (SD_, instruction_0); 4966 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX])); 4967} 4968 4969 4970 4971010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:32,f::MADD.fmt 4972"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>" 4973*mipsIV: 4974*mipsV: 4975*mips32r2: 4976*mips64: 4977*mips64r2: 4978*vr5000: 4979{ 4980 int fmt = FMT; 4981 check_fpu (SD_); 4982 check_u64 (SD_, instruction_0); 4983 check_fmt_p (SD_, fmt, instruction_0); 4984 StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt), 4985 ValueFPR (FR, fmt), fmt)); 4986} 4987 4988 4989010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a 4990"mfc1 r<RT>, f<FS>" 4991*mipsI: 4992*mipsII: 4993*mipsIII: 4994{ 4995 unsigned64 v; 4996 check_fpu (SD_); 4997 v = EXTEND32 (FGR[FS]); 4998 PENDING_FILL (RT, v); 4999 TRACE_ALU_RESULT (v); 5000} 5001 5002010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b 5003"mfc1 r<RT>, f<FS>" 5004*mipsIV: 5005*mipsV: 5006*mips32: 5007*mips32r2: 5008*mips64: 5009*mips64r2: 5010*vr4100: 5011*vr5000: 5012*r3900: 5013{ 5014 check_fpu (SD_); 5015 GPR[RT] = EXTEND32 (FGR[FS]); 5016 TRACE_ALU_RESULT (GPR[RT]); 5017} 5018 5019 5020010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt 5021"mov.%s<FMT> f<FD>, f<FS>" 5022*mipsI: 5023*mipsII: 5024*mipsIII: 5025*mipsIV: 5026*mipsV: 5027*mips32: 5028*mips32r2: 5029*mips64: 5030*mips64r2: 5031*vr4100: 5032*vr5000: 5033*r3900: 5034{ 5035 int fmt = FMT; 5036 check_fpu (SD_); 5037 check_fmt_p (SD_, fmt, instruction_0); 5038 StoreFPR (FD, fmt, ValueFPR (FS, fmt)); 5039} 5040 5041 5042// MOVF 5043// MOVT 5044000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf 5045"mov%s<TF> r<RD>, r<RS>, <CC>" 5046*mipsIV: 5047*mipsV: 5048*mips32: 5049*mips32r2: 5050*mips64: 5051*mips64r2: 5052*vr5000: 5053{ 5054 check_fpu (SD_); 5055 if (GETFCC(CC) == TF) 5056 GPR[RD] = GPR[RS]; 5057} 5058 5059 5060// MOVF.fmt 5061// MOVT.fmt 5062010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt 5063"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>" 5064*mipsIV: 5065*mipsV: 5066*mips32: 5067*mips32r2: 5068*mips64: 5069*mips64r2: 5070*vr5000: 5071{ 5072 int fmt = FMT; 5073 check_fpu (SD_); 5074 if (fmt != fmt_ps) 5075 { 5076 if (GETFCC(CC) == TF) 5077 StoreFPR (FD, fmt, ValueFPR (FS, fmt)); 5078 else 5079 StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */ 5080 } 5081 else 5082 { 5083 unsigned64 fd; 5084 fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD, 5085 fmt_ps)), 5086 PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD, 5087 fmt_ps))); 5088 StoreFPR (FD, fmt_ps, fd); 5089 } 5090} 5091 5092 5093010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt 5094"movn.%s<FMT> f<FD>, f<FS>, r<RT>" 5095*mipsIV: 5096*mipsV: 5097*mips32: 5098*mips32r2: 5099*mips64: 5100*mips64r2: 5101*vr5000: 5102{ 5103 check_fpu (SD_); 5104 if (GPR[RT] != 0) 5105 StoreFPR (FD, FMT, ValueFPR (FS, FMT)); 5106 else 5107 StoreFPR (FD, FMT, ValueFPR (FD, FMT)); 5108} 5109 5110 5111// MOVT see MOVtf 5112 5113 5114// MOVT.fmt see MOVtf.fmt 5115 5116 5117 5118010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt 5119"movz.%s<FMT> f<FD>, f<FS>, r<RT>" 5120*mipsIV: 5121*mipsV: 5122*mips32: 5123*mips32r2: 5124*mips64: 5125*mips64r2: 5126*vr5000: 5127{ 5128 check_fpu (SD_); 5129 if (GPR[RT] == 0) 5130 StoreFPR (FD, FMT, ValueFPR (FS, FMT)); 5131 else 5132 StoreFPR (FD, FMT, ValueFPR (FD, FMT)); 5133} 5134 5135 5136010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:32,f::MSUB.fmt 5137"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>" 5138*mipsIV: 5139*mipsV: 5140*mips32r2: 5141*mips64: 5142*mips64r2: 5143*vr5000: 5144{ 5145 int fmt = FMT; 5146 check_fpu (SD_); 5147 check_u64 (SD_, instruction_0); 5148 check_fmt_p (SD_, fmt, instruction_0); 5149 StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), 5150 ValueFPR (FR, fmt), fmt)); 5151} 5152 5153 5154010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a 5155"mtc1 r<RT>, f<FS>" 5156*mipsI: 5157*mipsII: 5158*mipsIII: 5159{ 5160 check_fpu (SD_); 5161 if (SizeFGR () == 64) 5162 PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT]))); 5163 else 5164 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT])); 5165 TRACE_FP_RESULT (GPR[RT]); 5166} 5167 5168010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b 5169"mtc1 r<RT>, f<FS>" 5170*mipsIV: 5171*mipsV: 5172*mips32: 5173*mips32r2: 5174*mips64: 5175*mips64r2: 5176*vr4100: 5177*vr5000: 5178*r3900: 5179{ 5180 check_fpu (SD_); 5181 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT])); 5182} 5183 5184 5185010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt 5186"mul.%s<FMT> f<FD>, f<FS>, f<FT>" 5187*mipsI: 5188*mipsII: 5189*mipsIII: 5190*mipsIV: 5191*mipsV: 5192*mips32: 5193*mips32r2: 5194*mips64: 5195*mips64r2: 5196*vr4100: 5197*vr5000: 5198*r3900: 5199{ 5200 int fmt = FMT; 5201 check_fpu (SD_); 5202 check_fmt_p (SD_, fmt, instruction_0); 5203 StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); 5204} 5205 5206 5207010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt 5208"neg.%s<FMT> f<FD>, f<FS>" 5209*mipsI: 5210*mipsII: 5211*mipsIII: 5212*mipsIV: 5213*mipsV: 5214*mips32: 5215*mips32r2: 5216*mips64: 5217*mips64r2: 5218*vr4100: 5219*vr5000: 5220*r3900: 5221{ 5222 int fmt = FMT; 5223 check_fpu (SD_); 5224 check_fmt_p (SD_, fmt, instruction_0); 5225 StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt)); 5226} 5227 5228 5229010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:32,f::NMADD.fmt 5230"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>" 5231*mipsIV: 5232*mipsV: 5233*mips32r2: 5234*mips64: 5235*mips64r2: 5236*vr5000: 5237{ 5238 int fmt = FMT; 5239 check_fpu (SD_); 5240 check_u64 (SD_, instruction_0); 5241 check_fmt_p (SD_, fmt, instruction_0); 5242 StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt), 5243 ValueFPR (FR, fmt), fmt)); 5244} 5245 5246 5247010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:32,f::NMSUB.fmt 5248"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>" 5249*mipsIV: 5250*mipsV: 5251*mips32r2: 5252*mips64: 5253*mips64r2: 5254*vr5000: 5255{ 5256 int fmt = FMT; 5257 check_fpu (SD_); 5258 check_u64 (SD_, instruction_0); 5259 check_fmt_p (SD_, fmt, instruction_0); 5260 StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), 5261 ValueFPR (FR, fmt), fmt)); 5262} 5263 5264 5265010001,10,110,5.FT,5.FS,5.FD,101100:COP1:32,f::PLL.PS 5266"pll.ps f<FD>, f<FS>, f<FT>" 5267*mipsV: 5268*mips32r2: 5269*mips64: 5270*mips64r2: 5271{ 5272 check_fpu (SD_); 5273 check_u64 (SD_, instruction_0); 5274 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)), 5275 PSLower (ValueFPR (FT, fmt_ps)))); 5276} 5277 5278 5279010001,10,110,5.FT,5.FS,5.FD,101101:COP1:32,f::PLU.PS 5280"plu.ps f<FD>, f<FS>, f<FT>" 5281*mipsV: 5282*mips32r2: 5283*mips64: 5284*mips64r2: 5285{ 5286 check_fpu (SD_); 5287 check_u64 (SD_, instruction_0); 5288 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)), 5289 PSUpper (ValueFPR (FT, fmt_ps)))); 5290} 5291 5292 5293010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX 5294"prefx <HINT>, r<INDEX>(r<BASE>)" 5295*mipsIV: 5296*mipsV: 5297*mips32r2: 5298*mips64: 5299*mips64r2: 5300*vr5000: 5301{ 5302 address_word base = GPR[BASE]; 5303 address_word index = GPR[INDEX]; 5304 { 5305 address_word vaddr = loadstore_ea (SD_, base, index); 5306 address_word paddr; 5307 int uncached; 5308 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) 5309 Prefetch(uncached,paddr,vaddr,isDATA,HINT); 5310 } 5311} 5312 5313 5314010001,10,110,5.FT,5.FS,5.FD,101110:COP1:32,f::PUL.PS 5315"pul.ps f<FD>, f<FS>, f<FT>" 5316*mipsV: 5317*mips32r2: 5318*mips64: 5319*mips64r2: 5320{ 5321 check_fpu (SD_); 5322 check_u64 (SD_, instruction_0); 5323 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)), 5324 PSLower (ValueFPR (FT, fmt_ps)))); 5325} 5326 5327 5328010001,10,110,5.FT,5.FS,5.FD,101111:COP1:32,f::PUU.PS 5329"puu.ps f<FD>, f<FS>, f<FT>" 5330*mipsV: 5331*mips32r2: 5332*mips64: 5333*mips64r2: 5334{ 5335 check_fpu (SD_); 5336 check_u64 (SD_, instruction_0); 5337 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)), 5338 PSUpper (ValueFPR (FT, fmt_ps)))); 5339} 5340 5341 5342010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt 5343"recip.%s<FMT> f<FD>, f<FS>" 5344*mipsIV: 5345*mipsV: 5346*mips32r2: 5347*mips64: 5348*mips64r2: 5349*vr5000: 5350{ 5351 int fmt = FMT; 5352 check_fpu (SD_); 5353 StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt)); 5354} 5355 5356 5357010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:32,f::ROUND.L.fmt 5358"round.l.%s<FMT> f<FD>, f<FS>" 5359*mipsIII: 5360*mipsIV: 5361*mipsV: 5362*mips32r2: 5363*mips64: 5364*mips64r2: 5365*vr4100: 5366*vr5000: 5367*r3900: 5368{ 5369 int fmt = FMT; 5370 check_fpu (SD_); 5371 StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt, 5372 fmt_long)); 5373} 5374 5375 5376010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt 5377"round.w.%s<FMT> f<FD>, f<FS>" 5378*mipsII: 5379*mipsIII: 5380*mipsIV: 5381*mipsV: 5382*mips32: 5383*mips32r2: 5384*mips64: 5385*mips64r2: 5386*vr4100: 5387*vr5000: 5388*r3900: 5389{ 5390 int fmt = FMT; 5391 check_fpu (SD_); 5392 StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt, 5393 fmt_word)); 5394} 5395 5396 5397010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt 5398"rsqrt.%s<FMT> f<FD>, f<FS>" 5399*mipsIV: 5400*mipsV: 5401*mips32r2: 5402*mips64: 5403*mips64r2: 5404*vr5000: 5405{ 5406 int fmt = FMT; 5407 check_fpu (SD_); 5408 StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt)); 5409} 5410 5411 5412111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a 5413"sdc1 f<FT>, <OFFSET>(r<BASE>)" 5414*mipsII: 5415*mips32: 5416*mips32r2: 5417{ 5418 check_fpu (SD_); 5419 do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT)); 5420} 5421 5422 5423111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b 5424"sdc1 f<FT>, <OFFSET>(r<BASE>)" 5425*mipsIII: 5426*mipsIV: 5427*mipsV: 5428*mips64: 5429*mips64r2: 5430*vr4100: 5431*vr5000: 5432*r3900: 5433{ 5434 check_fpu (SD_); 5435 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT)); 5436} 5437 5438 5439010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1 5440"sdxc1 f<FS>, r<INDEX>(r<BASE>)" 5441*mips32r2 5442{ 5443 check_fpu (SD_); 5444 do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS)); 5445} 5446 5447 5448010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1 5449"sdxc1 f<FS>, r<INDEX>(r<BASE>)" 5450*mipsIV: 5451*mipsV: 5452*mips64: 5453*mips64r2: 5454*vr5000: 5455{ 5456 check_fpu (SD_); 5457 check_u64 (SD_, instruction_0); 5458 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS)); 5459} 5460 5461 5462010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:32,f::SUXC1 5463"suxc1 f<FS>, r<INDEX>(r<BASE>)" 5464*mips32r2: 5465{ 5466 address_word base = GPR[BASE]; 5467 address_word index = GPR[INDEX]; 5468 address_word vaddr = base + index; 5469 check_fpu (SD_); 5470 if (SizeFGR () != 64) 5471 Unpredictable (); 5472 /* Arrange for the bottom 3 bits of (base + index) to be 0. */ 5473 if ((vaddr & 0x7) != 0) 5474 index -= (vaddr & 0x7); 5475 do_store_double (SD_, base, index, COP_SD (1, FS)); 5476} 5477 5478 5479010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1 5480"suxc1 f<FS>, r<INDEX>(r<BASE>)" 5481*mipsV: 5482*mips64: 5483*mips64r2: 5484{ 5485 address_word base = GPR[BASE]; 5486 address_word index = GPR[INDEX]; 5487 address_word vaddr = base + index; 5488 check_fpu (SD_); 5489 check_u64 (SD_, instruction_0); 5490 if (SizeFGR () != 64) 5491 Unpredictable (); 5492 /* Arrange for the bottom 3 bits of (base + index) to be 0. */ 5493 if ((vaddr & 0x7) != 0) 5494 index -= (vaddr & 0x7); 5495 do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS)); 5496} 5497 5498 5499010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt 5500"sqrt.%s<FMT> f<FD>, f<FS>" 5501*mipsII: 5502*mipsIII: 5503*mipsIV: 5504*mipsV: 5505*mips32: 5506*mips32r2: 5507*mips64: 5508*mips64r2: 5509*vr4100: 5510*vr5000: 5511*r3900: 5512{ 5513 int fmt = FMT; 5514 check_fpu (SD_); 5515 StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt))); 5516} 5517 5518 5519010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt 5520"sub.%s<FMT> f<FD>, f<FS>, f<FT>" 5521*mipsI: 5522*mipsII: 5523*mipsIII: 5524*mipsIV: 5525*mipsV: 5526*mips32: 5527*mips32r2: 5528*mips64: 5529*mips64r2: 5530*vr4100: 5531*vr5000: 5532*r3900: 5533{ 5534 int fmt = FMT; 5535 check_fpu (SD_); 5536 check_fmt_p (SD_, fmt, instruction_0); 5537 StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); 5538} 5539 5540 5541 5542111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1 5543"swc1 f<FT>, <OFFSET>(r<BASE>)" 5544*mipsI: 5545*mipsII: 5546*mipsIII: 5547*mipsIV: 5548*mipsV: 5549*mips32: 5550*mips32r2: 5551*mips64: 5552*mips64r2: 5553*vr4100: 5554*vr5000: 5555*r3900: 5556{ 5557 address_word base = GPR[BASE]; 5558 address_word offset = EXTEND16 (OFFSET); 5559 check_fpu (SD_); 5560 { 5561 address_word vaddr = loadstore_ea (SD_, base, offset); 5562 address_word paddr; 5563 int uncached; 5564 if ((vaddr & 3) != 0) 5565 { 5566 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal); 5567 } 5568 else 5569 { 5570 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) 5571 { 5572 uword64 memval = 0; 5573 uword64 memval1 = 0; 5574 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 5575 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0); 5576 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0); 5577 unsigned int byte; 5578 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); 5579 byte = ((vaddr & mask) ^ bigendiancpu); 5580 memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte)); 5581 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); 5582 } 5583 } 5584 } 5585} 5586 5587 5588010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1 5589"swxc1 f<FS>, r<INDEX>(r<BASE>)" 5590*mipsIV: 5591*mipsV: 5592*mips32r2: 5593*mips64: 5594*mips64r2: 5595*vr5000: 5596{ 5597 5598 address_word base = GPR[BASE]; 5599 address_word index = GPR[INDEX]; 5600 check_fpu (SD_); 5601 check_u64 (SD_, instruction_0); 5602 { 5603 address_word vaddr = loadstore_ea (SD_, base, index); 5604 address_word paddr; 5605 int uncached; 5606 if ((vaddr & 3) != 0) 5607 { 5608 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal); 5609 } 5610 else 5611 { 5612 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) 5613 { 5614 unsigned64 memval = 0; 5615 unsigned64 memval1 = 0; 5616 unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 5617 address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); 5618 address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); 5619 unsigned int byte; 5620 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); 5621 byte = ((vaddr & mask) ^ bigendiancpu); 5622 memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte)); 5623 { 5624 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); 5625 } 5626 } 5627 } 5628 } 5629} 5630 5631 5632010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:32,f::TRUNC.L.fmt 5633"trunc.l.%s<FMT> f<FD>, f<FS>" 5634*mipsIII: 5635*mipsIV: 5636*mipsV: 5637*mips32r2: 5638*mips64: 5639*mips64r2: 5640*vr4100: 5641*vr5000: 5642*r3900: 5643{ 5644 int fmt = FMT; 5645 check_fpu (SD_); 5646 StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt, 5647 fmt_long)); 5648} 5649 5650 5651010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W 5652"trunc.w.%s<FMT> f<FD>, f<FS>" 5653*mipsII: 5654*mipsIII: 5655*mipsIV: 5656*mipsV: 5657*mips32: 5658*mips32r2: 5659*mips64: 5660*mips64r2: 5661*vr4100: 5662*vr5000: 5663*r3900: 5664{ 5665 int fmt = FMT; 5666 check_fpu (SD_); 5667 StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt, 5668 fmt_word)); 5669} 5670 5671 5672// 5673// MIPS Architecture: 5674// 5675// System Control Instruction Set (COP0) 5676// 5677 5678 5679010000,01000,00000,16.OFFSET:COP0:32::BC0F 5680"bc0f <OFFSET>" 5681*mipsI: 5682*mipsII: 5683*mipsIII: 5684*mipsIV: 5685*mipsV: 5686*mips32: 5687*mips32r2: 5688*mips64: 5689*mips64r2: 5690*vr4100: 5691*vr5000: 5692 5693010000,01000,00000,16.OFFSET:COP0:32::BC0F 5694"bc0f <OFFSET>" 5695// stub needed for eCos as tx39 hardware bug workaround 5696*r3900: 5697{ 5698 /* do nothing */ 5699} 5700 5701 5702010000,01000,00010,16.OFFSET:COP0:32::BC0FL 5703"bc0fl <OFFSET>" 5704*mipsI: 5705*mipsII: 5706*mipsIII: 5707*mipsIV: 5708*mipsV: 5709*mips32: 5710*mips32r2: 5711*mips64: 5712*mips64r2: 5713*vr4100: 5714*vr5000: 5715 5716 5717010000,01000,00001,16.OFFSET:COP0:32::BC0T 5718"bc0t <OFFSET>" 5719*mipsI: 5720*mipsII: 5721*mipsIII: 5722*mipsIV: 5723*mipsV: 5724*mips32: 5725*mips32r2: 5726*mips64: 5727*mips64r2: 5728*vr4100: 5729 5730 5731010000,01000,00011,16.OFFSET:COP0:32::BC0TL 5732"bc0tl <OFFSET>" 5733*mipsI: 5734*mipsII: 5735*mipsIII: 5736*mipsIV: 5737*mipsV: 5738*mips32: 5739*mips32r2: 5740*mips64: 5741*mips64r2: 5742*vr4100: 5743*vr5000: 5744 5745 5746101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE 5747"cache <OP>, <OFFSET>(r<BASE>)" 5748*mipsIII: 5749*mipsIV: 5750*mipsV: 5751*mips32: 5752*mips32r2: 5753*mips64: 5754*mips64r2: 5755*vr4100: 5756*vr5000: 5757*r3900: 5758{ 5759 address_word base = GPR[BASE]; 5760 address_word offset = EXTEND16 (OFFSET); 5761 { 5762 address_word vaddr = loadstore_ea (SD_, base, offset); 5763 address_word paddr; 5764 int uncached; 5765 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) 5766 CacheOp(OP,vaddr,paddr,instruction_0); 5767 } 5768} 5769 5770 5771010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0 5772"dmfc0 r<RT>, r<RD>" 5773*mipsIII: 5774*mipsIV: 5775*mipsV: 5776*mips64: 5777*mips64r2: 5778{ 5779 check_u64 (SD_, instruction_0); 5780 DecodeCoproc (instruction_0); 5781} 5782 5783 5784010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0 5785"dmtc0 r<RT>, r<RD>" 5786*mipsIII: 5787*mipsIV: 5788*mipsV: 5789*mips64: 5790*mips64r2: 5791{ 5792 check_u64 (SD_, instruction_0); 5793 DecodeCoproc (instruction_0); 5794} 5795 5796 5797010000,1,0000000000000000000,011000:COP0:32::ERET 5798"eret" 5799*mipsIII: 5800*mipsIV: 5801*mipsV: 5802*mips32: 5803*mips32r2: 5804*mips64: 5805*mips64r2: 5806*vr4100: 5807*vr5000: 5808{ 5809 if (SR & status_ERL) 5810 { 5811 /* Oops, not yet available */ 5812 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported"); 5813 NIA = EPC; 5814 SR &= ~status_ERL; 5815 } 5816 else 5817 { 5818 NIA = EPC; 5819 SR &= ~status_EXL; 5820 } 5821} 5822 5823 5824010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0 5825"mfc0 r<RT>, r<RD> # <REGX>" 5826*mipsI: 5827*mipsII: 5828*mipsIII: 5829*mipsIV: 5830*mipsV: 5831*mips32: 5832*mips32r2: 5833*mips64: 5834*mips64r2: 5835*vr4100: 5836*vr5000: 5837*r3900: 5838{ 5839 TRACE_ALU_INPUT0 (); 5840 DecodeCoproc (instruction_0); 5841 TRACE_ALU_RESULT (GPR[RT]); 5842} 5843 5844010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0 5845"mtc0 r<RT>, r<RD> # <REGX>" 5846*mipsI: 5847*mipsII: 5848*mipsIII: 5849*mipsIV: 5850*mipsV: 5851*mips32: 5852*mips32r2: 5853*mips64: 5854*mips64r2: 5855*vr4100: 5856*vr5000: 5857*r3900: 5858{ 5859 DecodeCoproc (instruction_0); 5860} 5861 5862 5863010000,1,0000000000000000000,010000:COP0:32::RFE 5864"rfe" 5865*mipsI: 5866*mipsII: 5867*mipsIII: 5868*mipsIV: 5869*mipsV: 5870*vr4100: 5871*vr5000: 5872*r3900: 5873{ 5874 DecodeCoproc (instruction_0); 5875} 5876 5877 58780100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz 5879"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>" 5880*mipsI: 5881*mipsII: 5882*mipsIII: 5883*mipsIV: 5884*mipsV: 5885*mips32: 5886*mips32r2: 5887*mips64: 5888*mips64r2: 5889*vr4100: 5890*r3900: 5891{ 5892 DecodeCoproc (instruction_0); 5893} 5894 5895 5896 5897010000,1,0000000000000000000,001000:COP0:32::TLBP 5898"tlbp" 5899*mipsI: 5900*mipsII: 5901*mipsIII: 5902*mipsIV: 5903*mipsV: 5904*mips32: 5905*mips32r2: 5906*mips64: 5907*mips64r2: 5908*vr4100: 5909*vr5000: 5910 5911 5912010000,1,0000000000000000000,000001:COP0:32::TLBR 5913"tlbr" 5914*mipsI: 5915*mipsII: 5916*mipsIII: 5917*mipsIV: 5918*mipsV: 5919*mips32: 5920*mips32r2: 5921*mips64: 5922*mips64r2: 5923*vr4100: 5924*vr5000: 5925 5926 5927010000,1,0000000000000000000,000010:COP0:32::TLBWI 5928"tlbwi" 5929*mipsI: 5930*mipsII: 5931*mipsIII: 5932*mipsIV: 5933*mipsV: 5934*mips32: 5935*mips32r2: 5936*mips64: 5937*mips64r2: 5938*vr4100: 5939*vr5000: 5940 5941 5942010000,1,0000000000000000000,000110:COP0:32::TLBWR 5943"tlbwr" 5944*mipsI: 5945*mipsII: 5946*mipsIII: 5947*mipsIV: 5948*mipsV: 5949*mips32: 5950*mips32r2: 5951*mips64: 5952*mips64r2: 5953*vr4100: 5954*vr5000: 5955 5956 5957:include:::mips3264r2.igen 5958:include:::m16.igen 5959:include:::m16e.igen 5960:include:::mdmx.igen 5961:include:::mips3d.igen 5962:include:::sb1.igen 5963:include:::tx.igen 5964:include:::vr.igen 5965:include:::dsp.igen 5966:include:::dsp2.igen 5967:include:::smartmips.igen 5968 5969