1# Blackfin testcase for having RETI LSB set correctly when not self nested 2# mach: bfin 3# sim: --environment operating 4 5#include "test.h" 6 .include "testutils.inc" 7 8 start 9 10 # Set our handler 11 imm32 P5, EVT11; 12 loadsym R1, _ivg11; 13 [P5] = R1; 14 loadsym R1, _fail_lvl; 15 [P5 + 4] = R1; /* IVG12 */ 16 [P5 + 12] = R1; /* IVG14 */ 17 loadsym R1, _ivg13; 18 [P5 + 8] = R1; 19 20 # Disable self nesting 21 R2 = SYSCFG; 22 BITCLR (R2, 2); 23 SYSCFG = R2; 24 CSYNC; 25 26 # Enable IVG11/IVG13/IVG14 but not IVG12 27 cli R3; 28 BITSET (R3, 11); 29 BITCLR (R3, 12); 30 BITSET (R3, 13); 31 BITSET (R3, 14); 32 sti R3; 33 34 # Counters to keep track of nesting depth 35 R7 = 0; 36 R5 = 0; 37 38 # Lower ourselves to IVG11 39 loadsym R4, _fail_lvl; 40 RETI = R4; 41 RAISE 11; 42 RAISE 12; 43 RAISE 13; 44 RAISE 14; 45 RTI; 46 47# This IVG makes sure we don't re-enter when self RAISE is pending 48_ivg11: 49 R0 = RETI; 50 51 # Make sure we are indeed at IVG11 52 imm32 P0, IPEND; 53 R1 = [P0]; 54 CC = BITTST (R1, 11); 55 IF !CC JUMP _fail_lvl; 56 57 # Should not be re-entering 58 CC = R5 == 0; 59 IF !CC JUMP _fail_lvl; 60 61 # Make sure LSB of RETI is not set 62 CC = BITTST (R0, 0); 63 IF CC JUMP _fail_lvl; 64 65 # Try to avoid nesting a few times 66 R5 += 1; 67 R6 = 3; 68 CC = R7 < R6; 69 IF !CC JUMP 1f; 70 [--sp] = RETI; 71 R7 += 1; 72 RAISE 11; 73 MNOP;NOP;MNOP;NOP; 74 R5 = 0; 75 RTI; 76 77 # Move down to IVG13 for next test 781: loadsym R4, _fail_lvl; 79 RETI = R4; 80 RTI; 81 82# This IVG makes sure RETI LSB is ignored on transition out (RTI) 83_ivg13: 84 R0 = RETI; 85 86 # Make sure we are indeed at IVG13 87 imm32 P0, IPEND; 88 R1 = [P0]; 89 CC = BITTST (R1, 13); 90 IF !CC JUMP _fail_lvl; 91 92 # RETI LSB should not be set when entering IVG13 93 CC = BITTST (R0, 0); 94 IF CC JUMP _fail_lvl; 95 96 # Should get here only after a few IVG11 tests 97 CC = R7 == R6; 98 IF !CC JUMP _fail_lvl; 99 100 # Make sure IVG13 isn't pending 101 imm32 P0, ILAT; 102 R1 = [P0]; 103 CC = BITTST (R1, 13); 104 IF CC JUMP _fail_lvl; 105 106 # Manually set RETI to with LSB set so we should stay at IVG13 107 # even though SNEN is disabled 108 loadsym R1, 1f; 109 BITSET (R1, 0); 110 RETI = R1; 111 R7 += 1; 112 RTI; 113 1141: # Make sure we get here in right number of tests 115 R6 = 4; 116 CC = R7 == R6; 117 IF !CC JUMP _fail_lvl; 118 119 # Make sure we are still at IVG13 120 imm32 P0, IPEND; 121 R1 = [P0]; 122 CC = BITTST (R1, 13); 123 IF !CC JUMP _fail_lvl; 124 125 dbg_pass 126 127_fail_lvl: 128 dbg_fail; 129