1/* The instructions with non-zero register numbers are there to ensure we have 2 the correct argument positioning (i.e. check that the first argument is at 3 the end of the word etc). 4 The instructions with all-zero register numbers are to ensure the previous 5 encoding didn't just "happen" to fit -- so that if we change the registers 6 that changes the correct part of the word. 7 Each of the numbered patterns begin and end with a 1, so we can replace 8 them with all-zeros and see the entire range has changed. */ 9 10// SVE 11smmla z17.s, z21.b, z27.b 12smmla z0.s, z0.b, z0.b 13 14ummla z17.s, z21.b, z27.b 15ummla z0.s, z0.b, z0.b 16 17usmmla z17.s, z21.b, z27.b 18usmmla z0.s, z0.b, z0.b 19 20usdot z17.s, z21.b, z27.b 21usdot z0.s, z0.b, z0.b 22 23usdot z17.s, z21.b, z7.b[3] 24usdot z0.s, z0.b, z0.b[3] 25usdot z17.s, z21.b, z7.b[0] 26usdot z0.s, z0.b, z0.b[0] 27 28sudot z17.s, z21.b, z7.b[3] 29sudot z0.s, z0.b, z0.b[3] 30sudot z17.s, z21.b, z7.b[0] 31sudot z0.s, z0.b, z0.b[0] 32 33// SIMD 34smmla v17.4s, v21.16b, v27.16b 35smmla v17.4s, v21.16b, v27.16b 36 37ummla v17.4s, v21.16b, v27.16b 38ummla v0.4s, v0.16b, v0.16b 39 40usmmla v0.4s, v0.16b, v0.16b 41usmmla v17.4s, v21.16b, v27.16b 42 43usdot v17.2s, v21.8b, v27.8b 44usdot v0.2s, v0.8b, v0.8b 45usdot v17.4s, v21.16b, v27.16b 46usdot v0.4s, v0.16b, v0.16b 47 48usdot v17.2s, v21.8b, v27.4b[3] 49usdot v0.2s, v0.8b, v0.4b[3] 50usdot v17.2s, v21.8b, v27.4b[0] 51usdot v0.2s, v0.8b, v0.4b[0] 52usdot v17.4s, v21.16b, v27.4b[3] 53usdot v0.4s, v0.16b, v0.4b[3] 54usdot v17.4s, v21.16b, v27.4b[0] 55usdot v0.4s, v0.16b, v0.4b[0] 56 57sudot v17.2s, v21.8b, v27.4b[3] 58sudot v0.2s, v0.8b, v0.4b[3] 59sudot v17.2s, v21.8b, v27.4b[0] 60sudot v0.2s, v0.8b, v0.4b[0] 61sudot v17.4s, v21.16b, v27.4b[3] 62sudot v0.4s, v0.16b, v0.4b[3] 63sudot v17.4s, v21.16b, v27.4b[0] 64sudot v0.4s, v0.16b, v0.4b[0] 65