1 LIST 2 3;========================================================================== 4; Build date : Oct 21 2015 5; MPASM PIC18LF1230 processor include 6; 7; (c) Copyright 1999-2015 Microchip Technology, All rights reserved 8;========================================================================== 9 10 NOLIST 11 12;========================================================================== 13; This header file defines configurations, registers, and other useful 14; bits of information for the PIC18LF1230 microcontroller. These names 15; are taken to match the data sheets as closely as possible. 16; 17; Note that the processor must be selected before this file is included. 18; The processor may be selected the following ways: 19; 20; 1. Command line switch: 21; C:\MPASM MYFILE.ASM /PIC18LF1230 22; 2. LIST directive in the source file 23; LIST P=PIC18LF1230 24; 3. Processor Type entry in the MPASM full-screen interface 25; 4. Setting the processor in the MPLAB Project Dialog 26;========================================================================== 27 28;========================================================================== 29; 30; Verify Processor 31; 32;========================================================================== 33 IFNDEF __18LF1230 34 MESSG "Processor-header file mismatch. Verify selected processor." 35 ENDIF 36 37;========================================================================== 38; 18xxxx Family EQUates 39;========================================================================== 40FSR0 EQU 0 41FSR1 EQU 1 42FSR2 EQU 2 43 44FAST EQU 1 45 46W EQU 0 47A EQU 0 48ACCESS EQU 0 49BANKED EQU 1 50;========================================================================== 51 52;========================================================================== 53; 16Cxxx/17Cxxx Substitutions 54;========================================================================== 55 #define DDRA TRISA ; PIC17Cxxx SFR substitution 56 #define DDRB TRISB ; PIC17Cxxx SFR substitution 57 #define DDRC TRISC ; PIC17Cxxx SFR substitution 58 #define DDRD TRISD ; PIC17Cxxx SFR substitution 59 #define DDRE TRISE ; PIC17Cxxx SFR substitution 60 61;========================================================================== 62; 63; Register Definitions 64; 65;========================================================================== 66 67;----- Register Files ----------------------------------------------------- 68PORTA EQU H'0F80' 69PORTB EQU H'0F81' 70OVDCONS EQU H'0F82' 71OVDCOND EQU H'0F83' 72DTCON EQU H'0F84' 73PWMCON1 EQU H'0F85' 74PWMCON0 EQU H'0F86' 75SEVTCMPH EQU H'0F87' 76SEVTCMPL EQU H'0F88' 77LATA EQU H'0F89' 78LATB EQU H'0F8A' 79FLTCONFIG EQU H'0F8B' 80PDC2H EQU H'0F8C' 81PDC2L EQU H'0F8D' 82PDC1H EQU H'0F8E' 83PDC1L EQU H'0F8F' 84PDC0H EQU H'0F90' 85PDC0L EQU H'0F91' 86DDRA EQU H'0F92' 87TRISA EQU H'0F92' 88DDRB EQU H'0F93' 89TRISB EQU H'0F93' 90PTPERH EQU H'0F95' 91PTPERL EQU H'0F96' 92PTMRH EQU H'0F97' 93PTMRL EQU H'0F98' 94PTCON1 EQU H'0F99' 95PTCON0 EQU H'0F9A' 96OSCTUNE EQU H'0F9B' 97PIE1 EQU H'0F9D' 98PIR1 EQU H'0F9E' 99IPR1 EQU H'0F9F' 100PIE2 EQU H'0FA0' 101PIR2 EQU H'0FA1' 102IPR2 EQU H'0FA2' 103PIE3 EQU H'0FA3' 104PIR3 EQU H'0FA4' 105IPR3 EQU H'0FA5' 106EECON1 EQU H'0FA6' 107EECON2 EQU H'0FA7' 108EEDATA EQU H'0FA8' 109EEADR EQU H'0FA9' 110RCSTA EQU H'0FAB' 111TXSTA EQU H'0FAC' 112TXREG EQU H'0FAD' 113RCREG EQU H'0FAE' 114SPBRG EQU H'0FAF' 115SPBRGH EQU H'0FB0' 116CMCON EQU H'0FB4' 117CVRCON EQU H'0FB5' 118BAUDCON EQU H'0FB8' 119BAUDCTL EQU H'0FB8' 120ADCON2 EQU H'0FC0' 121ADCON1 EQU H'0FC1' 122ADCON0 EQU H'0FC2' 123ADRES EQU H'0FC3' 124ADRESL EQU H'0FC3' 125ADRESH EQU H'0FC4' 126T1CON EQU H'0FCD' 127TMR1 EQU H'0FCE' 128TMR1L EQU H'0FCE' 129TMR1H EQU H'0FCF' 130RCON EQU H'0FD0' 131WDTCON EQU H'0FD1' 132LVDCON EQU H'0FD2' 133OSCCON EQU H'0FD3' 134T0CON EQU H'0FD5' 135TMR0 EQU H'0FD6' 136TMR0L EQU H'0FD6' 137TMR0H EQU H'0FD7' 138STATUS EQU H'0FD8' 139FSR2L EQU H'0FD9' 140FSR2H EQU H'0FDA' 141PLUSW2 EQU H'0FDB' 142PREINC2 EQU H'0FDC' 143POSTDEC2 EQU H'0FDD' 144POSTINC2 EQU H'0FDE' 145INDF2 EQU H'0FDF' 146BSR EQU H'0FE0' 147FSR1L EQU H'0FE1' 148FSR1H EQU H'0FE2' 149PLUSW1 EQU H'0FE3' 150PREINC1 EQU H'0FE4' 151POSTDEC1 EQU H'0FE5' 152POSTINC1 EQU H'0FE6' 153INDF1 EQU H'0FE7' 154WREG EQU H'0FE8' 155FSR0L EQU H'0FE9' 156FSR0H EQU H'0FEA' 157PLUSW0 EQU H'0FEB' 158PREINC0 EQU H'0FEC' 159POSTDEC0 EQU H'0FED' 160POSTINC0 EQU H'0FEE' 161INDF0 EQU H'0FEF' 162INTCON3 EQU H'0FF0' 163INTCON2 EQU H'0FF1' 164INTCON EQU H'0FF2' 165PROD EQU H'0FF3' 166PRODL EQU H'0FF3' 167PRODH EQU H'0FF4' 168TABLAT EQU H'0FF5' 169TBLPTR EQU H'0FF6' 170TBLPTRL EQU H'0FF6' 171TBLPTRH EQU H'0FF7' 172TBLPTRU EQU H'0FF8' 173PC EQU H'0FF9' 174PCL EQU H'0FF9' 175PCLATH EQU H'0FFA' 176PCLATU EQU H'0FFB' 177STKPTR EQU H'0FFC' 178TOS EQU H'0FFD' 179TOSL EQU H'0FFD' 180TOSH EQU H'0FFE' 181TOSU EQU H'0FFF' 182 183;----- PORTA Bits ----------------------------------------------------- 184RA0 EQU H'0000' 185RA1 EQU H'0001' 186RA2 EQU H'0002' 187RA3 EQU H'0003' 188RA4 EQU H'0004' 189RA5 EQU H'0005' 190RA6 EQU H'0006' 191RA7 EQU H'0007' 192 193AN0 EQU H'0000' 194AN1 EQU H'0001' 195TX EQU H'0002' 196RX EQU H'0003' 197AN2 EQU H'0004' 198MCLR EQU H'0005' 199OSC2 EQU H'0006' 200OSC1 EQU H'0007' 201 202INT0 EQU H'0000' 203INT1 EQU H'0001' 204CK EQU H'0002' 205; DT is a reserved word 206; DT EQU H'0003' 207T0CKI EQU H'0004' 208CLKO EQU H'0006' 209CLKI EQU H'0007' 210 211KBI0 EQU H'0000' 212KBI1 EQU H'0001' 213VREFP EQU H'0004' 214T1OSO_PORTA EQU H'0006' 215T1OSI_PORTA EQU H'0007' 216 217CMP0 EQU H'0000' 218NOT_MCLR EQU H'0005' 219AN3 EQU H'0006' 220 221T1CKI_PORTA EQU H'0006' 222 223 224;----- PORTB Bits ----------------------------------------------------- 225RB0 EQU H'0000' 226RB1 EQU H'0001' 227RB2 EQU H'0002' 228RB3 EQU H'0003' 229RB4 EQU H'0004' 230RB5 EQU H'0005' 231RB6 EQU H'0006' 232RB7 EQU H'0007' 233 234PWM0 EQU H'0000' 235PWM1 EQU H'0001' 236INT2 EQU H'0002' 237INT3 EQU H'0003' 238PWM2 EQU H'0004' 239PWM3 EQU H'0005' 240PWM4 EQU H'0006' 241PWM5 EQU H'0007' 242 243KBI2 EQU H'0002' 244KBI3 EQU H'0003' 245PGC EQU H'0006' 246PGD EQU H'0007' 247 248CMP2 EQU H'0002' 249CMP1 EQU H'0003' 250 251T1OSO_PORTB EQU H'0002' 252T1OSI_PORTB EQU H'0003' 253 254T1CKI_PORTB EQU H'0002' 255 256 257;----- OVDCONS Bits ----------------------------------------------------- 258POUT0 EQU H'0000' 259POUT1 EQU H'0001' 260POUT2 EQU H'0002' 261POUT3 EQU H'0003' 262POUT4 EQU H'0004' 263POUT5 EQU H'0005' 264 265 266;----- OVDCOND Bits ----------------------------------------------------- 267POVD0 EQU H'0000' 268POVD1 EQU H'0001' 269POVD2 EQU H'0002' 270POVD3 EQU H'0003' 271POVD4 EQU H'0004' 272POVD5 EQU H'0005' 273 274 275;----- DTCON Bits ----------------------------------------------------- 276DT0 EQU H'0000' 277DT1 EQU H'0001' 278DT2 EQU H'0002' 279DT3 EQU H'0003' 280DT4 EQU H'0004' 281DT5 EQU H'0005' 282DTPS0 EQU H'0006' 283DTPS1 EQU H'0007' 284 285 286;----- PWMCON1 Bits ----------------------------------------------------- 287OSYNC EQU H'0000' 288UDIS EQU H'0001' 289SEVTDIR EQU H'0003' 290 291SEVOPS0 EQU H'0004' 292SEVOPS1 EQU H'0005' 293SEVOPS2 EQU H'0006' 294SEVOPS3 EQU H'0007' 295 296 297;----- PWMCON0 Bits ----------------------------------------------------- 298PMOD0 EQU H'0000' 299PMOD1 EQU H'0001' 300PMOD2 EQU H'0002' 301PWMEN0 EQU H'0004' 302PWMEN1 EQU H'0005' 303PWMEN2 EQU H'0006' 304 305 306;----- LATA Bits ----------------------------------------------------- 307LATA0 EQU H'0000' 308LATA1 EQU H'0001' 309LATA2 EQU H'0002' 310LATA3 EQU H'0003' 311LATA4 EQU H'0004' 312LATA5 EQU H'0005' 313LATA6 EQU H'0006' 314LATA7 EQU H'0007' 315 316 317;----- LATB Bits ----------------------------------------------------- 318LATB0 EQU H'0000' 319LATB1 EQU H'0001' 320LATB2 EQU H'0002' 321LATB3 EQU H'0003' 322LATB4 EQU H'0004' 323LATB5 EQU H'0005' 324LATB6 EQU H'0006' 325LATB7 EQU H'0007' 326 327 328;----- FLTCONFIG Bits ----------------------------------------------------- 329FLTAEN EQU H'0000' 330FLTAMOD EQU H'0001' 331FLTAS EQU H'0002' 332BRFEN EQU H'0007' 333 334 335;----- DDRA Bits ----------------------------------------------------- 336TRISA0 EQU H'0000' 337TRISA1 EQU H'0001' 338TRISA2 EQU H'0002' 339TRISA3 EQU H'0003' 340TRISA4 EQU H'0004' 341TRISA5 EQU H'0005' 342TRISA6 EQU H'0006' 343TRISA7 EQU H'0007' 344 345RA0 EQU H'0000' 346RA1 EQU H'0001' 347RA2 EQU H'0002' 348RA3 EQU H'0003' 349RA4 EQU H'0004' 350RA5 EQU H'0005' 351RA6 EQU H'0006' 352RA7 EQU H'0007' 353 354 355;----- TRISA Bits ----------------------------------------------------- 356TRISA0 EQU H'0000' 357TRISA1 EQU H'0001' 358TRISA2 EQU H'0002' 359TRISA3 EQU H'0003' 360TRISA4 EQU H'0004' 361TRISA5 EQU H'0005' 362TRISA6 EQU H'0006' 363TRISA7 EQU H'0007' 364 365RA0 EQU H'0000' 366RA1 EQU H'0001' 367RA2 EQU H'0002' 368RA3 EQU H'0003' 369RA4 EQU H'0004' 370RA5 EQU H'0005' 371RA6 EQU H'0006' 372RA7 EQU H'0007' 373 374 375;----- DDRB Bits ----------------------------------------------------- 376TRISB0 EQU H'0000' 377TRISB1 EQU H'0001' 378TRISB2 EQU H'0002' 379TRISB3 EQU H'0003' 380TRISB4 EQU H'0004' 381TRISB5 EQU H'0005' 382TRISB6 EQU H'0006' 383TRISB7 EQU H'0007' 384 385RB0 EQU H'0000' 386RB1 EQU H'0001' 387RB2 EQU H'0002' 388RB3 EQU H'0003' 389RB4 EQU H'0004' 390RB5 EQU H'0005' 391RB6 EQU H'0006' 392RB7 EQU H'0007' 393 394 395;----- TRISB Bits ----------------------------------------------------- 396TRISB0 EQU H'0000' 397TRISB1 EQU H'0001' 398TRISB2 EQU H'0002' 399TRISB3 EQU H'0003' 400TRISB4 EQU H'0004' 401TRISB5 EQU H'0005' 402TRISB6 EQU H'0006' 403TRISB7 EQU H'0007' 404 405RB0 EQU H'0000' 406RB1 EQU H'0001' 407RB2 EQU H'0002' 408RB3 EQU H'0003' 409RB4 EQU H'0004' 410RB5 EQU H'0005' 411RB6 EQU H'0006' 412RB7 EQU H'0007' 413 414 415;----- PTCON1 Bits ----------------------------------------------------- 416PTDIR EQU H'0006' 417PTEN EQU H'0007' 418 419 420;----- PTCON0 Bits ----------------------------------------------------- 421PTMOD0 EQU H'0000' 422PTMOD1 EQU H'0001' 423PTCKPS0 EQU H'0002' 424PTCKPS1 EQU H'0003' 425PTOPS0 EQU H'0004' 426PTOPS1 EQU H'0005' 427PTOPS2 EQU H'0006' 428PTOPS3 EQU H'0007' 429 430 431;----- OSCTUNE Bits ----------------------------------------------------- 432PLLEN EQU H'0006' 433INTSRC EQU H'0007' 434 435TUN0 EQU H'0000' 436TUN1 EQU H'0001' 437TUN2 EQU H'0002' 438TUN3 EQU H'0003' 439TUN4 EQU H'0004' 440 441 442;----- PIE1 Bits ----------------------------------------------------- 443TMR1IE EQU H'0000' 444CMP0IE EQU H'0001' 445CMP1IE EQU H'0002' 446CMP2IE EQU H'0003' 447TXIE EQU H'0004' 448RCIE EQU H'0005' 449ADIE EQU H'0006' 450 451 452;----- PIR1 Bits ----------------------------------------------------- 453TMR1IF EQU H'0000' 454CMP0IF EQU H'0001' 455CMP1IF EQU H'0002' 456CMP2IF EQU H'0003' 457TXIF EQU H'0004' 458RCIF EQU H'0005' 459ADIF EQU H'0006' 460 461 462;----- IPR1 Bits ----------------------------------------------------- 463TMR1IP EQU H'0000' 464CMP0IP EQU H'0001' 465CMP1IP EQU H'0002' 466CMP2IP EQU H'0003' 467TXIP EQU H'0004' 468RCIP EQU H'0005' 469ADIP EQU H'0006' 470 471 472;----- PIE2 Bits ----------------------------------------------------- 473LVDIE EQU H'0002' 474EEIE EQU H'0004' 475OSCFIE EQU H'0007' 476 477 478;----- PIR2 Bits ----------------------------------------------------- 479LVDIF EQU H'0002' 480EEIF EQU H'0004' 481OSCFIF EQU H'0007' 482 483 484;----- IPR2 Bits ----------------------------------------------------- 485LVDIP EQU H'0002' 486EEIP EQU H'0004' 487OSCFIP EQU H'0007' 488 489 490;----- PIE3 Bits ----------------------------------------------------- 491PTIE EQU H'0004' 492 493 494;----- PIR3 Bits ----------------------------------------------------- 495PTIF EQU H'0004' 496 497 498;----- IPR3 Bits ----------------------------------------------------- 499PTIP EQU H'0004' 500 501 502;----- EECON1 Bits ----------------------------------------------------- 503RD EQU H'0000' 504WR EQU H'0001' 505WREN EQU H'0002' 506WRERR EQU H'0003' 507FREE EQU H'0004' 508CFGS EQU H'0006' 509EEPGD EQU H'0007' 510 511 512;----- RCSTA Bits ----------------------------------------------------- 513RX9D EQU H'0000' 514OERR EQU H'0001' 515FERR EQU H'0002' 516ADEN EQU H'0003' 517CREN EQU H'0004' 518SREN EQU H'0005' 519RX9 EQU H'0006' 520SPEN EQU H'0007' 521 522ADDEN EQU H'0003' 523 524 525;----- TXSTA Bits ----------------------------------------------------- 526TX9D EQU H'0000' 527TRMT EQU H'0001' 528BRGH EQU H'0002' 529SENDB EQU H'0003' 530SYNC EQU H'0004' 531TXEN EQU H'0005' 532TX9 EQU H'0006' 533CSRC EQU H'0007' 534 535 536;----- CMCON Bits ----------------------------------------------------- 537C0OUT EQU H'0005' 538C1OUT EQU H'0006' 539C2OUT EQU H'0007' 540 541CMEN0 EQU H'0000' 542CMEN1 EQU H'0001' 543CMEN2 EQU H'0002' 544 545 546;----- CVRCON Bits ----------------------------------------------------- 547CVRSS EQU H'0004' 548CVRR EQU H'0005' 549CVREN EQU H'0007' 550 551CVR0 EQU H'0000' 552CVR1 EQU H'0001' 553CVR2 EQU H'0002' 554CVR3 EQU H'0003' 555CVREF EQU H'0004' 556 557 558;----- BAUDCON Bits ----------------------------------------------------- 559ABDEN EQU H'0000' 560WUE EQU H'0001' 561BRG16 EQU H'0003' 562TXCKP EQU H'0004' 563RXDTP EQU H'0005' 564RCIDL EQU H'0006' 565ABDOVF EQU H'0007' 566 567SCKP EQU H'0004' 568RCMT EQU H'0006' 569 570 571;----- BAUDCTL Bits ----------------------------------------------------- 572ABDEN EQU H'0000' 573WUE EQU H'0001' 574BRG16 EQU H'0003' 575TXCKP EQU H'0004' 576RXDTP EQU H'0005' 577RCIDL EQU H'0006' 578ABDOVF EQU H'0007' 579 580SCKP EQU H'0004' 581RCMT EQU H'0006' 582 583 584;----- ADCON2 Bits ----------------------------------------------------- 585ADFM EQU H'0007' 586 587ADCS0 EQU H'0000' 588ADCS1 EQU H'0001' 589ADCS2 EQU H'0002' 590ACQT0 EQU H'0003' 591ACQT1 EQU H'0004' 592ACQT2 EQU H'0005' 593 594 595;----- ADCON1 Bits ----------------------------------------------------- 596VCFG EQU H'0004' 597 598PCFG0 EQU H'0000' 599PCFG1 EQU H'0001' 600PCFG2 EQU H'0002' 601PCFG3 EQU H'0003' 602VCFG0 EQU H'0004' 603 604 605;----- ADCON0 Bits ----------------------------------------------------- 606ADON EQU H'0000' 607GO_NOT_DONE EQU H'0001' 608SEVTEN EQU H'0007' 609 610GO EQU H'0001' 611CHS0 EQU H'0002' 612CHS1 EQU H'0003' 613 614DONE EQU H'0001' 615 616NOT_DONE EQU H'0001' 617 618GO_DONE EQU H'0001' 619 620 621;----- T1CON Bits ----------------------------------------------------- 622TMR1ON EQU H'0000' 623TMR1CS EQU H'0001' 624NOT_T1SYNC EQU H'0002' 625T1OSCEN EQU H'0003' 626T1RUN EQU H'0006' 627RD16 EQU H'0007' 628 629T1CKPS0 EQU H'0004' 630T1CKPS1 EQU H'0005' 631 632T1SYNC EQU H'0002' 633 634 635;----- RCON Bits ----------------------------------------------------- 636NOT_BOR EQU H'0000' 637NOT_POR EQU H'0001' 638NOT_PD EQU H'0002' 639NOT_TO EQU H'0003' 640NOT_RI EQU H'0004' 641SBOREN EQU H'0006' 642IPEN EQU H'0007' 643 644BOR EQU H'0000' 645POR EQU H'0001' 646PD EQU H'0002' 647TO EQU H'0003' 648RI EQU H'0004' 649 650 651;----- WDTCON Bits ----------------------------------------------------- 652SWDTEN EQU H'0000' 653 654SWDTE EQU H'0000' 655 656 657;----- LVDCON Bits ----------------------------------------------------- 658LVDEN EQU H'0004' 659IRVST EQU H'0005' 660 661LVDL0 EQU H'0000' 662LVDL1 EQU H'0001' 663LVDL2 EQU H'0002' 664LVDL3 EQU H'0003' 665IVRST EQU H'0005' 666 667 668;----- OSCCON Bits ----------------------------------------------------- 669IOFS EQU H'0002' 670OSTS EQU H'0003' 671IDLEN EQU H'0007' 672 673SCS0 EQU H'0000' 674SCS1 EQU H'0001' 675FLTS EQU H'0002' 676IRCF0 EQU H'0004' 677IRCF1 EQU H'0005' 678IRCF2 EQU H'0006' 679 680 681;----- T0CON Bits ----------------------------------------------------- 682PSA EQU H'0003' 683T0SE EQU H'0004' 684T0CS EQU H'0005' 685T016BIT EQU H'0006' 686TMR0ON EQU H'0007' 687 688T0PS0 EQU H'0000' 689T0PS1 EQU H'0001' 690T0PS2 EQU H'0002' 691 692T08BIT EQU H'0006' 693 694 695;----- STATUS Bits ----------------------------------------------------- 696C EQU H'0000' 697DC EQU H'0001' 698Z EQU H'0002' 699OV EQU H'0003' 700N EQU H'0004' 701 702 703;----- INTCON3 Bits ----------------------------------------------------- 704INT1IF EQU H'0000' 705INT2IF EQU H'0001' 706INT3IF EQU H'0002' 707INT1IE EQU H'0003' 708INT2IE EQU H'0004' 709INT3IE EQU H'0005' 710INT1IP EQU H'0006' 711INT2IP EQU H'0007' 712 713INT1F EQU H'0000' 714INT2F EQU H'0001' 715INT3F EQU H'0002' 716INT1E EQU H'0003' 717INT2E EQU H'0004' 718INT3E EQU H'0005' 719INT1P EQU H'0006' 720INT2P EQU H'0007' 721 722 723;----- INTCON2 Bits ----------------------------------------------------- 724RBIP EQU H'0000' 725INT3IP EQU H'0001' 726TMR0IP EQU H'0002' 727INTEDG3 EQU H'0003' 728INTEDG2 EQU H'0004' 729INTEDG1 EQU H'0005' 730INTEDG0 EQU H'0006' 731NOT_RBPU EQU H'0007' 732 733INT3P EQU H'0001' 734RBPU EQU H'0007' 735 736 737;----- INTCON Bits ----------------------------------------------------- 738RBIF EQU H'0000' 739INT0IF EQU H'0001' 740TMR0IF EQU H'0002' 741RBIE EQU H'0003' 742INT0IE EQU H'0004' 743TMR0IE EQU H'0005' 744PEIE_GIEL EQU H'0006' 745GIE_GIEH EQU H'0007' 746 747INT0F EQU H'0001' 748T0IF EQU H'0002' 749INT0E EQU H'0004' 750T0IE EQU H'0005' 751PEIE EQU H'0006' 752GIE EQU H'0007' 753 754GIEL EQU H'0006' 755GIEH EQU H'0007' 756 757 758;----- STKPTR Bits ----------------------------------------------------- 759STKUNF EQU H'0006' 760STKFUL EQU H'0007' 761 762SP0 EQU H'0000' 763SP1 EQU H'0001' 764SP2 EQU H'0002' 765SP3 EQU H'0003' 766SP4 EQU H'0004' 767STKOVF EQU H'0007' 768 769 770 771;========================================================================== 772; 773; RAM Definitions 774; 775;========================================================================== 776 __MAXRAM H'0FFF' 777 __BADRAM H'0100'-H'0F7F' 778 __BADRAM H'0F94' 779 __BADRAM H'0F9C' 780 __BADRAM H'0FAA' 781 __BADRAM H'0FB1'-H'0FB3' 782 __BADRAM H'0FB6'-H'0FB7' 783 __BADRAM H'0FB9'-H'0FBF' 784 __BADRAM H'0FC5'-H'0FCC' 785 __BADRAM H'0FD4' 786 787;========================================================================== 788; 789; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been 790; superseded by the CONFIG directive. The following settings 791; are available for this device. 792; 793; Oscillator: 794; OSC = LP LP Oscillator 795; OSC = XT XT Oscillator 796; OSC = HS HS Oscillator 797; OSC = RC External RC oscillator, CLKO function on RA6 798; OSC = EC EC oscillator, CLKO function on RA6 799; OSC = ECIO EC oscillator, port function on RA6 800; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) 801; OSC = RCIO External RC oscillator, port function on RA6 802; OSC = INTIO2 Internal oscillator, port function on RA6 and RA7 803; OSC = INTIO1 Internal oscillator, CLKO function on RA6, port function on RA7 804; 805; Fail-Safe Clock Monitor Enable bit: 806; FCMEN = OFF Fail-Safe Clock Monitor disabled 807; FCMEN = ON Fail-Safe Clock Monitor enabled 808; 809; Internal/External Oscillator Switchover bit: 810; IESO = OFF Oscillator Switchover mode disabled 811; IESO = ON Oscillator Switchover mode enabled 812; 813; Power-up Timer Enable bit: 814; PWRT = ON PWRT enabled 815; PWRT = OFF PWRT disabled 816; 817; Brown-out Reset Enable bits: 818; BOR = OFF Brown-out Reset disabled in hardware and software 819; BOR = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) 820; BOR = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 821; BOR = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) 822; 823; Brown-out Reset Voltage bits: 824; BORV = 0 Maximum setting 825; BORV = 1 826; BORV = 2 827; BORV = 3 Minimum setting 828; 829; Watchdog Timer Enable bit: 830; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) 831; WDT = ON WDT enabled 832; 833; Watchdog Timer Postscale Select bits: 834; WDTPS = 1 1:1 835; WDTPS = 2 1:2 836; WDTPS = 4 1:4 837; WDTPS = 8 1:8 838; WDTPS = 16 1:16 839; WDTPS = 32 1:32 840; WDTPS = 64 1:64 841; WDTPS = 128 1:128 842; WDTPS = 256 1:256 843; WDTPS = 512 1:512 844; WDTPS = 1024 1:1024 845; WDTPS = 2048 1:2048 846; WDTPS = 4096 1:4096 847; WDTPS = 8192 1:8192 848; WDTPS = 16384 1:16384 849; WDTPS = 32768 1:32768 850; 851; PWM Output Pins Reset State Control bit: 852; PWMPIN = ON PWM outputs drive active states upon Reset 853; PWMPIN = OFF PWM outputs disabled upon Reset 854; 855; Low-Side Transistors Polarity bit (Even PWM Output Polarity Control bit): 856; LPOL = LOW PWM0, PWM2 and PWM4 are active-low 857; LPOL = HIGH PWM0, PWM2 and PWM4 are active-high (default) 858; 859; High Side Transistors Polarity bit (Odd PWM Output Polarity Control bit): 860; HPOL = LOW PWM1, PWM3 and PWM5 are active-low 861; HPOL = HIGH PWM1, PWM3 and PWM5 are active-high (default) 862; 863; FLTA Mux bit: 864; FLTAMX = RA7 FLTA input is muxed onto RA7 865; FLTAMX = RA5 FLTA input is muxed onto RA5 866; 867; T1OSO/T1CKI MUX bit: 868; T1OSCMX = LOW T1OSO/T1CKI pin resides on RB2 869; T1OSCMX = HIGH T1OSO/T1CKI pin resides on RA6 870; 871; Master Clear Enable bit: 872; MCLRE = OFF RA5 input pin enabled, MCLR pin disabled 873; MCLRE = ON MCLR pin enabled, RA5 input pin disabled 874; 875; Stack Overflow/Underflow Reset Enable bit: 876; STVREN = OFF Reset on stack overflow/underflow disabled 877; STVREN = ON Reset on stack overflow/underflow enabled 878; 879; Boot Block Size Select bits: 880; BBSIZ = BB256 256 Words (512 Bytes) Boot Block size 881; BBSIZ = BB512 512 Words (1024 Bytes) Boot Block size 882; 883; Extended Instruction Set Enable bit: 884; XINST = OFF Instruction set extension and Indexed Addressing mode disabled 885; XINST = ON Instruction set extension and Indexed Addressing mode enabled 886; 887; Background Debugger Enable bit: 888; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug 889; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 890; 891; Code Protection bit Block 0 (000400-0007FF): 892; CP0 = ON Block 0 is code-protected 893; CP0 = OFF Block 0 is not code-protected 894; 895; Code Protection bit Block 1 (000800-000FFF): 896; CP1 = ON Block 1 is code-protected 897; CP1 = OFF Block 1 is not code-protected 898; 899; Code Protection bit (Boot Block Memory Area): 900; CPB = ON Boot Block is code-protected 901; CPB = OFF Boot Block is not code-protected 902; 903; Code Protection bit (Data EEPROM): 904; CPD = ON Data EEPROM is code-protected 905; CPD = OFF Data EEPROM is not code-protected 906; 907; Write Protection bit Block 0 (000400-0007FF): 908; WRT0 = ON Block 0 is write-protected 909; WRT0 = OFF Block 0 is not write-protected 910; 911; Write Protection bit Block 1 (000800-000FFF): 912; WRT1 = ON Block 1 is write-protected 913; WRT1 = OFF Block 1 is not write-protected 914; 915; Write Protection bit (Configuration Registers): 916; WRTC = ON Configuration registers are write-protected 917; WRTC = OFF Configuration registers are not write-protected 918; 919; Write Protection bit (Boot Block Memory Area): 920; WRTB = ON Boot Block is write-protected 921; WRTB = OFF Boot Block is not write-protected 922; 923; Write Protection bit (Data EEPROM): 924; WRTD = ON Data EEPROM is write-protected 925; WRTD = OFF Data EEPROM is not write-protected 926; 927; Table Read Protection bit Block 0 (000400-0007FF): 928; EBTR0 = ON Block 0 is protected from table reads executed in other blocks 929; EBTR0 = OFF Block 0 is not protected from table reads executed in other blocks 930; 931; Table Read Protection bit Block 1 (000800-000FFF): 932; EBTR1 = ON Block 1 is protected from table reads executed in other blocks 933; EBTR1 = OFF Block 1 is not protected from table reads executed in other blocks 934; 935; Table Read Protection bit (Boot Block Memory Area): 936; EBTRB = ON Boot Block is protected from table reads executed in other blocks 937; EBTRB = OFF Boot Block is not protected from table reads executed in other blocks 938; 939;========================================================================== 940;========================================================================== 941; 942; Configuration Bits 943; 944; NAME Address 945; CONFIG1H 300001h 946; CONFIG2L 300002h 947; CONFIG2H 300003h 948; CONFIG3L 300004h 949; CONFIG3H 300005h 950; CONFIG4L 300006h 951; CONFIG5L 300008h 952; CONFIG5H 300009h 953; CONFIG6L 30000Ah 954; CONFIG6H 30000Bh 955; CONFIG7L 30000Ch 956; CONFIG7H 30000Dh 957; 958;========================================================================== 959 960; The following is an assignment of address values for all of the 961; configuration registers for the purpose of table reads 962_CONFIG1H EQU H'300001' 963_CONFIG2L EQU H'300002' 964_CONFIG2H EQU H'300003' 965_CONFIG3L EQU H'300004' 966_CONFIG3H EQU H'300005' 967_CONFIG4L EQU H'300006' 968_CONFIG5L EQU H'300008' 969_CONFIG5H EQU H'300009' 970_CONFIG6L EQU H'30000A' 971_CONFIG6H EQU H'30000B' 972_CONFIG7L EQU H'30000C' 973_CONFIG7H EQU H'30000D' 974 975;----- CONFIG1H Options -------------------------------------------------- 976_OSC_LP_1H EQU H'F0'; LP Oscillator 977_OSC_XT_1H EQU H'F1'; XT Oscillator 978_OSC_HS_1H EQU H'F2'; HS Oscillator 979_OSC_RC_1H EQU H'F3'; External RC oscillator, CLKO function on RA6 980_OSC_EC_1H EQU H'F4'; EC oscillator, CLKO function on RA6 981_OSC_ECIO_1H EQU H'F5'; EC oscillator, port function on RA6 982_OSC_HSPLL_1H EQU H'F6'; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) 983_OSC_RCIO_1H EQU H'F7'; External RC oscillator, port function on RA6 984_OSC_INTIO2_1H EQU H'F8'; Internal oscillator, port function on RA6 and RA7 985_OSC_INTIO1_1H EQU H'F9'; Internal oscillator, CLKO function on RA6, port function on RA7 986 987_FCMEN_OFF_1H EQU H'BF'; Fail-Safe Clock Monitor disabled 988_FCMEN_ON_1H EQU H'FF'; Fail-Safe Clock Monitor enabled 989 990_IESO_OFF_1H EQU H'7F'; Oscillator Switchover mode disabled 991_IESO_ON_1H EQU H'FF'; Oscillator Switchover mode enabled 992 993;----- CONFIG2L Options -------------------------------------------------- 994_PWRT_ON_2L EQU H'FE'; PWRT enabled 995_PWRT_OFF_2L EQU H'FF'; PWRT disabled 996 997_BOR_OFF_2L EQU H'F9'; Brown-out Reset disabled in hardware and software 998_BOR_SBORENCTRL_2L EQU H'FB'; Brown-out Reset enabled and controlled by software (SBOREN is enabled) 999_BOR_BOACTIVE_2L EQU H'FD'; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 1000_BOR_BOHW_2L EQU H'FF'; Brown-out Reset enabled in hardware only (SBOREN is disabled) 1001 1002_BORV_0_2L EQU H'E7'; Maximum setting 1003_BORV_1_2L EQU H'EF' 1004_BORV_2_2L EQU H'F7' 1005_BORV_3_2L EQU H'FF'; Minimum setting 1006 1007;----- CONFIG2H Options -------------------------------------------------- 1008_WDT_OFF_2H EQU H'FE'; WDT disabled (control is placed on the SWDTEN bit) 1009_WDT_ON_2H EQU H'FF'; WDT enabled 1010 1011_WDTPS_1_2H EQU H'E1'; 1:1 1012_WDTPS_2_2H EQU H'E3'; 1:2 1013_WDTPS_4_2H EQU H'E5'; 1:4 1014_WDTPS_8_2H EQU H'E7'; 1:8 1015_WDTPS_16_2H EQU H'E9'; 1:16 1016_WDTPS_32_2H EQU H'EB'; 1:32 1017_WDTPS_64_2H EQU H'ED'; 1:64 1018_WDTPS_128_2H EQU H'EF'; 1:128 1019_WDTPS_256_2H EQU H'F1'; 1:256 1020_WDTPS_512_2H EQU H'F3'; 1:512 1021_WDTPS_1024_2H EQU H'F5'; 1:1024 1022_WDTPS_2048_2H EQU H'F7'; 1:2048 1023_WDTPS_4096_2H EQU H'F9'; 1:4096 1024_WDTPS_8192_2H EQU H'FB'; 1:8192 1025_WDTPS_16384_2H EQU H'FD'; 1:16384 1026_WDTPS_32768_2H EQU H'FF'; 1:32768 1027 1028;----- CONFIG3L Options -------------------------------------------------- 1029_PWMPIN_ON_3L EQU H'FD'; PWM outputs drive active states upon Reset 1030_PWMPIN_OFF_3L EQU H'FF'; PWM outputs disabled upon Reset 1031 1032_LPOL_LOW_3L EQU H'FB'; PWM0, PWM2 and PWM4 are active-low 1033_LPOL_HIGH_3L EQU H'FF'; PWM0, PWM2 and PWM4 are active-high (default) 1034 1035_HPOL_LOW_3L EQU H'F7'; PWM1, PWM3 and PWM5 are active-low 1036_HPOL_HIGH_3L EQU H'FF'; PWM1, PWM3 and PWM5 are active-high (default) 1037 1038;----- CONFIG3H Options -------------------------------------------------- 1039_FLTAMX_RA7_3H EQU H'FE'; FLTA input is muxed onto RA7 1040_FLTAMX_RA5_3H EQU H'FF'; FLTA input is muxed onto RA5 1041 1042_T1OSCMX_LOW_3H EQU H'F7'; T1OSO/T1CKI pin resides on RB2 1043_T1OSCMX_HIGH_3H EQU H'FF'; T1OSO/T1CKI pin resides on RA6 1044 1045_MCLRE_OFF_3H EQU H'7F'; RA5 input pin enabled, MCLR pin disabled 1046_MCLRE_ON_3H EQU H'FF'; MCLR pin enabled, RA5 input pin disabled 1047 1048;----- CONFIG4L Options -------------------------------------------------- 1049_STVREN_OFF_4L EQU H'FE'; Reset on stack overflow/underflow disabled 1050_STVREN_ON_4L EQU H'FF'; Reset on stack overflow/underflow enabled 1051 1052_BBSIZ_BB256_4L EQU H'CF'; 256 Words (512 Bytes) Boot Block size 1053_BBSIZ_BB512_4L EQU H'FF'; 512 Words (1024 Bytes) Boot Block size 1054 1055_XINST_OFF_4L EQU H'BF'; Instruction set extension and Indexed Addressing mode disabled 1056_XINST_ON_4L EQU H'FF'; Instruction set extension and Indexed Addressing mode enabled 1057 1058_DEBUG_ON_4L EQU H'7F'; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug 1059_DEBUG_OFF_4L EQU H'FF'; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 1060 1061;----- CONFIG5L Options -------------------------------------------------- 1062_CP0_ON_5L EQU H'FE'; Block 0 is code-protected 1063_CP0_OFF_5L EQU H'FF'; Block 0 is not code-protected 1064 1065_CP1_ON_5L EQU H'FD'; Block 1 is code-protected 1066_CP1_OFF_5L EQU H'FF'; Block 1 is not code-protected 1067 1068;----- CONFIG5H Options -------------------------------------------------- 1069_CPB_ON_5H EQU H'BF'; Boot Block is code-protected 1070_CPB_OFF_5H EQU H'FF'; Boot Block is not code-protected 1071 1072_CPD_ON_5H EQU H'7F'; Data EEPROM is code-protected 1073_CPD_OFF_5H EQU H'FF'; Data EEPROM is not code-protected 1074 1075;----- CONFIG6L Options -------------------------------------------------- 1076_WRT0_ON_6L EQU H'FE'; Block 0 is write-protected 1077_WRT0_OFF_6L EQU H'FF'; Block 0 is not write-protected 1078 1079_WRT1_ON_6L EQU H'FD'; Block 1 is write-protected 1080_WRT1_OFF_6L EQU H'FF'; Block 1 is not write-protected 1081 1082;----- CONFIG6H Options -------------------------------------------------- 1083_WRTC_ON_6H EQU H'DF'; Configuration registers are write-protected 1084_WRTC_OFF_6H EQU H'FF'; Configuration registers are not write-protected 1085 1086_WRTB_ON_6H EQU H'BF'; Boot Block is write-protected 1087_WRTB_OFF_6H EQU H'FF'; Boot Block is not write-protected 1088 1089_WRTD_ON_6H EQU H'7F'; Data EEPROM is write-protected 1090_WRTD_OFF_6H EQU H'FF'; Data EEPROM is not write-protected 1091 1092;----- CONFIG7L Options -------------------------------------------------- 1093_EBTR0_ON_7L EQU H'FE'; Block 0 is protected from table reads executed in other blocks 1094_EBTR0_OFF_7L EQU H'FF'; Block 0 is not protected from table reads executed in other blocks 1095 1096_EBTR1_ON_7L EQU H'FD'; Block 1 is protected from table reads executed in other blocks 1097_EBTR1_OFF_7L EQU H'FF'; Block 1 is not protected from table reads executed in other blocks 1098 1099;----- CONFIG7H Options -------------------------------------------------- 1100_EBTRB_ON_7H EQU H'BF'; Boot Block is protected from table reads executed in other blocks 1101_EBTRB_OFF_7H EQU H'FF'; Boot Block is not protected from table reads executed in other blocks 1102 1103 1104;----- DEVID Equates -------------------------------------------------- 1105_DEVID1 EQU H'3FFFFE' 1106_DEVID2 EQU H'3FFFFF' 1107 1108;----- IDLOC Equates -------------------------------------------------- 1109_IDLOC0 EQU H'200000' 1110_IDLOC1 EQU H'200001' 1111_IDLOC2 EQU H'200002' 1112_IDLOC3 EQU H'200003' 1113_IDLOC4 EQU H'200004' 1114_IDLOC5 EQU H'200005' 1115_IDLOC6 EQU H'200006' 1116_IDLOC7 EQU H'200007' 1117 1118 LIST 1119