1 /*========================== begin_copyright_notice ============================ 2 3 Copyright (C) 2017-2021 Intel Corporation 4 5 SPDX-License-Identifier: MIT 6 7 ============================= end_copyright_notice ===========================*/ 8 9 // 10 // This file declares the TargetMachine that is used by the GenX backend. 11 // 12 // Unlike a normal CPU backend, the GenX backend does not use CodeGen (the 13 // LLVM target independent code generator). 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef GENXTARGETMACHINE_H 18 #define GENXTARGETMACHINE_H 19 20 #include "llvmWrapper/Target/TargetMachine.h" 21 22 #include "GenXIntrinsics.h" 23 #include "GenXSubtarget.h" 24 #include "TargetInfo/GenXTargetInfo.h" 25 26 #include "vc/Utils/General/Types.h" 27 28 #include "llvm/IR/DataLayout.h" 29 #include "llvm/CodeGen/BasicTTIImpl.h" 30 31 namespace llvm { 32 33 class raw_pwrite_stream; 34 class MachineModuleInfo; 35 36 class GenXTargetMachine : public IGCLLVM::LLVMTargetMachine { 37 bool Is64Bit; 38 GenXSubtarget Subtarget; 39 40 public: 41 GenXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, 42 StringRef FS, const TargetOptions &Options, 43 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, 44 CodeGenOpt::Level OL, bool Is64Bit); 45 46 ~GenXTargetMachine() override; 47 48 bool addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &o, raw_pwrite_stream *pi, 49 CodeGenFileType FileType, 50 bool /*DisableVerify*/ = true, 51 MachineModuleInfo *MMI = nullptr) override; 52 53 void adjustPassManager(PassManagerBuilder &PMBuilder) override; 54 55 TargetPassConfig *createPassConfig(PassManagerBase &PM) override; 56 getSubtargetImpl(const Function &)57 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override { 58 return &Subtarget; 59 } 60 TargetTransformInfo getTargetTransformInfo(const Function &F) override; 61 getGenXSubtarget()62 const GenXSubtarget &getGenXSubtarget() const { return Subtarget; } 63 }; 64 65 class GenXTargetMachine32 : public GenXTargetMachine { 66 public: 67 GenXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, 68 StringRef FS, const TargetOptions &Options, 69 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, 70 CodeGenOpt::Level OL, bool JIT); 71 }; 72 73 class GenXTargetMachine64 : public GenXTargetMachine { 74 public: 75 GenXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, 76 StringRef FS, const TargetOptions &Options, 77 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, 78 CodeGenOpt::Level OL, bool JIT); 79 }; 80 81 // This implementation allows us to define our own costs for 82 // the GenX backend. Did not use BasicTTIImplBase because the overloaded 83 // constructors have TragetMachine as an argument, so I inherited from 84 // its parent which has only DL as its arguments 85 class GenXTTIImpl : public TargetTransformInfoImplCRTPBase<GenXTTIImpl> 86 { 87 typedef TargetTransformInfoImplCRTPBase<GenXTTIImpl> BaseT; 88 typedef TargetTransformInfo TTI; 89 friend BaseT; 90 public: GenXTTIImpl(const DataLayout & DL)91 GenXTTIImpl(const DataLayout& DL) : BaseT(DL) {} 92 shouldBuildLookupTables()93 bool shouldBuildLookupTables() { return false; } getFlatAddressSpace()94 unsigned getFlatAddressSpace() { return vc::AddrSpace::Generic; } 95 96 #if LLVM_VERSION_MAJOR >= 13 97 InstructionCost 98 #else 99 int 100 #endif getUserCost(const User * U,ArrayRef<const Value * > Operands,TTI::TargetCostKind CostKind)101 getUserCost(const User *U, ArrayRef<const Value *> Operands 102 #if LLVM_VERSION_MAJOR >= 11 103 , 104 TTI::TargetCostKind CostKind 105 #endif 106 ) { 107 if (auto EV = dyn_cast<ExtractValueInst>(U)) { 108 switch(GenXIntrinsic::getGenXIntrinsicID(EV->getOperand(0))) { 109 case GenXIntrinsic::genx_simdcf_goto: 110 case GenXIntrinsic::genx_simdcf_join: 111 // Do not allow such EVs to be TCC_Free 112 return TTI::TCC_Basic; 113 default: 114 break; 115 } 116 } 117 118 return BaseT::getUserCost(U, Operands 119 #if LLVM_VERSION_MAJOR >= 11 120 , 121 CostKind 122 #endif 123 ); 124 } 125 isProfitableToHoist(Instruction * I)126 bool isProfitableToHoist(Instruction *I) const { 127 // genx_vload and genx_vstore are related to g_store bales 128 // and they shouldn't be hoisted from then/else blocks 129 // in front of the branch 130 auto IntrinsicID = GenXIntrinsic::getGenXIntrinsicID(I); 131 return IntrinsicID != GenXIntrinsic::genx_vload && 132 IntrinsicID != GenXIntrinsic::genx_vstore; 133 } 134 }; 135 136 /// Initialize all GenX passes for opt tool. 137 void initializeGenXPasses(PassRegistry &); 138 139 void initializeFunctionGroupAnalysisPass(PassRegistry &); 140 void initializeGenXAddressCommoningWrapperPass(PassRegistry &); 141 void initializeGenXArgIndirectionWrapperPass(PassRegistry &); 142 void initializeGenXCategoryWrapperPass(PassRegistry &); 143 void initializeGenXCFSimplificationPass(PassRegistry &); 144 void initializeGenXCisaBuilderWrapperPass(PassRegistry &); 145 void initializeGenXCoalescingWrapperPass(PassRegistry &); 146 void initializeGenXDeadVectorRemovalPass(PassRegistry &); 147 void initializeGenXDepressurizerWrapperPass(PassRegistry &); 148 void initializeGenXEarlySimdCFConformancePass(PassRegistry &); 149 void initializeGenXEmulationImportPass(PassRegistry &); 150 void initializeGenXEmulatePass(PassRegistry &); 151 void initializeGenXExtractVectorizerPass(PassRegistry &); 152 void initializeGenXFuncBalingPass(PassRegistry &); 153 void initializeGenXGEPLoweringPass(PassRegistry &); 154 void initializeGenXGroupBalingWrapperPass(PassRegistry &); 155 void initializeGenXInstCombineCleanup(PassRegistry &); 156 void initializeGenXIMadPostLegalizationPass(PassRegistry &); 157 void initializeGenXLateSimdCFConformanceWrapperPass(PassRegistry &); 158 void initializeGenXLegalizationPass(PassRegistry &); 159 void initializeGenXLiveRangesWrapperPass(PassRegistry &); 160 void initializeGenXLivenessWrapperPass(PassRegistry &); 161 void initializeGenXLoadStoreLoweringPass(PassRegistry &); 162 void initializeGenXLowerAggrCopiesPass(PassRegistry &); 163 void initializeGenXLoweringPass(PassRegistry &); 164 void initializeGenXModulePass(PassRegistry &); 165 void initializeGenXNumberingWrapperPass(PassRegistry &); 166 void initializeGenXPacketizePass(PassRegistry &); 167 void initializeGenXPatternMatchPass(PassRegistry &); 168 void initializeGenXPostLegalizationPass(PassRegistry &); 169 void initializeGenXPostLegalizationPass(PassRegistry &); 170 void initializeGenXPrologEpilogInsertionPass(PassRegistry &); 171 void initializeGenXPromotePredicatePass(PassRegistry &); 172 void initializeGenXRawSendRipperPass(PassRegistry &); 173 void initializeGenXReduceIntSizePass(PassRegistry &); 174 void initializeGenXRegionCollapsingPass(PassRegistry &); 175 void initializeGenXRematerializationWrapperPass(PassRegistry &); 176 void initializeGenXThreadPrivateMemoryPass(PassRegistry &); 177 void initializeGenXTidyControlFlowPass(PassRegistry &); 178 void initializeGenXUnbalingWrapperPass(PassRegistry &); 179 void initializeGenXVisaRegAllocWrapperPass(PassRegistry &); 180 void initializeTransformPrivMemPass(PassRegistry &); 181 void initializeGenXFunctionPointersLoweringPass(PassRegistry &); 182 void initializeGenXLowerJmpTableSwitchPass(PassRegistry &); 183 void initializeGenXGlobalValueLoweringPass(PassRegistry &); 184 void initializeGenXAggregatePseudoLoweringPass(PassRegistry &); 185 void initializeGenXVectorCombinerPass(PassRegistry &); 186 void initializeGenXPromoteStatefulToBindlessPass(PassRegistry &); 187 void initializeGenXStackUsagePass(PassRegistry &); 188 void initializeCMLowerVLoadVStorePass(PassRegistry &); 189 void initializeGenXStructSplitterPass(PassRegistry &); 190 } // End llvm namespace 191 192 #endif 193