1 /*
2 * Copyright (c) 2003 Hewlett-Packard Development Company, L.P.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 /* If AO_ASSUME_VISTA is defined, we assume Windows Server 2003, Vista */
24 /* or later. */
25
26 #include "../all_aligned_atomic_load_store.h"
27
28 #include "../test_and_set_t_is_char.h"
29
30 #if !defined(AO_ASSUME_WINDOWS98) \
31 && (defined(AO_ASSUME_VISTA) || _MSC_VER >= 1400)
32 /* Visual Studio 2005 (MS VC++ 8.0) discontinued support of Windows 95. */
33 # define AO_ASSUME_WINDOWS98
34 #endif
35
36 #ifndef AO_USE_INTERLOCKED_INTRINSICS
37 /* _Interlocked primitives (Inc, Dec, Xchg, Add) are always available */
38 # define AO_USE_INTERLOCKED_INTRINSICS
39 #endif
40 #include "common32_defs.h"
41
42 /* As far as we can tell, the lfence and sfence instructions are not */
43 /* currently needed or useful for cached memory accesses. */
44
45 /* Unfortunately mfence doesn't exist everywhere. */
46 /* IsProcessorFeaturePresent(PF_COMPARE_EXCHANGE128) is */
47 /* probably a conservative test for it? */
48
49 #if defined(AO_USE_PENTIUM4_INSTRS)
50
51 AO_INLINE void
AO_nop_full(void)52 AO_nop_full(void)
53 {
54 __asm { mfence }
55 }
56 #define AO_HAVE_nop_full
57
58 #else
59
60 /* We could use the cpuid instruction. But that seems to be slower */
61 /* than the default implementation based on test_and_set_full. Thus */
62 /* we omit that bit of misinformation here. */
63
64 #endif
65
66 #if !defined(AO_NO_ASM_XADD) && !defined(AO_HAVE_char_fetch_and_add_full)
67 AO_INLINE unsigned char
AO_char_fetch_and_add_full(volatile unsigned char * p,unsigned char incr)68 AO_char_fetch_and_add_full(volatile unsigned char *p, unsigned char incr)
69 {
70 __asm
71 {
72 mov al, incr
73 mov ebx, p
74 lock xadd byte ptr [ebx], al
75 }
76 /* Ignore possible "missing return value" warning here. */
77 }
78 # define AO_HAVE_char_fetch_and_add_full
79
80 AO_INLINE unsigned short
AO_short_fetch_and_add_full(volatile unsigned short * p,unsigned short incr)81 AO_short_fetch_and_add_full(volatile unsigned short *p, unsigned short incr)
82 {
83 __asm
84 {
85 mov ax, incr
86 mov ebx, p
87 lock xadd word ptr [ebx], ax
88 }
89 /* Ignore possible "missing return value" warning here. */
90 }
91 # define AO_HAVE_short_fetch_and_add_full
92 #endif /* !AO_NO_ASM_XADD */
93
94 AO_INLINE AO_TS_VAL_t
AO_test_and_set_full(volatile AO_TS_t * addr)95 AO_test_and_set_full(volatile AO_TS_t *addr)
96 {
97 __asm
98 {
99 mov eax,0xff ; /* AO_TS_SET */
100 mov ebx,addr ;
101 xchg byte ptr [ebx],al ;
102 }
103 /* Ignore possible "missing return value" warning here. */
104 }
105 #define AO_HAVE_test_and_set_full
106
107 #if defined(_WIN64) && !defined(CPPCHECK)
108 # error wrong architecture
109 #endif
110
111 #ifdef AO_ASSUME_VISTA
112 # include "../standard_ao_double_t.h"
113
114 /* Reading or writing a quadword aligned on a 64-bit boundary is */
115 /* always carried out atomically (requires at least a Pentium). */
116 # define AO_ACCESS_double_CHECK_ALIGNED
117 # include "../loadstore/double_atomic_load_store.h"
118
119 /* Whenever we run on a Pentium class machine, we have that certain */
120 /* function. */
121 # pragma intrinsic (_InterlockedCompareExchange64)
122
123 /* Returns nonzero if the comparison succeeded. */
124 AO_INLINE int
AO_double_compare_and_swap_full(volatile AO_double_t * addr,AO_double_t old_val,AO_double_t new_val)125 AO_double_compare_and_swap_full(volatile AO_double_t *addr,
126 AO_double_t old_val, AO_double_t new_val)
127 {
128 AO_ASSERT_ADDR_ALIGNED(addr);
129 return (double_ptr_storage)_InterlockedCompareExchange64(
130 (__int64 volatile *)addr,
131 new_val.AO_whole /* exchange */,
132 old_val.AO_whole) == old_val.AO_whole;
133 }
134 # define AO_HAVE_double_compare_and_swap_full
135 #endif /* AO_ASSUME_VISTA */
136
137 #define AO_T_IS_INT
138
139 /* Real X86 implementations, except for some old WinChips, appear */
140 /* to enforce ordering between memory operations, EXCEPT that a later */
141 /* read can pass earlier writes, presumably due to the visible */
142 /* presence of store buffers. */
143 /* We ignore both the WinChips, and the fact that the official specs */
144 /* seem to be much weaker (and arguably too weak to be usable). */
145 #include "../ordered_except_wr.h"
146