1 /**
2 * @file
3 * @brief The generated interface for the register allocator.
4 * Contains register classes and types and register constraints
5 * for all nodes where constraints were given in spec.
6 * @note DO NOT EDIT THIS FILE, your changes will be lost.
7 * Edit ir/be/sparc/sparc_spec.pl instead.
8 * created by: ir/be/scripts/generate_regalloc_if.pl ir/be/sparc/sparc_spec.pl ir/be/sparc
9 * $date Mon Nov 19 18:12:23 2012
10 */
11 #include "config.h"
12
13 #include "gen_sparc_regalloc_if.h"
14 #include "bearch_sparc_t.h"
15 #include "irmode.h"
16
17 static const arch_register_req_t sparc_class_reg_req_fpflags_class = {
18 arch_register_req_type_normal,
19 &sparc_reg_classes[CLASS_sparc_fpflags_class],
20 NULL,
21 0,
22 0,
23 1
24 };
25 static const unsigned sparc_limited_fpflags_class_fpflags [] = { (1 << REG_FPFLAGS_CLASS_FPFLAGS) };
26 static const arch_register_req_t sparc_single_reg_req_fpflags_class_fpflags = {
27 arch_register_req_type_limited,
28 &sparc_reg_classes[CLASS_sparc_fpflags_class],
29 sparc_limited_fpflags_class_fpflags,
30 0,
31 0,
32 1
33 };
34 static const arch_register_req_t sparc_class_reg_req_gp = {
35 arch_register_req_type_normal,
36 &sparc_reg_classes[CLASS_sparc_gp],
37 NULL,
38 0,
39 0,
40 1
41 };
42 static const unsigned sparc_limited_gp_l0 [] = { (1 << REG_GP_L0), 0 };
43 static const arch_register_req_t sparc_single_reg_req_gp_l0 = {
44 arch_register_req_type_limited,
45 &sparc_reg_classes[CLASS_sparc_gp],
46 sparc_limited_gp_l0,
47 0,
48 0,
49 1
50 };
51 static const unsigned sparc_limited_gp_l1 [] = { (1 << REG_GP_L1), 0 };
52 static const arch_register_req_t sparc_single_reg_req_gp_l1 = {
53 arch_register_req_type_limited,
54 &sparc_reg_classes[CLASS_sparc_gp],
55 sparc_limited_gp_l1,
56 0,
57 0,
58 1
59 };
60 static const unsigned sparc_limited_gp_l2 [] = { (1 << REG_GP_L2), 0 };
61 static const arch_register_req_t sparc_single_reg_req_gp_l2 = {
62 arch_register_req_type_limited,
63 &sparc_reg_classes[CLASS_sparc_gp],
64 sparc_limited_gp_l2,
65 0,
66 0,
67 1
68 };
69 static const unsigned sparc_limited_gp_l3 [] = { (1 << REG_GP_L3), 0 };
70 static const arch_register_req_t sparc_single_reg_req_gp_l3 = {
71 arch_register_req_type_limited,
72 &sparc_reg_classes[CLASS_sparc_gp],
73 sparc_limited_gp_l3,
74 0,
75 0,
76 1
77 };
78 static const unsigned sparc_limited_gp_l4 [] = { (1 << REG_GP_L4), 0 };
79 static const arch_register_req_t sparc_single_reg_req_gp_l4 = {
80 arch_register_req_type_limited,
81 &sparc_reg_classes[CLASS_sparc_gp],
82 sparc_limited_gp_l4,
83 0,
84 0,
85 1
86 };
87 static const unsigned sparc_limited_gp_l5 [] = { (1 << REG_GP_L5), 0 };
88 static const arch_register_req_t sparc_single_reg_req_gp_l5 = {
89 arch_register_req_type_limited,
90 &sparc_reg_classes[CLASS_sparc_gp],
91 sparc_limited_gp_l5,
92 0,
93 0,
94 1
95 };
96 static const unsigned sparc_limited_gp_l6 [] = { (1 << REG_GP_L6), 0 };
97 static const arch_register_req_t sparc_single_reg_req_gp_l6 = {
98 arch_register_req_type_limited,
99 &sparc_reg_classes[CLASS_sparc_gp],
100 sparc_limited_gp_l6,
101 0,
102 0,
103 1
104 };
105 static const unsigned sparc_limited_gp_l7 [] = { (1 << REG_GP_L7), 0 };
106 static const arch_register_req_t sparc_single_reg_req_gp_l7 = {
107 arch_register_req_type_limited,
108 &sparc_reg_classes[CLASS_sparc_gp],
109 sparc_limited_gp_l7,
110 0,
111 0,
112 1
113 };
114 static const unsigned sparc_limited_gp_g0 [] = { (1 << REG_GP_G0), 0 };
115 static const arch_register_req_t sparc_single_reg_req_gp_g0 = {
116 arch_register_req_type_limited,
117 &sparc_reg_classes[CLASS_sparc_gp],
118 sparc_limited_gp_g0,
119 0,
120 0,
121 1
122 };
123 static const unsigned sparc_limited_gp_g1 [] = { (1 << REG_GP_G1), 0 };
124 static const arch_register_req_t sparc_single_reg_req_gp_g1 = {
125 arch_register_req_type_limited,
126 &sparc_reg_classes[CLASS_sparc_gp],
127 sparc_limited_gp_g1,
128 0,
129 0,
130 1
131 };
132 static const unsigned sparc_limited_gp_g2 [] = { (1 << REG_GP_G2), 0 };
133 static const arch_register_req_t sparc_single_reg_req_gp_g2 = {
134 arch_register_req_type_limited,
135 &sparc_reg_classes[CLASS_sparc_gp],
136 sparc_limited_gp_g2,
137 0,
138 0,
139 1
140 };
141 static const unsigned sparc_limited_gp_g3 [] = { (1 << REG_GP_G3), 0 };
142 static const arch_register_req_t sparc_single_reg_req_gp_g3 = {
143 arch_register_req_type_limited,
144 &sparc_reg_classes[CLASS_sparc_gp],
145 sparc_limited_gp_g3,
146 0,
147 0,
148 1
149 };
150 static const unsigned sparc_limited_gp_g4 [] = { (1 << REG_GP_G4), 0 };
151 static const arch_register_req_t sparc_single_reg_req_gp_g4 = {
152 arch_register_req_type_limited,
153 &sparc_reg_classes[CLASS_sparc_gp],
154 sparc_limited_gp_g4,
155 0,
156 0,
157 1
158 };
159 static const unsigned sparc_limited_gp_g5 [] = { (1 << REG_GP_G5), 0 };
160 static const arch_register_req_t sparc_single_reg_req_gp_g5 = {
161 arch_register_req_type_limited,
162 &sparc_reg_classes[CLASS_sparc_gp],
163 sparc_limited_gp_g5,
164 0,
165 0,
166 1
167 };
168 static const unsigned sparc_limited_gp_g6 [] = { (1 << REG_GP_G6), 0 };
169 static const arch_register_req_t sparc_single_reg_req_gp_g6 = {
170 arch_register_req_type_limited,
171 &sparc_reg_classes[CLASS_sparc_gp],
172 sparc_limited_gp_g6,
173 0,
174 0,
175 1
176 };
177 static const unsigned sparc_limited_gp_g7 [] = { (1 << REG_GP_G7), 0 };
178 static const arch_register_req_t sparc_single_reg_req_gp_g7 = {
179 arch_register_req_type_limited,
180 &sparc_reg_classes[CLASS_sparc_gp],
181 sparc_limited_gp_g7,
182 0,
183 0,
184 1
185 };
186 static const unsigned sparc_limited_gp_o0 [] = { (1 << REG_GP_O0), 0 };
187 static const arch_register_req_t sparc_single_reg_req_gp_o0 = {
188 arch_register_req_type_limited,
189 &sparc_reg_classes[CLASS_sparc_gp],
190 sparc_limited_gp_o0,
191 0,
192 0,
193 1
194 };
195 static const unsigned sparc_limited_gp_o1 [] = { (1 << REG_GP_O1), 0 };
196 static const arch_register_req_t sparc_single_reg_req_gp_o1 = {
197 arch_register_req_type_limited,
198 &sparc_reg_classes[CLASS_sparc_gp],
199 sparc_limited_gp_o1,
200 0,
201 0,
202 1
203 };
204 static const unsigned sparc_limited_gp_o2 [] = { (1 << REG_GP_O2), 0 };
205 static const arch_register_req_t sparc_single_reg_req_gp_o2 = {
206 arch_register_req_type_limited,
207 &sparc_reg_classes[CLASS_sparc_gp],
208 sparc_limited_gp_o2,
209 0,
210 0,
211 1
212 };
213 static const unsigned sparc_limited_gp_o3 [] = { (1 << REG_GP_O3), 0 };
214 static const arch_register_req_t sparc_single_reg_req_gp_o3 = {
215 arch_register_req_type_limited,
216 &sparc_reg_classes[CLASS_sparc_gp],
217 sparc_limited_gp_o3,
218 0,
219 0,
220 1
221 };
222 static const unsigned sparc_limited_gp_o4 [] = { (1 << REG_GP_O4), 0 };
223 static const arch_register_req_t sparc_single_reg_req_gp_o4 = {
224 arch_register_req_type_limited,
225 &sparc_reg_classes[CLASS_sparc_gp],
226 sparc_limited_gp_o4,
227 0,
228 0,
229 1
230 };
231 static const unsigned sparc_limited_gp_o5 [] = { (1 << REG_GP_O5), 0 };
232 static const arch_register_req_t sparc_single_reg_req_gp_o5 = {
233 arch_register_req_type_limited,
234 &sparc_reg_classes[CLASS_sparc_gp],
235 sparc_limited_gp_o5,
236 0,
237 0,
238 1
239 };
240 static const unsigned sparc_limited_gp_sp [] = { (1 << REG_GP_SP), 0 };
241 static const arch_register_req_t sparc_single_reg_req_gp_sp = {
242 arch_register_req_type_limited,
243 &sparc_reg_classes[CLASS_sparc_gp],
244 sparc_limited_gp_sp,
245 0,
246 0,
247 1
248 };
249 static const unsigned sparc_limited_gp_o7 [] = { (1 << REG_GP_O7), 0 };
250 static const arch_register_req_t sparc_single_reg_req_gp_o7 = {
251 arch_register_req_type_limited,
252 &sparc_reg_classes[CLASS_sparc_gp],
253 sparc_limited_gp_o7,
254 0,
255 0,
256 1
257 };
258 static const unsigned sparc_limited_gp_i0 [] = { (1 << REG_GP_I0), 0 };
259 static const arch_register_req_t sparc_single_reg_req_gp_i0 = {
260 arch_register_req_type_limited,
261 &sparc_reg_classes[CLASS_sparc_gp],
262 sparc_limited_gp_i0,
263 0,
264 0,
265 1
266 };
267 static const unsigned sparc_limited_gp_i1 [] = { (1 << REG_GP_I1), 0 };
268 static const arch_register_req_t sparc_single_reg_req_gp_i1 = {
269 arch_register_req_type_limited,
270 &sparc_reg_classes[CLASS_sparc_gp],
271 sparc_limited_gp_i1,
272 0,
273 0,
274 1
275 };
276 static const unsigned sparc_limited_gp_i2 [] = { (1 << REG_GP_I2), 0 };
277 static const arch_register_req_t sparc_single_reg_req_gp_i2 = {
278 arch_register_req_type_limited,
279 &sparc_reg_classes[CLASS_sparc_gp],
280 sparc_limited_gp_i2,
281 0,
282 0,
283 1
284 };
285 static const unsigned sparc_limited_gp_i3 [] = { (1 << REG_GP_I3), 0 };
286 static const arch_register_req_t sparc_single_reg_req_gp_i3 = {
287 arch_register_req_type_limited,
288 &sparc_reg_classes[CLASS_sparc_gp],
289 sparc_limited_gp_i3,
290 0,
291 0,
292 1
293 };
294 static const unsigned sparc_limited_gp_i4 [] = { (1 << REG_GP_I4), 0 };
295 static const arch_register_req_t sparc_single_reg_req_gp_i4 = {
296 arch_register_req_type_limited,
297 &sparc_reg_classes[CLASS_sparc_gp],
298 sparc_limited_gp_i4,
299 0,
300 0,
301 1
302 };
303 static const unsigned sparc_limited_gp_i5 [] = { (1 << REG_GP_I5), 0 };
304 static const arch_register_req_t sparc_single_reg_req_gp_i5 = {
305 arch_register_req_type_limited,
306 &sparc_reg_classes[CLASS_sparc_gp],
307 sparc_limited_gp_i5,
308 0,
309 0,
310 1
311 };
312 static const unsigned sparc_limited_gp_frame_pointer [] = { (1 << REG_GP_FRAME_POINTER), 0 };
313 static const arch_register_req_t sparc_single_reg_req_gp_frame_pointer = {
314 arch_register_req_type_limited,
315 &sparc_reg_classes[CLASS_sparc_gp],
316 sparc_limited_gp_frame_pointer,
317 0,
318 0,
319 1
320 };
321 static const unsigned sparc_limited_gp_i7 [] = { (1 << REG_GP_I7), 0 };
322 static const arch_register_req_t sparc_single_reg_req_gp_i7 = {
323 arch_register_req_type_limited,
324 &sparc_reg_classes[CLASS_sparc_gp],
325 sparc_limited_gp_i7,
326 0,
327 0,
328 1
329 };
330 static const arch_register_req_t sparc_class_reg_req_fp = {
331 arch_register_req_type_normal,
332 &sparc_reg_classes[CLASS_sparc_fp],
333 NULL,
334 0,
335 0,
336 1
337 };
338 static const unsigned sparc_limited_fp_f0 [] = { (1 << REG_FP_F0), 0 };
339 static const arch_register_req_t sparc_single_reg_req_fp_f0 = {
340 arch_register_req_type_limited,
341 &sparc_reg_classes[CLASS_sparc_fp],
342 sparc_limited_fp_f0,
343 0,
344 0,
345 1
346 };
347 static const unsigned sparc_limited_fp_f1 [] = { (1 << REG_FP_F1), 0 };
348 static const arch_register_req_t sparc_single_reg_req_fp_f1 = {
349 arch_register_req_type_limited,
350 &sparc_reg_classes[CLASS_sparc_fp],
351 sparc_limited_fp_f1,
352 0,
353 0,
354 1
355 };
356 static const unsigned sparc_limited_fp_f2 [] = { (1 << REG_FP_F2), 0 };
357 static const arch_register_req_t sparc_single_reg_req_fp_f2 = {
358 arch_register_req_type_limited,
359 &sparc_reg_classes[CLASS_sparc_fp],
360 sparc_limited_fp_f2,
361 0,
362 0,
363 1
364 };
365 static const unsigned sparc_limited_fp_f3 [] = { (1 << REG_FP_F3), 0 };
366 static const arch_register_req_t sparc_single_reg_req_fp_f3 = {
367 arch_register_req_type_limited,
368 &sparc_reg_classes[CLASS_sparc_fp],
369 sparc_limited_fp_f3,
370 0,
371 0,
372 1
373 };
374 static const unsigned sparc_limited_fp_f4 [] = { (1 << REG_FP_F4), 0 };
375 static const arch_register_req_t sparc_single_reg_req_fp_f4 = {
376 arch_register_req_type_limited,
377 &sparc_reg_classes[CLASS_sparc_fp],
378 sparc_limited_fp_f4,
379 0,
380 0,
381 1
382 };
383 static const unsigned sparc_limited_fp_f5 [] = { (1 << REG_FP_F5), 0 };
384 static const arch_register_req_t sparc_single_reg_req_fp_f5 = {
385 arch_register_req_type_limited,
386 &sparc_reg_classes[CLASS_sparc_fp],
387 sparc_limited_fp_f5,
388 0,
389 0,
390 1
391 };
392 static const unsigned sparc_limited_fp_f6 [] = { (1 << REG_FP_F6), 0 };
393 static const arch_register_req_t sparc_single_reg_req_fp_f6 = {
394 arch_register_req_type_limited,
395 &sparc_reg_classes[CLASS_sparc_fp],
396 sparc_limited_fp_f6,
397 0,
398 0,
399 1
400 };
401 static const unsigned sparc_limited_fp_f7 [] = { (1 << REG_FP_F7), 0 };
402 static const arch_register_req_t sparc_single_reg_req_fp_f7 = {
403 arch_register_req_type_limited,
404 &sparc_reg_classes[CLASS_sparc_fp],
405 sparc_limited_fp_f7,
406 0,
407 0,
408 1
409 };
410 static const unsigned sparc_limited_fp_f8 [] = { (1 << REG_FP_F8), 0 };
411 static const arch_register_req_t sparc_single_reg_req_fp_f8 = {
412 arch_register_req_type_limited,
413 &sparc_reg_classes[CLASS_sparc_fp],
414 sparc_limited_fp_f8,
415 0,
416 0,
417 1
418 };
419 static const unsigned sparc_limited_fp_f9 [] = { (1 << REG_FP_F9), 0 };
420 static const arch_register_req_t sparc_single_reg_req_fp_f9 = {
421 arch_register_req_type_limited,
422 &sparc_reg_classes[CLASS_sparc_fp],
423 sparc_limited_fp_f9,
424 0,
425 0,
426 1
427 };
428 static const unsigned sparc_limited_fp_f10 [] = { (1 << REG_FP_F10), 0 };
429 static const arch_register_req_t sparc_single_reg_req_fp_f10 = {
430 arch_register_req_type_limited,
431 &sparc_reg_classes[CLASS_sparc_fp],
432 sparc_limited_fp_f10,
433 0,
434 0,
435 1
436 };
437 static const unsigned sparc_limited_fp_f11 [] = { (1 << REG_FP_F11), 0 };
438 static const arch_register_req_t sparc_single_reg_req_fp_f11 = {
439 arch_register_req_type_limited,
440 &sparc_reg_classes[CLASS_sparc_fp],
441 sparc_limited_fp_f11,
442 0,
443 0,
444 1
445 };
446 static const unsigned sparc_limited_fp_f12 [] = { (1 << REG_FP_F12), 0 };
447 static const arch_register_req_t sparc_single_reg_req_fp_f12 = {
448 arch_register_req_type_limited,
449 &sparc_reg_classes[CLASS_sparc_fp],
450 sparc_limited_fp_f12,
451 0,
452 0,
453 1
454 };
455 static const unsigned sparc_limited_fp_f13 [] = { (1 << REG_FP_F13), 0 };
456 static const arch_register_req_t sparc_single_reg_req_fp_f13 = {
457 arch_register_req_type_limited,
458 &sparc_reg_classes[CLASS_sparc_fp],
459 sparc_limited_fp_f13,
460 0,
461 0,
462 1
463 };
464 static const unsigned sparc_limited_fp_f14 [] = { (1 << REG_FP_F14), 0 };
465 static const arch_register_req_t sparc_single_reg_req_fp_f14 = {
466 arch_register_req_type_limited,
467 &sparc_reg_classes[CLASS_sparc_fp],
468 sparc_limited_fp_f14,
469 0,
470 0,
471 1
472 };
473 static const unsigned sparc_limited_fp_f15 [] = { (1 << REG_FP_F15), 0 };
474 static const arch_register_req_t sparc_single_reg_req_fp_f15 = {
475 arch_register_req_type_limited,
476 &sparc_reg_classes[CLASS_sparc_fp],
477 sparc_limited_fp_f15,
478 0,
479 0,
480 1
481 };
482 static const unsigned sparc_limited_fp_f16 [] = { (1 << REG_FP_F16), 0 };
483 static const arch_register_req_t sparc_single_reg_req_fp_f16 = {
484 arch_register_req_type_limited,
485 &sparc_reg_classes[CLASS_sparc_fp],
486 sparc_limited_fp_f16,
487 0,
488 0,
489 1
490 };
491 static const unsigned sparc_limited_fp_f17 [] = { (1 << REG_FP_F17), 0 };
492 static const arch_register_req_t sparc_single_reg_req_fp_f17 = {
493 arch_register_req_type_limited,
494 &sparc_reg_classes[CLASS_sparc_fp],
495 sparc_limited_fp_f17,
496 0,
497 0,
498 1
499 };
500 static const unsigned sparc_limited_fp_f18 [] = { (1 << REG_FP_F18), 0 };
501 static const arch_register_req_t sparc_single_reg_req_fp_f18 = {
502 arch_register_req_type_limited,
503 &sparc_reg_classes[CLASS_sparc_fp],
504 sparc_limited_fp_f18,
505 0,
506 0,
507 1
508 };
509 static const unsigned sparc_limited_fp_f19 [] = { (1 << REG_FP_F19), 0 };
510 static const arch_register_req_t sparc_single_reg_req_fp_f19 = {
511 arch_register_req_type_limited,
512 &sparc_reg_classes[CLASS_sparc_fp],
513 sparc_limited_fp_f19,
514 0,
515 0,
516 1
517 };
518 static const unsigned sparc_limited_fp_f20 [] = { (1 << REG_FP_F20), 0 };
519 static const arch_register_req_t sparc_single_reg_req_fp_f20 = {
520 arch_register_req_type_limited,
521 &sparc_reg_classes[CLASS_sparc_fp],
522 sparc_limited_fp_f20,
523 0,
524 0,
525 1
526 };
527 static const unsigned sparc_limited_fp_f21 [] = { (1 << REG_FP_F21), 0 };
528 static const arch_register_req_t sparc_single_reg_req_fp_f21 = {
529 arch_register_req_type_limited,
530 &sparc_reg_classes[CLASS_sparc_fp],
531 sparc_limited_fp_f21,
532 0,
533 0,
534 1
535 };
536 static const unsigned sparc_limited_fp_f22 [] = { (1 << REG_FP_F22), 0 };
537 static const arch_register_req_t sparc_single_reg_req_fp_f22 = {
538 arch_register_req_type_limited,
539 &sparc_reg_classes[CLASS_sparc_fp],
540 sparc_limited_fp_f22,
541 0,
542 0,
543 1
544 };
545 static const unsigned sparc_limited_fp_f23 [] = { (1 << REG_FP_F23), 0 };
546 static const arch_register_req_t sparc_single_reg_req_fp_f23 = {
547 arch_register_req_type_limited,
548 &sparc_reg_classes[CLASS_sparc_fp],
549 sparc_limited_fp_f23,
550 0,
551 0,
552 1
553 };
554 static const unsigned sparc_limited_fp_f24 [] = { (1 << REG_FP_F24), 0 };
555 static const arch_register_req_t sparc_single_reg_req_fp_f24 = {
556 arch_register_req_type_limited,
557 &sparc_reg_classes[CLASS_sparc_fp],
558 sparc_limited_fp_f24,
559 0,
560 0,
561 1
562 };
563 static const unsigned sparc_limited_fp_f25 [] = { (1 << REG_FP_F25), 0 };
564 static const arch_register_req_t sparc_single_reg_req_fp_f25 = {
565 arch_register_req_type_limited,
566 &sparc_reg_classes[CLASS_sparc_fp],
567 sparc_limited_fp_f25,
568 0,
569 0,
570 1
571 };
572 static const unsigned sparc_limited_fp_f26 [] = { (1 << REG_FP_F26), 0 };
573 static const arch_register_req_t sparc_single_reg_req_fp_f26 = {
574 arch_register_req_type_limited,
575 &sparc_reg_classes[CLASS_sparc_fp],
576 sparc_limited_fp_f26,
577 0,
578 0,
579 1
580 };
581 static const unsigned sparc_limited_fp_f27 [] = { (1 << REG_FP_F27), 0 };
582 static const arch_register_req_t sparc_single_reg_req_fp_f27 = {
583 arch_register_req_type_limited,
584 &sparc_reg_classes[CLASS_sparc_fp],
585 sparc_limited_fp_f27,
586 0,
587 0,
588 1
589 };
590 static const unsigned sparc_limited_fp_f28 [] = { (1 << REG_FP_F28), 0 };
591 static const arch_register_req_t sparc_single_reg_req_fp_f28 = {
592 arch_register_req_type_limited,
593 &sparc_reg_classes[CLASS_sparc_fp],
594 sparc_limited_fp_f28,
595 0,
596 0,
597 1
598 };
599 static const unsigned sparc_limited_fp_f29 [] = { (1 << REG_FP_F29), 0 };
600 static const arch_register_req_t sparc_single_reg_req_fp_f29 = {
601 arch_register_req_type_limited,
602 &sparc_reg_classes[CLASS_sparc_fp],
603 sparc_limited_fp_f29,
604 0,
605 0,
606 1
607 };
608 static const unsigned sparc_limited_fp_f30 [] = { (1 << REG_FP_F30), 0 };
609 static const arch_register_req_t sparc_single_reg_req_fp_f30 = {
610 arch_register_req_type_limited,
611 &sparc_reg_classes[CLASS_sparc_fp],
612 sparc_limited_fp_f30,
613 0,
614 0,
615 1
616 };
617 static const unsigned sparc_limited_fp_f31 [] = { (1 << REG_FP_F31), 0 };
618 static const arch_register_req_t sparc_single_reg_req_fp_f31 = {
619 arch_register_req_type_limited,
620 &sparc_reg_classes[CLASS_sparc_fp],
621 sparc_limited_fp_f31,
622 0,
623 0,
624 1
625 };
626 static const arch_register_req_t sparc_class_reg_req_mul_div_high_res = {
627 arch_register_req_type_normal,
628 &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
629 NULL,
630 0,
631 0,
632 1
633 };
634 static const unsigned sparc_limited_mul_div_high_res_y [] = { (1 << REG_MUL_DIV_HIGH_RES_Y) };
635 static const arch_register_req_t sparc_single_reg_req_mul_div_high_res_y = {
636 arch_register_req_type_limited,
637 &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
638 sparc_limited_mul_div_high_res_y,
639 0,
640 0,
641 1
642 };
643 static const arch_register_req_t sparc_class_reg_req_flags_class = {
644 arch_register_req_type_normal,
645 &sparc_reg_classes[CLASS_sparc_flags_class],
646 NULL,
647 0,
648 0,
649 1
650 };
651 static const unsigned sparc_limited_flags_class_flags [] = { (1 << REG_FLAGS_CLASS_FLAGS) };
652 static const arch_register_req_t sparc_single_reg_req_flags_class_flags = {
653 arch_register_req_type_limited,
654 &sparc_reg_classes[CLASS_sparc_flags_class],
655 sparc_limited_flags_class_flags,
656 0,
657 0,
658 1
659 };
660
661 arch_register_class_t sparc_reg_classes[] = {
662 { 0, "sparc_fpflags_class", 1, NULL, &sparc_registers[REG_FPFLAGS], arch_register_class_flag_manual_ra, &sparc_class_reg_req_fpflags_class },
663 { 1, "sparc_gp", 32, NULL, &sparc_registers[REG_L0], arch_register_class_flag_none, &sparc_class_reg_req_gp },
664 { 2, "sparc_fp", 32, NULL, &sparc_registers[REG_F0], arch_register_class_flag_none, &sparc_class_reg_req_fp },
665 { 3, "sparc_mul_div_high_res", 1, NULL, &sparc_registers[REG_Y], arch_register_class_flag_manual_ra, &sparc_class_reg_req_mul_div_high_res },
666 { 4, "sparc_flags_class", 1, NULL, &sparc_registers[REG_FLAGS], arch_register_class_flag_manual_ra, &sparc_class_reg_req_flags_class }
667 };
668
669
670 /** The array of all registers in the sparc architecture, sorted by its global index.*/
671 const arch_register_t sparc_registers[] = {
672 {
673 "fpflags",
674 &sparc_reg_classes[CLASS_sparc_fpflags_class],
675 REG_FPFLAGS_CLASS_FPFLAGS,
676 REG_FPFLAGS,
677 arch_register_type_none,
678 &sparc_single_reg_req_fpflags_class_fpflags,
679 0
680 },
681 {
682 "l0",
683 &sparc_reg_classes[CLASS_sparc_gp],
684 REG_GP_L0,
685 REG_L0,
686 arch_register_type_none,
687 &sparc_single_reg_req_gp_l0,
688 16
689 },
690 {
691 "l1",
692 &sparc_reg_classes[CLASS_sparc_gp],
693 REG_GP_L1,
694 REG_L1,
695 arch_register_type_none,
696 &sparc_single_reg_req_gp_l1,
697 17
698 },
699 {
700 "l2",
701 &sparc_reg_classes[CLASS_sparc_gp],
702 REG_GP_L2,
703 REG_L2,
704 arch_register_type_none,
705 &sparc_single_reg_req_gp_l2,
706 18
707 },
708 {
709 "l3",
710 &sparc_reg_classes[CLASS_sparc_gp],
711 REG_GP_L3,
712 REG_L3,
713 arch_register_type_none,
714 &sparc_single_reg_req_gp_l3,
715 19
716 },
717 {
718 "l4",
719 &sparc_reg_classes[CLASS_sparc_gp],
720 REG_GP_L4,
721 REG_L4,
722 arch_register_type_none,
723 &sparc_single_reg_req_gp_l4,
724 20
725 },
726 {
727 "l5",
728 &sparc_reg_classes[CLASS_sparc_gp],
729 REG_GP_L5,
730 REG_L5,
731 arch_register_type_none,
732 &sparc_single_reg_req_gp_l5,
733 21
734 },
735 {
736 "l6",
737 &sparc_reg_classes[CLASS_sparc_gp],
738 REG_GP_L6,
739 REG_L6,
740 arch_register_type_none,
741 &sparc_single_reg_req_gp_l6,
742 22
743 },
744 {
745 "l7",
746 &sparc_reg_classes[CLASS_sparc_gp],
747 REG_GP_L7,
748 REG_L7,
749 arch_register_type_none,
750 &sparc_single_reg_req_gp_l7,
751 23
752 },
753 {
754 "g0",
755 &sparc_reg_classes[CLASS_sparc_gp],
756 REG_GP_G0,
757 REG_G0,
758 arch_register_type_none,
759 &sparc_single_reg_req_gp_g0,
760 0
761 },
762 {
763 "g1",
764 &sparc_reg_classes[CLASS_sparc_gp],
765 REG_GP_G1,
766 REG_G1,
767 arch_register_type_none,
768 &sparc_single_reg_req_gp_g1,
769 1
770 },
771 {
772 "g2",
773 &sparc_reg_classes[CLASS_sparc_gp],
774 REG_GP_G2,
775 REG_G2,
776 arch_register_type_none,
777 &sparc_single_reg_req_gp_g2,
778 2
779 },
780 {
781 "g3",
782 &sparc_reg_classes[CLASS_sparc_gp],
783 REG_GP_G3,
784 REG_G3,
785 arch_register_type_none,
786 &sparc_single_reg_req_gp_g3,
787 3
788 },
789 {
790 "g4",
791 &sparc_reg_classes[CLASS_sparc_gp],
792 REG_GP_G4,
793 REG_G4,
794 arch_register_type_none,
795 &sparc_single_reg_req_gp_g4,
796 4
797 },
798 {
799 "g5",
800 &sparc_reg_classes[CLASS_sparc_gp],
801 REG_GP_G5,
802 REG_G5,
803 arch_register_type_none,
804 &sparc_single_reg_req_gp_g5,
805 5
806 },
807 {
808 "g6",
809 &sparc_reg_classes[CLASS_sparc_gp],
810 REG_GP_G6,
811 REG_G6,
812 arch_register_type_none,
813 &sparc_single_reg_req_gp_g6,
814 6
815 },
816 {
817 "g7",
818 &sparc_reg_classes[CLASS_sparc_gp],
819 REG_GP_G7,
820 REG_G7,
821 arch_register_type_none,
822 &sparc_single_reg_req_gp_g7,
823 7
824 },
825 {
826 "o0",
827 &sparc_reg_classes[CLASS_sparc_gp],
828 REG_GP_O0,
829 REG_O0,
830 arch_register_type_none,
831 &sparc_single_reg_req_gp_o0,
832 8
833 },
834 {
835 "o1",
836 &sparc_reg_classes[CLASS_sparc_gp],
837 REG_GP_O1,
838 REG_O1,
839 arch_register_type_none,
840 &sparc_single_reg_req_gp_o1,
841 9
842 },
843 {
844 "o2",
845 &sparc_reg_classes[CLASS_sparc_gp],
846 REG_GP_O2,
847 REG_O2,
848 arch_register_type_none,
849 &sparc_single_reg_req_gp_o2,
850 10
851 },
852 {
853 "o3",
854 &sparc_reg_classes[CLASS_sparc_gp],
855 REG_GP_O3,
856 REG_O3,
857 arch_register_type_none,
858 &sparc_single_reg_req_gp_o3,
859 11
860 },
861 {
862 "o4",
863 &sparc_reg_classes[CLASS_sparc_gp],
864 REG_GP_O4,
865 REG_O4,
866 arch_register_type_none,
867 &sparc_single_reg_req_gp_o4,
868 12
869 },
870 {
871 "o5",
872 &sparc_reg_classes[CLASS_sparc_gp],
873 REG_GP_O5,
874 REG_O5,
875 arch_register_type_none,
876 &sparc_single_reg_req_gp_o5,
877 13
878 },
879 {
880 "sp",
881 &sparc_reg_classes[CLASS_sparc_gp],
882 REG_GP_SP,
883 REG_SP,
884 arch_register_type_none,
885 &sparc_single_reg_req_gp_sp,
886 14
887 },
888 {
889 "o7",
890 &sparc_reg_classes[CLASS_sparc_gp],
891 REG_GP_O7,
892 REG_O7,
893 arch_register_type_none,
894 &sparc_single_reg_req_gp_o7,
895 15
896 },
897 {
898 "i0",
899 &sparc_reg_classes[CLASS_sparc_gp],
900 REG_GP_I0,
901 REG_I0,
902 arch_register_type_none,
903 &sparc_single_reg_req_gp_i0,
904 24
905 },
906 {
907 "i1",
908 &sparc_reg_classes[CLASS_sparc_gp],
909 REG_GP_I1,
910 REG_I1,
911 arch_register_type_none,
912 &sparc_single_reg_req_gp_i1,
913 25
914 },
915 {
916 "i2",
917 &sparc_reg_classes[CLASS_sparc_gp],
918 REG_GP_I2,
919 REG_I2,
920 arch_register_type_none,
921 &sparc_single_reg_req_gp_i2,
922 26
923 },
924 {
925 "i3",
926 &sparc_reg_classes[CLASS_sparc_gp],
927 REG_GP_I3,
928 REG_I3,
929 arch_register_type_none,
930 &sparc_single_reg_req_gp_i3,
931 27
932 },
933 {
934 "i4",
935 &sparc_reg_classes[CLASS_sparc_gp],
936 REG_GP_I4,
937 REG_I4,
938 arch_register_type_none,
939 &sparc_single_reg_req_gp_i4,
940 28
941 },
942 {
943 "i5",
944 &sparc_reg_classes[CLASS_sparc_gp],
945 REG_GP_I5,
946 REG_I5,
947 arch_register_type_none,
948 &sparc_single_reg_req_gp_i5,
949 29
950 },
951 {
952 "fp",
953 &sparc_reg_classes[CLASS_sparc_gp],
954 REG_GP_FRAME_POINTER,
955 REG_FRAME_POINTER,
956 arch_register_type_none,
957 &sparc_single_reg_req_gp_frame_pointer,
958 30
959 },
960 {
961 "i7",
962 &sparc_reg_classes[CLASS_sparc_gp],
963 REG_GP_I7,
964 REG_I7,
965 arch_register_type_none,
966 &sparc_single_reg_req_gp_i7,
967 30
968 },
969 {
970 "f0",
971 &sparc_reg_classes[CLASS_sparc_fp],
972 REG_FP_F0,
973 REG_F0,
974 arch_register_type_none,
975 &sparc_single_reg_req_fp_f0,
976 32
977 },
978 {
979 "f1",
980 &sparc_reg_classes[CLASS_sparc_fp],
981 REG_FP_F1,
982 REG_F1,
983 arch_register_type_none,
984 &sparc_single_reg_req_fp_f1,
985 33
986 },
987 {
988 "f2",
989 &sparc_reg_classes[CLASS_sparc_fp],
990 REG_FP_F2,
991 REG_F2,
992 arch_register_type_none,
993 &sparc_single_reg_req_fp_f2,
994 34
995 },
996 {
997 "f3",
998 &sparc_reg_classes[CLASS_sparc_fp],
999 REG_FP_F3,
1000 REG_F3,
1001 arch_register_type_none,
1002 &sparc_single_reg_req_fp_f3,
1003 35
1004 },
1005 {
1006 "f4",
1007 &sparc_reg_classes[CLASS_sparc_fp],
1008 REG_FP_F4,
1009 REG_F4,
1010 arch_register_type_none,
1011 &sparc_single_reg_req_fp_f4,
1012 36
1013 },
1014 {
1015 "f5",
1016 &sparc_reg_classes[CLASS_sparc_fp],
1017 REG_FP_F5,
1018 REG_F5,
1019 arch_register_type_none,
1020 &sparc_single_reg_req_fp_f5,
1021 37
1022 },
1023 {
1024 "f6",
1025 &sparc_reg_classes[CLASS_sparc_fp],
1026 REG_FP_F6,
1027 REG_F6,
1028 arch_register_type_none,
1029 &sparc_single_reg_req_fp_f6,
1030 38
1031 },
1032 {
1033 "f7",
1034 &sparc_reg_classes[CLASS_sparc_fp],
1035 REG_FP_F7,
1036 REG_F7,
1037 arch_register_type_none,
1038 &sparc_single_reg_req_fp_f7,
1039 39
1040 },
1041 {
1042 "f8",
1043 &sparc_reg_classes[CLASS_sparc_fp],
1044 REG_FP_F8,
1045 REG_F8,
1046 arch_register_type_none,
1047 &sparc_single_reg_req_fp_f8,
1048 40
1049 },
1050 {
1051 "f9",
1052 &sparc_reg_classes[CLASS_sparc_fp],
1053 REG_FP_F9,
1054 REG_F9,
1055 arch_register_type_none,
1056 &sparc_single_reg_req_fp_f9,
1057 41
1058 },
1059 {
1060 "f10",
1061 &sparc_reg_classes[CLASS_sparc_fp],
1062 REG_FP_F10,
1063 REG_F10,
1064 arch_register_type_none,
1065 &sparc_single_reg_req_fp_f10,
1066 42
1067 },
1068 {
1069 "f11",
1070 &sparc_reg_classes[CLASS_sparc_fp],
1071 REG_FP_F11,
1072 REG_F11,
1073 arch_register_type_none,
1074 &sparc_single_reg_req_fp_f11,
1075 43
1076 },
1077 {
1078 "f12",
1079 &sparc_reg_classes[CLASS_sparc_fp],
1080 REG_FP_F12,
1081 REG_F12,
1082 arch_register_type_none,
1083 &sparc_single_reg_req_fp_f12,
1084 44
1085 },
1086 {
1087 "f13",
1088 &sparc_reg_classes[CLASS_sparc_fp],
1089 REG_FP_F13,
1090 REG_F13,
1091 arch_register_type_none,
1092 &sparc_single_reg_req_fp_f13,
1093 45
1094 },
1095 {
1096 "f14",
1097 &sparc_reg_classes[CLASS_sparc_fp],
1098 REG_FP_F14,
1099 REG_F14,
1100 arch_register_type_none,
1101 &sparc_single_reg_req_fp_f14,
1102 46
1103 },
1104 {
1105 "f15",
1106 &sparc_reg_classes[CLASS_sparc_fp],
1107 REG_FP_F15,
1108 REG_F15,
1109 arch_register_type_none,
1110 &sparc_single_reg_req_fp_f15,
1111 47
1112 },
1113 {
1114 "f16",
1115 &sparc_reg_classes[CLASS_sparc_fp],
1116 REG_FP_F16,
1117 REG_F16,
1118 arch_register_type_none,
1119 &sparc_single_reg_req_fp_f16,
1120 48
1121 },
1122 {
1123 "f17",
1124 &sparc_reg_classes[CLASS_sparc_fp],
1125 REG_FP_F17,
1126 REG_F17,
1127 arch_register_type_none,
1128 &sparc_single_reg_req_fp_f17,
1129 49
1130 },
1131 {
1132 "f18",
1133 &sparc_reg_classes[CLASS_sparc_fp],
1134 REG_FP_F18,
1135 REG_F18,
1136 arch_register_type_none,
1137 &sparc_single_reg_req_fp_f18,
1138 50
1139 },
1140 {
1141 "f19",
1142 &sparc_reg_classes[CLASS_sparc_fp],
1143 REG_FP_F19,
1144 REG_F19,
1145 arch_register_type_none,
1146 &sparc_single_reg_req_fp_f19,
1147 51
1148 },
1149 {
1150 "f20",
1151 &sparc_reg_classes[CLASS_sparc_fp],
1152 REG_FP_F20,
1153 REG_F20,
1154 arch_register_type_none,
1155 &sparc_single_reg_req_fp_f20,
1156 52
1157 },
1158 {
1159 "f21",
1160 &sparc_reg_classes[CLASS_sparc_fp],
1161 REG_FP_F21,
1162 REG_F21,
1163 arch_register_type_none,
1164 &sparc_single_reg_req_fp_f21,
1165 53
1166 },
1167 {
1168 "f22",
1169 &sparc_reg_classes[CLASS_sparc_fp],
1170 REG_FP_F22,
1171 REG_F22,
1172 arch_register_type_none,
1173 &sparc_single_reg_req_fp_f22,
1174 54
1175 },
1176 {
1177 "f23",
1178 &sparc_reg_classes[CLASS_sparc_fp],
1179 REG_FP_F23,
1180 REG_F23,
1181 arch_register_type_none,
1182 &sparc_single_reg_req_fp_f23,
1183 55
1184 },
1185 {
1186 "f24",
1187 &sparc_reg_classes[CLASS_sparc_fp],
1188 REG_FP_F24,
1189 REG_F24,
1190 arch_register_type_none,
1191 &sparc_single_reg_req_fp_f24,
1192 56
1193 },
1194 {
1195 "f25",
1196 &sparc_reg_classes[CLASS_sparc_fp],
1197 REG_FP_F25,
1198 REG_F25,
1199 arch_register_type_none,
1200 &sparc_single_reg_req_fp_f25,
1201 57
1202 },
1203 {
1204 "f26",
1205 &sparc_reg_classes[CLASS_sparc_fp],
1206 REG_FP_F26,
1207 REG_F26,
1208 arch_register_type_none,
1209 &sparc_single_reg_req_fp_f26,
1210 58
1211 },
1212 {
1213 "f27",
1214 &sparc_reg_classes[CLASS_sparc_fp],
1215 REG_FP_F27,
1216 REG_F27,
1217 arch_register_type_none,
1218 &sparc_single_reg_req_fp_f27,
1219 59
1220 },
1221 {
1222 "f28",
1223 &sparc_reg_classes[CLASS_sparc_fp],
1224 REG_FP_F28,
1225 REG_F28,
1226 arch_register_type_none,
1227 &sparc_single_reg_req_fp_f28,
1228 60
1229 },
1230 {
1231 "f29",
1232 &sparc_reg_classes[CLASS_sparc_fp],
1233 REG_FP_F29,
1234 REG_F29,
1235 arch_register_type_none,
1236 &sparc_single_reg_req_fp_f29,
1237 61
1238 },
1239 {
1240 "f30",
1241 &sparc_reg_classes[CLASS_sparc_fp],
1242 REG_FP_F30,
1243 REG_F30,
1244 arch_register_type_none,
1245 &sparc_single_reg_req_fp_f30,
1246 62
1247 },
1248 {
1249 "f31",
1250 &sparc_reg_classes[CLASS_sparc_fp],
1251 REG_FP_F31,
1252 REG_F31,
1253 arch_register_type_none,
1254 &sparc_single_reg_req_fp_f31,
1255 63
1256 },
1257 {
1258 "y",
1259 &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
1260 REG_MUL_DIV_HIGH_RES_Y,
1261 REG_Y,
1262 arch_register_type_none,
1263 &sparc_single_reg_req_mul_div_high_res_y,
1264 0
1265 },
1266 {
1267 "flags",
1268 &sparc_reg_classes[CLASS_sparc_flags_class],
1269 REG_FLAGS_CLASS_FLAGS,
1270 REG_FLAGS,
1271 arch_register_type_none,
1272 &sparc_single_reg_req_flags_class_flags,
1273 0
1274 },
1275
1276 };
1277
1278 /**
1279 * Initializes sparc register classes.
1280 */
sparc_register_init(void)1281 void sparc_register_init(void)
1282 {
1283 sparc_reg_classes[CLASS_sparc_fpflags_class].mode = mode_Bu;
1284 sparc_reg_classes[CLASS_sparc_gp].mode = mode_Iu;
1285 sparc_reg_classes[CLASS_sparc_fp].mode = mode_F;
1286 sparc_reg_classes[CLASS_sparc_mul_div_high_res].mode = mode_Iu;
1287 sparc_reg_classes[CLASS_sparc_flags_class].mode = mode_Bu;
1288
1289 }
1290