1 /*
2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
3 *
4 * This file is part of libFirm.
5 *
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
10 *
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
14 *
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE.
18 */
19
20 /**
21 * @file
22 * @brief calling convention helpers
23 * @author Matthias Braun
24 */
25 #include "config.h"
26
27 #include "sparc_cconv.h"
28 #include "irmode.h"
29 #include "irgwalk.h"
30 #include "typerep.h"
31 #include "xmalloc.h"
32 #include "util.h"
33 #include "error.h"
34 #include "gen_sparc_regalloc_if.h"
35 #include "bitfiddle.h"
36
37 static const unsigned ignore_regs[] = {
38 REG_G0,
39 /* used in case an address offset does not fit into an immediate: */
40 REG_G4,
41 /* reserved for SPARC ABI: */
42 REG_G5,
43 REG_G6,
44 REG_G7,
45
46 REG_SP,
47 REG_O7,
48 REG_FRAME_POINTER,
49 REG_I7,
50
51 REG_FPFLAGS,
52 REG_FLAGS,
53 REG_Y,
54
55 REG_F31,
56 };
57
58 static const arch_register_t* const param_regs[] = {
59 &sparc_registers[REG_I0],
60 &sparc_registers[REG_I1],
61 &sparc_registers[REG_I2],
62 &sparc_registers[REG_I3],
63 &sparc_registers[REG_I4],
64 &sparc_registers[REG_I5],
65 };
66 COMPILETIME_ASSERT(ARRAY_SIZE(param_regs) == SPARC_N_PARAM_REGS, sparcparamregs)
67
68 static const arch_register_t* const float_result_regs[] = {
69 &sparc_registers[REG_F0],
70 &sparc_registers[REG_F1],
71 &sparc_registers[REG_F2],
72 &sparc_registers[REG_F3],
73 &sparc_registers[REG_F4],
74 &sparc_registers[REG_F5],
75 &sparc_registers[REG_F6],
76 &sparc_registers[REG_F7],
77 };
78 static arch_register_req_t float_result_reqs_double[8];
79 static arch_register_req_t float_result_reqs_quad[8];
80
81 static const unsigned caller_saves[] = {
82 REG_G1,
83 REG_G2,
84 REG_G3,
85 REG_O0,
86 REG_O1,
87 REG_O2,
88 REG_O3,
89 REG_O4,
90 REG_O5,
91 REG_F0,
92 REG_F1,
93 REG_F2,
94 REG_F3,
95 REG_F4,
96 REG_F5,
97 REG_F6,
98 REG_F7,
99 REG_F8,
100 REG_F9,
101 REG_F10,
102 REG_F11,
103 REG_F12,
104 REG_F13,
105 REG_F14,
106 REG_F15,
107 REG_F16,
108 REG_F17,
109 REG_F18,
110 REG_F19,
111 REG_F20,
112 REG_F21,
113 REG_F22,
114 REG_F23,
115 REG_F24,
116 REG_F25,
117 REG_F26,
118 REG_F27,
119 REG_F28,
120 REG_F29,
121 REG_F30,
122 REG_FLAGS,
123 REG_FPFLAGS,
124 REG_Y,
125 };
126 static unsigned default_caller_saves[BITSET_SIZE_ELEMS(N_SPARC_REGISTERS)];
127
128 static const unsigned returns_twice_saved[] = {
129 REG_SP,
130 REG_FRAME_POINTER,
131 REG_I7
132 };
133 static unsigned default_returns_twice_saves[BITSET_SIZE_ELEMS(N_SPARC_REGISTERS)];
134
135 /**
136 * Maps an input register representing the i'th register input
137 * to the i'th register output.
138 */
map_i_to_o_reg(const arch_register_t * reg)139 static const arch_register_t *map_i_to_o_reg(const arch_register_t *reg)
140 {
141 unsigned idx = reg->global_index;
142 assert(REG_I0 <= idx && idx <= REG_I7);
143 idx += REG_O0 - REG_I0;
144 assert(REG_O0 <= idx && idx <= REG_O7);
145 return &sparc_registers[idx];
146 }
147
check_omit_fp(ir_node * node,void * env)148 static void check_omit_fp(ir_node *node, void *env)
149 {
150 /* omit-fp is not possible if:
151 * - we have allocations on the stack
152 * - we have calls (with the exception of tail-calls once we support them)
153 */
154 if ((is_Alloc(node) && get_Alloc_where(node) == stack_alloc)
155 || (is_Free(node) && get_Free_where(node) == stack_alloc)
156 || is_Call(node)) {
157 bool *can_omit_fp = (bool*) env;
158 *can_omit_fp = false;
159 }
160 }
161
determine_n_float_regs(ir_mode * mode)162 static unsigned determine_n_float_regs(ir_mode *mode)
163 {
164 unsigned bits = get_mode_size_bits(mode);
165 switch (bits) {
166 case 32:
167 return 1;
168 case 64:
169 return 2;
170 case 128:
171 return 4;
172 default:
173 panic("Unexpected floatingpoint mode %+F", mode);
174 }
175 }
176
sparc_decide_calling_convention(ir_type * function_type,ir_graph * irg)177 calling_convention_t *sparc_decide_calling_convention(ir_type *function_type,
178 ir_graph *irg)
179 {
180 bool omit_fp = false;
181 if (irg != NULL) {
182 omit_fp = be_options.omit_fp;
183 /* our current vaarg handling needs the standard space to store the
184 * args 0-5 in it */
185 if (get_method_variadicity(function_type) == variadicity_variadic)
186 omit_fp = false;
187 if (omit_fp == true) {
188 irg_walk_graph(irg, check_omit_fp, NULL, &omit_fp);
189 }
190 }
191
192 mtp_additional_properties mtp
193 = get_method_additional_properties(function_type);
194 unsigned *caller_saves = rbitset_malloc(N_SPARC_REGISTERS);
195 if (mtp & mtp_property_returns_twice) {
196 rbitset_copy(caller_saves, default_returns_twice_saves,
197 N_SPARC_REGISTERS);
198 } else {
199 rbitset_copy(caller_saves, default_caller_saves, N_SPARC_REGISTERS);
200 }
201
202 /* determine how parameters are passed */
203 int n_params = get_method_n_params(function_type);
204 int regnum = 0;
205 reg_or_stackslot_t *params = XMALLOCNZ(reg_or_stackslot_t, n_params);
206
207 int n_param_regs = ARRAY_SIZE(param_regs);
208 unsigned stack_offset = 0;
209 for (int i = 0; i < n_params; ++i) {
210 ir_type *param_type = get_method_param_type(function_type,i);
211 ir_mode *mode;
212 int bits;
213 reg_or_stackslot_t *param;
214
215 if (is_compound_type(param_type))
216 panic("compound arguments not supported yet");
217
218 mode = get_type_mode(param_type);
219 bits = get_mode_size_bits(mode);
220 param = ¶ms[i];
221
222 if (i == 0 &&
223 (get_method_calling_convention(function_type) & cc_compound_ret)) {
224 assert(mode_is_reference(mode) && bits == 32);
225 /* special case, we have reserved space for this on the between
226 * type */
227 param->type = param_type;
228 param->offset = -SPARC_MIN_STACKSIZE+SPARC_AGGREGATE_RETURN_OFFSET;
229 continue;
230 }
231
232 if (regnum < n_param_regs) {
233 const arch_register_t *reg = param_regs[regnum];
234 if (irg == NULL || omit_fp)
235 reg = map_i_to_o_reg(reg);
236 param->reg0 = reg;
237 param->req0 = reg->single_req;
238 param->reg_offset = regnum;
239 ++regnum;
240 } else {
241 param->type = param_type;
242 param->offset = stack_offset;
243 /* increase offset by at least SPARC_REGISTER_SIZE bytes so everything is aligned */
244 stack_offset += bits > 8 * SPARC_REGISTER_SIZE ? bits / 8 : SPARC_REGISTER_SIZE;
245 continue;
246 }
247
248 /* we might need a 2nd 32bit component (for 64bit or double values) */
249 if (bits > 32) {
250 if (bits > 64)
251 panic("only 32 and 64bit modes supported");
252
253 if (regnum < n_param_regs) {
254 const arch_register_t *reg = param_regs[regnum];
255 if (irg == NULL || omit_fp)
256 reg = map_i_to_o_reg(reg);
257 param->reg1 = reg;
258 param->req1 = reg->single_req;
259 ++regnum;
260 } else {
261 ir_mode *regmode = param_regs[0]->reg_class->mode;
262 ir_type *type = get_type_for_mode(regmode);
263 param->type = type;
264 param->offset = stack_offset;
265 assert(get_mode_size_bits(regmode) == 32);
266 stack_offset += SPARC_REGISTER_SIZE;
267 }
268 }
269 }
270 unsigned n_param_regs_used = regnum;
271
272 /* determine how results are passed */
273 int n_results = get_method_n_ress(function_type);
274 unsigned float_regnum = 0;
275 unsigned n_reg_results = 0;
276 unsigned n_float_result_regs = ARRAY_SIZE(float_result_regs);
277 reg_or_stackslot_t *results = XMALLOCNZ(reg_or_stackslot_t, n_results);
278 regnum = 0;
279 for (int i = 0; i < n_results; ++i) {
280 ir_type *result_type = get_method_res_type(function_type, i);
281 ir_mode *result_mode = get_type_mode(result_type);
282 reg_or_stackslot_t *result = &results[i];
283
284 if (mode_is_float(result_mode)) {
285 unsigned n_regs = determine_n_float_regs(result_mode);
286 unsigned next_reg = round_up2(float_regnum, n_regs);
287
288 if (next_reg >= n_float_result_regs) {
289 panic("Too many float results");
290 } else {
291 const arch_register_t *reg = float_result_regs[next_reg];
292 rbitset_clear(caller_saves, reg->global_index);
293 result->reg_offset = i;
294 if (n_regs == 1) {
295 result->req0 = reg->single_req;
296 } else if (n_regs == 2) {
297 result->req0 = &float_result_reqs_double[next_reg];
298 rbitset_clear(caller_saves, reg->global_index+1);
299 } else if (n_regs == 4) {
300 result->req0 = &float_result_reqs_quad[next_reg];
301 rbitset_clear(caller_saves, reg->global_index+1);
302 rbitset_clear(caller_saves, reg->global_index+2);
303 rbitset_clear(caller_saves, reg->global_index+3);
304 } else {
305 panic("invalid number of registers in result");
306 }
307 float_regnum = next_reg + n_regs;
308
309 ++n_reg_results;
310 }
311 } else {
312 if (get_mode_size_bits(result_mode) > 32) {
313 panic("Results with more than 32bits not supported yet");
314 }
315
316 if (regnum >= n_param_regs) {
317 panic("Too many results");
318 } else {
319 const arch_register_t *reg = param_regs[regnum++];
320 if (irg == NULL || omit_fp)
321 reg = map_i_to_o_reg(reg);
322 result->req0 = reg->single_req;
323 result->reg_offset = i;
324 rbitset_clear(caller_saves, reg->global_index);
325 ++n_reg_results;
326 }
327 }
328 }
329
330 calling_convention_t *cconv = XMALLOCZ(calling_convention_t);
331 cconv->parameters = params;
332 cconv->param_stack_size = stack_offset;
333 cconv->n_param_regs = n_param_regs_used;
334 cconv->results = results;
335 cconv->omit_fp = omit_fp;
336 cconv->caller_saves = caller_saves;
337 cconv->n_reg_results = n_reg_results;
338
339 /* setup ignore register array */
340 if (irg != NULL) {
341 be_irg_t *birg = be_birg_from_irg(irg);
342 size_t n_ignores = ARRAY_SIZE(ignore_regs);
343 struct obstack *obst = &birg->obst;
344 size_t r;
345
346 birg->allocatable_regs = rbitset_obstack_alloc(obst, N_SPARC_REGISTERS);
347 rbitset_set_all(birg->allocatable_regs, N_SPARC_REGISTERS);
348 for (r = 0; r < n_ignores; ++r) {
349 rbitset_clear(birg->allocatable_regs, ignore_regs[r]);
350 }
351 }
352
353 return cconv;
354 }
355
sparc_free_calling_convention(calling_convention_t * cconv)356 void sparc_free_calling_convention(calling_convention_t *cconv)
357 {
358 free(cconv->parameters);
359 free(cconv->results);
360 free(cconv->caller_saves);
361 free(cconv);
362 }
363
sparc_cconv_init(void)364 void sparc_cconv_init(void)
365 {
366 for (size_t i = 0; i < ARRAY_SIZE(caller_saves); ++i) {
367 rbitset_set(default_caller_saves, caller_saves[i]);
368 }
369
370 rbitset_set_all(default_returns_twice_saves, N_SPARC_REGISTERS);
371 for (size_t i = 0; i < ARRAY_SIZE(returns_twice_saved); ++i) {
372 rbitset_clear(default_returns_twice_saves, returns_twice_saved[i]);
373 }
374 for (size_t i = 0; i < ARRAY_SIZE(ignore_regs); ++i) {
375 rbitset_clear(default_returns_twice_saves, ignore_regs[i]);
376 }
377
378 for (size_t i = 0; i < ARRAY_SIZE(float_result_reqs_double); i += 2) {
379 arch_register_req_t *req = &float_result_reqs_double[i];
380 *req = *float_result_regs[i]->single_req;
381 req->type |= arch_register_req_type_aligned;
382 req->width = 2;
383 }
384 for (size_t i = 0; i < ARRAY_SIZE(float_result_reqs_quad); i += 4) {
385 arch_register_req_t *req = &float_result_reqs_quad[i];
386 *req = *float_result_regs[i]->single_req;
387 req->type |= arch_register_req_type_aligned;
388 req->width = 4;
389 }
390 }
391