1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the XCoreTargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "XCoreISelLowering.h"
14 #include "XCore.h"
15 #include "XCoreMachineFunctionInfo.h"
16 #include "XCoreSubtarget.h"
17 #include "XCoreTargetMachine.h"
18 #include "XCoreTargetObjectFile.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/GlobalAlias.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/IR/Intrinsics.h"
34 #include "llvm/IR/IntrinsicsXCore.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/KnownBits.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include <algorithm>
40
41 using namespace llvm;
42
43 #define DEBUG_TYPE "xcore-lower"
44
45 const char *XCoreTargetLowering::
getTargetNodeName(unsigned Opcode) const46 getTargetNodeName(unsigned Opcode) const
47 {
48 switch ((XCoreISD::NodeType)Opcode)
49 {
50 case XCoreISD::FIRST_NUMBER : break;
51 case XCoreISD::BL : return "XCoreISD::BL";
52 case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
53 case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
54 case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
55 case XCoreISD::LDWSP : return "XCoreISD::LDWSP";
56 case XCoreISD::STWSP : return "XCoreISD::STWSP";
57 case XCoreISD::RETSP : return "XCoreISD::RETSP";
58 case XCoreISD::LADD : return "XCoreISD::LADD";
59 case XCoreISD::LSUB : return "XCoreISD::LSUB";
60 case XCoreISD::LMUL : return "XCoreISD::LMUL";
61 case XCoreISD::MACCU : return "XCoreISD::MACCU";
62 case XCoreISD::MACCS : return "XCoreISD::MACCS";
63 case XCoreISD::CRC8 : return "XCoreISD::CRC8";
64 case XCoreISD::BR_JT : return "XCoreISD::BR_JT";
65 case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32";
66 case XCoreISD::FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET";
67 case XCoreISD::EH_RETURN : return "XCoreISD::EH_RETURN";
68 case XCoreISD::MEMBARRIER : return "XCoreISD::MEMBARRIER";
69 }
70 return nullptr;
71 }
72
XCoreTargetLowering(const TargetMachine & TM,const XCoreSubtarget & Subtarget)73 XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
74 const XCoreSubtarget &Subtarget)
75 : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
76
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
79
80 // Compute derived properties from the register classes
81 computeRegisterProperties(Subtarget.getRegisterInfo());
82
83 setStackPointerRegisterToSaveRestore(XCore::SP);
84
85 setSchedulingPreference(Sched::Source);
86
87 // Use i32 for setcc operations results (slt, sgt, ...).
88 setBooleanContents(ZeroOrOneBooleanContent);
89 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
90
91 // XCore does not have the NodeTypes below.
92 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
93 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
94
95 // 64bit
96 setOperationAction(ISD::ADD, MVT::i64, Custom);
97 setOperationAction(ISD::SUB, MVT::i64, Custom);
98 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
99 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
100 setOperationAction(ISD::MULHS, MVT::i32, Expand);
101 setOperationAction(ISD::MULHU, MVT::i32, Expand);
102 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
103 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
104 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
105
106 // Bit Manipulation
107 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
108 setOperationAction(ISD::ROTL , MVT::i32, Expand);
109 setOperationAction(ISD::ROTR , MVT::i32, Expand);
110 setOperationAction(ISD::BITREVERSE , MVT::i32, Legal);
111
112 setOperationAction(ISD::TRAP, MVT::Other, Legal);
113
114 // Jump tables.
115 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
116
117 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
118 setOperationAction(ISD::BlockAddress, MVT::i32 , Custom);
119
120 // Conversion of i64 -> double produces constantpool nodes
121 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
122
123 // Loads
124 for (MVT VT : MVT::integer_valuetypes()) {
125 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
126 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
127 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
128
129 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
130 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand);
131 }
132
133 // Custom expand misaligned loads / stores.
134 setOperationAction(ISD::LOAD, MVT::i32, Custom);
135 setOperationAction(ISD::STORE, MVT::i32, Custom);
136
137 // Varargs
138 setOperationAction(ISD::VAEND, MVT::Other, Expand);
139 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
140 setOperationAction(ISD::VAARG, MVT::Other, Custom);
141 setOperationAction(ISD::VASTART, MVT::Other, Custom);
142
143 // Dynamic stack
144 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
145 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
146 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
147
148 // Exception handling
149 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
150 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
151
152 // Atomic operations
153 // We request a fence for ATOMIC_* instructions, to reduce them to Monotonic.
154 // As we are always Sequential Consistent, an ATOMIC_FENCE becomes a no OP.
155 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
156 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
157 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
158
159 // TRAMPOLINE is custom lowered.
160 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
161 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
162
163 // We want to custom lower some of our intrinsics.
164 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
165
166 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 4;
167 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize
168 = MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 2;
169
170 // We have target-specific dag combine patterns for the following nodes:
171 setTargetDAGCombine(ISD::STORE);
172 setTargetDAGCombine(ISD::ADD);
173 setTargetDAGCombine(ISD::INTRINSIC_VOID);
174 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
175
176 setMinFunctionAlignment(Align(2));
177 setPrefFunctionAlignment(Align(4));
178 }
179
isZExtFree(SDValue Val,EVT VT2) const180 bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
181 if (Val.getOpcode() != ISD::LOAD)
182 return false;
183
184 EVT VT1 = Val.getValueType();
185 if (!VT1.isSimple() || !VT1.isInteger() ||
186 !VT2.isSimple() || !VT2.isInteger())
187 return false;
188
189 switch (VT1.getSimpleVT().SimpleTy) {
190 default: break;
191 case MVT::i8:
192 return true;
193 }
194
195 return false;
196 }
197
198 SDValue XCoreTargetLowering::
LowerOperation(SDValue Op,SelectionDAG & DAG) const199 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
200 switch (Op.getOpcode())
201 {
202 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
203 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
204 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
205 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
206 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
207 case ISD::LOAD: return LowerLOAD(Op, DAG);
208 case ISD::STORE: return LowerSTORE(Op, DAG);
209 case ISD::VAARG: return LowerVAARG(Op, DAG);
210 case ISD::VASTART: return LowerVASTART(Op, DAG);
211 case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG);
212 case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG);
213 // FIXME: Remove these when LegalizeDAGTypes lands.
214 case ISD::ADD:
215 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
216 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
217 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
218 case ISD::FRAME_TO_ARGS_OFFSET: return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
219 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
220 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
221 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
222 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
223 case ISD::ATOMIC_LOAD: return LowerATOMIC_LOAD(Op, DAG);
224 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op, DAG);
225 default:
226 llvm_unreachable("unimplemented operand");
227 }
228 }
229
230 /// ReplaceNodeResults - Replace the results of node with an illegal result
231 /// type with new values built out of custom code.
ReplaceNodeResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const232 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
233 SmallVectorImpl<SDValue>&Results,
234 SelectionDAG &DAG) const {
235 switch (N->getOpcode()) {
236 default:
237 llvm_unreachable("Don't know how to custom expand this!");
238 case ISD::ADD:
239 case ISD::SUB:
240 Results.push_back(ExpandADDSUB(N, DAG));
241 return;
242 }
243 }
244
245 //===----------------------------------------------------------------------===//
246 // Misc Lower Operation implementation
247 //===----------------------------------------------------------------------===//
248
getGlobalAddressWrapper(SDValue GA,const GlobalValue * GV,SelectionDAG & DAG) const249 SDValue XCoreTargetLowering::getGlobalAddressWrapper(SDValue GA,
250 const GlobalValue *GV,
251 SelectionDAG &DAG) const {
252 // FIXME there is no actual debug info here
253 SDLoc dl(GA);
254
255 if (GV->getValueType()->isFunctionTy())
256 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
257
258 const auto *GVar = dyn_cast<GlobalVariable>(GV);
259 if ((GV->hasSection() && GV->getSection().startswith(".cp.")) ||
260 (GVar && GVar->isConstant() && GV->hasLocalLinkage()))
261 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
262
263 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
264 }
265
IsSmallObject(const GlobalValue * GV,const XCoreTargetLowering & XTL)266 static bool IsSmallObject(const GlobalValue *GV, const XCoreTargetLowering &XTL) {
267 if (XTL.getTargetMachine().getCodeModel() == CodeModel::Small)
268 return true;
269
270 Type *ObjType = GV->getValueType();
271 if (!ObjType->isSized())
272 return false;
273
274 auto &DL = GV->getParent()->getDataLayout();
275 unsigned ObjSize = DL.getTypeAllocSize(ObjType);
276 return ObjSize < CodeModelLargeSize && ObjSize != 0;
277 }
278
279 SDValue XCoreTargetLowering::
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const280 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
281 {
282 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
283 const GlobalValue *GV = GN->getGlobal();
284 SDLoc DL(GN);
285 int64_t Offset = GN->getOffset();
286 if (IsSmallObject(GV, *this)) {
287 // We can only fold positive offsets that are a multiple of the word size.
288 int64_t FoldedOffset = std::max(Offset & ~3, (int64_t)0);
289 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, FoldedOffset);
290 GA = getGlobalAddressWrapper(GA, GV, DAG);
291 // Handle the rest of the offset.
292 if (Offset != FoldedOffset) {
293 SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, DL, MVT::i32);
294 GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining);
295 }
296 return GA;
297 } else {
298 // Ideally we would not fold in offset with an index <= 11.
299 Type *Ty = Type::getInt8PtrTy(*DAG.getContext());
300 Constant *GA = ConstantExpr::getBitCast(const_cast<GlobalValue*>(GV), Ty);
301 Ty = Type::getInt32Ty(*DAG.getContext());
302 Constant *Idx = ConstantInt::get(Ty, Offset);
303 Constant *GAI = ConstantExpr::getGetElementPtr(
304 Type::getInt8Ty(*DAG.getContext()), GA, Idx);
305 SDValue CP = DAG.getConstantPool(GAI, MVT::i32);
306 return DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL,
307 DAG.getEntryNode(), CP, MachinePointerInfo());
308 }
309 }
310
311 SDValue XCoreTargetLowering::
LowerBlockAddress(SDValue Op,SelectionDAG & DAG) const312 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
313 {
314 SDLoc DL(Op);
315 auto PtrVT = getPointerTy(DAG.getDataLayout());
316 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
317 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
318
319 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, PtrVT, Result);
320 }
321
322 SDValue XCoreTargetLowering::
LowerConstantPool(SDValue Op,SelectionDAG & DAG) const323 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
324 {
325 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
326 // FIXME there isn't really debug info here
327 SDLoc dl(CP);
328 EVT PtrVT = Op.getValueType();
329 SDValue Res;
330 if (CP->isMachineConstantPoolEntry()) {
331 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
332 CP->getAlign(), CP->getOffset());
333 } else {
334 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign(),
335 CP->getOffset());
336 }
337 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
338 }
339
getJumpTableEncoding() const340 unsigned XCoreTargetLowering::getJumpTableEncoding() const {
341 return MachineJumpTableInfo::EK_Inline;
342 }
343
344 SDValue XCoreTargetLowering::
LowerBR_JT(SDValue Op,SelectionDAG & DAG) const345 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
346 {
347 SDValue Chain = Op.getOperand(0);
348 SDValue Table = Op.getOperand(1);
349 SDValue Index = Op.getOperand(2);
350 SDLoc dl(Op);
351 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
352 unsigned JTI = JT->getIndex();
353 MachineFunction &MF = DAG.getMachineFunction();
354 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
355 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
356
357 unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size();
358 if (NumEntries <= 32) {
359 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index);
360 }
361 assert((NumEntries >> 31) == 0);
362 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
363 DAG.getConstant(1, dl, MVT::i32));
364 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
365 ScaledIndex);
366 }
367
lowerLoadWordFromAlignedBasePlusOffset(const SDLoc & DL,SDValue Chain,SDValue Base,int64_t Offset,SelectionDAG & DAG) const368 SDValue XCoreTargetLowering::lowerLoadWordFromAlignedBasePlusOffset(
369 const SDLoc &DL, SDValue Chain, SDValue Base, int64_t Offset,
370 SelectionDAG &DAG) const {
371 auto PtrVT = getPointerTy(DAG.getDataLayout());
372 if ((Offset & 0x3) == 0) {
373 return DAG.getLoad(PtrVT, DL, Chain, Base, MachinePointerInfo());
374 }
375 // Lower to pair of consecutive word aligned loads plus some bit shifting.
376 int32_t HighOffset = alignTo(Offset, 4);
377 int32_t LowOffset = HighOffset - 4;
378 SDValue LowAddr, HighAddr;
379 if (GlobalAddressSDNode *GASD =
380 dyn_cast<GlobalAddressSDNode>(Base.getNode())) {
381 LowAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(),
382 LowOffset);
383 HighAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(),
384 HighOffset);
385 } else {
386 LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
387 DAG.getConstant(LowOffset, DL, MVT::i32));
388 HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
389 DAG.getConstant(HighOffset, DL, MVT::i32));
390 }
391 SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, DL, MVT::i32);
392 SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, DL, MVT::i32);
393
394 SDValue Low = DAG.getLoad(PtrVT, DL, Chain, LowAddr, MachinePointerInfo());
395 SDValue High = DAG.getLoad(PtrVT, DL, Chain, HighAddr, MachinePointerInfo());
396 SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
397 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
398 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted);
399 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
400 High.getValue(1));
401 SDValue Ops[] = { Result, Chain };
402 return DAG.getMergeValues(Ops, DL);
403 }
404
isWordAligned(SDValue Value,SelectionDAG & DAG)405 static bool isWordAligned(SDValue Value, SelectionDAG &DAG)
406 {
407 KnownBits Known = DAG.computeKnownBits(Value);
408 return Known.countMinTrailingZeros() >= 2;
409 }
410
LowerLOAD(SDValue Op,SelectionDAG & DAG) const411 SDValue XCoreTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
412 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
413 LLVMContext &Context = *DAG.getContext();
414 LoadSDNode *LD = cast<LoadSDNode>(Op);
415 assert(LD->getExtensionType() == ISD::NON_EXTLOAD &&
416 "Unexpected extension type");
417 assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT");
418
419 if (allowsMemoryAccessForAlignment(Context, DAG.getDataLayout(),
420 LD->getMemoryVT(), *LD->getMemOperand()))
421 return SDValue();
422
423 SDValue Chain = LD->getChain();
424 SDValue BasePtr = LD->getBasePtr();
425 SDLoc DL(Op);
426
427 if (!LD->isVolatile()) {
428 const GlobalValue *GV;
429 int64_t Offset = 0;
430 if (DAG.isBaseWithConstantOffset(BasePtr) &&
431 isWordAligned(BasePtr->getOperand(0), DAG)) {
432 SDValue NewBasePtr = BasePtr->getOperand(0);
433 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue();
434 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr,
435 Offset, DAG);
436 }
437 if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) &&
438 GV->getPointerAlignment(DAG.getDataLayout()) >= 4) {
439 SDValue NewBasePtr = DAG.getGlobalAddress(GV, DL,
440 BasePtr->getValueType(0));
441 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr,
442 Offset, DAG);
443 }
444 }
445
446 if (LD->getAlignment() == 2) {
447 SDValue Low =
448 DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, BasePtr,
449 LD->getPointerInfo(), MVT::i16,
450 /* Alignment = */ 2, LD->getMemOperand()->getFlags());
451 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
452 DAG.getConstant(2, DL, MVT::i32));
453 SDValue High =
454 DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, HighAddr,
455 LD->getPointerInfo().getWithOffset(2), MVT::i16,
456 /* Alignment = */ 2, LD->getMemOperand()->getFlags());
457 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
458 DAG.getConstant(16, DL, MVT::i32));
459 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
460 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
461 High.getValue(1));
462 SDValue Ops[] = { Result, Chain };
463 return DAG.getMergeValues(Ops, DL);
464 }
465
466 // Lower to a call to __misaligned_load(BasePtr).
467 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(Context);
468 TargetLowering::ArgListTy Args;
469 TargetLowering::ArgListEntry Entry;
470
471 Entry.Ty = IntPtrTy;
472 Entry.Node = BasePtr;
473 Args.push_back(Entry);
474
475 TargetLowering::CallLoweringInfo CLI(DAG);
476 CLI.setDebugLoc(DL).setChain(Chain).setLibCallee(
477 CallingConv::C, IntPtrTy,
478 DAG.getExternalFunctionSymbol("__misaligned_load"), std::move(Args));
479
480 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
481 SDValue Ops[] = { CallResult.first, CallResult.second };
482 return DAG.getMergeValues(Ops, DL);
483 }
484
LowerSTORE(SDValue Op,SelectionDAG & DAG) const485 SDValue XCoreTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
486 LLVMContext &Context = *DAG.getContext();
487 StoreSDNode *ST = cast<StoreSDNode>(Op);
488 assert(!ST->isTruncatingStore() && "Unexpected store type");
489 assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT");
490
491 if (allowsMemoryAccessForAlignment(Context, DAG.getDataLayout(),
492 ST->getMemoryVT(), *ST->getMemOperand()))
493 return SDValue();
494
495 SDValue Chain = ST->getChain();
496 SDValue BasePtr = ST->getBasePtr();
497 SDValue Value = ST->getValue();
498 SDLoc dl(Op);
499
500 if (ST->getAlignment() == 2) {
501 SDValue Low = Value;
502 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
503 DAG.getConstant(16, dl, MVT::i32));
504 SDValue StoreLow = DAG.getTruncStore(
505 Chain, dl, Low, BasePtr, ST->getPointerInfo(), MVT::i16,
506 /* Alignment = */ 2, ST->getMemOperand()->getFlags());
507 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
508 DAG.getConstant(2, dl, MVT::i32));
509 SDValue StoreHigh = DAG.getTruncStore(
510 Chain, dl, High, HighAddr, ST->getPointerInfo().getWithOffset(2),
511 MVT::i16, /* Alignment = */ 2, ST->getMemOperand()->getFlags());
512 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh);
513 }
514
515 // Lower to a call to __misaligned_store(BasePtr, Value).
516 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(Context);
517 TargetLowering::ArgListTy Args;
518 TargetLowering::ArgListEntry Entry;
519
520 Entry.Ty = IntPtrTy;
521 Entry.Node = BasePtr;
522 Args.push_back(Entry);
523
524 Entry.Node = Value;
525 Args.push_back(Entry);
526
527 TargetLowering::CallLoweringInfo CLI(DAG);
528 CLI.setDebugLoc(dl).setChain(Chain).setCallee(
529 CallingConv::C, Type::getVoidTy(Context),
530 DAG.getExternalSymbol("__misaligned_store",
531 getPointerTy(DAG.getDataLayout())),
532 std::move(Args));
533
534 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
535 return CallResult.second;
536 }
537
538 SDValue XCoreTargetLowering::
LowerSMUL_LOHI(SDValue Op,SelectionDAG & DAG) const539 LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
540 {
541 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
542 "Unexpected operand to lower!");
543 SDLoc dl(Op);
544 SDValue LHS = Op.getOperand(0);
545 SDValue RHS = Op.getOperand(1);
546 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
547 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
548 DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
549 LHS, RHS);
550 SDValue Lo(Hi.getNode(), 1);
551 SDValue Ops[] = { Lo, Hi };
552 return DAG.getMergeValues(Ops, dl);
553 }
554
555 SDValue XCoreTargetLowering::
LowerUMUL_LOHI(SDValue Op,SelectionDAG & DAG) const556 LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
557 {
558 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
559 "Unexpected operand to lower!");
560 SDLoc dl(Op);
561 SDValue LHS = Op.getOperand(0);
562 SDValue RHS = Op.getOperand(1);
563 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
564 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
565 DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
566 Zero, Zero);
567 SDValue Lo(Hi.getNode(), 1);
568 SDValue Ops[] = { Lo, Hi };
569 return DAG.getMergeValues(Ops, dl);
570 }
571
572 /// isADDADDMUL - Return whether Op is in a form that is equivalent to
573 /// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then
574 /// each intermediate result in the calculation must also have a single use.
575 /// If the Op is in the correct form the constituent parts are written to Mul0,
576 /// Mul1, Addend0 and Addend1.
577 static bool
isADDADDMUL(SDValue Op,SDValue & Mul0,SDValue & Mul1,SDValue & Addend0,SDValue & Addend1,bool requireIntermediatesHaveOneUse)578 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0,
579 SDValue &Addend1, bool requireIntermediatesHaveOneUse)
580 {
581 if (Op.getOpcode() != ISD::ADD)
582 return false;
583 SDValue N0 = Op.getOperand(0);
584 SDValue N1 = Op.getOperand(1);
585 SDValue AddOp;
586 SDValue OtherOp;
587 if (N0.getOpcode() == ISD::ADD) {
588 AddOp = N0;
589 OtherOp = N1;
590 } else if (N1.getOpcode() == ISD::ADD) {
591 AddOp = N1;
592 OtherOp = N0;
593 } else {
594 return false;
595 }
596 if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse())
597 return false;
598 if (OtherOp.getOpcode() == ISD::MUL) {
599 // add(add(a,b),mul(x,y))
600 if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse())
601 return false;
602 Mul0 = OtherOp.getOperand(0);
603 Mul1 = OtherOp.getOperand(1);
604 Addend0 = AddOp.getOperand(0);
605 Addend1 = AddOp.getOperand(1);
606 return true;
607 }
608 if (AddOp.getOperand(0).getOpcode() == ISD::MUL) {
609 // add(add(mul(x,y),a),b)
610 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(0).hasOneUse())
611 return false;
612 Mul0 = AddOp.getOperand(0).getOperand(0);
613 Mul1 = AddOp.getOperand(0).getOperand(1);
614 Addend0 = AddOp.getOperand(1);
615 Addend1 = OtherOp;
616 return true;
617 }
618 if (AddOp.getOperand(1).getOpcode() == ISD::MUL) {
619 // add(add(a,mul(x,y)),b)
620 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(1).hasOneUse())
621 return false;
622 Mul0 = AddOp.getOperand(1).getOperand(0);
623 Mul1 = AddOp.getOperand(1).getOperand(1);
624 Addend0 = AddOp.getOperand(0);
625 Addend1 = OtherOp;
626 return true;
627 }
628 return false;
629 }
630
631 SDValue XCoreTargetLowering::
TryExpandADDWithMul(SDNode * N,SelectionDAG & DAG) const632 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
633 {
634 SDValue Mul;
635 SDValue Other;
636 if (N->getOperand(0).getOpcode() == ISD::MUL) {
637 Mul = N->getOperand(0);
638 Other = N->getOperand(1);
639 } else if (N->getOperand(1).getOpcode() == ISD::MUL) {
640 Mul = N->getOperand(1);
641 Other = N->getOperand(0);
642 } else {
643 return SDValue();
644 }
645 SDLoc dl(N);
646 SDValue LL, RL, AddendL, AddendH;
647 LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
648 Mul.getOperand(0), DAG.getConstant(0, dl, MVT::i32));
649 RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
650 Mul.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
651 AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
652 Other, DAG.getConstant(0, dl, MVT::i32));
653 AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
654 Other, DAG.getConstant(1, dl, MVT::i32));
655 APInt HighMask = APInt::getHighBitsSet(64, 32);
656 unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
657 unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
658 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) &&
659 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) {
660 // The inputs are both zero-extended.
661 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
662 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
663 AddendL, LL, RL);
664 SDValue Lo(Hi.getNode(), 1);
665 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
666 }
667 if (LHSSB > 32 && RHSSB > 32) {
668 // The inputs are both sign-extended.
669 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
670 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
671 AddendL, LL, RL);
672 SDValue Lo(Hi.getNode(), 1);
673 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
674 }
675 SDValue LH, RH;
676 LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
677 Mul.getOperand(0), DAG.getConstant(1, dl, MVT::i32));
678 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
679 Mul.getOperand(1), DAG.getConstant(1, dl, MVT::i32));
680 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
681 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
682 AddendL, LL, RL);
683 SDValue Lo(Hi.getNode(), 1);
684 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH);
685 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
686 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH);
687 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH);
688 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
689 }
690
691 SDValue XCoreTargetLowering::
ExpandADDSUB(SDNode * N,SelectionDAG & DAG) const692 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
693 {
694 assert(N->getValueType(0) == MVT::i64 &&
695 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
696 "Unknown operand to lower!");
697
698 if (N->getOpcode() == ISD::ADD)
699 if (SDValue Result = TryExpandADDWithMul(N, DAG))
700 return Result;
701
702 SDLoc dl(N);
703
704 // Extract components
705 SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
706 N->getOperand(0),
707 DAG.getConstant(0, dl, MVT::i32));
708 SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
709 N->getOperand(0),
710 DAG.getConstant(1, dl, MVT::i32));
711 SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
712 N->getOperand(1),
713 DAG.getConstant(0, dl, MVT::i32));
714 SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
715 N->getOperand(1),
716 DAG.getConstant(1, dl, MVT::i32));
717
718 // Expand
719 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
720 XCoreISD::LSUB;
721 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
722 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
723 LHSL, RHSL, Zero);
724 SDValue Carry(Lo.getNode(), 1);
725
726 SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
727 LHSH, RHSH, Carry);
728 SDValue Ignored(Hi.getNode(), 1);
729 // Merge the pieces
730 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
731 }
732
733 SDValue XCoreTargetLowering::
LowerVAARG(SDValue Op,SelectionDAG & DAG) const734 LowerVAARG(SDValue Op, SelectionDAG &DAG) const
735 {
736 // Whist llvm does not support aggregate varargs we can ignore
737 // the possibility of the ValueType being an implicit byVal vararg.
738 SDNode *Node = Op.getNode();
739 EVT VT = Node->getValueType(0); // not an aggregate
740 SDValue InChain = Node->getOperand(0);
741 SDValue VAListPtr = Node->getOperand(1);
742 EVT PtrVT = VAListPtr.getValueType();
743 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
744 SDLoc dl(Node);
745 SDValue VAList =
746 DAG.getLoad(PtrVT, dl, InChain, VAListPtr, MachinePointerInfo(SV));
747 // Increment the pointer, VAList, to the next vararg
748 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList,
749 DAG.getIntPtrConstant(VT.getSizeInBits() / 8,
750 dl));
751 // Store the incremented VAList to the legalized pointer
752 InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr,
753 MachinePointerInfo(SV));
754 // Load the actual argument out of the pointer VAList
755 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo());
756 }
757
758 SDValue XCoreTargetLowering::
LowerVASTART(SDValue Op,SelectionDAG & DAG) const759 LowerVASTART(SDValue Op, SelectionDAG &DAG) const
760 {
761 SDLoc dl(Op);
762 // vastart stores the address of the VarArgsFrameIndex slot into the
763 // memory location argument
764 MachineFunction &MF = DAG.getMachineFunction();
765 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
766 SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
767 return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1),
768 MachinePointerInfo());
769 }
770
LowerFRAMEADDR(SDValue Op,SelectionDAG & DAG) const771 SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op,
772 SelectionDAG &DAG) const {
773 // This nodes represent llvm.frameaddress on the DAG.
774 // It takes one operand, the index of the frame address to return.
775 // An index of zero corresponds to the current function's frame address.
776 // An index of one to the parent's frame address, and so on.
777 // Depths > 0 not supported yet!
778 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
779 return SDValue();
780
781 MachineFunction &MF = DAG.getMachineFunction();
782 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
783 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op),
784 RegInfo->getFrameRegister(MF), MVT::i32);
785 }
786
787 SDValue XCoreTargetLowering::
LowerRETURNADDR(SDValue Op,SelectionDAG & DAG) const788 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
789 // This nodes represent llvm.returnaddress on the DAG.
790 // It takes one operand, the index of the return address to return.
791 // An index of zero corresponds to the current function's return address.
792 // An index of one to the parent's return address, and so on.
793 // Depths > 0 not supported yet!
794 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
795 return SDValue();
796
797 MachineFunction &MF = DAG.getMachineFunction();
798 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
799 int FI = XFI->createLRSpillSlot(MF);
800 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
801 return DAG.getLoad(getPointerTy(DAG.getDataLayout()), SDLoc(Op),
802 DAG.getEntryNode(), FIN,
803 MachinePointerInfo::getFixedStack(MF, FI));
804 }
805
806 SDValue XCoreTargetLowering::
LowerFRAME_TO_ARGS_OFFSET(SDValue Op,SelectionDAG & DAG) const807 LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const {
808 // This node represents offset from frame pointer to first on-stack argument.
809 // This is needed for correct stack adjustment during unwind.
810 // However, we don't know the offset until after the frame has be finalised.
811 // This is done during the XCoreFTAOElim pass.
812 return DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, SDLoc(Op), MVT::i32);
813 }
814
815 SDValue XCoreTargetLowering::
LowerEH_RETURN(SDValue Op,SelectionDAG & DAG) const816 LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
817 // OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER)
818 // This node represents 'eh_return' gcc dwarf builtin, which is used to
819 // return from exception. The general meaning is: adjust stack by OFFSET and
820 // pass execution to HANDLER.
821 MachineFunction &MF = DAG.getMachineFunction();
822 SDValue Chain = Op.getOperand(0);
823 SDValue Offset = Op.getOperand(1);
824 SDValue Handler = Op.getOperand(2);
825 SDLoc dl(Op);
826
827 // Absolute SP = (FP + FrameToArgs) + Offset
828 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
829 SDValue Stack = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
830 RegInfo->getFrameRegister(MF), MVT::i32);
831 SDValue FrameToArgs = DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, dl,
832 MVT::i32);
833 Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, FrameToArgs);
834 Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, Offset);
835
836 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
837 // which leaves 2 caller saved registers, R2 & R3 for us to use.
838 unsigned StackReg = XCore::R2;
839 unsigned HandlerReg = XCore::R3;
840
841 SDValue OutChains[] = {
842 DAG.getCopyToReg(Chain, dl, StackReg, Stack),
843 DAG.getCopyToReg(Chain, dl, HandlerReg, Handler)
844 };
845
846 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
847
848 return DAG.getNode(XCoreISD::EH_RETURN, dl, MVT::Other, Chain,
849 DAG.getRegister(StackReg, MVT::i32),
850 DAG.getRegister(HandlerReg, MVT::i32));
851
852 }
853
854 SDValue XCoreTargetLowering::
LowerADJUST_TRAMPOLINE(SDValue Op,SelectionDAG & DAG) const855 LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
856 return Op.getOperand(0);
857 }
858
859 SDValue XCoreTargetLowering::
LowerINIT_TRAMPOLINE(SDValue Op,SelectionDAG & DAG) const860 LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
861 SDValue Chain = Op.getOperand(0);
862 SDValue Trmp = Op.getOperand(1); // trampoline
863 SDValue FPtr = Op.getOperand(2); // nested function
864 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
865
866 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
867
868 // .align 4
869 // LDAPF_u10 r11, nest
870 // LDW_2rus r11, r11[0]
871 // STWSP_ru6 r11, sp[0]
872 // LDAPF_u10 r11, fptr
873 // LDW_2rus r11, r11[0]
874 // BAU_1r r11
875 // nest:
876 // .word nest
877 // fptr:
878 // .word fptr
879 SDValue OutChains[5];
880
881 SDValue Addr = Trmp;
882
883 SDLoc dl(Op);
884 OutChains[0] =
885 DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, dl, MVT::i32), Addr,
886 MachinePointerInfo(TrmpAddr));
887
888 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
889 DAG.getConstant(4, dl, MVT::i32));
890 OutChains[1] =
891 DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, dl, MVT::i32), Addr,
892 MachinePointerInfo(TrmpAddr, 4));
893
894 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
895 DAG.getConstant(8, dl, MVT::i32));
896 OutChains[2] =
897 DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, dl, MVT::i32), Addr,
898 MachinePointerInfo(TrmpAddr, 8));
899
900 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
901 DAG.getConstant(12, dl, MVT::i32));
902 OutChains[3] =
903 DAG.getStore(Chain, dl, Nest, Addr, MachinePointerInfo(TrmpAddr, 12));
904
905 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
906 DAG.getConstant(16, dl, MVT::i32));
907 OutChains[4] =
908 DAG.getStore(Chain, dl, FPtr, Addr, MachinePointerInfo(TrmpAddr, 16));
909
910 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
911 }
912
913 SDValue XCoreTargetLowering::
LowerINTRINSIC_WO_CHAIN(SDValue Op,SelectionDAG & DAG) const914 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
915 SDLoc DL(Op);
916 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
917 switch (IntNo) {
918 case Intrinsic::xcore_crc8:
919 EVT VT = Op.getValueType();
920 SDValue Data =
921 DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT),
922 Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3));
923 SDValue Crc(Data.getNode(), 1);
924 SDValue Results[] = { Crc, Data };
925 return DAG.getMergeValues(Results, DL);
926 }
927 return SDValue();
928 }
929
930 SDValue XCoreTargetLowering::
LowerATOMIC_FENCE(SDValue Op,SelectionDAG & DAG) const931 LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const {
932 SDLoc DL(Op);
933 return DAG.getNode(XCoreISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
934 }
935
936 SDValue XCoreTargetLowering::
LowerATOMIC_LOAD(SDValue Op,SelectionDAG & DAG) const937 LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const {
938 AtomicSDNode *N = cast<AtomicSDNode>(Op);
939 assert(N->getOpcode() == ISD::ATOMIC_LOAD && "Bad Atomic OP");
940 assert((N->getOrdering() == AtomicOrdering::Unordered ||
941 N->getOrdering() == AtomicOrdering::Monotonic) &&
942 "setInsertFencesForAtomic(true) expects unordered / monotonic");
943 if (N->getMemoryVT() == MVT::i32) {
944 if (N->getAlignment() < 4)
945 report_fatal_error("atomic load must be aligned");
946 return DAG.getLoad(getPointerTy(DAG.getDataLayout()), SDLoc(Op),
947 N->getChain(), N->getBasePtr(), N->getPointerInfo(),
948 N->getAlignment(), N->getMemOperand()->getFlags(),
949 N->getAAInfo(), N->getRanges());
950 }
951 if (N->getMemoryVT() == MVT::i16) {
952 if (N->getAlignment() < 2)
953 report_fatal_error("atomic load must be aligned");
954 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(),
955 N->getBasePtr(), N->getPointerInfo(), MVT::i16,
956 N->getAlignment(), N->getMemOperand()->getFlags(),
957 N->getAAInfo());
958 }
959 if (N->getMemoryVT() == MVT::i8)
960 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(),
961 N->getBasePtr(), N->getPointerInfo(), MVT::i8,
962 N->getAlignment(), N->getMemOperand()->getFlags(),
963 N->getAAInfo());
964 return SDValue();
965 }
966
967 SDValue XCoreTargetLowering::
LowerATOMIC_STORE(SDValue Op,SelectionDAG & DAG) const968 LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const {
969 AtomicSDNode *N = cast<AtomicSDNode>(Op);
970 assert(N->getOpcode() == ISD::ATOMIC_STORE && "Bad Atomic OP");
971 assert((N->getOrdering() == AtomicOrdering::Unordered ||
972 N->getOrdering() == AtomicOrdering::Monotonic) &&
973 "setInsertFencesForAtomic(true) expects unordered / monotonic");
974 if (N->getMemoryVT() == MVT::i32) {
975 if (N->getAlignment() < 4)
976 report_fatal_error("atomic store must be aligned");
977 return DAG.getStore(N->getChain(), SDLoc(Op), N->getVal(), N->getBasePtr(),
978 N->getPointerInfo(), N->getAlignment(),
979 N->getMemOperand()->getFlags(), N->getAAInfo());
980 }
981 if (N->getMemoryVT() == MVT::i16) {
982 if (N->getAlignment() < 2)
983 report_fatal_error("atomic store must be aligned");
984 return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(),
985 N->getBasePtr(), N->getPointerInfo(), MVT::i16,
986 N->getAlignment(), N->getMemOperand()->getFlags(),
987 N->getAAInfo());
988 }
989 if (N->getMemoryVT() == MVT::i8)
990 return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(),
991 N->getBasePtr(), N->getPointerInfo(), MVT::i8,
992 N->getAlignment(), N->getMemOperand()->getFlags(),
993 N->getAAInfo());
994 return SDValue();
995 }
996
997 MachineMemOperand::Flags
getTargetMMOFlags(const Instruction & I) const998 XCoreTargetLowering::getTargetMMOFlags(const Instruction &I) const {
999 // Because of how we convert atomic_load and atomic_store to normal loads and
1000 // stores in the DAG, we need to ensure that the MMOs are marked volatile
1001 // since DAGCombine hasn't been updated to account for atomic, but non
1002 // volatile loads. (See D57601)
1003 if (auto *SI = dyn_cast<StoreInst>(&I))
1004 if (SI->isAtomic())
1005 return MachineMemOperand::MOVolatile;
1006 if (auto *LI = dyn_cast<LoadInst>(&I))
1007 if (LI->isAtomic())
1008 return MachineMemOperand::MOVolatile;
1009 if (auto *AI = dyn_cast<AtomicRMWInst>(&I))
1010 if (AI->isAtomic())
1011 return MachineMemOperand::MOVolatile;
1012 if (auto *AI = dyn_cast<AtomicCmpXchgInst>(&I))
1013 if (AI->isAtomic())
1014 return MachineMemOperand::MOVolatile;
1015 return MachineMemOperand::MONone;
1016 }
1017
1018 //===----------------------------------------------------------------------===//
1019 // Calling Convention Implementation
1020 //===----------------------------------------------------------------------===//
1021
1022 #include "XCoreGenCallingConv.inc"
1023
1024 //===----------------------------------------------------------------------===//
1025 // Call Calling Convention Implementation
1026 //===----------------------------------------------------------------------===//
1027
1028 /// XCore call implementation
1029 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const1030 XCoreTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1031 SmallVectorImpl<SDValue> &InVals) const {
1032 SelectionDAG &DAG = CLI.DAG;
1033 SDLoc &dl = CLI.DL;
1034 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1035 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1036 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1037 SDValue Chain = CLI.Chain;
1038 SDValue Callee = CLI.Callee;
1039 bool &isTailCall = CLI.IsTailCall;
1040 CallingConv::ID CallConv = CLI.CallConv;
1041 bool isVarArg = CLI.IsVarArg;
1042
1043 // XCore target does not yet support tail call optimization.
1044 isTailCall = false;
1045
1046 // For now, only CallingConv::C implemented
1047 switch (CallConv)
1048 {
1049 default:
1050 report_fatal_error("Unsupported calling convention");
1051 case CallingConv::Fast:
1052 case CallingConv::C:
1053 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
1054 Outs, OutVals, Ins, dl, DAG, InVals);
1055 }
1056 }
1057
1058 /// LowerCallResult - Lower the result values of a call into the
1059 /// appropriate copies out of appropriate physical registers / memory locations.
LowerCallResult(SDValue Chain,SDValue InFlag,const SmallVectorImpl<CCValAssign> & RVLocs,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals)1060 static SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1061 const SmallVectorImpl<CCValAssign> &RVLocs,
1062 const SDLoc &dl, SelectionDAG &DAG,
1063 SmallVectorImpl<SDValue> &InVals) {
1064 SmallVector<std::pair<int, unsigned>, 4> ResultMemLocs;
1065 // Copy results out of physical registers.
1066 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1067 const CCValAssign &VA = RVLocs[i];
1068 if (VA.isRegLoc()) {
1069 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(),
1070 InFlag).getValue(1);
1071 InFlag = Chain.getValue(2);
1072 InVals.push_back(Chain.getValue(0));
1073 } else {
1074 assert(VA.isMemLoc());
1075 ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(),
1076 InVals.size()));
1077 // Reserve space for this result.
1078 InVals.push_back(SDValue());
1079 }
1080 }
1081
1082 // Copy results out of memory.
1083 SmallVector<SDValue, 4> MemOpChains;
1084 for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) {
1085 int offset = ResultMemLocs[i].first;
1086 unsigned index = ResultMemLocs[i].second;
1087 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1088 SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, dl, MVT::i32) };
1089 SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops);
1090 InVals[index] = load;
1091 MemOpChains.push_back(load.getValue(1));
1092 }
1093
1094 // Transform all loads nodes into one single node because
1095 // all load nodes are independent of each other.
1096 if (!MemOpChains.empty())
1097 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1098
1099 return Chain;
1100 }
1101
1102 /// LowerCCCCallTo - functions arguments are copied from virtual
1103 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
1104 /// CALLSEQ_END are emitted.
1105 /// TODO: isTailCall, sret.
LowerCCCCallTo(SDValue Chain,SDValue Callee,CallingConv::ID CallConv,bool isVarArg,bool isTailCall,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const1106 SDValue XCoreTargetLowering::LowerCCCCallTo(
1107 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
1108 bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
1109 const SmallVectorImpl<SDValue> &OutVals,
1110 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1111 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1112
1113 // Analyze operands of the call, assigning locations to each operand.
1114 SmallVector<CCValAssign, 16> ArgLocs;
1115 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1116 *DAG.getContext());
1117
1118 // The ABI dictates there should be one stack slot available to the callee
1119 // on function entry (for saving lr).
1120 CCInfo.AllocateStack(4, Align(4));
1121
1122 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
1123
1124 SmallVector<CCValAssign, 16> RVLocs;
1125 // Analyze return values to determine the number of bytes of stack required.
1126 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1127 *DAG.getContext());
1128 RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), Align(4));
1129 RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
1130
1131 // Get a count of how many bytes are to be pushed on the stack.
1132 unsigned NumBytes = RetCCInfo.getNextStackOffset();
1133 auto PtrVT = getPointerTy(DAG.getDataLayout());
1134
1135 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
1136
1137 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
1138 SmallVector<SDValue, 12> MemOpChains;
1139
1140 // Walk the register/memloc assignments, inserting copies/loads.
1141 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1142 CCValAssign &VA = ArgLocs[i];
1143 SDValue Arg = OutVals[i];
1144
1145 // Promote the value if needed.
1146 switch (VA.getLocInfo()) {
1147 default: llvm_unreachable("Unknown loc info!");
1148 case CCValAssign::Full: break;
1149 case CCValAssign::SExt:
1150 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1151 break;
1152 case CCValAssign::ZExt:
1153 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1154 break;
1155 case CCValAssign::AExt:
1156 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1157 break;
1158 }
1159
1160 // Arguments that can be passed on register must be kept at
1161 // RegsToPass vector
1162 if (VA.isRegLoc()) {
1163 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1164 } else {
1165 assert(VA.isMemLoc());
1166
1167 int Offset = VA.getLocMemOffset();
1168
1169 MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
1170 Chain, Arg,
1171 DAG.getConstant(Offset/4, dl,
1172 MVT::i32)));
1173 }
1174 }
1175
1176 // Transform all store nodes into one single node because
1177 // all store nodes are independent of each other.
1178 if (!MemOpChains.empty())
1179 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1180
1181 // Build a sequence of copy-to-reg nodes chained together with token
1182 // chain and flag operands which copy the outgoing args into registers.
1183 // The InFlag in necessary since all emitted instructions must be
1184 // stuck together.
1185 SDValue InFlag;
1186 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1187 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1188 RegsToPass[i].second, InFlag);
1189 InFlag = Chain.getValue(1);
1190 }
1191
1192 // If the callee is a GlobalAddress node (quite common, every direct call is)
1193 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1194 // Likewise ExternalSymbol -> TargetExternalSymbol.
1195 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1196 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
1197 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1198 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
1199
1200 // XCoreBranchLink = #chain, #target_address, #opt_in_flags...
1201 // = Chain, Callee, Reg#1, Reg#2, ...
1202 //
1203 // Returns a chain & a flag for retval copy to use.
1204 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1205 SmallVector<SDValue, 8> Ops;
1206 Ops.push_back(Chain);
1207 Ops.push_back(Callee);
1208
1209 // Add argument registers to the end of the list so that they are
1210 // known live into the call.
1211 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1212 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1213 RegsToPass[i].second.getValueType()));
1214
1215 if (InFlag.getNode())
1216 Ops.push_back(InFlag);
1217
1218 Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, Ops);
1219 InFlag = Chain.getValue(1);
1220
1221 // Create the CALLSEQ_END node.
1222 Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
1223 DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
1224 InFlag = Chain.getValue(1);
1225
1226 // Handle result values, copying them out of physregs into vregs that we
1227 // return.
1228 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals);
1229 }
1230
1231 //===----------------------------------------------------------------------===//
1232 // Formal Arguments Calling Convention Implementation
1233 //===----------------------------------------------------------------------===//
1234
1235 namespace {
1236 struct ArgDataPair { SDValue SDV; ISD::ArgFlagsTy Flags; };
1237 }
1238
1239 /// XCore formal arguments implementation
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const1240 SDValue XCoreTargetLowering::LowerFormalArguments(
1241 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1242 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1243 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1244 switch (CallConv)
1245 {
1246 default:
1247 report_fatal_error("Unsupported calling convention");
1248 case CallingConv::C:
1249 case CallingConv::Fast:
1250 return LowerCCCArguments(Chain, CallConv, isVarArg,
1251 Ins, dl, DAG, InVals);
1252 }
1253 }
1254
1255 /// LowerCCCArguments - transform physical registers into
1256 /// virtual registers and generate load operations for
1257 /// arguments places on the stack.
1258 /// TODO: sret
LowerCCCArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const1259 SDValue XCoreTargetLowering::LowerCCCArguments(
1260 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1261 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1262 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1263 MachineFunction &MF = DAG.getMachineFunction();
1264 MachineFrameInfo &MFI = MF.getFrameInfo();
1265 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1266 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1267
1268 // Assign locations to all of the incoming arguments.
1269 SmallVector<CCValAssign, 16> ArgLocs;
1270 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1271 *DAG.getContext());
1272
1273 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);
1274
1275 unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize();
1276
1277 unsigned LRSaveSize = StackSlotSize;
1278
1279 if (!isVarArg)
1280 XFI->setReturnStackOffset(CCInfo.getNextStackOffset() + LRSaveSize);
1281
1282 // All getCopyFromReg ops must precede any getMemcpys to prevent the
1283 // scheduler clobbering a register before it has been copied.
1284 // The stages are:
1285 // 1. CopyFromReg (and load) arg & vararg registers.
1286 // 2. Chain CopyFromReg nodes into a TokenFactor.
1287 // 3. Memcpy 'byVal' args & push final InVals.
1288 // 4. Chain mem ops nodes into a TokenFactor.
1289 SmallVector<SDValue, 4> CFRegNode;
1290 SmallVector<ArgDataPair, 4> ArgData;
1291 SmallVector<SDValue, 4> MemOps;
1292
1293 // 1a. CopyFromReg (and load) arg registers.
1294 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1295
1296 CCValAssign &VA = ArgLocs[i];
1297 SDValue ArgIn;
1298
1299 if (VA.isRegLoc()) {
1300 // Arguments passed in registers
1301 EVT RegVT = VA.getLocVT();
1302 switch (RegVT.getSimpleVT().SimpleTy) {
1303 default:
1304 {
1305 #ifndef NDEBUG
1306 errs() << "LowerFormalArguments Unhandled argument type: "
1307 << RegVT.getEVTString() << "\n";
1308 #endif
1309 llvm_unreachable(nullptr);
1310 }
1311 case MVT::i32:
1312 Register VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1313 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1314 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
1315 CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1));
1316 }
1317 } else {
1318 // sanity check
1319 assert(VA.isMemLoc());
1320 // Load the argument to a virtual register
1321 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
1322 if (ObjSize > StackSlotSize) {
1323 errs() << "LowerFormalArguments Unhandled argument type: "
1324 << EVT(VA.getLocVT()).getEVTString()
1325 << "\n";
1326 }
1327 // Create the frame index object for this incoming parameter...
1328 int FI = MFI.CreateFixedObject(ObjSize,
1329 LRSaveSize + VA.getLocMemOffset(),
1330 true);
1331
1332 // Create the SelectionDAG nodes corresponding to a load
1333 //from this parameter
1334 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1335 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1336 MachinePointerInfo::getFixedStack(MF, FI));
1337 }
1338 const ArgDataPair ADP = { ArgIn, Ins[i].Flags };
1339 ArgData.push_back(ADP);
1340 }
1341
1342 // 1b. CopyFromReg vararg registers.
1343 if (isVarArg) {
1344 // Argument registers
1345 static const MCPhysReg ArgRegs[] = {
1346 XCore::R0, XCore::R1, XCore::R2, XCore::R3
1347 };
1348 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1349 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);
1350 if (FirstVAReg < array_lengthof(ArgRegs)) {
1351 int offset = 0;
1352 // Save remaining registers, storing higher register numbers at a higher
1353 // address
1354 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
1355 // Create a stack slot
1356 int FI = MFI.CreateFixedObject(4, offset, true);
1357 if (i == (int)FirstVAReg) {
1358 XFI->setVarArgsFrameIndex(FI);
1359 }
1360 offset -= StackSlotSize;
1361 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1362 // Move argument from phys reg -> virt reg
1363 Register VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1364 RegInfo.addLiveIn(ArgRegs[i], VReg);
1365 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1366 CFRegNode.push_back(Val.getValue(Val->getNumValues() - 1));
1367 // Move argument from virt reg -> stack
1368 SDValue Store =
1369 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
1370 MemOps.push_back(Store);
1371 }
1372 } else {
1373 // This will point to the next argument passed via stack.
1374 XFI->setVarArgsFrameIndex(
1375 MFI.CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(),
1376 true));
1377 }
1378 }
1379
1380 // 2. chain CopyFromReg nodes into a TokenFactor.
1381 if (!CFRegNode.empty())
1382 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, CFRegNode);
1383
1384 // 3. Memcpy 'byVal' args & push final InVals.
1385 // Aggregates passed "byVal" need to be copied by the callee.
1386 // The callee will use a pointer to this copy, rather than the original
1387 // pointer.
1388 for (SmallVectorImpl<ArgDataPair>::const_iterator ArgDI = ArgData.begin(),
1389 ArgDE = ArgData.end();
1390 ArgDI != ArgDE; ++ArgDI) {
1391 if (ArgDI->Flags.isByVal() && ArgDI->Flags.getByValSize()) {
1392 unsigned Size = ArgDI->Flags.getByValSize();
1393 Align Alignment =
1394 std::max(Align(StackSlotSize), ArgDI->Flags.getNonZeroByValAlign());
1395 // Create a new object on the stack and copy the pointee into it.
1396 int FI = MFI.CreateStackObject(Size, Alignment, false);
1397 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1398 InVals.push_back(FIN);
1399 MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV,
1400 DAG.getConstant(Size, dl, MVT::i32),
1401 Alignment, false, false, false, false,
1402 MachinePointerInfo(),
1403 MachinePointerInfo()));
1404 } else {
1405 InVals.push_back(ArgDI->SDV);
1406 }
1407 }
1408
1409 // 4, chain mem ops nodes into a TokenFactor.
1410 if (!MemOps.empty()) {
1411 MemOps.push_back(Chain);
1412 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
1413 }
1414
1415 return Chain;
1416 }
1417
1418 //===----------------------------------------------------------------------===//
1419 // Return Value Calling Convention Implementation
1420 //===----------------------------------------------------------------------===//
1421
1422 bool XCoreTargetLowering::
CanLowerReturn(CallingConv::ID CallConv,MachineFunction & MF,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,LLVMContext & Context) const1423 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1424 bool isVarArg,
1425 const SmallVectorImpl<ISD::OutputArg> &Outs,
1426 LLVMContext &Context) const {
1427 SmallVector<CCValAssign, 16> RVLocs;
1428 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1429 if (!CCInfo.CheckReturn(Outs, RetCC_XCore))
1430 return false;
1431 if (CCInfo.getNextStackOffset() != 0 && isVarArg)
1432 return false;
1433 return true;
1434 }
1435
1436 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & dl,SelectionDAG & DAG) const1437 XCoreTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1438 bool isVarArg,
1439 const SmallVectorImpl<ISD::OutputArg> &Outs,
1440 const SmallVectorImpl<SDValue> &OutVals,
1441 const SDLoc &dl, SelectionDAG &DAG) const {
1442
1443 XCoreFunctionInfo *XFI =
1444 DAG.getMachineFunction().getInfo<XCoreFunctionInfo>();
1445 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1446
1447 // CCValAssign - represent the assignment of
1448 // the return value to a location
1449 SmallVector<CCValAssign, 16> RVLocs;
1450
1451 // CCState - Info about the registers and stack slot.
1452 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1453 *DAG.getContext());
1454
1455 // Analyze return values.
1456 if (!isVarArg)
1457 CCInfo.AllocateStack(XFI->getReturnStackOffset(), Align(4));
1458
1459 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
1460
1461 SDValue Flag;
1462 SmallVector<SDValue, 4> RetOps(1, Chain);
1463
1464 // Return on XCore is always a "retsp 0"
1465 RetOps.push_back(DAG.getConstant(0, dl, MVT::i32));
1466
1467 SmallVector<SDValue, 4> MemOpChains;
1468 // Handle return values that must be copied to memory.
1469 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1470 CCValAssign &VA = RVLocs[i];
1471 if (VA.isRegLoc())
1472 continue;
1473 assert(VA.isMemLoc());
1474 if (isVarArg) {
1475 report_fatal_error("Can't return value from vararg function in memory");
1476 }
1477
1478 int Offset = VA.getLocMemOffset();
1479 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
1480 // Create the frame index object for the memory location.
1481 int FI = MFI.CreateFixedObject(ObjSize, Offset, false);
1482
1483 // Create a SelectionDAG node corresponding to a store
1484 // to this memory location.
1485 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1486 MemOpChains.push_back(DAG.getStore(
1487 Chain, dl, OutVals[i], FIN,
1488 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
1489 }
1490
1491 // Transform all store nodes into one single node because
1492 // all stores are independent of each other.
1493 if (!MemOpChains.empty())
1494 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1495
1496 // Now handle return values copied to registers.
1497 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1498 CCValAssign &VA = RVLocs[i];
1499 if (!VA.isRegLoc())
1500 continue;
1501 // Copy the result values into the output registers.
1502 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1503
1504 // guarantee that all emitted copies are
1505 // stuck together, avoiding something bad
1506 Flag = Chain.getValue(1);
1507 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1508 }
1509
1510 RetOps[0] = Chain; // Update chain.
1511
1512 // Add the flag if we have it.
1513 if (Flag.getNode())
1514 RetOps.push_back(Flag);
1515
1516 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, RetOps);
1517 }
1518
1519 //===----------------------------------------------------------------------===//
1520 // Other Lowering Code
1521 //===----------------------------------------------------------------------===//
1522
1523 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr & MI,MachineBasicBlock * BB) const1524 XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1525 MachineBasicBlock *BB) const {
1526 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1527 DebugLoc dl = MI.getDebugLoc();
1528 assert((MI.getOpcode() == XCore::SELECT_CC) &&
1529 "Unexpected instr type to insert");
1530
1531 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1532 // control-flow pattern. The incoming instruction knows the destination vreg
1533 // to set, the condition code register to branch on, the true/false values to
1534 // select between, and a branch opcode to use.
1535 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1536 MachineFunction::iterator It = ++BB->getIterator();
1537
1538 // thisMBB:
1539 // ...
1540 // TrueVal = ...
1541 // cmpTY ccX, r1, r2
1542 // bCC copy1MBB
1543 // fallthrough --> copy0MBB
1544 MachineBasicBlock *thisMBB = BB;
1545 MachineFunction *F = BB->getParent();
1546 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1547 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1548 F->insert(It, copy0MBB);
1549 F->insert(It, sinkMBB);
1550
1551 // Transfer the remainder of BB and its successor edges to sinkMBB.
1552 sinkMBB->splice(sinkMBB->begin(), BB,
1553 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1554 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1555
1556 // Next, add the true and fallthrough blocks as its successors.
1557 BB->addSuccessor(copy0MBB);
1558 BB->addSuccessor(sinkMBB);
1559
1560 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
1561 .addReg(MI.getOperand(1).getReg())
1562 .addMBB(sinkMBB);
1563
1564 // copy0MBB:
1565 // %FalseValue = ...
1566 // # fallthrough to sinkMBB
1567 BB = copy0MBB;
1568
1569 // Update machine-CFG edges
1570 BB->addSuccessor(sinkMBB);
1571
1572 // sinkMBB:
1573 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1574 // ...
1575 BB = sinkMBB;
1576 BuildMI(*BB, BB->begin(), dl, TII.get(XCore::PHI), MI.getOperand(0).getReg())
1577 .addReg(MI.getOperand(3).getReg())
1578 .addMBB(copy0MBB)
1579 .addReg(MI.getOperand(2).getReg())
1580 .addMBB(thisMBB);
1581
1582 MI.eraseFromParent(); // The pseudo instruction is gone now.
1583 return BB;
1584 }
1585
1586 //===----------------------------------------------------------------------===//
1587 // Target Optimization Hooks
1588 //===----------------------------------------------------------------------===//
1589
PerformDAGCombine(SDNode * N,DAGCombinerInfo & DCI) const1590 SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
1591 DAGCombinerInfo &DCI) const {
1592 SelectionDAG &DAG = DCI.DAG;
1593 SDLoc dl(N);
1594 switch (N->getOpcode()) {
1595 default: break;
1596 case ISD::INTRINSIC_VOID:
1597 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
1598 case Intrinsic::xcore_outt:
1599 case Intrinsic::xcore_outct:
1600 case Intrinsic::xcore_chkct: {
1601 SDValue OutVal = N->getOperand(3);
1602 // These instructions ignore the high bits.
1603 if (OutVal.hasOneUse()) {
1604 unsigned BitWidth = OutVal.getValueSizeInBits();
1605 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 8);
1606 KnownBits Known;
1607 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1608 !DCI.isBeforeLegalizeOps());
1609 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1610 if (TLI.ShrinkDemandedConstant(OutVal, DemandedMask, TLO) ||
1611 TLI.SimplifyDemandedBits(OutVal, DemandedMask, Known, TLO))
1612 DCI.CommitTargetLoweringOpt(TLO);
1613 }
1614 break;
1615 }
1616 case Intrinsic::xcore_setpt: {
1617 SDValue Time = N->getOperand(3);
1618 // This instruction ignores the high bits.
1619 if (Time.hasOneUse()) {
1620 unsigned BitWidth = Time.getValueSizeInBits();
1621 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16);
1622 KnownBits Known;
1623 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1624 !DCI.isBeforeLegalizeOps());
1625 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1626 if (TLI.ShrinkDemandedConstant(Time, DemandedMask, TLO) ||
1627 TLI.SimplifyDemandedBits(Time, DemandedMask, Known, TLO))
1628 DCI.CommitTargetLoweringOpt(TLO);
1629 }
1630 break;
1631 }
1632 }
1633 break;
1634 case XCoreISD::LADD: {
1635 SDValue N0 = N->getOperand(0);
1636 SDValue N1 = N->getOperand(1);
1637 SDValue N2 = N->getOperand(2);
1638 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1639 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1640 EVT VT = N0.getValueType();
1641
1642 // canonicalize constant to RHS
1643 if (N0C && !N1C)
1644 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1645
1646 // fold (ladd 0, 0, x) -> 0, x & 1
1647 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1648 SDValue Carry = DAG.getConstant(0, dl, VT);
1649 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
1650 DAG.getConstant(1, dl, VT));
1651 SDValue Ops[] = { Result, Carry };
1652 return DAG.getMergeValues(Ops, dl);
1653 }
1654
1655 // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the
1656 // low bit set
1657 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) {
1658 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1659 VT.getSizeInBits() - 1);
1660 KnownBits Known = DAG.computeKnownBits(N2);
1661 if ((Known.Zero & Mask) == Mask) {
1662 SDValue Carry = DAG.getConstant(0, dl, VT);
1663 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
1664 SDValue Ops[] = { Result, Carry };
1665 return DAG.getMergeValues(Ops, dl);
1666 }
1667 }
1668 }
1669 break;
1670 case XCoreISD::LSUB: {
1671 SDValue N0 = N->getOperand(0);
1672 SDValue N1 = N->getOperand(1);
1673 SDValue N2 = N->getOperand(2);
1674 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1675 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1676 EVT VT = N0.getValueType();
1677
1678 // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set
1679 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1680 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1681 VT.getSizeInBits() - 1);
1682 KnownBits Known = DAG.computeKnownBits(N2);
1683 if ((Known.Zero & Mask) == Mask) {
1684 SDValue Borrow = N2;
1685 SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
1686 DAG.getConstant(0, dl, VT), N2);
1687 SDValue Ops[] = { Result, Borrow };
1688 return DAG.getMergeValues(Ops, dl);
1689 }
1690 }
1691
1692 // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the
1693 // low bit set
1694 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) {
1695 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1696 VT.getSizeInBits() - 1);
1697 KnownBits Known = DAG.computeKnownBits(N2);
1698 if ((Known.Zero & Mask) == Mask) {
1699 SDValue Borrow = DAG.getConstant(0, dl, VT);
1700 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
1701 SDValue Ops[] = { Result, Borrow };
1702 return DAG.getMergeValues(Ops, dl);
1703 }
1704 }
1705 }
1706 break;
1707 case XCoreISD::LMUL: {
1708 SDValue N0 = N->getOperand(0);
1709 SDValue N1 = N->getOperand(1);
1710 SDValue N2 = N->getOperand(2);
1711 SDValue N3 = N->getOperand(3);
1712 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1713 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1714 EVT VT = N0.getValueType();
1715 // Canonicalize multiplicative constant to RHS. If both multiplicative
1716 // operands are constant canonicalize smallest to RHS.
1717 if ((N0C && !N1C) ||
1718 (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue()))
1719 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT),
1720 N1, N0, N2, N3);
1721
1722 // lmul(x, 0, a, b)
1723 if (N1C && N1C->isNullValue()) {
1724 // If the high result is unused fold to add(a, b)
1725 if (N->hasNUsesOfValue(0, 0)) {
1726 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3);
1727 SDValue Ops[] = { Lo, Lo };
1728 return DAG.getMergeValues(Ops, dl);
1729 }
1730 // Otherwise fold to ladd(a, b, 0)
1731 SDValue Result =
1732 DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1);
1733 SDValue Carry(Result.getNode(), 1);
1734 SDValue Ops[] = { Carry, Result };
1735 return DAG.getMergeValues(Ops, dl);
1736 }
1737 }
1738 break;
1739 case ISD::ADD: {
1740 // Fold 32 bit expressions such as add(add(mul(x,y),a),b) ->
1741 // lmul(x, y, a, b). The high result of lmul will be ignored.
1742 // This is only profitable if the intermediate results are unused
1743 // elsewhere.
1744 SDValue Mul0, Mul1, Addend0, Addend1;
1745 if (N->getValueType(0) == MVT::i32 &&
1746 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) {
1747 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl,
1748 DAG.getVTList(MVT::i32, MVT::i32), Mul0,
1749 Mul1, Addend0, Addend1);
1750 SDValue Result(Ignored.getNode(), 1);
1751 return Result;
1752 }
1753 APInt HighMask = APInt::getHighBitsSet(64, 32);
1754 // Fold 64 bit expression such as add(add(mul(x,y),a),b) ->
1755 // lmul(x, y, a, b) if all operands are zero-extended. We do this
1756 // before type legalization as it is messy to match the operands after
1757 // that.
1758 if (N->getValueType(0) == MVT::i64 &&
1759 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) &&
1760 DAG.MaskedValueIsZero(Mul0, HighMask) &&
1761 DAG.MaskedValueIsZero(Mul1, HighMask) &&
1762 DAG.MaskedValueIsZero(Addend0, HighMask) &&
1763 DAG.MaskedValueIsZero(Addend1, HighMask)) {
1764 SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1765 Mul0, DAG.getConstant(0, dl, MVT::i32));
1766 SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1767 Mul1, DAG.getConstant(0, dl, MVT::i32));
1768 SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1769 Addend0, DAG.getConstant(0, dl, MVT::i32));
1770 SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1771 Addend1, DAG.getConstant(0, dl, MVT::i32));
1772 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
1773 DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
1774 Addend0L, Addend1L);
1775 SDValue Lo(Hi.getNode(), 1);
1776 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1777 }
1778 }
1779 break;
1780 case ISD::STORE: {
1781 // Replace unaligned store of unaligned load with memmove.
1782 StoreSDNode *ST = cast<StoreSDNode>(N);
1783 if (!DCI.isBeforeLegalize() ||
1784 allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(),
1785 ST->getMemoryVT(),
1786 *ST->getMemOperand()) ||
1787 ST->isVolatile() || ST->isIndexed()) {
1788 break;
1789 }
1790 SDValue Chain = ST->getChain();
1791
1792 unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits();
1793 assert((StoreBits % 8) == 0 &&
1794 "Store size in bits must be a multiple of 8");
1795 unsigned Alignment = ST->getAlignment();
1796
1797 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) {
1798 if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() &&
1799 LD->getAlignment() == Alignment &&
1800 !LD->isVolatile() && !LD->isIndexed() &&
1801 Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) {
1802 bool isTail = isInTailCallPosition(DAG, ST, Chain);
1803 return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
1804 LD->getBasePtr(),
1805 DAG.getConstant(StoreBits/8, dl, MVT::i32),
1806 Align(Alignment), false, isTail, false,
1807 ST->getPointerInfo(), LD->getPointerInfo());
1808 }
1809 }
1810 break;
1811 }
1812 }
1813 return SDValue();
1814 }
1815
computeKnownBitsForTargetNode(const SDValue Op,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const1816 void XCoreTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1817 KnownBits &Known,
1818 const APInt &DemandedElts,
1819 const SelectionDAG &DAG,
1820 unsigned Depth) const {
1821 Known.resetAll();
1822 switch (Op.getOpcode()) {
1823 default: break;
1824 case XCoreISD::LADD:
1825 case XCoreISD::LSUB:
1826 if (Op.getResNo() == 1) {
1827 // Top bits of carry / borrow are clear.
1828 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1829 Known.getBitWidth() - 1);
1830 }
1831 break;
1832 case ISD::INTRINSIC_W_CHAIN:
1833 {
1834 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1835 switch (IntNo) {
1836 case Intrinsic::xcore_getts:
1837 // High bits are known to be zero.
1838 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1839 Known.getBitWidth() - 16);
1840 break;
1841 case Intrinsic::xcore_int:
1842 case Intrinsic::xcore_inct:
1843 // High bits are known to be zero.
1844 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1845 Known.getBitWidth() - 8);
1846 break;
1847 case Intrinsic::xcore_testct:
1848 // Result is either 0 or 1.
1849 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1850 Known.getBitWidth() - 1);
1851 break;
1852 case Intrinsic::xcore_testwct:
1853 // Result is in the range 0 - 4.
1854 Known.Zero = APInt::getHighBitsSet(Known.getBitWidth(),
1855 Known.getBitWidth() - 3);
1856 break;
1857 }
1858 }
1859 break;
1860 }
1861 }
1862
1863 //===----------------------------------------------------------------------===//
1864 // Addressing mode description hooks
1865 //===----------------------------------------------------------------------===//
1866
isImmUs(int64_t val)1867 static inline bool isImmUs(int64_t val)
1868 {
1869 return (val >= 0 && val <= 11);
1870 }
1871
isImmUs2(int64_t val)1872 static inline bool isImmUs2(int64_t val)
1873 {
1874 return (val%2 == 0 && isImmUs(val/2));
1875 }
1876
isImmUs4(int64_t val)1877 static inline bool isImmUs4(int64_t val)
1878 {
1879 return (val%4 == 0 && isImmUs(val/4));
1880 }
1881
1882 /// isLegalAddressingMode - Return true if the addressing mode represented
1883 /// by AM is legal for this target, for a load/store of the specified type.
isLegalAddressingMode(const DataLayout & DL,const AddrMode & AM,Type * Ty,unsigned AS,Instruction * I) const1884 bool XCoreTargetLowering::isLegalAddressingMode(const DataLayout &DL,
1885 const AddrMode &AM, Type *Ty,
1886 unsigned AS,
1887 Instruction *I) const {
1888 if (Ty->getTypeID() == Type::VoidTyID)
1889 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
1890
1891 unsigned Size = DL.getTypeAllocSize(Ty);
1892 if (AM.BaseGV) {
1893 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
1894 AM.BaseOffs%4 == 0;
1895 }
1896
1897 switch (Size) {
1898 case 1:
1899 // reg + imm
1900 if (AM.Scale == 0) {
1901 return isImmUs(AM.BaseOffs);
1902 }
1903 // reg + reg
1904 return AM.Scale == 1 && AM.BaseOffs == 0;
1905 case 2:
1906 case 3:
1907 // reg + imm
1908 if (AM.Scale == 0) {
1909 return isImmUs2(AM.BaseOffs);
1910 }
1911 // reg + reg<<1
1912 return AM.Scale == 2 && AM.BaseOffs == 0;
1913 default:
1914 // reg + imm
1915 if (AM.Scale == 0) {
1916 return isImmUs4(AM.BaseOffs);
1917 }
1918 // reg + reg<<2
1919 return AM.Scale == 4 && AM.BaseOffs == 0;
1920 }
1921 }
1922
1923 //===----------------------------------------------------------------------===//
1924 // XCore Inline Assembly Support
1925 //===----------------------------------------------------------------------===//
1926
1927 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,StringRef Constraint,MVT VT) const1928 XCoreTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1929 StringRef Constraint,
1930 MVT VT) const {
1931 if (Constraint.size() == 1) {
1932 switch (Constraint[0]) {
1933 default : break;
1934 case 'r':
1935 return std::make_pair(0U, &XCore::GRRegsRegClass);
1936 }
1937 }
1938 // Use the default implementation in TargetLowering to convert the register
1939 // constraint into a member of a register class.
1940 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
1941 }
1942