1; RUN: llc -march=amdgcn -mattr=+mad-mac-f32-insts -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 2; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 3 4 ; FIXME: None of these trigger madmk emission anymore. It is still 5 ; possible, but requires the correct registers to be used which is 6 ; hard to trigger. 7 8declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 9declare float @llvm.fabs.f32(float) nounwind readnone 10 11; GCN-LABEL: {{^}}madmk_f32: 12; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 13; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 14; GCN: v_mac_f32_e32 [[VB]], 0x41200000, [[VA]] 15define amdgpu_kernel void @madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { 16 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 17 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 18 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 19 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 20 21 %a = load volatile float, float addrspace(1)* %gep.0, align 4 22 %b = load volatile float, float addrspace(1)* %gep.1, align 4 23 24 %mul = fmul float %a, 10.0 25 %madmk = fadd float %mul, %b 26 store float %madmk, float addrspace(1)* %out.gep, align 4 27 ret void 28} 29 30; GCN-LABEL: {{^}}madmk_2_use_f32: 31; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 32; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 33; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 34; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x41200000 35; GCN-DAG: v_mac_f32_e32 [[VB]], [[SK]], [[VA]] 36; GCN-DAG: v_mac_f32_e32 [[VC]], [[SK]], [[VA]] 37; GCN: s_endpgm 38define amdgpu_kernel void @madmk_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { 39 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 40 41 %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 42 %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 43 %in.gep.2 = getelementptr float, float addrspace(1)* %in.gep.0, i32 2 44 45 %out.gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid 46 %out.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 47 48 %a = load volatile float, float addrspace(1)* %in.gep.0, align 4 49 %b = load volatile float, float addrspace(1)* %in.gep.1, align 4 50 %c = load volatile float, float addrspace(1)* %in.gep.2, align 4 51 52 %mul0 = fmul float %a, 10.0 53 %mul1 = fmul float %a, 10.0 54 %madmk0 = fadd float %mul0, %b 55 %madmk1 = fadd float %mul1, %c 56 57 store float %madmk0, float addrspace(1)* %out.gep.0, align 4 58 store float %madmk1, float addrspace(1)* %out.gep.1, align 4 59 ret void 60} 61 62; We don't get any benefit if the constant is an inline immediate. 63; GCN-LABEL: {{^}}madmk_inline_imm_f32: 64; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 65; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 66; GCN: v_mac_f32_e32 [[VB]], 4.0, [[VA]] 67define amdgpu_kernel void @madmk_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { 68 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 69 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 70 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 71 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 72 73 %a = load volatile float, float addrspace(1)* %gep.0, align 4 74 %b = load volatile float, float addrspace(1)* %gep.1, align 4 75 76 %mul = fmul float %a, 4.0 77 %madmk = fadd float %mul, %b 78 store float %madmk, float addrspace(1)* %out.gep, align 4 79 ret void 80} 81 82; GCN-LABEL: {{^}}s_s_madmk_f32: 83; GCN-NOT: v_madmk_f32 84; GCN: v_mac_f32_e32 85; GCN: s_endpgm 86define amdgpu_kernel void @s_s_madmk_f32(float addrspace(1)* noalias %out, [8 x i32], float %a, [8 x i32], float %b) #0 { 87 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 88 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 89 90 %mul = fmul float %a, 10.0 91 %madmk = fadd float %mul, %b 92 store float %madmk, float addrspace(1)* %out.gep, align 4 93 ret void 94} 95 96; GCN-LABEL: {{^}}v_s_madmk_f32: 97; GCN-DAG: s_load_dword [[SREG:s[0-9]+]] 98; GCN-DAG: buffer_load_dword [[VREG1:v[0-9]+]] 99; GCN: v_mov_b32_e32 [[VREG2:v[0-9]+]], [[SREG]] 100; GCN: v_mac_f32_e32 [[VREG2]], 0x41200000, [[VREG1]] 101; GCN: s_endpgm 102define amdgpu_kernel void @v_s_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %b) #0 { 103 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 104 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 105 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 106 %a = load float, float addrspace(1)* %gep.0, align 4 107 108 %mul = fmul float %a, 10.0 109 %madmk = fadd float %mul, %b 110 store float %madmk, float addrspace(1)* %out.gep, align 4 111 ret void 112} 113 114; GCN-LABEL: {{^}}scalar_vector_madmk_f32: 115; GCN-NOT: v_madmk_f32 116; GCN: v_mac_f32_e32 117; GCN: s_endpgm 118define amdgpu_kernel void @scalar_vector_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %a) #0 { 119 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 120 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 121 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 122 %b = load float, float addrspace(1)* %gep.0, align 4 123 124 %mul = fmul float %a, 10.0 125 %madmk = fadd float %mul, %b 126 store float %madmk, float addrspace(1)* %out.gep, align 4 127 ret void 128} 129 130; GCN-LABEL: {{^}}no_madmk_src0_modifier_f32: 131; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 132; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 133; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x41200000 134; GCN: v_mad_f32 {{v[0-9]+}}, |[[VA]]|, [[SK]], [[VB]] 135define amdgpu_kernel void @no_madmk_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { 136 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 137 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 138 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 139 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 140 141 %a = load volatile float, float addrspace(1)* %gep.0, align 4 142 %b = load volatile float, float addrspace(1)* %gep.1, align 4 143 144 %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone 145 146 %mul = fmul float %a.fabs, 10.0 147 %madmk = fadd float %mul, %b 148 store float %madmk, float addrspace(1)* %out.gep, align 4 149 ret void 150} 151 152; GCN-LABEL: {{^}}no_madmk_src2_modifier_f32: 153; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 154; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 155; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{[sv][0-9]+}}, |{{v[0-9]+}}| 156define amdgpu_kernel void @no_madmk_src2_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { 157 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 158 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 159 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 160 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 161 162 %a = load volatile float, float addrspace(1)* %gep.0, align 4 163 %b = load volatile float, float addrspace(1)* %gep.1, align 4 164 165 %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone 166 167 %mul = fmul float %a, 10.0 168 %madmk = fadd float %mul, %b.fabs 169 store float %madmk, float addrspace(1)* %out.gep, align 4 170 ret void 171} 172 173; GCN-LABEL: {{^}}madmk_add_inline_imm_f32: 174; GCN: buffer_load_dword [[A:v[0-9]+]] 175; GCN: s_mov_b32 [[SK:s[0-9]+]], 0x41200000 176; GCN: v_mad_f32 {{v[0-9]+}}, [[A]], [[SK]], 2.0 177define amdgpu_kernel void @madmk_add_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { 178 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 179 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 180 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 181 182 %a = load float, float addrspace(1)* %gep.0, align 4 183 184 %mul = fmul float %a, 10.0 185 %madmk = fadd float %mul, 2.0 186 store float %madmk, float addrspace(1)* %out.gep, align 4 187 ret void 188} 189 190; SI-LABEL: {{^}}kill_madmk_verifier_error: 191; SI: s_or_b64 192; SI: s_xor_b64 193; SI: v_mac_f32_e32 {{v[0-9]+}}, 0x472aee8c, {{v[0-9]+}} 194define amdgpu_kernel void @kill_madmk_verifier_error() #0 { 195bb: 196 br label %bb2 197 198bb1: ; preds = %bb2 199 ret void 200 201bb2: ; preds = %bb6, %bb 202 %tmp = phi float [ undef, %bb ], [ %tmp8, %bb6 ] 203 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1 204 %f_tid = bitcast i32 %tid to float 205 %tmp3 = fsub float %f_tid, %tmp 206 %tmp5 = fcmp oeq float %tmp3, 1.000000e+04 207 br i1 %tmp5, label %bb1, label %bb6 208 209bb6: ; preds = %bb2 210 %tmp7 = fmul float %tmp, 0x40E55DD180000000 211 %tmp8 = fadd float %tmp7, %tmp 212 br label %bb2 213} 214 215declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 216 217attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } 218attributes #1 = { nounwind readnone } 219