1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
3
4; Test that bitcasts between vector types are lowered to zero instructions
5
6target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
7target triple = "wasm32-unknown-unknown"
8
9; CHECK-LABEL: v16i8_to_v16i8:
10; NO-SIMD128-NOT: return $0
11; SIMD128: return $0
12define <16 x i8> @v16i8_to_v16i8(<16 x i8> %v) {
13  %res = bitcast <16 x i8> %v to <16 x i8>
14  ret <16 x i8> %res
15}
16
17; CHECK-LABEL: v16i8_to_v8i16:
18; NO-SIMD128-NOT: return $0
19; SIMD128: return $0
20define <8 x i16> @v16i8_to_v8i16(<16 x i8> %v) {
21  %res = bitcast <16 x i8> %v to <8 x i16>
22  ret <8 x i16> %res
23}
24
25; CHECK-LABEL: v16i8_to_v4i32:
26; NO-SIMD128-NOT: return $0
27; SIMD128: return $0
28define <4 x i32> @v16i8_to_v4i32(<16 x i8> %v) {
29  %res = bitcast <16 x i8> %v to <4 x i32>
30  ret <4 x i32> %res
31}
32
33; CHECK-LABEL: v16i8_to_v2i64:
34; NO-SIMD128-NOT: return $0
35; SIMD128: return $0
36define <2 x i64> @v16i8_to_v2i64(<16 x i8> %v) {
37  %res = bitcast <16 x i8> %v to <2 x i64>
38  ret <2 x i64> %res
39}
40
41; CHECK-LABEL: v16i8_to_v4f32:
42; NO-SIMD128-NOT: return $0
43; SIMD128: return $0
44define <4 x float> @v16i8_to_v4f32(<16 x i8> %v) {
45  %res = bitcast <16 x i8> %v to <4 x float>
46  ret <4 x float> %res
47}
48
49; CHECK-LABEL: v16i8_to_v2f64:
50; NO-SIMD128-NOT: return $0
51; SIMD128: return $0
52define <2 x double> @v16i8_to_v2f64(<16 x i8> %v) {
53  %res = bitcast <16 x i8> %v to <2 x double>
54  ret <2 x double> %res
55}
56
57; CHECK-LABEL: v8i16_to_v16i8:
58; NO-SIMD128-NOT: return $0
59; SIMD128: return $0
60define <16 x i8> @v8i16_to_v16i8(<8 x i16> %v) {
61  %res = bitcast <8 x i16> %v to <16 x i8>
62  ret <16 x i8> %res
63}
64
65; CHECK-LABEL: v8i16_to_v8i16:
66; NO-SIMD128-NOT: return $0
67; SIMD128: return $0
68define <8 x i16> @v8i16_to_v8i16(<8 x i16> %v) {
69  %res = bitcast <8 x i16> %v to <8 x i16>
70  ret <8 x i16> %res
71}
72
73; CHECK-LABEL: v8i16_to_v4i32:
74; NO-SIMD128-NOT: return $0
75; SIMD128: return $0
76define <4 x i32> @v8i16_to_v4i32(<8 x i16> %v) {
77  %res = bitcast <8 x i16> %v to <4 x i32>
78  ret <4 x i32> %res
79}
80
81; CHECK-LABEL: v8i16_to_v2i64:
82; NO-SIMD128-NOT: return $0
83; SIMD128: return $0
84define <2 x i64> @v8i16_to_v2i64(<8 x i16> %v) {
85  %res = bitcast <8 x i16> %v to <2 x i64>
86  ret <2 x i64> %res
87}
88
89; CHECK-LABEL: v8i16_to_v4f32:
90; NO-SIMD128-NOT: return $0
91; SIMD128: return $0
92define <4 x float> @v8i16_to_v4f32(<8 x i16> %v) {
93  %res = bitcast <8 x i16> %v to <4 x float>
94  ret <4 x float> %res
95}
96
97; CHECK-LABEL: v8i16_to_v2f64:
98; NO-SIMD128-NOT: return $0
99; SIMD128: return $0
100define <2 x double> @v8i16_to_v2f64(<8 x i16> %v) {
101  %res = bitcast <8 x i16> %v to <2 x double>
102  ret <2 x double> %res
103}
104
105; CHECK-LABEL: v4i32_to_v16i8:
106; NO-SIMD128-NOT: return $0
107; SIMD128: return $0
108define <16 x i8> @v4i32_to_v16i8(<4 x i32> %v) {
109  %res = bitcast <4 x i32> %v to <16 x i8>
110  ret <16 x i8> %res
111}
112
113; CHECK-LABEL: v4i32_to_v8i16:
114; NO-SIMD128-NOT: return $0
115; SIMD128: return $0
116define <8 x i16> @v4i32_to_v8i16(<4 x i32> %v) {
117  %res = bitcast <4 x i32> %v to <8 x i16>
118  ret <8 x i16> %res
119}
120
121; CHECK-LABEL: v4i32_to_v4i32:
122; NO-SIMD128-NOT: return $0
123; SIMD128: return $0
124define <4 x i32> @v4i32_to_v4i32(<4 x i32> %v) {
125  %res = bitcast <4 x i32> %v to <4 x i32>
126  ret <4 x i32> %res
127}
128
129; CHECK-LABEL: v4i32_to_v2i64:
130; NO-SIMD128-NOT: return $0
131; SIMD128: return $0
132define <2 x i64> @v4i32_to_v2i64(<4 x i32> %v) {
133  %res = bitcast <4 x i32> %v to <2 x i64>
134  ret <2 x i64> %res
135}
136
137; CHECK-LABEL: v4i32_to_v4f32:
138; NO-SIMD128-NOT: return $0
139; SIMD128: return $0
140define <4 x float> @v4i32_to_v4f32(<4 x i32> %v) {
141  %res = bitcast <4 x i32> %v to <4 x float>
142  ret <4 x float> %res
143}
144
145; CHECK-LABEL: v4i32_to_v2f64:
146; NO-SIMD128-NOT: return $0
147; SIMD128: return $0
148define <2 x double> @v4i32_to_v2f64(<4 x i32> %v) {
149  %res = bitcast <4 x i32> %v to <2 x double>
150  ret <2 x double> %res
151}
152
153; CHECK-LABEL: v2i64_to_v16i8:
154; NO-SIMD128-NOT: return $0
155; SIMD128: return $0
156define <16 x i8> @v2i64_to_v16i8(<2 x i64> %v) {
157  %res = bitcast <2 x i64> %v to <16 x i8>
158  ret <16 x i8> %res
159}
160
161; CHECK-LABEL: v2i64_to_v8i16:
162; NO-SIMD128-NOT: return $0
163; SIMD128: return $0
164define <8 x i16> @v2i64_to_v8i16(<2 x i64> %v) {
165  %res = bitcast <2 x i64> %v to <8 x i16>
166  ret <8 x i16> %res
167}
168
169; CHECK-LABEL: v2i64_to_v4i32:
170; NO-SIMD128-NOT: return $0
171; SIMD128: return $0
172define <4 x i32> @v2i64_to_v4i32(<2 x i64> %v) {
173  %res = bitcast <2 x i64> %v to <4 x i32>
174  ret <4 x i32> %res
175}
176
177; CHECK-LABEL: v2i64_to_v2i64:
178; NO-SIMD128-NOT: return $0
179; SIMD128: return $0
180define <2 x i64> @v2i64_to_v2i64(<2 x i64> %v) {
181  %res = bitcast <2 x i64> %v to <2 x i64>
182  ret <2 x i64> %res
183}
184
185; CHECK-LABEL: v2i64_to_v4f32:
186; NO-SIMD128-NOT: return $0
187; SIMD128: return $0
188define <4 x float> @v2i64_to_v4f32(<2 x i64> %v) {
189  %res = bitcast <2 x i64> %v to <4 x float>
190  ret <4 x float> %res
191}
192
193; CHECK-LABEL: v2i64_to_v2f64:
194; NO-SIMD128-NOT: return $0
195; SIMD128: return $0
196define <2 x double> @v2i64_to_v2f64(<2 x i64> %v) {
197  %res = bitcast <2 x i64> %v to <2 x double>
198  ret <2 x double> %res
199}
200
201; CHECK-LABEL: v4f32_to_v16i8:
202; NO-SIMD128-NOT: return $0
203; SIMD128: return $0
204define <16 x i8> @v4f32_to_v16i8(<4 x float> %v) {
205  %res = bitcast <4 x float> %v to <16 x i8>
206  ret <16 x i8> %res
207}
208
209; CHECK-LABEL: v4f32_to_v8i16:
210; NO-SIMD128-NOT: return $0
211; SIMD128: return $0
212define <8 x i16> @v4f32_to_v8i16(<4 x float> %v) {
213  %res = bitcast <4 x float> %v to <8 x i16>
214  ret <8 x i16> %res
215}
216
217; CHECK-LABEL: v4f32_to_v4i32:
218; NO-SIMD128-NOT: return $0
219; SIMD128: return $0
220define <4 x i32> @v4f32_to_v4i32(<4 x float> %v) {
221  %res = bitcast <4 x float> %v to <4 x i32>
222  ret <4 x i32> %res
223}
224
225; CHECK-LABEL: v4f32_to_v2i64:
226; NO-SIMD128-NOT: return $0
227; SIMD128: return $0
228define <2 x i64> @v4f32_to_v2i64(<4 x float> %v) {
229  %res = bitcast <4 x float> %v to <2 x i64>
230  ret <2 x i64> %res
231}
232
233; CHECK-LABEL: v4f32_to_v4f32:
234; NO-SIMD128-NOT: return $0
235; SIMD128: return $0
236define <4 x float> @v4f32_to_v4f32(<4 x float> %v) {
237  %res = bitcast <4 x float> %v to <4 x float>
238  ret <4 x float> %res
239}
240
241; CHECK-LABEL: v4f32_to_v2f64:
242; NO-SIMD128-NOT: return $0
243; SIMD128: return $0
244define <2 x double> @v4f32_to_v2f64(<4 x float> %v) {
245  %res = bitcast <4 x float> %v to <2 x double>
246  ret <2 x double> %res
247}
248
249; CHECK-LABEL: v2f64_to_v16i8:
250; NO-SIMD128-NOT: return $0
251; SIMD128: return $0
252define <16 x i8> @v2f64_to_v16i8(<2 x double> %v) {
253  %res = bitcast <2 x double> %v to <16 x i8>
254  ret <16 x i8> %res
255}
256
257; CHECK-LABEL: v2f64_to_v8i16:
258; NO-SIMD128-NOT: return $0
259; SIMD128: return $0
260define <8 x i16> @v2f64_to_v8i16(<2 x double> %v) {
261  %res = bitcast <2 x double> %v to <8 x i16>
262  ret <8 x i16> %res
263}
264
265; CHECK-LABEL: v2f64_to_v4i32:
266; NO-SIMD128-NOT: return $0
267; SIMD128: return $0
268define <4 x i32> @v2f64_to_v4i32(<2 x double> %v) {
269  %res = bitcast <2 x double> %v to <4 x i32>
270  ret <4 x i32> %res
271}
272
273; CHECK-LABEL: v2f64_to_v2i64:
274; NO-SIMD128-NOT: return $0
275; SIMD128: return $0
276define <2 x i64> @v2f64_to_v2i64(<2 x double> %v) {
277  %res = bitcast <2 x double> %v to <2 x i64>
278  ret <2 x i64> %res
279}
280
281; CHECK-LABEL: v2f64_to_v4f32:
282; NO-SIMD128-NOT: return $0
283; SIMD128: return $0
284define <4 x float> @v2f64_to_v4f32(<2 x double> %v) {
285  %res = bitcast <2 x double> %v to <4 x float>
286  ret <4 x float> %res
287}
288
289; CHECK-LABEL: v2f64_to_v2f64:
290; NO-SIMD128-NOT: return $0
291; SIMD128: return $0
292define <2 x double> @v2f64_to_v2f64(<2 x double> %v) {
293  %res = bitcast <2 x double> %v to <2 x double>
294  ret <2 x double> %res
295}
296