1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128 2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128 3 4; Test that SIMD128 intrinsics lower as expected. These intrinsics are 5; only expected to lower successfully if the simd128 attribute is 6; enabled and legal types are used. 7 8target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" 9target triple = "wasm32-unknown-unknown" 10 11; ============================================================================== 12; 16 x i8 13; ============================================================================== 14; CHECK-LABEL: swizzle_v16i8: 15; SIMD128-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}} 16; SIMD128-NEXT: v8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}} 17; SIMD128-NEXT: return $pop[[R]]{{$}} 18declare <16 x i8> @llvm.wasm.swizzle(<16 x i8>, <16 x i8>) 19define <16 x i8> @swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) { 20 %a = call <16 x i8> @llvm.wasm.swizzle(<16 x i8> %x, <16 x i8> %y) 21 ret <16 x i8> %a 22} 23 24; CHECK-LABEL: add_sat_s_v16i8: 25; SIMD128-NEXT: .functype add_sat_s_v16i8 (v128, v128) -> (v128){{$}} 26; SIMD128-NEXT: i8x16.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}} 27; SIMD128-NEXT: return $pop[[R]]{{$}} 28declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>) 29define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 30 %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 31 ret <16 x i8> %a 32} 33 34; CHECK-LABEL: add_sat_u_v16i8: 35; SIMD128-NEXT: .functype add_sat_u_v16i8 (v128, v128) -> (v128){{$}} 36; SIMD128-NEXT: i8x16.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}} 37; SIMD128-NEXT: return $pop[[R]]{{$}} 38declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) 39define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 40 %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) 41 ret <16 x i8> %a 42} 43 44; CHECK-LABEL: sub_sat_s_v16i8: 45; SIMD128-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}} 46; SIMD128-NEXT: i8x16.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}} 47; SIMD128-NEXT: return $pop[[R]]{{$}} 48declare <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8(<16 x i8>, <16 x i8>) 49define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) { 50 %a = call <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8( 51 <16 x i8> %x, <16 x i8> %y 52 ) 53 ret <16 x i8> %a 54} 55 56; CHECK-LABEL: sub_sat_u_v16i8: 57; SIMD128-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}} 58; SIMD128-NEXT: i8x16.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}} 59; SIMD128-NEXT: return $pop[[R]]{{$}} 60declare <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(<16 x i8>, <16 x i8>) 61define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 62 %a = call <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8( 63 <16 x i8> %x, <16 x i8> %y 64 ) 65 ret <16 x i8> %a 66} 67 68; CHECK-LABEL: avgr_u_v16i8: 69; SIMD128-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}} 70; SIMD128-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 71; SIMD128-NEXT: return $pop[[R]]{{$}} 72declare <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8>, <16 x i8>) 73define <16 x i8> @avgr_u_v16i8(<16 x i8> %x, <16 x i8> %y) { 74 %a = call <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(<16 x i8> %x, <16 x i8> %y) 75 ret <16 x i8> %a 76} 77 78; CHECK-LABEL: any_v16i8: 79; SIMD128-NEXT: .functype any_v16i8 (v128) -> (i32){{$}} 80; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}} 81; SIMD128-NEXT: return $pop[[R]]{{$}} 82declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>) 83define i32 @any_v16i8(<16 x i8> %x) { 84 %a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x) 85 ret i32 %a 86} 87 88; CHECK-LABEL: all_v16i8: 89; SIMD128-NEXT: .functype all_v16i8 (v128) -> (i32){{$}} 90; SIMD128-NEXT: i8x16.all_true $push[[R:[0-9]+]]=, $0{{$}} 91; SIMD128-NEXT: return $pop[[R]]{{$}} 92declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>) 93define i32 @all_v16i8(<16 x i8> %x) { 94 %a = call i32 @llvm.wasm.alltrue.v16i8(<16 x i8> %x) 95 ret i32 %a 96} 97 98; CHECK-LABEL: bitmask_v16i8: 99; SIMD128-NEXT: .functype bitmask_v16i8 (v128) -> (i32){{$}} 100; SIMD128-NEXT: i8x16.bitmask $push[[R:[0-9]+]]=, $0{{$}} 101; SIMD128-NEXT: return $pop[[R]]{{$}} 102declare i32 @llvm.wasm.bitmask.v16i8(<16 x i8>) 103define i32 @bitmask_v16i8(<16 x i8> %x) { 104 %a = call i32 @llvm.wasm.bitmask.v16i8(<16 x i8> %x) 105 ret i32 %a 106} 107 108; CHECK-LABEL: bitselect_v16i8: 109; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}} 110; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 111; SIMD128-NEXT: return $pop[[R]]{{$}} 112declare <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) 113define <16 x i8> @bitselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) { 114 %a = call <16 x i8> @llvm.wasm.bitselect.v16i8( 115 <16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c 116 ) 117 ret <16 x i8> %a 118} 119 120; CHECK-LABEL: narrow_signed_v16i8: 121; SIMD128-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}} 122; SIMD128-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 123; SIMD128-NEXT: return $pop[[R]]{{$}} 124declare <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16>, <8 x i16>) 125define <16 x i8> @narrow_signed_v16i8(<8 x i16> %low, <8 x i16> %high) { 126 %a = call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16( 127 <8 x i16> %low, <8 x i16> %high 128 ) 129 ret <16 x i8> %a 130} 131 132; CHECK-LABEL: narrow_unsigned_v16i8: 133; SIMD128-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}} 134; SIMD128-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}} 135; SIMD128-NEXT: return $pop[[R]]{{$}} 136declare <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(<8 x i16>, <8 x i16>) 137define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) { 138 %a = call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16( 139 <8 x i16> %low, <8 x i16> %high 140 ) 141 ret <16 x i8> %a 142} 143 144; CHECK-LABEL: shuffle_v16i8: 145; NO-SIMD128-NOT: v8x16 146; SIMD128-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}} 147; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1, 148; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}} 149; SIMD128-NEXT: return $pop[[R]]{{$}} 150declare <16 x i8> @llvm.wasm.shuffle( 151 <16 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, 152 i32, i32, i32, i32, i32) 153define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) { 154 %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y, 155 i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, 156 i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 35) 157 ret <16 x i8> %res 158} 159 160; CHECK-LABEL: shuffle_undef_v16i8: 161; NO-SIMD128-NOT: v8x16 162; SIMD128-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}} 163; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1, 164; SIMD128-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}} 165; SIMD128-NEXT: return $pop[[R]]{{$}} 166define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) { 167 %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y, 168 i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, 169 i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, 170 i32 undef, i32 undef, i32 undef, i32 2) 171 ret <16 x i8> %res 172} 173 174; ============================================================================== 175; 8 x i16 176; ============================================================================== 177; CHECK-LABEL: add_sat_s_v8i16: 178; SIMD128-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}} 179; SIMD128-NEXT: i16x8.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}} 180; SIMD128-NEXT: return $pop[[R]]{{$}} 181declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) 182define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 183 %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 184 ret <8 x i16> %a 185} 186 187; CHECK-LABEL: add_sat_u_v8i16: 188; SIMD128-NEXT: .functype add_sat_u_v8i16 (v128, v128) -> (v128){{$}} 189; SIMD128-NEXT: i16x8.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}} 190; SIMD128-NEXT: return $pop[[R]]{{$}} 191declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>) 192define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 193 %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) 194 ret <8 x i16> %a 195} 196 197; CHECK-LABEL: sub_sat_s_v8i16: 198; SIMD128-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}} 199; SIMD128-NEXT: i16x8.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}} 200; SIMD128-NEXT: return $pop[[R]]{{$}} 201declare <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16(<8 x i16>, <8 x i16>) 202define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) { 203 %a = call <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16( 204 <8 x i16> %x, <8 x i16> %y 205 ) 206 ret <8 x i16> %a 207} 208 209; CHECK-LABEL: sub_sat_u_v8i16: 210; SIMD128-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}} 211; SIMD128-NEXT: i16x8.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}} 212; SIMD128-NEXT: return $pop[[R]]{{$}} 213declare <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16(<8 x i16>, <8 x i16>) 214define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 215 %a = call <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16( 216 <8 x i16> %x, <8 x i16> %y 217 ) 218 ret <8 x i16> %a 219} 220 221; CHECK-LABEL: avgr_u_v8i16: 222; SIMD128-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}} 223; SIMD128-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}} 224; SIMD128-NEXT: return $pop[[R]]{{$}} 225declare <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16>, <8 x i16>) 226define <8 x i16> @avgr_u_v8i16(<8 x i16> %x, <8 x i16> %y) { 227 %a = call <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16> %x, <8 x i16> %y) 228 ret <8 x i16> %a 229} 230 231; CHECK-LABEL: any_v8i16: 232; SIMD128-NEXT: .functype any_v8i16 (v128) -> (i32){{$}} 233; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}} 234; SIMD128-NEXT: return $pop[[R]]{{$}} 235declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>) 236define i32 @any_v8i16(<8 x i16> %x) { 237 %a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x) 238 ret i32 %a 239} 240 241; CHECK-LABEL: all_v8i16: 242; SIMD128-NEXT: .functype all_v8i16 (v128) -> (i32){{$}} 243; SIMD128-NEXT: i16x8.all_true $push[[R:[0-9]+]]=, $0{{$}} 244; SIMD128-NEXT: return $pop[[R]]{{$}} 245declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>) 246define i32 @all_v8i16(<8 x i16> %x) { 247 %a = call i32 @llvm.wasm.alltrue.v8i16(<8 x i16> %x) 248 ret i32 %a 249} 250 251; CHECK-LABEL: bitmask_v8i16: 252; SIMD128-NEXT: .functype bitmask_v8i16 (v128) -> (i32){{$}} 253; SIMD128-NEXT: i16x8.bitmask $push[[R:[0-9]+]]=, $0{{$}} 254; SIMD128-NEXT: return $pop[[R]]{{$}} 255declare i32 @llvm.wasm.bitmask.v8i16(<8 x i16>) 256define i32 @bitmask_v8i16(<8 x i16> %x) { 257 %a = call i32 @llvm.wasm.bitmask.v8i16(<8 x i16> %x) 258 ret i32 %a 259} 260 261; CHECK-LABEL: bitselect_v8i16: 262; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}} 263; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 264; SIMD128-NEXT: return $pop[[R]]{{$}} 265declare <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) 266define <8 x i16> @bitselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) { 267 %a = call <8 x i16> @llvm.wasm.bitselect.v8i16( 268 <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c 269 ) 270 ret <8 x i16> %a 271} 272 273; CHECK-LABEL: narrow_signed_v8i16: 274; SIMD128-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}} 275; SIMD128-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}} 276; SIMD128-NEXT: return $pop[[R]]{{$}} 277declare <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(<4 x i32>, <4 x i32>) 278define <8 x i16> @narrow_signed_v8i16(<4 x i32> %low, <4 x i32> %high) { 279 %a = call <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32( 280 <4 x i32> %low, <4 x i32> %high 281 ) 282 ret <8 x i16> %a 283} 284 285; CHECK-LABEL: narrow_unsigned_v8i16: 286; SIMD128-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}} 287; SIMD128-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}} 288; SIMD128-NEXT: return $pop[[R]]{{$}} 289declare <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(<4 x i32>, <4 x i32>) 290define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) { 291 %a = call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32( 292 <4 x i32> %low, <4 x i32> %high 293 ) 294 ret <8 x i16> %a 295} 296 297; CHECK-LABEL: widen_low_signed_v8i16: 298; SIMD128-NEXT: .functype widen_low_signed_v8i16 (v128) -> (v128){{$}} 299; SIMD128-NEXT: i16x8.widen_low_i8x16_s $push[[R:[0-9]+]]=, $0{{$}} 300; SIMD128-NEXT: return $pop[[R]]{{$}} 301declare <8 x i16> @llvm.wasm.widen.low.signed.v8i16.v16i8(<16 x i8>) 302define <8 x i16> @widen_low_signed_v8i16(<16 x i8> %v) { 303 %a = call <8 x i16> @llvm.wasm.widen.low.signed.v8i16.v16i8(<16 x i8> %v) 304 ret <8 x i16> %a 305} 306 307; CHECK-LABEL: widen_high_signed_v8i16: 308; SIMD128-NEXT: .functype widen_high_signed_v8i16 (v128) -> (v128){{$}} 309; SIMD128-NEXT: i16x8.widen_high_i8x16_s $push[[R:[0-9]+]]=, $0{{$}} 310; SIMD128-NEXT: return $pop[[R]]{{$}} 311declare <8 x i16> @llvm.wasm.widen.high.signed.v8i16.v16i8(<16 x i8>) 312define <8 x i16> @widen_high_signed_v8i16(<16 x i8> %v) { 313 %a = call <8 x i16> @llvm.wasm.widen.high.signed.v8i16.v16i8(<16 x i8> %v) 314 ret <8 x i16> %a 315} 316 317; CHECK-LABEL: widen_low_unsigned_v8i16: 318; SIMD128-NEXT: .functype widen_low_unsigned_v8i16 (v128) -> (v128){{$}} 319; SIMD128-NEXT: i16x8.widen_low_i8x16_u $push[[R:[0-9]+]]=, $0{{$}} 320; SIMD128-NEXT: return $pop[[R]]{{$}} 321declare <8 x i16> @llvm.wasm.widen.low.unsigned.v8i16.v16i8(<16 x i8>) 322define <8 x i16> @widen_low_unsigned_v8i16(<16 x i8> %v) { 323 %a = call <8 x i16> @llvm.wasm.widen.low.unsigned.v8i16.v16i8(<16 x i8> %v) 324 ret <8 x i16> %a 325} 326 327; CHECK-LABEL: widen_high_unsigned_v8i16: 328; SIMD128-NEXT: .functype widen_high_unsigned_v8i16 (v128) -> (v128){{$}} 329; SIMD128-NEXT: i16x8.widen_high_i8x16_u $push[[R:[0-9]+]]=, $0{{$}} 330; SIMD128-NEXT: return $pop[[R]]{{$}} 331declare <8 x i16> @llvm.wasm.widen.high.unsigned.v8i16.v16i8(<16 x i8>) 332define <8 x i16> @widen_high_unsigned_v8i16(<16 x i8> %v) { 333 %a = call <8 x i16> @llvm.wasm.widen.high.unsigned.v8i16.v16i8(<16 x i8> %v) 334 ret <8 x i16> %a 335} 336 337; ============================================================================== 338; 4 x i32 339; ============================================================================== 340; CHECK-LABEL: dot: 341; SIMD128-NEXT: .functype dot (v128, v128) -> (v128){{$}} 342; SIMD128-NEXT: i32x4.dot_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}} 343; SIMD128-NEXT: return $pop[[R]]{{$}} 344declare <4 x i32> @llvm.wasm.dot(<8 x i16>, <8 x i16>) 345define <4 x i32> @dot(<8 x i16> %x, <8 x i16> %y) { 346 %a = call <4 x i32> @llvm.wasm.dot(<8 x i16> %x, <8 x i16> %y) 347 ret <4 x i32> %a 348} 349 350; CHECK-LABEL: any_v4i32: 351; SIMD128-NEXT: .functype any_v4i32 (v128) -> (i32){{$}} 352; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}} 353; SIMD128-NEXT: return $pop[[R]]{{$}} 354declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>) 355define i32 @any_v4i32(<4 x i32> %x) { 356 %a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x) 357 ret i32 %a 358} 359 360; CHECK-LABEL: all_v4i32: 361; SIMD128-NEXT: .functype all_v4i32 (v128) -> (i32){{$}} 362; SIMD128-NEXT: i32x4.all_true $push[[R:[0-9]+]]=, $0{{$}} 363; SIMD128-NEXT: return $pop[[R]]{{$}} 364declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>) 365define i32 @all_v4i32(<4 x i32> %x) { 366 %a = call i32 @llvm.wasm.alltrue.v4i32(<4 x i32> %x) 367 ret i32 %a 368} 369 370; CHECK-LABEL: bitmask_v4i32: 371; SIMD128-NEXT: .functype bitmask_v4i32 (v128) -> (i32){{$}} 372; SIMD128-NEXT: i32x4.bitmask $push[[R:[0-9]+]]=, $0{{$}} 373; SIMD128-NEXT: return $pop[[R]]{{$}} 374declare i32 @llvm.wasm.bitmask.v4i32(<4 x i32>) 375define i32 @bitmask_v4i32(<4 x i32> %x) { 376 %a = call i32 @llvm.wasm.bitmask.v4i32(<4 x i32> %x) 377 ret i32 %a 378} 379 380; CHECK-LABEL: bitselect_v4i32: 381; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}} 382; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 383; SIMD128-NEXT: return $pop[[R]]{{$}} 384declare <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 385define <4 x i32> @bitselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) { 386 %a = call <4 x i32> @llvm.wasm.bitselect.v4i32( 387 <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c 388 ) 389 ret <4 x i32> %a 390} 391 392; CHECK-LABEL: trunc_sat_s_v4i32: 393; NO-SIMD128-NOT: f32x4 394; SIMD128-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}} 395; SIMD128-NEXT: i32x4.trunc_sat_f32x4_s $push[[R:[0-9]+]]=, $0 396; SIMD128-NEXT: return $pop[[R]] 397declare <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float>) 398define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) { 399 %a = call <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float> %x) 400 ret <4 x i32> %a 401} 402 403; CHECK-LABEL: trunc_sat_u_v4i32: 404; NO-SIMD128-NOT: f32x4 405; SIMD128-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}} 406; SIMD128-NEXT: i32x4.trunc_sat_f32x4_u $push[[R:[0-9]+]]=, $0 407; SIMD128-NEXT: return $pop[[R]] 408declare <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float>) 409define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) { 410 %a = call <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float> %x) 411 ret <4 x i32> %a 412} 413 414; CHECK-LABEL: widen_low_signed_v4i32: 415; SIMD128-NEXT: .functype widen_low_signed_v4i32 (v128) -> (v128){{$}} 416; SIMD128-NEXT: i32x4.widen_low_i16x8_s $push[[R:[0-9]+]]=, $0{{$}} 417; SIMD128-NEXT: return $pop[[R]]{{$}} 418declare <4 x i32> @llvm.wasm.widen.low.signed.v4i32.v8i16(<8 x i16>) 419define <4 x i32> @widen_low_signed_v4i32(<8 x i16> %v) { 420 %a = call <4 x i32> @llvm.wasm.widen.low.signed.v4i32.v8i16(<8 x i16> %v) 421 ret <4 x i32> %a 422} 423 424; CHECK-LABEL: widen_high_signed_v4i32: 425; SIMD128-NEXT: .functype widen_high_signed_v4i32 (v128) -> (v128){{$}} 426; SIMD128-NEXT: i32x4.widen_high_i16x8_s $push[[R:[0-9]+]]=, $0{{$}} 427; SIMD128-NEXT: return $pop[[R]]{{$}} 428declare <4 x i32> @llvm.wasm.widen.high.signed.v4i32.v8i16(<8 x i16>) 429define <4 x i32> @widen_high_signed_v4i32(<8 x i16> %v) { 430 %a = call <4 x i32> @llvm.wasm.widen.high.signed.v4i32.v8i16(<8 x i16> %v) 431 ret <4 x i32> %a 432} 433 434; CHECK-LABEL: widen_low_unsigned_v4i32: 435; SIMD128-NEXT: .functype widen_low_unsigned_v4i32 (v128) -> (v128){{$}} 436; SIMD128-NEXT: i32x4.widen_low_i16x8_u $push[[R:[0-9]+]]=, $0{{$}} 437; SIMD128-NEXT: return $pop[[R]]{{$}} 438declare <4 x i32> @llvm.wasm.widen.low.unsigned.v4i32.v8i16(<8 x i16>) 439define <4 x i32> @widen_low_unsigned_v4i32(<8 x i16> %v) { 440 %a = call <4 x i32> @llvm.wasm.widen.low.unsigned.v4i32.v8i16(<8 x i16> %v) 441 ret <4 x i32> %a 442} 443 444; CHECK-LABEL: widen_high_unsigned_v4i32: 445; SIMD128-NEXT: .functype widen_high_unsigned_v4i32 (v128) -> (v128){{$}} 446; SIMD128-NEXT: i32x4.widen_high_i16x8_u $push[[R:[0-9]+]]=, $0{{$}} 447; SIMD128-NEXT: return $pop[[R]]{{$}} 448declare <4 x i32> @llvm.wasm.widen.high.unsigned.v4i32.v8i16(<8 x i16>) 449define <4 x i32> @widen_high_unsigned_v4i32(<8 x i16> %v) { 450 %a = call <4 x i32> @llvm.wasm.widen.high.unsigned.v4i32.v8i16(<8 x i16> %v) 451 ret <4 x i32> %a 452} 453 454; ============================================================================== 455; 2 x i64 456; ============================================================================== 457; CHECK-LABEL: any_v2i64: 458; SIMD128-NEXT: .functype any_v2i64 (v128) -> (i32){{$}} 459; SIMD128-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}} 460; SIMD128-NEXT: return $pop[[R]]{{$}} 461declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>) 462define i32 @any_v2i64(<2 x i64> %x) { 463 %a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x) 464 ret i32 %a 465} 466 467; CHECK-LABEL: all_v2i64: 468; SIMD128-NEXT: .functype all_v2i64 (v128) -> (i32){{$}} 469; SIMD128-NEXT: i64x2.all_true $push[[R:[0-9]+]]=, $0{{$}} 470; SIMD128-NEXT: return $pop[[R]]{{$}} 471declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>) 472define i32 @all_v2i64(<2 x i64> %x) { 473 %a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x) 474 ret i32 %a 475} 476 477; CHECK-LABEL: bitselect_v2i64: 478; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}} 479; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 480; SIMD128-NEXT: return $pop[[R]]{{$}} 481declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 482define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) { 483 %a = call <2 x i64> @llvm.wasm.bitselect.v2i64( 484 <2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c 485 ) 486 ret <2 x i64> %a 487} 488 489; ============================================================================== 490; 4 x f32 491; ============================================================================== 492; CHECK-LABEL: bitselect_v4f32: 493; SIMD128-NEXT: .functype bitselect_v4f32 (v128, v128, v128) -> (v128){{$}} 494; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 495; SIMD128-NEXT: return $pop[[R]]{{$}} 496declare <4 x float> @llvm.wasm.bitselect.v4f32(<4 x float>, <4 x float>, <4 x float>) 497define <4 x float> @bitselect_v4f32(<4 x float> %v1, <4 x float> %v2, <4 x float> %c) { 498 %a = call <4 x float> @llvm.wasm.bitselect.v4f32( 499 <4 x float> %v1, <4 x float> %v2, <4 x float> %c 500 ) 501 ret <4 x float> %a 502} 503 504; CHECK-LABEL: pmin_v4f32: 505; SIMD128-NEXT: .functype pmin_v4f32 (v128, v128) -> (v128){{$}} 506; SIMD128-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 507; SIMD128-NEXT: return $pop[[R]]{{$}} 508declare <4 x float> @llvm.wasm.pmin.v4f32(<4 x float>, <4 x float>) 509define <4 x float> @pmin_v4f32(<4 x float> %a, <4 x float> %b) { 510 %v = call <4 x float> @llvm.wasm.pmin.v4f32(<4 x float> %a, <4 x float> %b) 511 ret <4 x float> %v 512} 513 514; CHECK-LABEL: pmax_v4f32: 515; SIMD128-NEXT: .functype pmax_v4f32 (v128, v128) -> (v128){{$}} 516; SIMD128-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 517; SIMD128-NEXT: return $pop[[R]]{{$}} 518declare <4 x float> @llvm.wasm.pmax.v4f32(<4 x float>, <4 x float>) 519define <4 x float> @pmax_v4f32(<4 x float> %a, <4 x float> %b) { 520 %v = call <4 x float> @llvm.wasm.pmax.v4f32(<4 x float> %a, <4 x float> %b) 521 ret <4 x float> %v 522} 523 524; CHECK-LABEL: ceil_v4f32: 525; SIMD128-NEXT: .functype ceil_v4f32 (v128) -> (v128){{$}} 526; SIMD128-NEXT: f32x4.ceil $push[[R:[0-9]+]]=, $0{{$}} 527; SIMD128-NEXT: return $pop[[R]]{{$}} 528declare <4 x float> @llvm.wasm.ceil.v4f32(<4 x float>) 529define <4 x float> @ceil_v4f32(<4 x float> %a) { 530 %v = call <4 x float> @llvm.wasm.ceil.v4f32(<4 x float> %a) 531 ret <4 x float> %v 532} 533 534; CHECK-LABEL: floor_v4f32: 535; SIMD128-NEXT: .functype floor_v4f32 (v128) -> (v128){{$}} 536; SIMD128-NEXT: f32x4.floor $push[[R:[0-9]+]]=, $0{{$}} 537; SIMD128-NEXT: return $pop[[R]]{{$}} 538declare <4 x float> @llvm.wasm.floor.v4f32(<4 x float>) 539define <4 x float> @floor_v4f32(<4 x float> %a) { 540 %v = call <4 x float> @llvm.wasm.floor.v4f32(<4 x float> %a) 541 ret <4 x float> %v 542} 543 544; CHECK-LABEL: trunc_v4f32: 545; SIMD128-NEXT: .functype trunc_v4f32 (v128) -> (v128){{$}} 546; SIMD128-NEXT: f32x4.trunc $push[[R:[0-9]+]]=, $0{{$}} 547; SIMD128-NEXT: return $pop[[R]]{{$}} 548declare <4 x float> @llvm.wasm.trunc.v4f32(<4 x float>) 549define <4 x float> @trunc_v4f32(<4 x float> %a) { 550 %v = call <4 x float> @llvm.wasm.trunc.v4f32(<4 x float> %a) 551 ret <4 x float> %v 552} 553 554; CHECK-LABEL: nearest_v4f32: 555; SIMD128-NEXT: .functype nearest_v4f32 (v128) -> (v128){{$}} 556; SIMD128-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}} 557; SIMD128-NEXT: return $pop[[R]]{{$}} 558declare <4 x float> @llvm.wasm.nearest.v4f32(<4 x float>) 559define <4 x float> @nearest_v4f32(<4 x float> %a) { 560 %v = call <4 x float> @llvm.wasm.nearest.v4f32(<4 x float> %a) 561 ret <4 x float> %v 562} 563 564; CHECK-LABEL: qfma_v4f32: 565; SIMD128-NEXT: .functype qfma_v4f32 (v128, v128, v128) -> (v128){{$}} 566; SIMD128-NEXT: f32x4.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 567; SIMD128-NEXT: return $pop[[R]]{{$}} 568declare <4 x float> @llvm.wasm.qfma.v4f32(<4 x float>, <4 x float>, <4 x float>) 569define <4 x float> @qfma_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { 570 %v = call <4 x float> @llvm.wasm.qfma.v4f32( 571 <4 x float> %a, <4 x float> %b, <4 x float> %c 572 ) 573 ret <4 x float> %v 574} 575 576; CHECK-LABEL: qfms_v4f32: 577; SIMD128-NEXT: .functype qfms_v4f32 (v128, v128, v128) -> (v128){{$}} 578; SIMD128-NEXT: f32x4.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 579; SIMD128-NEXT: return $pop[[R]]{{$}} 580declare <4 x float> @llvm.wasm.qfms.v4f32(<4 x float>, <4 x float>, <4 x float>) 581define <4 x float> @qfms_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { 582 %v = call <4 x float> @llvm.wasm.qfms.v4f32( 583 <4 x float> %a, <4 x float> %b, <4 x float> %c 584 ) 585 ret <4 x float> %v 586} 587 588; ============================================================================== 589; 2 x f64 590; ============================================================================== 591; CHECK-LABEL: bitselect_v2f64: 592; SIMD128-NEXT: .functype bitselect_v2f64 (v128, v128, v128) -> (v128){{$}} 593; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 594; SIMD128-NEXT: return $pop[[R]]{{$}} 595declare <2 x double> @llvm.wasm.bitselect.v2f64(<2 x double>, <2 x double>, <2 x double>) 596define <2 x double> @bitselect_v2f64(<2 x double> %v1, <2 x double> %v2, <2 x double> %c) { 597 %a = call <2 x double> @llvm.wasm.bitselect.v2f64( 598 <2 x double> %v1, <2 x double> %v2, <2 x double> %c 599 ) 600 ret <2 x double> %a 601} 602 603; CHECK-LABEL: pmin_v2f64: 604; SIMD128-NEXT: .functype pmin_v2f64 (v128, v128) -> (v128){{$}} 605; SIMD128-NEXT: f64x2.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 606; SIMD128-NEXT: return $pop[[R]]{{$}} 607declare <2 x double> @llvm.wasm.pmin.v2f64(<2 x double>, <2 x double>) 608define <2 x double> @pmin_v2f64(<2 x double> %a, <2 x double> %b) { 609 %v = call <2 x double> @llvm.wasm.pmin.v2f64(<2 x double> %a, <2 x double> %b) 610 ret <2 x double> %v 611} 612 613; CHECK-LABEL: pmax_v2f64: 614; SIMD128-NEXT: .functype pmax_v2f64 (v128, v128) -> (v128){{$}} 615; SIMD128-NEXT: f64x2.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 616; SIMD128-NEXT: return $pop[[R]]{{$}} 617declare <2 x double> @llvm.wasm.pmax.v2f64(<2 x double>, <2 x double>) 618define <2 x double> @pmax_v2f64(<2 x double> %a, <2 x double> %b) { 619 %v = call <2 x double> @llvm.wasm.pmax.v2f64(<2 x double> %a, <2 x double> %b) 620 ret <2 x double> %v 621} 622 623; CHECK-LABEL: ceil_v2f64: 624; SIMD128-NEXT: .functype ceil_v2f64 (v128) -> (v128){{$}} 625; SIMD128-NEXT: f64x2.ceil $push[[R:[0-9]+]]=, $0{{$}} 626; SIMD128-NEXT: return $pop[[R]]{{$}} 627declare <2 x double> @llvm.wasm.ceil.v2f64(<2 x double>) 628define <2 x double> @ceil_v2f64(<2 x double> %a) { 629 %v = call <2 x double> @llvm.wasm.ceil.v2f64(<2 x double> %a) 630 ret <2 x double> %v 631} 632 633; CHECK-LABEL: floor_v2f64: 634; SIMD128-NEXT: .functype floor_v2f64 (v128) -> (v128){{$}} 635; SIMD128-NEXT: f64x2.floor $push[[R:[0-9]+]]=, $0{{$}} 636; SIMD128-NEXT: return $pop[[R]]{{$}} 637declare <2 x double> @llvm.wasm.floor.v2f64(<2 x double>) 638define <2 x double> @floor_v2f64(<2 x double> %a) { 639 %v = call <2 x double> @llvm.wasm.floor.v2f64(<2 x double> %a) 640 ret <2 x double> %v 641} 642 643; CHECK-LABEL: trunc_v2f64: 644; SIMD128-NEXT: .functype trunc_v2f64 (v128) -> (v128){{$}} 645; SIMD128-NEXT: f64x2.trunc $push[[R:[0-9]+]]=, $0{{$}} 646; SIMD128-NEXT: return $pop[[R]]{{$}} 647declare <2 x double> @llvm.wasm.trunc.v2f64(<2 x double>) 648define <2 x double> @trunc_v2f64(<2 x double> %a) { 649 %v = call <2 x double> @llvm.wasm.trunc.v2f64(<2 x double> %a) 650 ret <2 x double> %v 651} 652 653; CHECK-LABEL: nearest_v2f64: 654; SIMD128-NEXT: .functype nearest_v2f64 (v128) -> (v128){{$}} 655; SIMD128-NEXT: f64x2.nearest $push[[R:[0-9]+]]=, $0{{$}} 656; SIMD128-NEXT: return $pop[[R]]{{$}} 657declare <2 x double> @llvm.wasm.nearest.v2f64(<2 x double>) 658define <2 x double> @nearest_v2f64(<2 x double> %a) { 659 %v = call <2 x double> @llvm.wasm.nearest.v2f64(<2 x double> %a) 660 ret <2 x double> %v 661} 662 663; CHECK-LABEL: qfma_v2f64: 664; SIMD128-NEXT: .functype qfma_v2f64 (v128, v128, v128) -> (v128){{$}} 665; SIMD128-NEXT: f64x2.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 666; SIMD128-NEXT: return $pop[[R]]{{$}} 667declare <2 x double> @llvm.wasm.qfma.v2f64(<2 x double>, <2 x double>, <2 x double>) 668define <2 x double> @qfma_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { 669 %v = call <2 x double> @llvm.wasm.qfma.v2f64( 670 <2 x double> %a, <2 x double> %b, <2 x double> %c 671 ) 672 ret <2 x double> %v 673} 674 675; CHECK-LABEL: qfms_v2f64: 676; SIMD128-NEXT: .functype qfms_v2f64 (v128, v128, v128) -> (v128){{$}} 677; SIMD128-NEXT: f64x2.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 678; SIMD128-NEXT: return $pop[[R]]{{$}} 679declare <2 x double> @llvm.wasm.qfms.v2f64(<2 x double>, <2 x double>, <2 x double>) 680define <2 x double> @qfms_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) { 681 %v = call <2 x double> @llvm.wasm.qfms.v2f64( 682 <2 x double> %a, <2 x double> %b, <2 x double> %c 683 ) 684 ret <2 x double> %v 685} 686