1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -mattr=+simd128 | FileCheck %s
2
3; A regression test for a bug in the lowering of SIGN_EXTEND_INREG
4; with SIMD and without sign-ext where ISel would crash if the index
5; of the vector extract was not a constant.
6
7target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
8target triple = "wasm32"
9
10; CHECK-LABEL: foo:
11; CHECK-NEXT: .functype foo () -> (f32)
12; CHECK: i32x4.load16x4_u
13; CHECK: f32.convert_i32_s
14define float @foo() {
15  %1 = load <4 x i16>, <4 x i16>* undef, align 8
16  %2 = load i32, i32* undef, align 4
17  %vecext = extractelement <4 x i16> %1, i32 %2
18  %conv = sitofp i16 %vecext to float
19  ret float %conv
20}
21