1//===- IntrinsicsAMDGPU.td - Defines AMDGPU intrinsics -----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines all of the R600-specific intrinsics. 10// 11//===----------------------------------------------------------------------===// 12 13class AMDGPUReadPreloadRegisterIntrinsic 14 : Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 15 16class AMDGPUReadPreloadRegisterIntrinsicNamed<string name> 17 : Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable, IntrWillReturn]>, GCCBuiltin<name>; 18 19// Used to tag image and resource intrinsics with information used to generate 20// mem operands. 21class AMDGPURsrcIntrinsic<int rsrcarg, bit isimage = false> { 22 int RsrcArg = rsrcarg; 23 bit IsImage = isimage; 24} 25 26let TargetPrefix = "r600" in { 27 28multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz { 29 def _x : AMDGPUReadPreloadRegisterIntrinsic; 30 def _y : AMDGPUReadPreloadRegisterIntrinsic; 31 def _z : AMDGPUReadPreloadRegisterIntrinsic; 32} 33 34multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz_named<string prefix> { 35 def _x : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_x")>; 36 def _y : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_y")>; 37 def _z : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_z")>; 38} 39 40defm int_r600_read_global_size : AMDGPUReadPreloadRegisterIntrinsic_xyz_named 41 <"__builtin_r600_read_global_size">; 42defm int_r600_read_ngroups : AMDGPUReadPreloadRegisterIntrinsic_xyz_named 43 <"__builtin_r600_read_ngroups">; 44defm int_r600_read_tgid : AMDGPUReadPreloadRegisterIntrinsic_xyz_named 45 <"__builtin_r600_read_tgid">; 46 47defm int_r600_read_local_size : AMDGPUReadPreloadRegisterIntrinsic_xyz; 48defm int_r600_read_tidig : AMDGPUReadPreloadRegisterIntrinsic_xyz; 49 50def int_r600_group_barrier : GCCBuiltin<"__builtin_r600_group_barrier">, 51 Intrinsic<[], [], [IntrConvergent, IntrWillReturn]>; 52 53// AS 7 is PARAM_I_ADDRESS, used for kernel arguments 54def int_r600_implicitarg_ptr : 55 GCCBuiltin<"__builtin_r600_implicitarg_ptr">, 56 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 7>], [], 57 [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 58 59def int_r600_rat_store_typed : 60 // 1st parameter: Data 61 // 2nd parameter: Index 62 // 3rd parameter: Constant RAT ID 63 Intrinsic<[], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty], [IntrWillReturn]>, 64 GCCBuiltin<"__builtin_r600_rat_store_typed">; 65 66def int_r600_recipsqrt_ieee : Intrinsic< 67 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 68>; 69 70def int_r600_recipsqrt_clamped : Intrinsic< 71 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 72>; 73 74def int_r600_cube : Intrinsic< 75 [llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 76>; 77 78def int_r600_store_stream_output : Intrinsic< 79 [], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrWillReturn] 80>; 81 82class TextureIntrinsicFloatInput : Intrinsic<[llvm_v4f32_ty], [ 83 llvm_v4f32_ty, // Coord 84 llvm_i32_ty, // offset_x 85 llvm_i32_ty, // offset_y, 86 llvm_i32_ty, // offset_z, 87 llvm_i32_ty, // resource_id 88 llvm_i32_ty, // samplerid 89 llvm_i32_ty, // coord_type_x 90 llvm_i32_ty, // coord_type_y 91 llvm_i32_ty, // coord_type_z 92 llvm_i32_ty], // coord_type_w 93 [IntrNoMem, IntrWillReturn] 94>; 95 96class TextureIntrinsicInt32Input : Intrinsic<[llvm_v4i32_ty], [ 97 llvm_v4i32_ty, // Coord 98 llvm_i32_ty, // offset_x 99 llvm_i32_ty, // offset_y, 100 llvm_i32_ty, // offset_z, 101 llvm_i32_ty, // resource_id 102 llvm_i32_ty, // samplerid 103 llvm_i32_ty, // coord_type_x 104 llvm_i32_ty, // coord_type_y 105 llvm_i32_ty, // coord_type_z 106 llvm_i32_ty], // coord_type_w 107 [IntrNoMem, IntrWillReturn] 108>; 109 110def int_r600_store_swizzle : 111 Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrWillReturn] 112>; 113 114def int_r600_tex : TextureIntrinsicFloatInput; 115def int_r600_texc : TextureIntrinsicFloatInput; 116def int_r600_txl : TextureIntrinsicFloatInput; 117def int_r600_txlc : TextureIntrinsicFloatInput; 118def int_r600_txb : TextureIntrinsicFloatInput; 119def int_r600_txbc : TextureIntrinsicFloatInput; 120def int_r600_txf : TextureIntrinsicInt32Input; 121def int_r600_txq : TextureIntrinsicInt32Input; 122def int_r600_ddx : TextureIntrinsicFloatInput; 123def int_r600_ddy : TextureIntrinsicFloatInput; 124 125def int_r600_dot4 : Intrinsic<[llvm_float_ty], 126 [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 127>; 128 129def int_r600_kill : Intrinsic<[], [llvm_float_ty], [IntrWillReturn]>; 130 131} // End TargetPrefix = "r600" 132 133let TargetPrefix = "amdgcn" in { 134 135//===----------------------------------------------------------------------===// 136// ABI Special Intrinsics 137//===----------------------------------------------------------------------===// 138 139defm int_amdgcn_workitem_id : AMDGPUReadPreloadRegisterIntrinsic_xyz; 140defm int_amdgcn_workgroup_id : AMDGPUReadPreloadRegisterIntrinsic_xyz_named 141 <"__builtin_amdgcn_workgroup_id">; 142 143def int_amdgcn_dispatch_ptr : 144 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [], 145 [Align<RetIndex, 4>, IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 146 147def int_amdgcn_queue_ptr : 148 GCCBuiltin<"__builtin_amdgcn_queue_ptr">, 149 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [], 150 [Align<RetIndex, 4>, IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 151 152def int_amdgcn_kernarg_segment_ptr : 153 GCCBuiltin<"__builtin_amdgcn_kernarg_segment_ptr">, 154 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [], 155 [Align<RetIndex, 4>, IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 156 157def int_amdgcn_implicitarg_ptr : 158 GCCBuiltin<"__builtin_amdgcn_implicitarg_ptr">, 159 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [], 160 [Align<RetIndex, 4>, IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 161 162def int_amdgcn_groupstaticsize : 163 GCCBuiltin<"__builtin_amdgcn_groupstaticsize">, 164 Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 165 166def int_amdgcn_dispatch_id : 167 GCCBuiltin<"__builtin_amdgcn_dispatch_id">, 168 Intrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 169 170def int_amdgcn_implicit_buffer_ptr : 171 GCCBuiltin<"__builtin_amdgcn_implicit_buffer_ptr">, 172 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [], 173 [Align<RetIndex, 4>, IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 174 175// Set EXEC to the 64-bit value given. 176// This is always moved to the beginning of the basic block. 177// FIXME: Should be mangled for wave size. 178def int_amdgcn_init_exec : Intrinsic<[], 179 [llvm_i64_ty], // 64-bit literal constant 180 [IntrConvergent, ImmArg<ArgIndex<0>>]>; 181 182// Set EXEC according to a thread count packed in an SGPR input: 183// thread_count = (input >> bitoffset) & 0x7f; 184// This is always moved to the beginning of the basic block. 185// Note: only inreg arguments to the parent function are valid as 186// inputs to this intrinsic, computed values cannot be used. 187def int_amdgcn_init_exec_from_input : Intrinsic<[], 188 [llvm_i32_ty, // 32-bit SGPR input 189 llvm_i32_ty], // bit offset of the thread count 190 [IntrConvergent, ImmArg<ArgIndex<1>>]>; 191 192def int_amdgcn_wavefrontsize : 193 GCCBuiltin<"__builtin_amdgcn_wavefrontsize">, 194 Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 195 196 197//===----------------------------------------------------------------------===// 198// Instruction Intrinsics 199//===----------------------------------------------------------------------===// 200 201// The first parameter is s_sendmsg immediate (i16), 202// the second one is copied to m0 203def int_amdgcn_s_sendmsg : GCCBuiltin<"__builtin_amdgcn_s_sendmsg">, 204 Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], 205 [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects]>; 206def int_amdgcn_s_sendmsghalt : GCCBuiltin<"__builtin_amdgcn_s_sendmsghalt">, 207 Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], 208 [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects]>; 209 210def int_amdgcn_s_barrier : GCCBuiltin<"__builtin_amdgcn_s_barrier">, 211 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrConvergent, IntrWillReturn]>; 212 213def int_amdgcn_wave_barrier : GCCBuiltin<"__builtin_amdgcn_wave_barrier">, 214 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrConvergent, IntrWillReturn]>; 215 216def int_amdgcn_s_waitcnt : GCCBuiltin<"__builtin_amdgcn_s_waitcnt">, 217 Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 218 219def int_amdgcn_div_scale : Intrinsic< 220 // 1st parameter: Numerator 221 // 2nd parameter: Denominator 222 // 3rd parameter: Select quotient. Must equal Numerator or Denominator. 223 // (0 = Denominator, 1 = Numerator). 224 [llvm_anyfloat_ty, llvm_i1_ty], 225 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty], 226 [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>, IntrWillReturn] 227>; 228 229def int_amdgcn_div_fmas : Intrinsic<[llvm_anyfloat_ty], 230 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty], 231 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 232>; 233 234def int_amdgcn_div_fixup : Intrinsic<[llvm_anyfloat_ty], 235 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 236 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 237>; 238 239// Look Up 2.0 / pi src0 with segment select src1[4:0] 240def int_amdgcn_trig_preop : Intrinsic< 241 [llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], 242 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 243>; 244 245def int_amdgcn_sin : Intrinsic< 246 [llvm_anyfloat_ty], [LLVMMatchType<0>], 247 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 248>; 249 250def int_amdgcn_cos : Intrinsic< 251 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 252>; 253 254def int_amdgcn_log_clamp : Intrinsic< 255 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 256>; 257 258def int_amdgcn_fmul_legacy : GCCBuiltin<"__builtin_amdgcn_fmul_legacy">, 259 Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], 260 [IntrNoMem, IntrSpeculatable, IntrWillReturn, Commutative] 261>; 262 263// Fused single-precision multiply-add with legacy behaviour for the multiply, 264// which is that +/- 0.0 * anything (even NaN or infinity) is +0.0. This is 265// intended for use on subtargets that have the v_fma_legacy_f32 and/or 266// v_fmac_legacy_f32 instructions. (Note that v_fma_legacy_f16 is unrelated and 267// has a completely different kind of legacy behaviour.) 268def int_amdgcn_fma_legacy : 269 Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], 270 [IntrNoMem, IntrSpeculatable, IntrWillReturn, Commutative] 271>; 272 273def int_amdgcn_rcp : Intrinsic< 274 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 275>; 276 277def int_amdgcn_rcp_legacy : GCCBuiltin<"__builtin_amdgcn_rcp_legacy">, 278 Intrinsic<[llvm_float_ty], [llvm_float_ty], 279 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 280>; 281 282def int_amdgcn_sqrt : Intrinsic< 283 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 284>; 285 286def int_amdgcn_rsq : Intrinsic< 287 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 288>; 289 290def int_amdgcn_rsq_legacy : GCCBuiltin<"__builtin_amdgcn_rsq_legacy">, 291 Intrinsic< 292 [llvm_float_ty], [llvm_float_ty], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 293>; 294 295// out = 1.0 / sqrt(a) result clamped to +/- max_float. 296def int_amdgcn_rsq_clamp : Intrinsic< 297 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 298 299def int_amdgcn_ldexp : Intrinsic< 300 [llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], 301 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 302>; 303 304def int_amdgcn_frexp_mant : Intrinsic< 305 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 306>; 307 308def int_amdgcn_frexp_exp : Intrinsic< 309 [llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 310>; 311 312// v_fract is buggy on SI/CI. It mishandles infinities, may return 1.0 313// and always uses rtz, so is not suitable for implementing the OpenCL 314// fract function. It should be ok on VI. 315def int_amdgcn_fract : Intrinsic< 316 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 317>; 318 319def int_amdgcn_cvt_pkrtz : GCCBuiltin<"__builtin_amdgcn_cvt_pkrtz">, 320 Intrinsic<[llvm_v2f16_ty], [llvm_float_ty, llvm_float_ty], 321 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 322>; 323 324def int_amdgcn_cvt_pknorm_i16 : 325 GCCBuiltin<"__builtin_amdgcn_cvt_pknorm_i16">, 326 Intrinsic<[llvm_v2i16_ty], [llvm_float_ty, llvm_float_ty], 327 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 328>; 329 330def int_amdgcn_cvt_pknorm_u16 : 331 GCCBuiltin<"__builtin_amdgcn_cvt_pknorm_u16">, 332 Intrinsic<[llvm_v2i16_ty], [llvm_float_ty, llvm_float_ty], 333 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 334>; 335 336def int_amdgcn_cvt_pk_i16 : 337 GCCBuiltin<"__builtin_amdgcn_cvt_pk_i16">, 338 Intrinsic< 339 [llvm_v2i16_ty], [llvm_i32_ty, llvm_i32_ty], 340 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 341>; 342 343def int_amdgcn_cvt_pk_u16 : GCCBuiltin<"__builtin_amdgcn_cvt_pk_u16">, 344 Intrinsic<[llvm_v2i16_ty], [llvm_i32_ty, llvm_i32_ty], 345 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 346>; 347 348def int_amdgcn_class : Intrinsic< 349 [llvm_i1_ty], [llvm_anyfloat_ty, llvm_i32_ty], 350 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 351>; 352 353def int_amdgcn_fmed3 : GCCBuiltin<"__builtin_amdgcn_fmed3">, 354 Intrinsic<[llvm_anyfloat_ty], 355 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 356 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 357>; 358 359def int_amdgcn_cubeid : GCCBuiltin<"__builtin_amdgcn_cubeid">, 360 Intrinsic<[llvm_float_ty], 361 [llvm_float_ty, llvm_float_ty, llvm_float_ty], 362 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 363>; 364 365def int_amdgcn_cubema : GCCBuiltin<"__builtin_amdgcn_cubema">, 366 Intrinsic<[llvm_float_ty], 367 [llvm_float_ty, llvm_float_ty, llvm_float_ty], 368 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 369>; 370 371def int_amdgcn_cubesc : GCCBuiltin<"__builtin_amdgcn_cubesc">, 372 Intrinsic<[llvm_float_ty], 373 [llvm_float_ty, llvm_float_ty, llvm_float_ty], 374 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 375>; 376 377def int_amdgcn_cubetc : GCCBuiltin<"__builtin_amdgcn_cubetc">, 378 Intrinsic<[llvm_float_ty], 379 [llvm_float_ty, llvm_float_ty, llvm_float_ty], 380 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 381>; 382 383// v_ffbh_i32, as opposed to v_ffbh_u32. For v_ffbh_u32, llvm.ctlz 384// should be used. 385def int_amdgcn_sffbh : 386 Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], 387 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 388>; 389 390// v_mad_f32|f16/v_mac_f32|f16, selected regardless of denorm support. 391def int_amdgcn_fmad_ftz : 392 Intrinsic<[llvm_anyfloat_ty], 393 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 394 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 395>; 396 397// Fields should mirror atomicrmw 398class AMDGPUAtomicIncIntrin : Intrinsic<[llvm_anyint_ty], 399 [llvm_anyptr_ty, 400 LLVMMatchType<0>, 401 llvm_i32_ty, // ordering 402 llvm_i32_ty, // scope 403 llvm_i1_ty], // isVolatile 404 [IntrArgMemOnly, IntrWillReturn, NoCapture<ArgIndex<0>>, 405 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>], "", 406 [SDNPMemOperand] 407>; 408 409def int_amdgcn_atomic_inc : AMDGPUAtomicIncIntrin; 410def int_amdgcn_atomic_dec : AMDGPUAtomicIncIntrin; 411 412class AMDGPULDSIntrin : 413 Intrinsic<[llvm_any_ty], 414 [LLVMQualPointerType<LLVMMatchType<0>, 3>, 415 LLVMMatchType<0>, 416 llvm_i32_ty, // ordering 417 llvm_i32_ty, // scope 418 llvm_i1_ty], // isVolatile 419 [IntrArgMemOnly, IntrWillReturn, NoCapture<ArgIndex<0>>, 420 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>] 421>; 422 423// FIXME: The m0 argument should be moved after the normal arguments 424class AMDGPUDSOrderedIntrinsic : Intrinsic< 425 [llvm_i32_ty], 426 // M0 = {hi16:address, lo16:waveID}. Allow passing M0 as a pointer, so that 427 // the bit packing can be optimized at the IR level. 428 [LLVMQualPointerType<llvm_i32_ty, 2>, // IntToPtr(M0) 429 llvm_i32_ty, // value to add or swap 430 llvm_i32_ty, // ordering 431 llvm_i32_ty, // scope 432 llvm_i1_ty, // isVolatile 433 llvm_i32_ty, // ordered count index (OA index), also added to the address 434 // gfx10: bits 24-27 indicate the number of active threads/dwords 435 llvm_i1_ty, // wave release, usually set to 1 436 llvm_i1_ty], // wave done, set to 1 for the last ordered instruction 437 [IntrWillReturn, NoCapture<ArgIndex<0>>, 438 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, 439 ImmArg<ArgIndex<5>>, ImmArg<ArgIndex<6>>, ImmArg<ArgIndex<7>> 440 ] 441>; 442 443class AMDGPUDSAppendConsumedIntrinsic : Intrinsic< 444 [llvm_i32_ty], 445 [llvm_anyptr_ty, // LDS or GDS ptr 446 llvm_i1_ty], // isVolatile 447 [IntrConvergent, IntrWillReturn, IntrArgMemOnly, 448 NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<1>>], 449 "", 450 [SDNPMemOperand] 451>; 452 453def int_amdgcn_ds_ordered_add : AMDGPUDSOrderedIntrinsic; 454def int_amdgcn_ds_ordered_swap : AMDGPUDSOrderedIntrinsic; 455 456// The pointer argument is assumed to be dynamically uniform if a VGPR. 457def int_amdgcn_ds_append : AMDGPUDSAppendConsumedIntrinsic; 458def int_amdgcn_ds_consume : AMDGPUDSAppendConsumedIntrinsic; 459 460def int_amdgcn_ds_fadd : AMDGPULDSIntrin; 461def int_amdgcn_ds_fmin : AMDGPULDSIntrin; 462def int_amdgcn_ds_fmax : AMDGPULDSIntrin; 463 464} // TargetPrefix = "amdgcn" 465 466// New-style image intrinsics 467 468////////////////////////////////////////////////////////////////////////// 469// Dimension-aware image intrinsics framework 470////////////////////////////////////////////////////////////////////////// 471 472// Helper class to represent (type, name) combinations of arguments. The 473// argument names are explanatory and used as DAG operand names for codegen 474// pattern matching. 475class AMDGPUArg<LLVMType ty, string name> { 476 LLVMType Type = ty; 477 string Name = name; 478} 479 480// Return [AMDGPUArg<basety, names[0]>, AMDGPUArg<LLVMMatchType<0>, names[1]>, ...] 481class makeArgList<list<string> names, LLVMType basety> { 482 list<AMDGPUArg> ret = 483 !listconcat([AMDGPUArg<basety, names[0]>], 484 !foreach(name, !tail(names), AMDGPUArg<LLVMMatchType<0>, name>)); 485} 486 487// Return arglist, with LLVMMatchType's references shifted by 'shift'. 488class arglistmatchshift<list<AMDGPUArg> arglist, int shift> { 489 list<AMDGPUArg> ret = 490 !foreach(arg, arglist, 491 !if(!isa<LLVMMatchType>(arg.Type), 492 AMDGPUArg<LLVMMatchType<!add(!cast<LLVMMatchType>(arg.Type).Number, shift)>, 493 arg.Name>, 494 arg)); 495} 496 497// Return the concatenation of the given arglists. LLVMMatchType's are adjusted 498// accordingly, and shifted by an additional 'shift'. 499class arglistconcat<list<list<AMDGPUArg>> arglists, int shift = 0> { 500 list<AMDGPUArg> ret = 501 !foldl([]<AMDGPUArg>, arglists, lhs, rhs, 502 !listconcat( 503 lhs, 504 arglistmatchshift<rhs, 505 !add(shift, !foldl(0, lhs, a, b, 506 !add(a, b.Type.isAny)))>.ret)); 507} 508 509// Represent texture/image types / dimensionality. 510class AMDGPUDimProps<bits<3> enc, string name, string asmsuffix, 511 list<string> coord_names, list<string> slice_names, 512 bit msaa = 0> { 513 AMDGPUDimProps Dim = !cast<AMDGPUDimProps>(NAME); 514 string Name = name; // e.g. "2darraymsaa" 515 string AsmSuffix = asmsuffix; // e.g. 2D_MSAA_ARRAY (used in assembly strings) 516 bits<3> Encoding = enc; 517 bit DA = 0; // DA bit in MIMG encoding 518 bit MSAA = msaa; 519 520 list<AMDGPUArg> CoordSliceArgs = 521 makeArgList<!listconcat(coord_names, slice_names), llvm_anyfloat_ty>.ret; 522 list<AMDGPUArg> CoordSliceIntArgs = 523 makeArgList<!listconcat(coord_names, slice_names), llvm_anyint_ty>.ret; 524 list<AMDGPUArg> GradientArgs = 525 makeArgList<!listconcat(!foreach(name, coord_names, "d" # name # "dh"), 526 !foreach(name, coord_names, "d" # name # "dv")), 527 llvm_anyfloat_ty>.ret; 528 529 bits<8> NumCoords = !size(CoordSliceArgs); 530 bits<8> NumGradients = !size(GradientArgs); 531} 532 533def AMDGPUDim1D : AMDGPUDimProps<0x0, "1d", "1D", ["s"], []>; 534def AMDGPUDim2D : AMDGPUDimProps<0x1, "2d", "2D", ["s", "t"], []>; 535def AMDGPUDim3D : AMDGPUDimProps<0x2, "3d", "3D", ["s", "t", "r"], []>; 536let DA = 1 in { 537 def AMDGPUDimCube : AMDGPUDimProps<0x3, "cube", "CUBE", ["s", "t"], ["face"]>; 538 def AMDGPUDim1DArray : AMDGPUDimProps<0x4, "1darray", "1D_ARRAY", ["s"], ["slice"]>; 539 def AMDGPUDim2DArray : AMDGPUDimProps<0x5, "2darray", "2D_ARRAY", ["s", "t"], ["slice"]>; 540} 541def AMDGPUDim2DMsaa : AMDGPUDimProps<0x6, "2dmsaa", "2D_MSAA", ["s", "t"], ["fragid"], 1>; 542let DA = 1 in { 543 def AMDGPUDim2DArrayMsaa : AMDGPUDimProps<0x7, "2darraymsaa", "2D_MSAA_ARRAY", ["s", "t"], ["slice", "fragid"], 1>; 544} 545 546def AMDGPUDims { 547 list<AMDGPUDimProps> NoMsaa = [AMDGPUDim1D, AMDGPUDim2D, AMDGPUDim3D, 548 AMDGPUDimCube, AMDGPUDim1DArray, 549 AMDGPUDim2DArray]; 550 list<AMDGPUDimProps> Msaa = [AMDGPUDim2DMsaa, AMDGPUDim2DArrayMsaa]; 551 list<AMDGPUDimProps> All = !listconcat(NoMsaa, Msaa); 552} 553 554// Represent sample variants, i.e. _C, _O, _B, ... and combinations thereof. 555class AMDGPUSampleVariant<string ucmod, string lcmod, list<AMDGPUArg> extra_addr> { 556 string UpperCaseMod = ucmod; 557 string LowerCaseMod = lcmod; 558 559 // {offset} {bias} {z-compare} 560 list<AMDGPUArg> ExtraAddrArgs = extra_addr; 561 bit Gradients = false; 562 563 // Name of the {lod} or {clamp} argument that is appended to the coordinates, 564 // if any. 565 string LodOrClamp = ""; 566} 567 568// AMDGPUSampleVariants: all variants supported by IMAGE_SAMPLE 569// AMDGPUSampleVariantsNoGradients: variants supported by IMAGE_GATHER4 570defset list<AMDGPUSampleVariant> AMDGPUSampleVariants = { 571 multiclass AMDGPUSampleHelper_Offset<string ucmod, string lcmod, 572 list<AMDGPUArg> extra_addr> { 573 def NAME#lcmod : AMDGPUSampleVariant<ucmod, lcmod, extra_addr>; 574 def NAME#lcmod#_o : AMDGPUSampleVariant< 575 ucmod#"_O", lcmod#"_o", !listconcat([AMDGPUArg<llvm_i32_ty, "offset">], extra_addr)>; 576 } 577 578 multiclass AMDGPUSampleHelper_Compare<string ucmod, string lcmod, 579 list<AMDGPUArg> extra_addr> { 580 defm NAME : AMDGPUSampleHelper_Offset<ucmod, lcmod, extra_addr>; 581 defm NAME : AMDGPUSampleHelper_Offset< 582 "_C"#ucmod, "_c"#lcmod, !listconcat(extra_addr, [AMDGPUArg<llvm_float_ty, "zcompare">])>; 583 } 584 585 multiclass AMDGPUSampleHelper_Clamp<string ucmod, string lcmod, 586 list<AMDGPUArg> extra_addr> { 587 defm NAME : AMDGPUSampleHelper_Compare<ucmod, lcmod, extra_addr>; 588 let LodOrClamp = "clamp" in 589 defm NAME : AMDGPUSampleHelper_Compare<ucmod#"_CL", lcmod#"_cl", extra_addr>; 590 } 591 592 defset list<AMDGPUSampleVariant> AMDGPUSampleVariantsNoGradients = { 593 defm AMDGPUSample : AMDGPUSampleHelper_Clamp<"", "", []>; 594 defm AMDGPUSample : AMDGPUSampleHelper_Clamp< 595 "_B", "_b", [AMDGPUArg<llvm_anyfloat_ty, "bias">]>; 596 let LodOrClamp = "lod" in 597 defm AMDGPUSample : AMDGPUSampleHelper_Compare<"_L", "_l", []>; 598 defm AMDGPUSample : AMDGPUSampleHelper_Compare<"_LZ", "_lz", []>; 599 } 600 601 let Gradients = true in { 602 defm AMDGPUSample : AMDGPUSampleHelper_Clamp<"_D", "_d", []>; 603 defm AMDGPUSample : AMDGPUSampleHelper_Clamp<"_CD", "_cd", []>; 604 } 605} 606 607// Helper class to capture the profile of a dimension-aware image intrinsic. 608// This information is used to generate the intrinsic's type and to inform 609// codegen pattern matching. 610class AMDGPUDimProfile<string opmod, 611 AMDGPUDimProps dim> { 612 AMDGPUDimProps Dim = dim; 613 string OpMod = opmod; // the corresponding instruction is named IMAGE_OpMod 614 615 // These are intended to be overwritten by subclasses 616 bit IsSample = false; 617 bit IsAtomic = false; 618 list<LLVMType> RetTypes = []; 619 list<AMDGPUArg> DataArgs = []; 620 list<AMDGPUArg> ExtraAddrArgs = []; 621 bit Gradients = false; 622 string LodClampMip = ""; 623 624 int NumRetAndDataAnyTypes = 625 !foldl(0, !listconcat(RetTypes, !foreach(arg, DataArgs, arg.Type)), a, b, 626 !add(a, b.isAny)); 627 628 list<AMDGPUArg> AddrArgs = 629 arglistconcat<[ExtraAddrArgs, 630 !if(Gradients, dim.GradientArgs, []), 631 !listconcat(!if(IsSample, dim.CoordSliceArgs, dim.CoordSliceIntArgs), 632 !if(!empty(LodClampMip), 633 []<AMDGPUArg>, 634 [AMDGPUArg<LLVMMatchType<0>, LodClampMip>]))], 635 NumRetAndDataAnyTypes>.ret; 636 list<LLVMType> AddrTypes = !foreach(arg, AddrArgs, arg.Type); 637 list<AMDGPUArg> AddrDefaultArgs = 638 !foreach(arg, AddrArgs, 639 AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), 640 !if(IsSample, llvm_float_ty, llvm_i32_ty), arg.Type), 641 arg.Name>); 642 list<AMDGPUArg> AddrA16Args = 643 !foreach(arg, AddrArgs, 644 AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)), 645 !if(IsSample, llvm_half_ty, llvm_i16_ty), arg.Type), 646 arg.Name>); 647} 648 649class AMDGPUDimProfileCopy<AMDGPUDimProfile base> : AMDGPUDimProfile<base.OpMod, base.Dim> { 650 let IsSample = base.IsSample; 651 let IsAtomic = base.IsAtomic; 652 let RetTypes = base.RetTypes; 653 let DataArgs = base.DataArgs; 654 let ExtraAddrArgs = base.ExtraAddrArgs; 655 let Gradients = base.Gradients; 656 let LodClampMip = base.LodClampMip; 657} 658 659class AMDGPUDimSampleProfile<string opmod, 660 AMDGPUDimProps dim, 661 AMDGPUSampleVariant sample> : AMDGPUDimProfile<opmod, dim> { 662 let IsSample = true; 663 let RetTypes = [llvm_any_ty]; 664 let ExtraAddrArgs = sample.ExtraAddrArgs; 665 let Gradients = sample.Gradients; 666 let LodClampMip = sample.LodOrClamp; 667} 668 669class AMDGPUDimNoSampleProfile<string opmod, 670 AMDGPUDimProps dim, 671 list<LLVMType> retty, 672 list<AMDGPUArg> dataargs, 673 bit Mip = false> : AMDGPUDimProfile<opmod, dim> { 674 let RetTypes = retty; 675 let DataArgs = dataargs; 676 let LodClampMip = !if(Mip, "mip", ""); 677} 678 679class AMDGPUDimAtomicProfile<string opmod, 680 AMDGPUDimProps dim, 681 list<AMDGPUArg> dataargs> : AMDGPUDimProfile<opmod, dim> { 682 let RetTypes = [llvm_anyint_ty]; 683 let DataArgs = dataargs; 684 let IsAtomic = true; 685} 686 687class AMDGPUDimAtomicFloatProfile<string opmod, AMDGPUDimProps dim, 688 list<AMDGPUArg> dataargs> 689 : AMDGPUDimAtomicProfile<opmod, dim, dataargs> { 690 let RetTypes = [llvm_anyfloat_ty]; 691} 692 693class AMDGPUDimGetResInfoProfile<AMDGPUDimProps dim> 694 : AMDGPUDimProfile<"GET_RESINFO", dim> { 695 let RetTypes = [llvm_anyfloat_ty]; 696 let DataArgs = []; 697 let AddrArgs = [AMDGPUArg<llvm_anyint_ty, "mip">]; 698 let LodClampMip = "mip"; 699} 700 701// Helper class for figuring out image intrinsic argument indexes. 702class AMDGPUImageDimIntrinsicEval<AMDGPUDimProfile P_> { 703 int NumDataArgs = !size(P_.DataArgs); 704 int NumDmaskArgs = !not(P_.IsAtomic); 705 int NumExtraAddrArgs = !size(P_.ExtraAddrArgs); 706 int NumVAddrArgs = !size(P_.AddrArgs); 707 int NumGradientArgs = !if(P_.Gradients, !size(P_.Dim.GradientArgs), 0); 708 int NumCoordArgs = !if(P_.IsSample, !size(P_.Dim.CoordSliceArgs), !size(P_.Dim.CoordSliceIntArgs)); 709 int NumRSrcArgs = 1; 710 int NumSampArgs = !if(P_.IsSample, 2, 0); 711 int DmaskArgIndex = NumDataArgs; 712 int VAddrArgIndex = !add(DmaskArgIndex, NumDmaskArgs); 713 int GradientArgIndex = !add(VAddrArgIndex, NumExtraAddrArgs); 714 int CoordArgIndex = !add(GradientArgIndex, NumGradientArgs); 715 int LodArgIndex = !add(VAddrArgIndex, NumVAddrArgs, -1); 716 int MipArgIndex = LodArgIndex; 717 int RsrcArgIndex = !add(VAddrArgIndex, NumVAddrArgs); 718 int SampArgIndex = !add(RsrcArgIndex, NumRSrcArgs); 719 int UnormArgIndex = !add(SampArgIndex, 1); 720 int TexFailCtrlArgIndex = !add(SampArgIndex, NumSampArgs); 721 int CachePolicyArgIndex = !add(TexFailCtrlArgIndex, 1); 722} 723 724// All dimension-aware intrinsics are derived from this class. 725class AMDGPUImageDimIntrinsic<AMDGPUDimProfile P_, 726 list<IntrinsicProperty> props, 727 list<SDNodeProperty> sdnodeprops> : Intrinsic< 728 P_.RetTypes, // vdata(VGPR) -- for load/atomic-with-return 729 !listconcat( 730 !foreach(arg, P_.DataArgs, arg.Type), // vdata(VGPR) -- for store/atomic 731 !if(P_.IsAtomic, [], [llvm_i32_ty]), // dmask(imm) 732 P_.AddrTypes, // vaddr(VGPR) 733 [llvm_v8i32_ty], // rsrc(SGPR) 734 !if(P_.IsSample, [llvm_v4i32_ty, // samp(SGPR) 735 llvm_i1_ty], []), // unorm(imm) 736 [llvm_i32_ty, // texfailctrl(imm; bit 0 = tfe, bit 1 = lwe) 737 llvm_i32_ty]), // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc) 738 739 !listconcat(props, 740 !if(P_.IsAtomic, [], [ImmArg<ArgIndex<AMDGPUImageDimIntrinsicEval<P_>.DmaskArgIndex>>]), 741 !if(P_.IsSample, [ImmArg<ArgIndex<AMDGPUImageDimIntrinsicEval<P_>.UnormArgIndex>>], []), 742 [IntrWillReturn], 743 [ImmArg<ArgIndex<AMDGPUImageDimIntrinsicEval<P_>.TexFailCtrlArgIndex>>, 744 ImmArg<ArgIndex<AMDGPUImageDimIntrinsicEval<P_>.CachePolicyArgIndex>>]), 745 746 747 "", sdnodeprops>, 748 AMDGPURsrcIntrinsic<!add(!size(P_.DataArgs), !size(P_.AddrTypes), 749 !if(P_.IsAtomic, 0, 1)), 1> { 750 AMDGPUDimProfile P = P_; 751 752 AMDGPUImageDimIntrinsic Intr = !cast<AMDGPUImageDimIntrinsic>(NAME); 753 754 let TargetPrefix = "amdgcn"; 755} 756 757// Marker class for intrinsics with a DMask that determines the returned 758// channels. 759class AMDGPUImageDMaskIntrinsic; 760 761defset list<AMDGPUImageDimIntrinsic> AMDGPUImageDimIntrinsics = { 762 763 ////////////////////////////////////////////////////////////////////////// 764 // Load and store intrinsics 765 ////////////////////////////////////////////////////////////////////////// 766 multiclass AMDGPUImageDimIntrinsicsNoMsaa<string opmod, 767 list<LLVMType> retty, 768 list<AMDGPUArg> dataargs, 769 list<IntrinsicProperty> props, 770 list<SDNodeProperty> sdnodeprops, 771 bit Mip = false> { 772 foreach dim = AMDGPUDims.NoMsaa in { 773 def !strconcat(NAME, "_", dim.Name) 774 : AMDGPUImageDimIntrinsic< 775 AMDGPUDimNoSampleProfile<opmod, dim, retty, dataargs, Mip>, 776 props, sdnodeprops>; 777 } 778 } 779 780 multiclass AMDGPUImageDimIntrinsicsAll<string opmod, 781 list<LLVMType> retty, 782 list<AMDGPUArg> dataargs, 783 list<IntrinsicProperty> props, 784 list<SDNodeProperty> sdnodeprops, 785 bit Mip = false> { 786 foreach dim = AMDGPUDims.All in { 787 def !strconcat(NAME, "_", dim.Name) 788 : AMDGPUImageDimIntrinsic< 789 AMDGPUDimNoSampleProfile<opmod, dim, retty, dataargs, Mip>, 790 props, sdnodeprops>; 791 } 792 } 793 794 defm int_amdgcn_image_load 795 : AMDGPUImageDimIntrinsicsAll<"LOAD", [llvm_any_ty], [], [IntrReadMem], 796 [SDNPMemOperand]>, 797 AMDGPUImageDMaskIntrinsic; 798 defm int_amdgcn_image_load_mip 799 : AMDGPUImageDimIntrinsicsNoMsaa<"LOAD_MIP", [llvm_any_ty], [], 800 [IntrReadMem, IntrWillReturn], [SDNPMemOperand], 1>, 801 AMDGPUImageDMaskIntrinsic; 802 803 defm int_amdgcn_image_store : AMDGPUImageDimIntrinsicsAll< 804 "STORE", [], [AMDGPUArg<llvm_anyfloat_ty, "vdata">], 805 [IntrWriteMem, IntrWillReturn], [SDNPMemOperand]>; 806 defm int_amdgcn_image_store_mip : AMDGPUImageDimIntrinsicsNoMsaa< 807 "STORE_MIP", [], [AMDGPUArg<llvm_anyfloat_ty, "vdata">], 808 [IntrWriteMem, IntrWillReturn], [SDNPMemOperand], 1>; 809 810 ////////////////////////////////////////////////////////////////////////// 811 // MSAA intrinsics 812 ////////////////////////////////////////////////////////////////////////// 813 foreach dim = AMDGPUDims.Msaa in { 814 def int_amdgcn_image_msaa_load_x # _ # dim.Name: 815 AMDGPUImageDimIntrinsic< 816 AMDGPUDimNoSampleProfile<"MSAA_LOAD_X", dim, [llvm_any_ty], []>, 817 [IntrReadMem], [SDNPMemOperand]>; 818 } 819 820 ////////////////////////////////////////////////////////////////////////// 821 // sample and getlod intrinsics 822 ////////////////////////////////////////////////////////////////////////// 823 multiclass AMDGPUImageDimSampleDims<string opmod, 824 AMDGPUSampleVariant sample, 825 bit NoMem = false> { 826 foreach dim = AMDGPUDims.NoMsaa in { 827 def !strconcat(NAME, "_", dim.Name) : AMDGPUImageDimIntrinsic< 828 AMDGPUDimSampleProfile<opmod, dim, sample>, 829 !if(NoMem, [IntrNoMem], [IntrReadMem]), 830 !if(NoMem, [], [SDNPMemOperand])>; 831 } 832 } 833 834 foreach sample = AMDGPUSampleVariants in { 835 defm int_amdgcn_image_sample # sample.LowerCaseMod 836 : AMDGPUImageDimSampleDims<"SAMPLE" # sample.UpperCaseMod, sample>, 837 AMDGPUImageDMaskIntrinsic; 838 } 839 840 defm int_amdgcn_image_getlod 841 : AMDGPUImageDimSampleDims<"GET_LOD", AMDGPUSample, 1>, 842 AMDGPUImageDMaskIntrinsic; 843 844 ////////////////////////////////////////////////////////////////////////// 845 // getresinfo intrinsics 846 ////////////////////////////////////////////////////////////////////////// 847 foreach dim = AMDGPUDims.All in { 848 def !strconcat("int_amdgcn_image_getresinfo_", dim.Name) 849 : AMDGPUImageDimIntrinsic<AMDGPUDimGetResInfoProfile<dim>, [IntrNoMem], []>, 850 AMDGPUImageDMaskIntrinsic; 851 } 852 853 ////////////////////////////////////////////////////////////////////////// 854 // gather4 intrinsics 855 ////////////////////////////////////////////////////////////////////////// 856 foreach sample = AMDGPUSampleVariantsNoGradients in { 857 foreach dim = [AMDGPUDim2D, AMDGPUDimCube, AMDGPUDim2DArray] in { 858 def int_amdgcn_image_gather4 # sample.LowerCaseMod # _ # dim.Name: 859 AMDGPUImageDimIntrinsic< 860 AMDGPUDimSampleProfile<"GATHER4" # sample.UpperCaseMod, dim, sample>, 861 [IntrReadMem], [SDNPMemOperand]>; 862 } 863 } 864} 865 866////////////////////////////////////////////////////////////////////////// 867// atomic intrinsics 868////////////////////////////////////////////////////////////////////////// 869defset list<AMDGPUImageDimIntrinsic> AMDGPUImageDimAtomicIntrinsics = { 870 multiclass AMDGPUImageDimAtomicX<string opmod, list<AMDGPUArg> dataargs, 871 int isFloat = 0> { 872 foreach dim = AMDGPUDims.All in { 873 def !strconcat(NAME, "_", dim.Name): AMDGPUImageDimIntrinsic< 874 !if (isFloat, AMDGPUDimAtomicFloatProfile<opmod, dim, dataargs>, 875 AMDGPUDimAtomicProfile<opmod, dim, dataargs>), 876 [], [SDNPMemOperand]>; 877 } 878 } 879 880 multiclass AMDGPUImageDimAtomic<string opmod, int isFloat = 0> { 881 defm "" 882 : AMDGPUImageDimAtomicX<opmod, [AMDGPUArg<LLVMMatchType<0>, "vdata">], 883 isFloat>; 884 } 885 886 multiclass AMDGPUImageDimFloatAtomic<string opmod> { 887 defm "" : AMDGPUImageDimAtomic<opmod, 1 /*isFloat*/>; 888 } 889 890 defm int_amdgcn_image_atomic_swap : AMDGPUImageDimAtomic<"ATOMIC_SWAP">; 891 defm int_amdgcn_image_atomic_add : AMDGPUImageDimAtomic<"ATOMIC_ADD">; 892 defm int_amdgcn_image_atomic_sub : AMDGPUImageDimAtomic<"ATOMIC_SUB">; 893 defm int_amdgcn_image_atomic_smin : AMDGPUImageDimAtomic<"ATOMIC_SMIN">; 894 defm int_amdgcn_image_atomic_umin : AMDGPUImageDimAtomic<"ATOMIC_UMIN">; 895 defm int_amdgcn_image_atomic_fmin : AMDGPUImageDimFloatAtomic<"ATOMIC_FMIN">; 896 defm int_amdgcn_image_atomic_smax : AMDGPUImageDimAtomic<"ATOMIC_SMAX">; 897 defm int_amdgcn_image_atomic_umax : AMDGPUImageDimAtomic<"ATOMIC_UMAX">; 898 defm int_amdgcn_image_atomic_fmax : AMDGPUImageDimFloatAtomic<"ATOMIC_FMAX">; 899 defm int_amdgcn_image_atomic_and : AMDGPUImageDimAtomic<"ATOMIC_AND">; 900 defm int_amdgcn_image_atomic_or : AMDGPUImageDimAtomic<"ATOMIC_OR">; 901 defm int_amdgcn_image_atomic_xor : AMDGPUImageDimAtomic<"ATOMIC_XOR">; 902 defm int_amdgcn_image_atomic_inc : AMDGPUImageDimAtomic<"ATOMIC_INC">; 903 defm int_amdgcn_image_atomic_dec : AMDGPUImageDimAtomic<"ATOMIC_DEC">; 904 905 defm int_amdgcn_image_atomic_cmpswap : 906 AMDGPUImageDimAtomicX<"ATOMIC_CMPSWAP", [AMDGPUArg<LLVMMatchType<0>, "src">, 907 AMDGPUArg<LLVMMatchType<0>, "cmp">]>; 908} 909 910////////////////////////////////////////////////////////////////////////// 911// Buffer intrinsics 912////////////////////////////////////////////////////////////////////////// 913 914let TargetPrefix = "amdgcn" in { 915 916defset list<AMDGPURsrcIntrinsic> AMDGPUBufferIntrinsics = { 917 918class AMDGPUBufferLoad<LLVMType data_ty = llvm_any_ty> : Intrinsic < 919 [data_ty], 920 [llvm_v4i32_ty, // rsrc(SGPR) 921 llvm_i32_ty, // vindex(VGPR) 922 llvm_i32_ty, // offset(SGPR/VGPR/imm) 923 llvm_i1_ty, // glc(imm) 924 llvm_i1_ty], // slc(imm) 925 [IntrReadMem, IntrWillReturn, 926 ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>, 927 AMDGPURsrcIntrinsic<0>; 928def int_amdgcn_buffer_load_format : AMDGPUBufferLoad<llvm_anyfloat_ty>; 929def int_amdgcn_buffer_load : AMDGPUBufferLoad; 930 931def int_amdgcn_s_buffer_load : Intrinsic < 932 [llvm_any_ty], 933 [llvm_v4i32_ty, // rsrc(SGPR) 934 llvm_i32_ty, // byte offset(SGPR/imm) 935 llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 2 = dlc) 936 [IntrNoMem, IntrWillReturn, ImmArg<ArgIndex<2>>]>, 937 AMDGPURsrcIntrinsic<0>; 938 939class AMDGPUBufferStore<LLVMType data_ty = llvm_any_ty> : Intrinsic < 940 [], 941 [data_ty, // vdata(VGPR) 942 llvm_v4i32_ty, // rsrc(SGPR) 943 llvm_i32_ty, // vindex(VGPR) 944 llvm_i32_ty, // offset(SGPR/VGPR/imm) 945 llvm_i1_ty, // glc(imm) 946 llvm_i1_ty], // slc(imm) 947 [IntrWriteMem, IntrWillReturn, 948 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>, 949 AMDGPURsrcIntrinsic<1>; 950def int_amdgcn_buffer_store_format : AMDGPUBufferStore<llvm_anyfloat_ty>; 951def int_amdgcn_buffer_store : AMDGPUBufferStore; 952 953// New buffer intrinsics with separate raw and struct variants. The raw 954// variant never has an index. The struct variant always has an index, even if 955// it is const 0. A struct intrinsic with constant 0 index is different to the 956// corresponding raw intrinsic on gfx9+ because the behavior of bound checking 957// and swizzling changes depending on whether idxen is set in the instruction. 958// These new instrinsics also keep the offset and soffset arguments separate as 959// they behave differently in bounds checking and swizzling. 960class AMDGPURawBufferLoad<LLVMType data_ty = llvm_any_ty> : Intrinsic < 961 [data_ty], 962 [llvm_v4i32_ty, // rsrc(SGPR) 963 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 964 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 965 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 966 // bit 1 = slc, 967 // bit 2 = dlc on gfx10+), 968 // swizzled buffer (bit 3 = swz)) 969 [IntrReadMem, IntrWillReturn, ImmArg<ArgIndex<3>>], "", [SDNPMemOperand]>, 970 AMDGPURsrcIntrinsic<0>; 971def int_amdgcn_raw_buffer_load_format : AMDGPURawBufferLoad<llvm_anyfloat_ty>; 972def int_amdgcn_raw_buffer_load : AMDGPURawBufferLoad; 973 974class AMDGPUStructBufferLoad<LLVMType data_ty = llvm_any_ty> : Intrinsic < 975 [data_ty], 976 [llvm_v4i32_ty, // rsrc(SGPR) 977 llvm_i32_ty, // vindex(VGPR) 978 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 979 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 980 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 981 // bit 1 = slc, 982 // bit 2 = dlc on gfx10+), 983 // swizzled buffer (bit 3 = swz)) 984 [IntrReadMem, IntrWillReturn, ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>, 985 AMDGPURsrcIntrinsic<0>; 986def int_amdgcn_struct_buffer_load_format : AMDGPUStructBufferLoad; 987def int_amdgcn_struct_buffer_load : AMDGPUStructBufferLoad; 988 989class AMDGPURawBufferStore<LLVMType data_ty = llvm_any_ty> : Intrinsic < 990 [], 991 [data_ty, // vdata(VGPR) 992 llvm_v4i32_ty, // rsrc(SGPR) 993 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 994 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 995 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 996 // bit 1 = slc, 997 // bit 2 = dlc on gfx10+), 998 // swizzled buffer (bit 3 = swz)) 999 [IntrWriteMem, IntrWillReturn, ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>, 1000 AMDGPURsrcIntrinsic<1>; 1001def int_amdgcn_raw_buffer_store_format : AMDGPURawBufferStore<llvm_anyfloat_ty>; 1002def int_amdgcn_raw_buffer_store : AMDGPURawBufferStore; 1003 1004class AMDGPUStructBufferStore<LLVMType data_ty = llvm_any_ty> : Intrinsic < 1005 [], 1006 [data_ty, // vdata(VGPR) 1007 llvm_v4i32_ty, // rsrc(SGPR) 1008 llvm_i32_ty, // vindex(VGPR) 1009 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1010 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1011 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 1012 // bit 1 = slc, 1013 // bit 2 = dlc on gfx10+), 1014 // swizzled buffer (bit 3 = swz)) 1015 [IntrWriteMem, IntrWillReturn, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>, 1016 AMDGPURsrcIntrinsic<1>; 1017def int_amdgcn_struct_buffer_store_format : AMDGPUStructBufferStore; 1018def int_amdgcn_struct_buffer_store : AMDGPUStructBufferStore; 1019 1020class AMDGPURawBufferAtomic<LLVMType data_ty = llvm_any_ty, bit NoRtn = false> : Intrinsic < 1021 !if(NoRtn, [], [data_ty]), 1022 [!if(NoRtn, data_ty, LLVMMatchType<0>), // vdata(VGPR) 1023 llvm_v4i32_ty, // rsrc(SGPR) 1024 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1025 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1026 llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) 1027 [ImmArg<ArgIndex<4>>, IntrWillReturn], "", [SDNPMemOperand]>, 1028 AMDGPURsrcIntrinsic<1, 0>; 1029def int_amdgcn_raw_buffer_atomic_swap : AMDGPURawBufferAtomic; 1030def int_amdgcn_raw_buffer_atomic_add : AMDGPURawBufferAtomic; 1031def int_amdgcn_raw_buffer_atomic_sub : AMDGPURawBufferAtomic; 1032def int_amdgcn_raw_buffer_atomic_smin : AMDGPURawBufferAtomic; 1033def int_amdgcn_raw_buffer_atomic_umin : AMDGPURawBufferAtomic; 1034def int_amdgcn_raw_buffer_atomic_fmin : AMDGPURawBufferAtomic<llvm_anyfloat_ty>; 1035def int_amdgcn_raw_buffer_atomic_smax : AMDGPURawBufferAtomic; 1036def int_amdgcn_raw_buffer_atomic_umax : AMDGPURawBufferAtomic; 1037def int_amdgcn_raw_buffer_atomic_fmax : AMDGPURawBufferAtomic<llvm_anyfloat_ty>; 1038def int_amdgcn_raw_buffer_atomic_and : AMDGPURawBufferAtomic; 1039def int_amdgcn_raw_buffer_atomic_or : AMDGPURawBufferAtomic; 1040def int_amdgcn_raw_buffer_atomic_xor : AMDGPURawBufferAtomic; 1041def int_amdgcn_raw_buffer_atomic_inc : AMDGPURawBufferAtomic; 1042def int_amdgcn_raw_buffer_atomic_dec : AMDGPURawBufferAtomic; 1043def int_amdgcn_raw_buffer_atomic_cmpswap : Intrinsic< 1044 [llvm_anyint_ty], 1045 [LLVMMatchType<0>, // src(VGPR) 1046 LLVMMatchType<0>, // cmp(VGPR) 1047 llvm_v4i32_ty, // rsrc(SGPR) 1048 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1049 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1050 llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) 1051 [ImmArg<ArgIndex<5>>, IntrWillReturn], "", [SDNPMemOperand]>, 1052 AMDGPURsrcIntrinsic<2, 0>; 1053 1054// gfx908 intrinsic 1055def int_amdgcn_raw_buffer_atomic_fadd : AMDGPURawBufferAtomic<llvm_anyfloat_ty>; 1056 1057class AMDGPUStructBufferAtomic<LLVMType data_ty = llvm_any_ty, bit NoRtn = false> : Intrinsic < 1058 !if(NoRtn, [], [data_ty]), 1059 [!if(NoRtn, data_ty, LLVMMatchType<0>), // vdata(VGPR) 1060 llvm_v4i32_ty, // rsrc(SGPR) 1061 llvm_i32_ty, // vindex(VGPR) 1062 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1063 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1064 llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) 1065 [ImmArg<ArgIndex<5>>, IntrWillReturn], "", [SDNPMemOperand]>, 1066 AMDGPURsrcIntrinsic<1, 0>; 1067def int_amdgcn_struct_buffer_atomic_swap : AMDGPUStructBufferAtomic; 1068def int_amdgcn_struct_buffer_atomic_add : AMDGPUStructBufferAtomic; 1069def int_amdgcn_struct_buffer_atomic_sub : AMDGPUStructBufferAtomic; 1070def int_amdgcn_struct_buffer_atomic_smin : AMDGPUStructBufferAtomic; 1071def int_amdgcn_struct_buffer_atomic_umin : AMDGPUStructBufferAtomic; 1072def int_amdgcn_struct_buffer_atomic_smax : AMDGPUStructBufferAtomic; 1073def int_amdgcn_struct_buffer_atomic_umax : AMDGPUStructBufferAtomic; 1074def int_amdgcn_struct_buffer_atomic_and : AMDGPUStructBufferAtomic; 1075def int_amdgcn_struct_buffer_atomic_or : AMDGPUStructBufferAtomic; 1076def int_amdgcn_struct_buffer_atomic_xor : AMDGPUStructBufferAtomic; 1077def int_amdgcn_struct_buffer_atomic_inc : AMDGPUStructBufferAtomic; 1078def int_amdgcn_struct_buffer_atomic_dec : AMDGPUStructBufferAtomic; 1079def int_amdgcn_struct_buffer_atomic_cmpswap : Intrinsic< 1080 [llvm_anyint_ty], 1081 [LLVMMatchType<0>, // src(VGPR) 1082 LLVMMatchType<0>, // cmp(VGPR) 1083 llvm_v4i32_ty, // rsrc(SGPR) 1084 llvm_i32_ty, // vindex(VGPR) 1085 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1086 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1087 llvm_i32_ty], // cachepolicy(imm; bit 1 = slc) 1088 [ImmArg<ArgIndex<6>>, IntrWillReturn], "", [SDNPMemOperand]>, 1089 AMDGPURsrcIntrinsic<2, 0>; 1090 1091// gfx908 intrinsic 1092def int_amdgcn_struct_buffer_atomic_fadd : AMDGPUStructBufferAtomic<llvm_anyfloat_ty>; 1093 1094// gfx90a intrinsics 1095def int_amdgcn_struct_buffer_atomic_fmin : AMDGPUStructBufferAtomic<llvm_anyfloat_ty>; 1096def int_amdgcn_struct_buffer_atomic_fmax : AMDGPUStructBufferAtomic<llvm_anyfloat_ty>; 1097 1098 1099// Obsolescent tbuffer intrinsics. 1100def int_amdgcn_tbuffer_load : Intrinsic < 1101 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32 1102 [llvm_v4i32_ty, // rsrc(SGPR) 1103 llvm_i32_ty, // vindex(VGPR) 1104 llvm_i32_ty, // voffset(VGPR) 1105 llvm_i32_ty, // soffset(SGPR) 1106 llvm_i32_ty, // offset(imm) 1107 llvm_i32_ty, // dfmt(imm) 1108 llvm_i32_ty, // nfmt(imm) 1109 llvm_i1_ty, // glc(imm) 1110 llvm_i1_ty], // slc(imm) 1111 [IntrReadMem, IntrWillReturn, 1112 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>, ImmArg<ArgIndex<6>>, 1113 ImmArg<ArgIndex<7>>, ImmArg<ArgIndex<8>>], "", [SDNPMemOperand]>, 1114 AMDGPURsrcIntrinsic<0>; 1115 1116def int_amdgcn_tbuffer_store : Intrinsic < 1117 [], 1118 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32 1119 llvm_v4i32_ty, // rsrc(SGPR) 1120 llvm_i32_ty, // vindex(VGPR) 1121 llvm_i32_ty, // voffset(VGPR) 1122 llvm_i32_ty, // soffset(SGPR) 1123 llvm_i32_ty, // offset(imm) 1124 llvm_i32_ty, // dfmt(imm) 1125 llvm_i32_ty, // nfmt(imm) 1126 llvm_i1_ty, // glc(imm) 1127 llvm_i1_ty], // slc(imm) 1128 [IntrWriteMem, IntrWillReturn, ImmArg<ArgIndex<5>>, 1129 ImmArg<ArgIndex<6>>, ImmArg<ArgIndex<7>>, 1130 ImmArg<ArgIndex<8>>, ImmArg<ArgIndex<9>>], "", [SDNPMemOperand]>, 1131 AMDGPURsrcIntrinsic<1>; 1132 1133// New tbuffer intrinsics, with: 1134// - raw and struct variants 1135// - joint format field 1136// - joint cachepolicy field 1137def int_amdgcn_raw_tbuffer_load : Intrinsic < 1138 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32 1139 [llvm_v4i32_ty, // rsrc(SGPR) 1140 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1141 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1142 llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) 1143 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 1144 // bit 1 = slc, 1145 // bit 2 = dlc on gfx10+), 1146 // swizzled buffer (bit 3 = swz)) 1147 [IntrReadMem, IntrWillReturn, 1148 ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>, 1149 AMDGPURsrcIntrinsic<0>; 1150 1151def int_amdgcn_raw_tbuffer_store : Intrinsic < 1152 [], 1153 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32 1154 llvm_v4i32_ty, // rsrc(SGPR) 1155 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1156 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1157 llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) 1158 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 1159 // bit 1 = slc, 1160 // bit 2 = dlc on gfx10+), 1161 // swizzled buffer (bit 3 = swz)) 1162 [IntrWriteMem, IntrWillReturn, 1163 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>, 1164 AMDGPURsrcIntrinsic<1>; 1165 1166def int_amdgcn_struct_tbuffer_load : Intrinsic < 1167 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32 1168 [llvm_v4i32_ty, // rsrc(SGPR) 1169 llvm_i32_ty, // vindex(VGPR) 1170 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1171 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1172 llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) 1173 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 1174 // bit 1 = slc, 1175 // bit 2 = dlc on gfx10+), 1176 // swizzled buffer (bit 3 = swz)) 1177 [IntrReadMem, IntrWillReturn, 1178 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>, 1179 AMDGPURsrcIntrinsic<0>; 1180 1181def int_amdgcn_struct_tbuffer_store : Intrinsic < 1182 [], 1183 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32 1184 llvm_v4i32_ty, // rsrc(SGPR) 1185 llvm_i32_ty, // vindex(VGPR) 1186 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling) 1187 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling) 1188 llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt) 1189 llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc, 1190 // bit 1 = slc, 1191 // bit 2 = dlc on gfx10+), 1192 // swizzled buffer (bit 3 = swz)) 1193 [IntrWriteMem, IntrWillReturn, 1194 ImmArg<ArgIndex<5>>, ImmArg<ArgIndex<6>>], "", [SDNPMemOperand]>, 1195 AMDGPURsrcIntrinsic<1>; 1196 1197class AMDGPUBufferAtomic : Intrinsic < 1198 [llvm_anyint_ty], 1199 [LLVMMatchType<0>, // vdata(VGPR) 1200 llvm_v4i32_ty, // rsrc(SGPR) 1201 llvm_i32_ty, // vindex(VGPR) 1202 llvm_i32_ty, // offset(SGPR/VGPR/imm) 1203 llvm_i1_ty], // slc(imm) 1204 [ImmArg<ArgIndex<4>>, IntrWillReturn], "", [SDNPMemOperand]>, 1205 AMDGPURsrcIntrinsic<1, 0>; 1206def int_amdgcn_buffer_atomic_swap : AMDGPUBufferAtomic; 1207def int_amdgcn_buffer_atomic_add : AMDGPUBufferAtomic; 1208def int_amdgcn_buffer_atomic_sub : AMDGPUBufferAtomic; 1209def int_amdgcn_buffer_atomic_smin : AMDGPUBufferAtomic; 1210def int_amdgcn_buffer_atomic_umin : AMDGPUBufferAtomic; 1211def int_amdgcn_buffer_atomic_smax : AMDGPUBufferAtomic; 1212def int_amdgcn_buffer_atomic_umax : AMDGPUBufferAtomic; 1213def int_amdgcn_buffer_atomic_and : AMDGPUBufferAtomic; 1214def int_amdgcn_buffer_atomic_or : AMDGPUBufferAtomic; 1215def int_amdgcn_buffer_atomic_xor : AMDGPUBufferAtomic; 1216def int_amdgcn_buffer_atomic_cmpswap : Intrinsic< 1217 [llvm_i32_ty], 1218 [llvm_i32_ty, // src(VGPR) 1219 llvm_i32_ty, // cmp(VGPR) 1220 llvm_v4i32_ty, // rsrc(SGPR) 1221 llvm_i32_ty, // vindex(VGPR) 1222 llvm_i32_ty, // offset(SGPR/VGPR/imm) 1223 llvm_i1_ty], // slc(imm) 1224 [ImmArg<ArgIndex<5>>, IntrWillReturn], "", [SDNPMemOperand]>, 1225 AMDGPURsrcIntrinsic<2, 0>; 1226 1227def int_amdgcn_buffer_atomic_csub : AMDGPUBufferAtomic; 1228 1229class AMDGPUBufferAtomicFP : Intrinsic < 1230 [llvm_anyfloat_ty], 1231 [LLVMMatchType<0>, // vdata(VGPR) 1232 llvm_v4i32_ty, // rsrc(SGPR) 1233 llvm_i32_ty, // vindex(VGPR) 1234 llvm_i32_ty, // offset(SGPR/VGPR/imm) 1235 llvm_i1_ty], // slc(imm) 1236 [ImmArg<ArgIndex<4>>, IntrWillReturn], "", [SDNPMemOperand]>, 1237 AMDGPURsrcIntrinsic<1, 0>; 1238 1239// Legacy form of the intrinsic. raw and struct forms should be preferred. 1240def int_amdgcn_buffer_atomic_fadd : AMDGPUBufferAtomicFP; 1241} // defset AMDGPUBufferIntrinsics 1242 1243// Uses that do not set the done bit should set IntrWriteMem on the 1244// call site. 1245def int_amdgcn_exp : Intrinsic <[], [ 1246 llvm_i32_ty, // tgt, 1247 llvm_i32_ty, // en 1248 llvm_any_ty, // src0 (f32 or i32) 1249 LLVMMatchType<0>, // src1 1250 LLVMMatchType<0>, // src2 1251 LLVMMatchType<0>, // src3 1252 llvm_i1_ty, // done 1253 llvm_i1_ty // vm 1254 ], 1255 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<6>>, 1256 ImmArg<ArgIndex<7>>, IntrWriteMem, IntrInaccessibleMemOnly, 1257 IntrWillReturn] 1258>; 1259 1260// exp with compr bit set. 1261def int_amdgcn_exp_compr : Intrinsic <[], [ 1262 llvm_i32_ty, // tgt, 1263 llvm_i32_ty, // en 1264 llvm_anyvector_ty, // src0 (v2f16 or v2i16) 1265 LLVMMatchType<0>, // src1 1266 llvm_i1_ty, // done 1267 llvm_i1_ty], // vm 1268 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<4>>, 1269 ImmArg<ArgIndex<5>>, IntrWriteMem, IntrInaccessibleMemOnly, 1270 IntrWillReturn] 1271>; 1272 1273def int_amdgcn_buffer_wbinvl1_sc : 1274 GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_sc">, 1275 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 1276 1277def int_amdgcn_buffer_wbinvl1 : 1278 GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1">, 1279 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 1280 1281def int_amdgcn_s_dcache_inv : 1282 GCCBuiltin<"__builtin_amdgcn_s_dcache_inv">, 1283 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 1284 1285def int_amdgcn_s_memtime : 1286 GCCBuiltin<"__builtin_amdgcn_s_memtime">, 1287 Intrinsic<[llvm_i64_ty], [], [IntrWillReturn]>; 1288 1289def int_amdgcn_s_sleep : 1290 GCCBuiltin<"__builtin_amdgcn_s_sleep">, 1291 Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, 1292 IntrHasSideEffects, IntrWillReturn]> { 1293} 1294 1295def int_amdgcn_s_incperflevel : 1296 GCCBuiltin<"__builtin_amdgcn_s_incperflevel">, 1297 Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, 1298 IntrHasSideEffects, IntrWillReturn]> { 1299} 1300 1301def int_amdgcn_s_decperflevel : 1302 GCCBuiltin<"__builtin_amdgcn_s_decperflevel">, 1303 Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, 1304 IntrHasSideEffects, IntrWillReturn]> { 1305} 1306 1307def int_amdgcn_s_sethalt : 1308 Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, 1309 IntrHasSideEffects, IntrWillReturn]>; 1310 1311def int_amdgcn_s_getreg : 1312 GCCBuiltin<"__builtin_amdgcn_s_getreg">, 1313 Intrinsic<[llvm_i32_ty], [llvm_i32_ty], 1314 [IntrInaccessibleMemOnly, IntrReadMem, IntrSpeculatable, 1315 IntrWillReturn, ImmArg<ArgIndex<0>>] 1316>; 1317 1318// Note this can be used to set FP environment properties that are 1319// unsafe to change in non-strictfp functions. The register properties 1320// available (and value required to access them) may differ per 1321// subtarget. llvm.amdgcn.s.setreg(hwmode, value) 1322def int_amdgcn_s_setreg : 1323 GCCBuiltin<"__builtin_amdgcn_s_setreg">, 1324 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], 1325 [IntrNoMem, IntrHasSideEffects, IntrWillReturn, ImmArg<ArgIndex<0>>] 1326>; 1327 1328// int_amdgcn_s_getpc is provided to allow a specific style of position 1329// independent code to determine the high part of its address when it is 1330// known (through convention) that the code and any data of interest does 1331// not cross a 4Gb address boundary. Use for any other purpose may not 1332// produce the desired results as optimizations may cause code movement, 1333// especially as we explicitly use IntrNoMem to allow optimizations. 1334def int_amdgcn_s_getpc : 1335 GCCBuiltin<"__builtin_amdgcn_s_getpc">, 1336 Intrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrSpeculatable, 1337 IntrWillReturn]>; 1338 1339// __builtin_amdgcn_interp_mov <param>, <attr_chan>, <attr>, <m0> 1340// param values: 0 = P10, 1 = P20, 2 = P0 1341def int_amdgcn_interp_mov : 1342 GCCBuiltin<"__builtin_amdgcn_interp_mov">, 1343 Intrinsic<[llvm_float_ty], 1344 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1345 [IntrNoMem, IntrSpeculatable, IntrWillReturn, 1346 ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 1347 1348// __builtin_amdgcn_interp_p1 <i>, <attr_chan>, <attr>, <m0> 1349// This intrinsic reads from lds, but the memory values are constant, 1350// so it behaves like IntrNoMem. 1351def int_amdgcn_interp_p1 : 1352 GCCBuiltin<"__builtin_amdgcn_interp_p1">, 1353 Intrinsic<[llvm_float_ty], 1354 [llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1355 [IntrNoMem, IntrSpeculatable, IntrWillReturn, 1356 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 1357 1358// __builtin_amdgcn_interp_p2 <p1>, <j>, <attr_chan>, <attr>, <m0> 1359def int_amdgcn_interp_p2 : 1360 GCCBuiltin<"__builtin_amdgcn_interp_p2">, 1361 Intrinsic<[llvm_float_ty], 1362 [llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1363 [IntrNoMem, IntrSpeculatable, IntrWillReturn, 1364 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 1365 // See int_amdgcn_v_interp_p1 for why this is IntrNoMem. 1366 1367// __builtin_amdgcn_interp_p1_f16 <i>, <attr_chan>, <attr>, <high>, <m0> 1368// high selects whether high or low 16-bits are loaded from LDS 1369def int_amdgcn_interp_p1_f16 : 1370 GCCBuiltin<"__builtin_amdgcn_interp_p1_f16">, 1371 Intrinsic<[llvm_float_ty], 1372 [llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i32_ty], 1373 [IntrNoMem, IntrSpeculatable, IntrWillReturn, 1374 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 1375 1376// __builtin_amdgcn_interp_p2_f16 <p1>, <j>, <attr_chan>, <attr>, <high>, <m0> 1377// high selects whether high or low 16-bits are loaded from LDS 1378def int_amdgcn_interp_p2_f16 : 1379 GCCBuiltin<"__builtin_amdgcn_interp_p2_f16">, 1380 Intrinsic<[llvm_half_ty], 1381 [llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i32_ty], 1382 [IntrNoMem, IntrSpeculatable, IntrWillReturn, 1383 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>; 1384 1385// Deprecated: use llvm.amdgcn.live.mask instead. 1386def int_amdgcn_ps_live : Intrinsic < 1387 [llvm_i1_ty], 1388 [], 1389 [IntrNoMem, IntrWillReturn]>; 1390 1391// Query currently live lanes. 1392// Returns true if lane is live (and not a helper lane). 1393def int_amdgcn_live_mask : Intrinsic <[llvm_i1_ty], 1394 [], [IntrReadMem, IntrInaccessibleMemOnly, IntrWillReturn] 1395>; 1396 1397def int_amdgcn_mbcnt_lo : 1398 GCCBuiltin<"__builtin_amdgcn_mbcnt_lo">, 1399 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 1400 [IntrNoMem, IntrWillReturn]>; 1401 1402def int_amdgcn_mbcnt_hi : 1403 GCCBuiltin<"__builtin_amdgcn_mbcnt_hi">, 1404 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 1405 [IntrNoMem, IntrWillReturn]>; 1406 1407// llvm.amdgcn.ds.swizzle src offset 1408def int_amdgcn_ds_swizzle : 1409 GCCBuiltin<"__builtin_amdgcn_ds_swizzle">, 1410 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 1411 [IntrNoMem, IntrConvergent, IntrWillReturn, 1412 ImmArg<ArgIndex<1>>]>; 1413 1414def int_amdgcn_ubfe : Intrinsic<[llvm_anyint_ty], 1415 [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty], 1416 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1417>; 1418 1419def int_amdgcn_sbfe : Intrinsic<[llvm_anyint_ty], 1420 [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty], 1421 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1422>; 1423 1424def int_amdgcn_lerp : 1425 GCCBuiltin<"__builtin_amdgcn_lerp">, 1426 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1427 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1428>; 1429 1430def int_amdgcn_sad_u8 : 1431 GCCBuiltin<"__builtin_amdgcn_sad_u8">, 1432 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1433 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1434>; 1435 1436def int_amdgcn_msad_u8 : 1437 GCCBuiltin<"__builtin_amdgcn_msad_u8">, 1438 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1439 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1440>; 1441 1442def int_amdgcn_sad_hi_u8 : 1443 GCCBuiltin<"__builtin_amdgcn_sad_hi_u8">, 1444 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1445 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1446>; 1447 1448def int_amdgcn_sad_u16 : 1449 GCCBuiltin<"__builtin_amdgcn_sad_u16">, 1450 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1451 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1452>; 1453 1454def int_amdgcn_qsad_pk_u16_u8 : 1455 GCCBuiltin<"__builtin_amdgcn_qsad_pk_u16_u8">, 1456 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty], 1457 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1458>; 1459 1460def int_amdgcn_mqsad_pk_u16_u8 : 1461 GCCBuiltin<"__builtin_amdgcn_mqsad_pk_u16_u8">, 1462 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty], 1463 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1464>; 1465 1466def int_amdgcn_mqsad_u32_u8 : 1467 GCCBuiltin<"__builtin_amdgcn_mqsad_u32_u8">, 1468 Intrinsic<[llvm_v4i32_ty], [llvm_i64_ty, llvm_i32_ty, llvm_v4i32_ty], 1469 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1470>; 1471 1472def int_amdgcn_cvt_pk_u8_f32 : 1473 GCCBuiltin<"__builtin_amdgcn_cvt_pk_u8_f32">, 1474 Intrinsic<[llvm_i32_ty], [llvm_float_ty, llvm_i32_ty, llvm_i32_ty], 1475 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1476>; 1477 1478def int_amdgcn_icmp : 1479 Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty, LLVMMatchType<1>, llvm_i32_ty], 1480 [IntrNoMem, IntrConvergent, IntrWillReturn, 1481 ImmArg<ArgIndex<2>>]>; 1482 1483def int_amdgcn_fcmp : 1484 Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>, llvm_i32_ty], 1485 [IntrNoMem, IntrConvergent, IntrWillReturn, 1486 ImmArg<ArgIndex<2>>]>; 1487 1488def int_amdgcn_ballot : 1489 Intrinsic<[llvm_anyint_ty], [llvm_i1_ty], 1490 [IntrNoMem, IntrConvergent, IntrWillReturn]>; 1491 1492def int_amdgcn_readfirstlane : 1493 GCCBuiltin<"__builtin_amdgcn_readfirstlane">, 1494 Intrinsic<[llvm_i32_ty], [llvm_i32_ty], 1495 [IntrNoMem, IntrConvergent, IntrWillReturn]>; 1496 1497// The lane argument must be uniform across the currently active threads of the 1498// current wave. Otherwise, the result is undefined. 1499def int_amdgcn_readlane : 1500 GCCBuiltin<"__builtin_amdgcn_readlane">, 1501 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 1502 [IntrNoMem, IntrConvergent, IntrWillReturn]>; 1503 1504// The value to write and lane select arguments must be uniform across the 1505// currently active threads of the current wave. Otherwise, the result is 1506// undefined. 1507def int_amdgcn_writelane : 1508 GCCBuiltin<"__builtin_amdgcn_writelane">, 1509 Intrinsic<[llvm_i32_ty], [ 1510 llvm_i32_ty, // uniform value to write: returned by the selected lane 1511 llvm_i32_ty, // uniform lane select 1512 llvm_i32_ty // returned by all lanes other than the selected one 1513 ], 1514 [IntrNoMem, IntrConvergent, IntrWillReturn] 1515>; 1516 1517// FIXME: Deprecated. This is equivalent to llvm.fshr 1518def int_amdgcn_alignbit : Intrinsic<[llvm_i32_ty], 1519 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1520 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1521>; 1522 1523def int_amdgcn_alignbyte : GCCBuiltin<"__builtin_amdgcn_alignbyte">, 1524 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1525 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1526>; 1527 1528def int_amdgcn_mul_i24 : Intrinsic<[llvm_i32_ty], 1529 [llvm_i32_ty, llvm_i32_ty], 1530 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1531>; 1532 1533def int_amdgcn_mul_u24 : Intrinsic<[llvm_i32_ty], 1534 [llvm_i32_ty, llvm_i32_ty], 1535 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1536>; 1537 1538// llvm.amdgcn.ds.gws.init(i32 bar_val, i32 resource_id) 1539// 1540// bar_val is the total number of waves that will wait on this 1541// barrier, minus 1. 1542def int_amdgcn_ds_gws_init : 1543 GCCBuiltin<"__builtin_amdgcn_ds_gws_init">, 1544 Intrinsic<[], 1545 [llvm_i32_ty, llvm_i32_ty], 1546 [IntrConvergent, IntrWriteMem, 1547 IntrInaccessibleMemOnly, IntrWillReturn], "", 1548 [SDNPMemOperand] 1549>; 1550 1551// llvm.amdgcn.ds.gws.barrier(i32 vsrc0, i32 resource_id) 1552// bar_val is the total number of waves that will wait on this 1553// barrier, minus 1. 1554def int_amdgcn_ds_gws_barrier : 1555 GCCBuiltin<"__builtin_amdgcn_ds_gws_barrier">, 1556 Intrinsic<[], 1557 [llvm_i32_ty, llvm_i32_ty], 1558 [IntrConvergent, IntrInaccessibleMemOnly, IntrWillReturn], "", 1559 [SDNPMemOperand] 1560>; 1561 1562// llvm.amdgcn.ds.gws.sema.v(i32 resource_id) 1563def int_amdgcn_ds_gws_sema_v : 1564 GCCBuiltin<"__builtin_amdgcn_ds_gws_sema_v">, 1565 Intrinsic<[], 1566 [llvm_i32_ty], 1567 [IntrConvergent, IntrInaccessibleMemOnly, IntrWillReturn], "", 1568 [SDNPMemOperand] 1569>; 1570 1571// llvm.amdgcn.ds.gws.sema.br(i32 vsrc, i32 resource_id) 1572def int_amdgcn_ds_gws_sema_br : 1573 GCCBuiltin<"__builtin_amdgcn_ds_gws_sema_br">, 1574 Intrinsic<[], 1575 [llvm_i32_ty, llvm_i32_ty], 1576 [IntrConvergent, IntrInaccessibleMemOnly, IntrWillReturn], "", 1577 [SDNPMemOperand] 1578>; 1579 1580// llvm.amdgcn.ds.gws.sema.p(i32 resource_id) 1581def int_amdgcn_ds_gws_sema_p : 1582 GCCBuiltin<"__builtin_amdgcn_ds_gws_sema_p">, 1583 Intrinsic<[], 1584 [llvm_i32_ty], 1585 [IntrConvergent, IntrInaccessibleMemOnly, IntrWillReturn], "", 1586 [SDNPMemOperand] 1587>; 1588 1589// llvm.amdgcn.ds.gws.sema.release.all(i32 resource_id) 1590def int_amdgcn_ds_gws_sema_release_all : 1591 GCCBuiltin<"__builtin_amdgcn_ds_gws_sema_release_all">, 1592 Intrinsic<[], 1593 [llvm_i32_ty], 1594 [IntrConvergent, IntrInaccessibleMemOnly, IntrWillReturn], "", 1595 [SDNPMemOperand] 1596>; 1597 1598 1599// Copies the source value to the destination value, with the guarantee that 1600// the source value is computed as if the entire program were executed in WQM. 1601def int_amdgcn_wqm : Intrinsic<[llvm_any_ty], 1602 [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1603>; 1604 1605// Copies the source value to the destination value, such that the source 1606// is computed as if the entire program were executed in WQM if any other 1607// program code executes in WQM. 1608def int_amdgcn_softwqm : Intrinsic<[llvm_any_ty], 1609 [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1610>; 1611 1612// Return true if at least one thread within the pixel quad passes true into 1613// the function. 1614def int_amdgcn_wqm_vote : Intrinsic<[llvm_i1_ty], 1615 [llvm_i1_ty], [IntrNoMem, IntrConvergent, IntrWillReturn] 1616>; 1617 1618// If false, set EXEC=0 for the current thread until the end of program. 1619// FIXME: Should this be IntrNoMem, IntrHasSideEffects, or IntrWillReturn? 1620def int_amdgcn_kill : Intrinsic<[], [llvm_i1_ty], []>; 1621 1622def int_amdgcn_endpgm : GCCBuiltin<"__builtin_amdgcn_endpgm">, 1623 Intrinsic<[], [], [IntrNoReturn, IntrCold, IntrNoMem, IntrHasSideEffects] 1624>; 1625 1626// If false, mark all active lanes as helper lanes until the end of program. 1627def int_amdgcn_wqm_demote : Intrinsic<[], 1628 [llvm_i1_ty], [IntrWriteMem, IntrInaccessibleMemOnly] 1629>; 1630 1631// Copies the active channels of the source value to the destination value, 1632// with the guarantee that the source value is computed as if the entire 1633// program were executed in Whole Wavefront Mode, i.e. with all channels 1634// enabled, with a few exceptions: - Phi nodes which require WWM return an 1635// undefined value. 1636def int_amdgcn_strict_wwm : Intrinsic<[llvm_any_ty], 1637 [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, 1638 IntrConvergent, IntrWillReturn] 1639>; 1640// Deprecated. Use int_amdgcn_strict_wwm instead. 1641def int_amdgcn_wwm : Intrinsic<[llvm_any_ty], 1642 [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, 1643 IntrConvergent, IntrWillReturn] 1644>; 1645def int_amdgcn_strict_wqm : Intrinsic<[llvm_any_ty], 1646 [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, 1647 IntrConvergent, IntrWillReturn] 1648>; 1649 1650// Given a value, copies it while setting all the inactive lanes to a given 1651// value. Note that OpenGL helper lanes are considered active, so if the 1652// program ever uses WQM, then the instruction and the first source will be 1653// computed in WQM. 1654def int_amdgcn_set_inactive : 1655 Intrinsic<[llvm_anyint_ty], 1656 [LLVMMatchType<0>, // value to be copied 1657 LLVMMatchType<0>], // value for the inactive lanes to take 1658 [IntrNoMem, IntrConvergent, IntrWillReturn]>; 1659 1660// Return if the given flat pointer points to a local memory address. 1661def int_amdgcn_is_shared : GCCBuiltin<"__builtin_amdgcn_is_shared">, 1662 Intrinsic<[llvm_i1_ty], [llvm_ptr_ty], 1663 [IntrNoMem, IntrSpeculatable, NoCapture<ArgIndex<0>>, IntrWillReturn] 1664>; 1665 1666// Return if the given flat pointer points to a prvate memory address. 1667def int_amdgcn_is_private : GCCBuiltin<"__builtin_amdgcn_is_private">, 1668 Intrinsic<[llvm_i1_ty], [llvm_ptr_ty], 1669 [IntrNoMem, IntrSpeculatable, NoCapture<ArgIndex<0>>, IntrWillReturn] 1670>; 1671 1672//===----------------------------------------------------------------------===// 1673// CI+ Intrinsics 1674//===----------------------------------------------------------------------===// 1675 1676def int_amdgcn_s_dcache_inv_vol : 1677 GCCBuiltin<"__builtin_amdgcn_s_dcache_inv_vol">, 1678 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 1679 1680def int_amdgcn_buffer_wbinvl1_vol : 1681 GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_vol">, 1682 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 1683 1684//===----------------------------------------------------------------------===// 1685// VI Intrinsics 1686//===----------------------------------------------------------------------===// 1687 1688// llvm.amdgcn.mov.dpp.i32 <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl> 1689def int_amdgcn_mov_dpp : 1690 Intrinsic<[llvm_anyint_ty], 1691 [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 1692 llvm_i1_ty], 1693 [IntrNoMem, IntrConvergent, IntrWillReturn, 1694 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, 1695 ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>; 1696 1697// llvm.amdgcn.update.dpp.i32 <old> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl> 1698// Should be equivalent to: 1699// v_mov_b32 <dest> <old> 1700// v_mov_b32 <dest> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl> 1701def int_amdgcn_update_dpp : 1702 Intrinsic<[llvm_anyint_ty], 1703 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty, 1704 llvm_i32_ty, llvm_i32_ty, llvm_i1_ty], 1705 [IntrNoMem, IntrConvergent, IntrWillReturn, 1706 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, 1707 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>; 1708 1709def int_amdgcn_s_dcache_wb : 1710 GCCBuiltin<"__builtin_amdgcn_s_dcache_wb">, 1711 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 1712 1713def int_amdgcn_s_dcache_wb_vol : 1714 GCCBuiltin<"__builtin_amdgcn_s_dcache_wb_vol">, 1715 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]>; 1716 1717def int_amdgcn_s_memrealtime : 1718 GCCBuiltin<"__builtin_amdgcn_s_memrealtime">, 1719 Intrinsic<[llvm_i64_ty], [], [IntrWillReturn]>; 1720 1721// llvm.amdgcn.ds.permute <index> <src> 1722def int_amdgcn_ds_permute : 1723 GCCBuiltin<"__builtin_amdgcn_ds_permute">, 1724 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 1725 [IntrNoMem, IntrConvergent, IntrWillReturn]>; 1726 1727// llvm.amdgcn.ds.bpermute <index> <src> 1728def int_amdgcn_ds_bpermute : 1729 GCCBuiltin<"__builtin_amdgcn_ds_bpermute">, 1730 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 1731 [IntrNoMem, IntrConvergent, IntrWillReturn]>; 1732 1733// llvm.amdgcn.perm <src0> <src1> <selector> 1734def int_amdgcn_perm : 1735 GCCBuiltin<"__builtin_amdgcn_perm">, 1736 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1737 [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; 1738 1739//===----------------------------------------------------------------------===// 1740// GFX10 Intrinsics 1741//===----------------------------------------------------------------------===// 1742 1743// llvm.amdgcn.permlane16 <old> <src0> <src1> <src2> <fi> <bound_control> 1744def int_amdgcn_permlane16 : GCCBuiltin<"__builtin_amdgcn_permlane16">, 1745 Intrinsic<[llvm_i32_ty], 1746 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty], 1747 [IntrNoMem, IntrConvergent, IntrWillReturn, 1748 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>; 1749 1750// llvm.amdgcn.permlanex16 <old> <src0> <src1> <src2> <fi> <bound_control> 1751def int_amdgcn_permlanex16 : GCCBuiltin<"__builtin_amdgcn_permlanex16">, 1752 Intrinsic<[llvm_i32_ty], 1753 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty], 1754 [IntrNoMem, IntrConvergent, IntrWillReturn, 1755 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>; 1756 1757// llvm.amdgcn.mov.dpp8.i32 <src> <sel> 1758// <sel> is a 32-bit constant whose high 8 bits must be zero which selects 1759// the lanes to read from. 1760def int_amdgcn_mov_dpp8 : 1761 Intrinsic<[llvm_anyint_ty], 1762 [LLVMMatchType<0>, llvm_i32_ty], 1763 [IntrNoMem, IntrConvergent, IntrWillReturn, 1764 ImmArg<ArgIndex<1>>]>; 1765 1766def int_amdgcn_s_get_waveid_in_workgroup : 1767 GCCBuiltin<"__builtin_amdgcn_s_get_waveid_in_workgroup">, 1768 Intrinsic<[llvm_i32_ty], [], 1769 [IntrReadMem, IntrInaccessibleMemOnly, IntrWillReturn]>; 1770 1771class AMDGPUGlobalAtomicRtn<LLVMType vt> : Intrinsic < 1772 [vt], 1773 [llvm_anyptr_ty, // vaddr 1774 vt], // vdata(VGPR) 1775 [IntrArgMemOnly, IntrWillReturn, NoCapture<ArgIndex<0>>], "", 1776 [SDNPMemOperand]>; 1777 1778def int_amdgcn_global_atomic_csub : AMDGPUGlobalAtomicRtn<llvm_i32_ty>; 1779 1780// uint4 llvm.amdgcn.image.bvh.intersect.ray <node_ptr>, <ray_extent>, <ray_origin>, 1781// <ray_dir>, <ray_inv_dir>, <texture_descr> 1782def int_amdgcn_image_bvh_intersect_ray : 1783 Intrinsic<[llvm_v4i32_ty], 1784 [llvm_anyint_ty, llvm_float_ty, llvm_v4f32_ty, llvm_anyvector_ty, 1785 LLVMMatchType<1>, llvm_v4i32_ty], 1786 [IntrReadMem, IntrWillReturn]>; 1787 1788//===----------------------------------------------------------------------===// 1789// Deep learning intrinsics. 1790//===----------------------------------------------------------------------===// 1791 1792// f32 %r = llvm.amdgcn.fdot2(v2f16 %a, v2f16 %b, f32 %c, i1 %clamp) 1793// %r = %a[0] * %b[0] + %a[1] * %b[1] + %c 1794def int_amdgcn_fdot2 : 1795 GCCBuiltin<"__builtin_amdgcn_fdot2">, 1796 Intrinsic< 1797 [llvm_float_ty], // %r 1798 [ 1799 llvm_v2f16_ty, // %a 1800 llvm_v2f16_ty, // %b 1801 llvm_float_ty, // %c 1802 llvm_i1_ty // %clamp 1803 ], 1804 [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<3>>] 1805 >; 1806 1807// i32 %r = llvm.amdgcn.sdot2(v2i16 %a, v2i16 %b, i32 %c, i1 %clamp) 1808// %r = %a[0] * %b[0] + %a[1] * %b[1] + %c 1809def int_amdgcn_sdot2 : 1810 GCCBuiltin<"__builtin_amdgcn_sdot2">, 1811 Intrinsic< 1812 [llvm_i32_ty], // %r 1813 [ 1814 llvm_v2i16_ty, // %a 1815 llvm_v2i16_ty, // %b 1816 llvm_i32_ty, // %c 1817 llvm_i1_ty // %clamp 1818 ], 1819 [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<3>>] 1820 >; 1821 1822// u32 %r = llvm.amdgcn.udot2(v2u16 %a, v2u16 %b, u32 %c, i1 %clamp) 1823// %r = %a[0] * %b[0] + %a[1] * %b[1] + %c 1824def int_amdgcn_udot2 : 1825 GCCBuiltin<"__builtin_amdgcn_udot2">, 1826 Intrinsic< 1827 [llvm_i32_ty], // %r 1828 [ 1829 llvm_v2i16_ty, // %a 1830 llvm_v2i16_ty, // %b 1831 llvm_i32_ty, // %c 1832 llvm_i1_ty // %clamp 1833 ], 1834 [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<3>>] 1835 >; 1836 1837// i32 %r = llvm.amdgcn.sdot4(v4i8 (as i32) %a, v4i8 (as i32) %b, i32 %c, i1 %clamp) 1838// %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + %c 1839def int_amdgcn_sdot4 : 1840 GCCBuiltin<"__builtin_amdgcn_sdot4">, 1841 Intrinsic< 1842 [llvm_i32_ty], // %r 1843 [ 1844 llvm_i32_ty, // %a 1845 llvm_i32_ty, // %b 1846 llvm_i32_ty, // %c 1847 llvm_i1_ty // %clamp 1848 ], 1849 [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<3>>] 1850 >; 1851 1852// u32 %r = llvm.amdgcn.udot4(v4u8 (as u32) %a, v4u8 (as u32) %b, u32 %c, i1 %clamp) 1853// %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + %c 1854def int_amdgcn_udot4 : 1855 GCCBuiltin<"__builtin_amdgcn_udot4">, 1856 Intrinsic< 1857 [llvm_i32_ty], // %r 1858 [ 1859 llvm_i32_ty, // %a 1860 llvm_i32_ty, // %b 1861 llvm_i32_ty, // %c 1862 llvm_i1_ty // %clamp 1863 ], 1864 [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<3>>] 1865 >; 1866 1867// i32 %r = llvm.amdgcn.sdot8(v8i4 (as i32) %a, v8i4 (as i32) %b, i32 %c, i1 %clamp) 1868// %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + 1869// %a[4] * %b[4] + %a[5] * %b[5] + %a[6] * %b[6] + %a[7] * %b[7] + %c 1870def int_amdgcn_sdot8 : 1871 GCCBuiltin<"__builtin_amdgcn_sdot8">, 1872 Intrinsic< 1873 [llvm_i32_ty], // %r 1874 [ 1875 llvm_i32_ty, // %a 1876 llvm_i32_ty, // %b 1877 llvm_i32_ty, // %c 1878 llvm_i1_ty // %clamp 1879 ], 1880 [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<3>>] 1881 >; 1882 1883// u32 %r = llvm.amdgcn.udot8(v8u4 (as u32) %a, v8u4 (as u32) %b, u32 %c, i1 %clamp) 1884// %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + 1885// %a[4] * %b[4] + %a[5] * %b[5] + %a[6] * %b[6] + %a[7] * %b[7] + %c 1886def int_amdgcn_udot8 : 1887 GCCBuiltin<"__builtin_amdgcn_udot8">, 1888 Intrinsic< 1889 [llvm_i32_ty], // %r 1890 [ 1891 llvm_i32_ty, // %a 1892 llvm_i32_ty, // %b 1893 llvm_i32_ty, // %c 1894 llvm_i1_ty // %clamp 1895 ], 1896 [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<3>>] 1897 >; 1898 1899//===----------------------------------------------------------------------===// 1900// gfx908 intrinsics 1901// ===----------------------------------------------------------------------===// 1902 1903def int_amdgcn_global_atomic_fadd : AMDGPUGlobalAtomicRtn<llvm_anyfloat_ty>; 1904 1905// llvm.amdgcn.mfma.*.* vdst, srcA, srcB, srcC, cbsz, abid, blgp 1906class AMDGPUMfmaIntrinsic<LLVMType DestTy, LLVMType SrcABTy> : 1907 GCCBuiltin<!subst("int", "__builtin", NAME)>, 1908 Intrinsic<[DestTy], 1909 [SrcABTy, SrcABTy, DestTy, 1910 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], 1911 [IntrConvergent, IntrNoMem, IntrWillReturn, 1912 ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>; 1913 1914def int_amdgcn_mfma_f32_32x32x1f32 : AMDGPUMfmaIntrinsic<llvm_v32f32_ty, llvm_float_ty>; 1915def int_amdgcn_mfma_f32_16x16x1f32 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_float_ty>; 1916def int_amdgcn_mfma_f32_4x4x1f32 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_float_ty>; 1917def int_amdgcn_mfma_f32_32x32x2f32 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_float_ty>; 1918def int_amdgcn_mfma_f32_16x16x4f32 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_float_ty>; 1919def int_amdgcn_mfma_f32_32x32x4f16 : AMDGPUMfmaIntrinsic<llvm_v32f32_ty, llvm_v4f16_ty>; 1920def int_amdgcn_mfma_f32_16x16x4f16 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v4f16_ty>; 1921def int_amdgcn_mfma_f32_4x4x4f16 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v4f16_ty>; 1922def int_amdgcn_mfma_f32_32x32x8f16 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v4f16_ty>; 1923def int_amdgcn_mfma_f32_16x16x16f16 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v4f16_ty>; 1924def int_amdgcn_mfma_i32_32x32x4i8 : AMDGPUMfmaIntrinsic<llvm_v32i32_ty, llvm_i32_ty>; 1925def int_amdgcn_mfma_i32_16x16x4i8 : AMDGPUMfmaIntrinsic<llvm_v16i32_ty, llvm_i32_ty>; 1926def int_amdgcn_mfma_i32_4x4x4i8 : AMDGPUMfmaIntrinsic<llvm_v4i32_ty, llvm_i32_ty>; 1927def int_amdgcn_mfma_i32_32x32x8i8 : AMDGPUMfmaIntrinsic<llvm_v16i32_ty, llvm_i32_ty>; 1928def int_amdgcn_mfma_i32_16x16x16i8 : AMDGPUMfmaIntrinsic<llvm_v4i32_ty, llvm_i32_ty>; 1929def int_amdgcn_mfma_f32_32x32x2bf16 : AMDGPUMfmaIntrinsic<llvm_v32f32_ty, llvm_v2i16_ty>; 1930def int_amdgcn_mfma_f32_16x16x2bf16 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v2i16_ty>; 1931def int_amdgcn_mfma_f32_4x4x2bf16 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v2i16_ty>; 1932def int_amdgcn_mfma_f32_32x32x4bf16 : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v2i16_ty>; 1933def int_amdgcn_mfma_f32_16x16x8bf16 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v2i16_ty>; 1934 1935//===----------------------------------------------------------------------===// 1936// gfx90a intrinsics 1937// ===----------------------------------------------------------------------===// 1938 1939def int_amdgcn_global_atomic_fmin : AMDGPUGlobalAtomicRtn<llvm_anyfloat_ty>; 1940def int_amdgcn_global_atomic_fmax : AMDGPUGlobalAtomicRtn<llvm_anyfloat_ty>; 1941def int_amdgcn_flat_atomic_fadd : AMDGPUGlobalAtomicRtn<llvm_anyfloat_ty>; 1942def int_amdgcn_flat_atomic_fmin : AMDGPUGlobalAtomicRtn<llvm_anyfloat_ty>; 1943def int_amdgcn_flat_atomic_fmax : AMDGPUGlobalAtomicRtn<llvm_anyfloat_ty>; 1944 1945def int_amdgcn_mfma_f32_32x32x4bf16_1k : AMDGPUMfmaIntrinsic<llvm_v32f32_ty, llvm_v4i16_ty>; 1946def int_amdgcn_mfma_f32_16x16x4bf16_1k : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v4i16_ty>; 1947def int_amdgcn_mfma_f32_4x4x4bf16_1k : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v4i16_ty>; 1948def int_amdgcn_mfma_f32_32x32x8bf16_1k : AMDGPUMfmaIntrinsic<llvm_v16f32_ty, llvm_v4i16_ty>; 1949def int_amdgcn_mfma_f32_16x16x16bf16_1k : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v4i16_ty>; 1950 1951def int_amdgcn_mfma_f64_16x16x4f64 : AMDGPUMfmaIntrinsic<llvm_v4f64_ty, llvm_double_ty>; 1952def int_amdgcn_mfma_f64_4x4x4f64 : AMDGPUMfmaIntrinsic<llvm_double_ty, llvm_double_ty>; 1953 1954//===----------------------------------------------------------------------===// 1955// Special Intrinsics for backend internal use only. No frontend 1956// should emit calls to these. 1957// ===----------------------------------------------------------------------===// 1958def int_amdgcn_if : Intrinsic<[llvm_i1_ty, llvm_anyint_ty], 1959 [llvm_i1_ty], [IntrConvergent, IntrWillReturn] 1960>; 1961 1962def int_amdgcn_else : Intrinsic<[llvm_i1_ty, llvm_anyint_ty], 1963 [llvm_anyint_ty], [IntrConvergent, IntrWillReturn] 1964>; 1965 1966def int_amdgcn_if_break : Intrinsic<[llvm_anyint_ty], 1967 [llvm_i1_ty, LLVMMatchType<0>], 1968 [IntrNoMem, IntrConvergent, IntrWillReturn] 1969>; 1970 1971def int_amdgcn_loop : Intrinsic<[llvm_i1_ty], 1972 [llvm_anyint_ty], [IntrConvergent, IntrWillReturn] 1973>; 1974 1975def int_amdgcn_end_cf : Intrinsic<[], [llvm_anyint_ty], 1976 [IntrConvergent, IntrWillReturn]>; 1977 1978// Represent unreachable in a divergent region. 1979def int_amdgcn_unreachable : Intrinsic<[], [], [IntrConvergent]>; 1980 1981// Emit 2.5 ulp, no denormal division. Should only be inserted by 1982// pass based on !fpmath metadata. 1983def int_amdgcn_fdiv_fast : Intrinsic< 1984 [llvm_float_ty], [llvm_float_ty, llvm_float_ty], 1985 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1986>; 1987 1988// Represent a relocation constant. 1989def int_amdgcn_reloc_constant : Intrinsic< 1990 [llvm_i32_ty], [llvm_metadata_ty], 1991 [IntrNoMem, IntrSpeculatable, IntrWillReturn] 1992>; 1993} 1994