1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
11 //
12 //===----------------------------------------------------------------------===//
13 //
14
15 #include "AMDGPUMCInstLower.h"
16 #include "AMDGPUAsmPrinter.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "MCTargetDesc/AMDGPUInstPrinter.h"
19 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/IR/Constants.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/MC/MCCodeEmitter.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/MC/MCInst.h"
29 #include "llvm/MC/MCObjectStreamer.h"
30 #include "llvm/MC/MCStreamer.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/Format.h"
33 #include <algorithm>
34
35 using namespace llvm;
36
37 #include "AMDGPUGenMCPseudoLowering.inc"
38
AMDGPUMCInstLower(MCContext & ctx,const TargetSubtargetInfo & st,const AsmPrinter & ap)39 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx,
40 const TargetSubtargetInfo &st,
41 const AsmPrinter &ap):
42 Ctx(ctx), ST(st), AP(ap) { }
43
getVariantKind(unsigned MOFlags)44 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
45 switch (MOFlags) {
46 default:
47 return MCSymbolRefExpr::VK_None;
48 case SIInstrInfo::MO_GOTPCREL:
49 return MCSymbolRefExpr::VK_GOTPCREL;
50 case SIInstrInfo::MO_GOTPCREL32_LO:
51 return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO;
52 case SIInstrInfo::MO_GOTPCREL32_HI:
53 return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI;
54 case SIInstrInfo::MO_REL32_LO:
55 return MCSymbolRefExpr::VK_AMDGPU_REL32_LO;
56 case SIInstrInfo::MO_REL32_HI:
57 return MCSymbolRefExpr::VK_AMDGPU_REL32_HI;
58 case SIInstrInfo::MO_ABS32_LO:
59 return MCSymbolRefExpr::VK_AMDGPU_ABS32_LO;
60 case SIInstrInfo::MO_ABS32_HI:
61 return MCSymbolRefExpr::VK_AMDGPU_ABS32_HI;
62 }
63 }
64
lowerOperand(const MachineOperand & MO,MCOperand & MCOp) const65 bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
66 MCOperand &MCOp) const {
67 switch (MO.getType()) {
68 default:
69 break;
70 case MachineOperand::MO_Immediate:
71 MCOp = MCOperand::createImm(MO.getImm());
72 return true;
73 case MachineOperand::MO_Register:
74 MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
75 return true;
76 case MachineOperand::MO_MachineBasicBlock:
77 MCOp = MCOperand::createExpr(
78 MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx));
79 return true;
80 case MachineOperand::MO_GlobalAddress: {
81 const GlobalValue *GV = MO.getGlobal();
82 SmallString<128> SymbolName;
83 AP.getNameWithPrefix(SymbolName, GV);
84 MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
85 const MCExpr *Expr =
86 MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
87 int64_t Offset = MO.getOffset();
88 if (Offset != 0) {
89 Expr = MCBinaryExpr::createAdd(Expr,
90 MCConstantExpr::create(Offset, Ctx), Ctx);
91 }
92 MCOp = MCOperand::createExpr(Expr);
93 return true;
94 }
95 case MachineOperand::MO_ExternalSymbol: {
96 MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
97 Sym->setExternal(true);
98 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
99 MCOp = MCOperand::createExpr(Expr);
100 return true;
101 }
102 case MachineOperand::MO_RegisterMask:
103 // Regmasks are like implicit defs.
104 return false;
105 case MachineOperand::MO_MCSymbol:
106 if (MO.getTargetFlags() == SIInstrInfo::MO_FAR_BRANCH_OFFSET) {
107 MCSymbol *Sym = MO.getMCSymbol();
108 MCOp = MCOperand::createExpr(Sym->getVariableValue());
109 return true;
110 }
111 break;
112 }
113 llvm_unreachable("unknown operand type");
114 }
115
lower(const MachineInstr * MI,MCInst & OutMI) const116 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
117 unsigned Opcode = MI->getOpcode();
118 const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
119
120 // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
121 // need to select it to the subtarget specific version, and there's no way to
122 // do that with a single pseudo source operation.
123 if (Opcode == AMDGPU::S_SETPC_B64_return)
124 Opcode = AMDGPU::S_SETPC_B64;
125 else if (Opcode == AMDGPU::SI_CALL) {
126 // SI_CALL is just S_SWAPPC_B64 with an additional operand to track the
127 // called function (which we need to remove here).
128 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
129 MCOperand Dest, Src;
130 lowerOperand(MI->getOperand(0), Dest);
131 lowerOperand(MI->getOperand(1), Src);
132 OutMI.addOperand(Dest);
133 OutMI.addOperand(Src);
134 return;
135 } else if (Opcode == AMDGPU::SI_TCRETURN) {
136 // TODO: How to use branch immediate and avoid register+add?
137 Opcode = AMDGPU::S_SETPC_B64;
138 }
139
140 int MCOpcode = TII->pseudoToMCOpcode(Opcode);
141 if (MCOpcode == -1) {
142 LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
143 C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
144 "a target-specific version: " + Twine(MI->getOpcode()));
145 }
146
147 OutMI.setOpcode(MCOpcode);
148
149 for (const MachineOperand &MO : MI->explicit_operands()) {
150 MCOperand MCOp;
151 lowerOperand(MO, MCOp);
152 OutMI.addOperand(MCOp);
153 }
154
155 int FIIdx = AMDGPU::getNamedOperandIdx(MCOpcode, AMDGPU::OpName::fi);
156 if (FIIdx >= (int)OutMI.getNumOperands())
157 OutMI.addOperand(MCOperand::createImm(0));
158 }
159
lowerOperand(const MachineOperand & MO,MCOperand & MCOp) const160 bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO,
161 MCOperand &MCOp) const {
162 const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
163 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
164 return MCInstLowering.lowerOperand(MO, MCOp);
165 }
166
lowerConstant(const Constant * CV)167 const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV) {
168 if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
169 return E;
170 return AsmPrinter::lowerConstant(CV);
171 }
172
emitInstruction(const MachineInstr * MI)173 void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) {
174 if (emitPseudoExpansionLowering(*OutStreamer, MI))
175 return;
176
177 const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
178 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
179
180 StringRef Err;
181 if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
182 LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
183 C.emitError("Illegal instruction detected: " + Err);
184 MI->print(errs());
185 }
186
187 if (MI->isBundle()) {
188 const MachineBasicBlock *MBB = MI->getParent();
189 MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
190 while (I != MBB->instr_end() && I->isInsideBundle()) {
191 emitInstruction(&*I);
192 ++I;
193 }
194 } else {
195 // We don't want these pseudo instructions encoded. They are
196 // placeholder terminator instructions and should only be printed as
197 // comments.
198 if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
199 if (isVerbose())
200 OutStreamer->emitRawComment(" return to shader part epilog");
201 return;
202 }
203
204 if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
205 if (isVerbose())
206 OutStreamer->emitRawComment(" wave barrier");
207 return;
208 }
209
210 if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
211 if (isVerbose())
212 OutStreamer->emitRawComment(" divergent unreachable");
213 return;
214 }
215
216 if (MI->isMetaInstruction()) {
217 if (isVerbose())
218 OutStreamer->emitRawComment(" meta instruction");
219 return;
220 }
221
222 MCInst TmpInst;
223 MCInstLowering.lower(MI, TmpInst);
224 EmitToStreamer(*OutStreamer, TmpInst);
225
226 #ifdef EXPENSIVE_CHECKS
227 // Sanity-check getInstSizeInBytes on explicitly specified CPUs (it cannot
228 // work correctly for the generic CPU).
229 //
230 // The isPseudo check really shouldn't be here, but unfortunately there are
231 // some negative lit tests that depend on being able to continue through
232 // here even when pseudo instructions haven't been lowered.
233 //
234 // We also overestimate branch sizes with the offset bug.
235 if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU()) &&
236 (!STI.hasOffset3fBug() || !MI->isBranch())) {
237 SmallVector<MCFixup, 4> Fixups;
238 SmallVector<char, 16> CodeBytes;
239 raw_svector_ostream CodeStream(CodeBytes);
240
241 std::unique_ptr<MCCodeEmitter> InstEmitter(createSIMCCodeEmitter(
242 *STI.getInstrInfo(), *OutContext.getRegisterInfo(), OutContext));
243 InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI);
244
245 assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI));
246 }
247 #endif
248
249 if (DumpCodeInstEmitter) {
250 // Disassemble instruction/operands to text
251 DisasmLines.resize(DisasmLines.size() + 1);
252 std::string &DisasmLine = DisasmLines.back();
253 raw_string_ostream DisasmStream(DisasmLine);
254
255 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *STI.getInstrInfo(),
256 *STI.getRegisterInfo());
257 InstPrinter.printInst(&TmpInst, 0, StringRef(), STI, DisasmStream);
258
259 // Disassemble instruction/operands to hex representation.
260 SmallVector<MCFixup, 4> Fixups;
261 SmallVector<char, 16> CodeBytes;
262 raw_svector_ostream CodeStream(CodeBytes);
263
264 DumpCodeInstEmitter->encodeInstruction(
265 TmpInst, CodeStream, Fixups, MF->getSubtarget<MCSubtargetInfo>());
266 HexLines.resize(HexLines.size() + 1);
267 std::string &HexLine = HexLines.back();
268 raw_string_ostream HexStream(HexLine);
269
270 for (size_t i = 0; i < CodeBytes.size(); i += 4) {
271 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
272 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
273 }
274
275 DisasmStream.flush();
276 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
277 }
278 }
279 }
280