1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that RISCV uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 16 17 #include "RISCV.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/CodeGen/TargetLowering.h" 21 22 namespace llvm { 23 class RISCVSubtarget; 24 struct RISCVRegisterInfo; 25 namespace RISCVISD { 26 enum NodeType : unsigned { 27 FIRST_NUMBER = ISD::BUILTIN_OP_END, 28 RET_FLAG, 29 URET_FLAG, 30 SRET_FLAG, 31 MRET_FLAG, 32 CALL, 33 /// Select with condition operator - This selects between a true value and 34 /// a false value (ops #3 and #4) based on the boolean result of comparing 35 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 36 /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum. 37 /// The lhs and rhs are XLenVT integers. The true and false values can be 38 /// integer or floating point. 39 SELECT_CC, 40 BR_CC, 41 BuildPairF64, 42 SplitF64, 43 TAIL, 44 // Multiply high for signedxunsigned. 45 MULHSU, 46 // RV64I shifts, directly matching the semantics of the named RISC-V 47 // instructions. 48 SLLW, 49 SRAW, 50 SRLW, 51 // 32-bit operations from RV64M that can't be simply matched with a pattern 52 // at instruction selection time. These have undefined behavior for division 53 // by 0 or overflow (divw) like their target independent counterparts. 54 DIVW, 55 DIVUW, 56 REMUW, 57 // RV64IB rotates, directly matching the semantics of the named RISC-V 58 // instructions. 59 ROLW, 60 RORW, 61 // RV64IZbb bit counting instructions directly matching the semantics of the 62 // named RISC-V instructions. 63 CLZW, 64 CTZW, 65 // RV64IB/RV32IB funnel shifts, with the semantics of the named RISC-V 66 // instructions, but the same operand order as fshl/fshr intrinsics. 67 FSR, 68 FSL, 69 // RV64IB funnel shifts, with the semantics of the named RISC-V instructions, 70 // but the same operand order as fshl/fshr intrinsics. 71 FSRW, 72 FSLW, 73 // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as 74 // XLEN is the only legal integer width. 75 // 76 // FMV_H_X matches the semantics of the FMV.H.X. 77 // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result. 78 // FMV_W_X_RV64 matches the semantics of the FMV.W.X. 79 // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result. 80 // 81 // This is a more convenient semantic for producing dagcombines that remove 82 // unnecessary GPR->FPR->GPR moves. 83 FMV_H_X, 84 FMV_X_ANYEXTH, 85 FMV_W_X_RV64, 86 FMV_X_ANYEXTW_RV64, 87 // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and 88 // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of 89 // range inputs. These are used for FP_TO_S/UINT_SAT lowering. 90 FCVT_X_RTZ, 91 FCVT_XU_RTZ, 92 // FP to 32 bit int conversions for RV64. These are used to keep track of the 93 // result being sign extended to 64 bit. These saturate out of range inputs. 94 // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. 95 FCVT_W_RTZ_RV64, 96 FCVT_WU_RTZ_RV64, 97 // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target 98 // (returns (Lo, Hi)). It takes a chain operand. 99 READ_CYCLE_WIDE, 100 // Generalized Reverse and Generalized Or-Combine - directly matching the 101 // semantics of the named RISC-V instructions. Lowered as custom nodes as 102 // TableGen chokes when faced with commutative permutations in deeply-nested 103 // DAGs. Each node takes an input operand and a control operand and outputs a 104 // bit-manipulated version of input. All operands are i32 or XLenVT. 105 GREV, 106 GREVW, 107 GORC, 108 GORCW, 109 SHFL, 110 SHFLW, 111 UNSHFL, 112 UNSHFLW, 113 // Bit Compress/Decompress implement the generic bit extract and bit deposit 114 // functions. This operation is also referred to as bit gather/scatter, bit 115 // pack/unpack, parallel extract/deposit, compress/expand, or right 116 // compress/right expand. 117 BCOMPRESS, 118 BCOMPRESSW, 119 BDECOMPRESS, 120 BDECOMPRESSW, 121 // Vector Extension 122 // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand 123 // for the VL value to be used for the operation. 124 VMV_V_X_VL, 125 // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand 126 // for the VL value to be used for the operation. 127 VFMV_V_F_VL, 128 // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign 129 // extended from the vector element size. 130 VMV_X_S, 131 // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand. 132 VMV_S_X_VL, 133 // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand. 134 VFMV_S_F_VL, 135 // Splats an i64 scalar to a vector type (with element type i64) where the 136 // scalar is a sign-extended i32. 137 SPLAT_VECTOR_I64, 138 // Splats an 64-bit value that has been split into two i32 parts. This is 139 // expanded late to two scalar stores and a stride 0 vector load. 140 SPLAT_VECTOR_SPLIT_I64_VL, 141 // Read VLENB CSR 142 READ_VLENB, 143 // Truncates a RVV integer vector by one power-of-two. Carries both an extra 144 // mask and VL operand. 145 TRUNCATE_VECTOR_VL, 146 // Matches the semantics of vslideup/vslidedown. The first operand is the 147 // pass-thru operand, the second is the source vector, the third is the 148 // XLenVT index (either constant or non-constant), the fourth is the mask 149 // and the fifth the VL. 150 VSLIDEUP_VL, 151 VSLIDEDOWN_VL, 152 // Matches the semantics of vslide1up/slide1down. The first operand is the 153 // source vector, the second is the XLenVT scalar value. The third and fourth 154 // operands are the mask and VL operands. 155 VSLIDE1UP_VL, 156 VSLIDE1DOWN_VL, 157 // Matches the semantics of the vid.v instruction, with a mask and VL 158 // operand. 159 VID_VL, 160 // Matches the semantics of the vfcnvt.rod function (Convert double-width 161 // float to single-width float, rounding towards odd). Takes a double-width 162 // float vector and produces a single-width float vector. Also has a mask and 163 // VL operand. 164 VFNCVT_ROD_VL, 165 // These nodes match the semantics of the corresponding RVV vector reduction 166 // instructions. They produce a vector result which is the reduction 167 // performed over the second vector operand plus the first element of the 168 // third vector operand. The first operand is the pass-thru operand. The 169 // second operand is an unconstrained vector type, and the result, first, and 170 // third operand's types are expected to be the corresponding full-width 171 // LMUL=1 type for the second operand: 172 // nxv8i8 = vecreduce_add nxv8i8, nxv32i8, nxv8i8 173 // nxv2i32 = vecreduce_add nxv2i32, nxv8i32, nxv2i32 174 // The different in types does introduce extra vsetvli instructions but 175 // similarly it reduces the number of registers consumed per reduction. 176 // Also has a mask and VL operand. 177 VECREDUCE_ADD_VL, 178 VECREDUCE_UMAX_VL, 179 VECREDUCE_SMAX_VL, 180 VECREDUCE_UMIN_VL, 181 VECREDUCE_SMIN_VL, 182 VECREDUCE_AND_VL, 183 VECREDUCE_OR_VL, 184 VECREDUCE_XOR_VL, 185 VECREDUCE_FADD_VL, 186 VECREDUCE_SEQ_FADD_VL, 187 VECREDUCE_FMIN_VL, 188 VECREDUCE_FMAX_VL, 189 190 // Vector binary and unary ops with a mask as a third operand, and VL as a 191 // fourth operand. 192 // FIXME: Can we replace these with ISD::VP_*? 193 ADD_VL, 194 AND_VL, 195 MUL_VL, 196 OR_VL, 197 SDIV_VL, 198 SHL_VL, 199 SREM_VL, 200 SRA_VL, 201 SRL_VL, 202 SUB_VL, 203 UDIV_VL, 204 UREM_VL, 205 XOR_VL, 206 207 SADDSAT_VL, 208 UADDSAT_VL, 209 SSUBSAT_VL, 210 USUBSAT_VL, 211 212 FADD_VL, 213 FSUB_VL, 214 FMUL_VL, 215 FDIV_VL, 216 FNEG_VL, 217 FABS_VL, 218 FSQRT_VL, 219 FMA_VL, 220 FCOPYSIGN_VL, 221 SMIN_VL, 222 SMAX_VL, 223 UMIN_VL, 224 UMAX_VL, 225 FMINNUM_VL, 226 FMAXNUM_VL, 227 MULHS_VL, 228 MULHU_VL, 229 FP_TO_SINT_VL, 230 FP_TO_UINT_VL, 231 SINT_TO_FP_VL, 232 UINT_TO_FP_VL, 233 FP_ROUND_VL, 234 FP_EXTEND_VL, 235 236 // Widening instructions 237 VWMUL_VL, 238 VWMULU_VL, 239 240 // Vector compare producing a mask. Fourth operand is input mask. Fifth 241 // operand is VL. 242 SETCC_VL, 243 244 // Vector select with an additional VL operand. This operation is unmasked. 245 VSELECT_VL, 246 247 // Mask binary operators. 248 VMAND_VL, 249 VMOR_VL, 250 VMXOR_VL, 251 252 // Set mask vector to all zeros or ones. 253 VMCLR_VL, 254 VMSET_VL, 255 256 // Matches the semantics of vrgather.vx and vrgather.vv with an extra operand 257 // for VL. 258 VRGATHER_VX_VL, 259 VRGATHER_VV_VL, 260 VRGATHEREI16_VV_VL, 261 262 // Vector sign/zero extend with additional mask & VL operands. 263 VSEXT_VL, 264 VZEXT_VL, 265 266 // vpopc.m with additional mask and VL operands. 267 VPOPC_VL, 268 269 // Reads value of CSR. 270 // The first operand is a chain pointer. The second specifies address of the 271 // required CSR. Two results are produced, the read value and the new chain 272 // pointer. 273 READ_CSR, 274 // Write value to CSR. 275 // The first operand is a chain pointer, the second specifies address of the 276 // required CSR and the third is the value to write. The result is the new 277 // chain pointer. 278 WRITE_CSR, 279 // Read and write value of CSR. 280 // The first operand is a chain pointer, the second specifies address of the 281 // required CSR and the third is the value to write. Two results are produced, 282 // the value read before the modification and the new chain pointer. 283 SWAP_CSR, 284 285 // Memory opcodes start here. 286 VLE_VL = ISD::FIRST_TARGET_MEMORY_OPCODE, 287 VSE_VL, 288 289 // WARNING: Do not add anything in the end unless you want the node to 290 // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all 291 // opcodes will be thought as target memory ops! 292 }; 293 } // namespace RISCVISD 294 295 class RISCVTargetLowering : public TargetLowering { 296 const RISCVSubtarget &Subtarget; 297 298 public: 299 explicit RISCVTargetLowering(const TargetMachine &TM, 300 const RISCVSubtarget &STI); 301 getSubtarget()302 const RISCVSubtarget &getSubtarget() const { return Subtarget; } 303 304 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 305 MachineFunction &MF, 306 unsigned Intrinsic) const override; 307 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 308 unsigned AS, 309 Instruction *I = nullptr) const override; 310 bool isLegalICmpImmediate(int64_t Imm) const override; 311 bool isLegalAddImmediate(int64_t Imm) const override; 312 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 313 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 314 bool isZExtFree(SDValue Val, EVT VT2) const override; 315 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override; 316 bool isCheapToSpeculateCttz() const override; 317 bool isCheapToSpeculateCtlz() const override; 318 bool shouldSinkOperands(Instruction *I, 319 SmallVectorImpl<Use *> &Ops) const override; 320 bool isFPImmLegal(const APFloat &Imm, EVT VT, 321 bool ForCodeSize) const override; 322 softPromoteHalfType()323 bool softPromoteHalfType() const override { return true; } 324 325 /// Return the register type for a given MVT, ensuring vectors are treated 326 /// as a series of gpr sized integers. 327 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 328 EVT VT) const override; 329 330 /// Return the number of registers for a given MVT, ensuring vectors are 331 /// treated as a series of gpr sized integers. 332 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 333 CallingConv::ID CC, 334 EVT VT) const override; 335 336 /// Return true if the given shuffle mask can be codegen'd directly, or if it 337 /// should be stack expanded. 338 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 339 340 bool hasBitPreservingFPLogic(EVT VT) const override; 341 bool 342 shouldExpandBuildVectorWithShuffles(EVT VT, 343 unsigned DefinedValues) const override; 344 345 // Provide custom lowering hooks for some operations. 346 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 347 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 348 SelectionDAG &DAG) const override; 349 350 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 351 352 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 353 const APInt &DemandedElts, 354 TargetLoweringOpt &TLO) const override; 355 356 void computeKnownBitsForTargetNode(const SDValue Op, 357 KnownBits &Known, 358 const APInt &DemandedElts, 359 const SelectionDAG &DAG, 360 unsigned Depth) const override; 361 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 362 const APInt &DemandedElts, 363 const SelectionDAG &DAG, 364 unsigned Depth) const override; 365 366 // This method returns the name of a target specific DAG node. 367 const char *getTargetNodeName(unsigned Opcode) const override; 368 369 ConstraintType getConstraintType(StringRef Constraint) const override; 370 371 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override; 372 373 std::pair<unsigned, const TargetRegisterClass *> 374 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 375 StringRef Constraint, MVT VT) const override; 376 377 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 378 std::vector<SDValue> &Ops, 379 SelectionDAG &DAG) const override; 380 381 MachineBasicBlock * 382 EmitInstrWithCustomInserter(MachineInstr &MI, 383 MachineBasicBlock *BB) const override; 384 385 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 386 EVT VT) const override; 387 convertSetCCLogicToBitwiseLogic(EVT VT)388 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 389 return VT.isScalarInteger(); 390 } convertSelectOfConstantsToMath(EVT VT)391 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; } 392 shouldInsertFencesForAtomic(const Instruction * I)393 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 394 return isa<LoadInst>(I) || isa<StoreInst>(I); 395 } 396 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, 397 AtomicOrdering Ord) const override; 398 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, 399 AtomicOrdering Ord) const override; 400 401 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 402 EVT VT) const override; 403 getExtendForAtomicOps()404 ISD::NodeType getExtendForAtomicOps() const override { 405 return ISD::SIGN_EXTEND; 406 } 407 getExtendForAtomicCmpSwapArg()408 ISD::NodeType getExtendForAtomicCmpSwapArg() const override { 409 return ISD::SIGN_EXTEND; 410 } 411 shouldExpandShift(SelectionDAG & DAG,SDNode * N)412 bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override { 413 if (DAG.getMachineFunction().getFunction().hasMinSize()) 414 return false; 415 return true; 416 } 417 bool isDesirableToCommuteWithShift(const SDNode *N, 418 CombineLevel Level) const override; 419 420 /// If a physical register, this returns the register that receives the 421 /// exception address on entry to an EH pad. 422 Register 423 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 424 425 /// If a physical register, this returns the register that receives the 426 /// exception typeid on entry to a landing pad. 427 Register 428 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 429 430 bool shouldExtendTypeInLibCall(EVT Type) const override; 431 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; 432 433 /// Returns the register with the specified architectural or ABI name. This 434 /// method is necessary to lower the llvm.read_register.* and 435 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved 436 /// with the clang -ffixed-xX flag for access to be allowed. 437 Register getRegisterByName(const char *RegName, LLT VT, 438 const MachineFunction &MF) const override; 439 440 // Lower incoming arguments, copy physregs into vregs 441 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 442 bool IsVarArg, 443 const SmallVectorImpl<ISD::InputArg> &Ins, 444 const SDLoc &DL, SelectionDAG &DAG, 445 SmallVectorImpl<SDValue> &InVals) const override; 446 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 447 bool IsVarArg, 448 const SmallVectorImpl<ISD::OutputArg> &Outs, 449 LLVMContext &Context) const override; 450 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 451 const SmallVectorImpl<ISD::OutputArg> &Outs, 452 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 453 SelectionDAG &DAG) const override; 454 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 455 SmallVectorImpl<SDValue> &InVals) const override; 456 shouldConvertConstantLoadToIntImm(const APInt & Imm,Type * Ty)457 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 458 Type *Ty) const override { 459 return true; 460 } 461 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; shouldConsiderGEPOffsetSplit()462 bool shouldConsiderGEPOffsetSplit() const override { return true; } 463 464 bool decomposeMulByConstant(LLVMContext &Context, EVT VT, 465 SDValue C) const override; 466 467 bool isMulAddWithConstProfitable(const SDValue &AddNode, 468 const SDValue &ConstNode) const override; 469 470 TargetLowering::AtomicExpansionKind 471 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 472 Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, 473 Value *AlignedAddr, Value *Incr, 474 Value *Mask, Value *ShiftAmt, 475 AtomicOrdering Ord) const override; 476 TargetLowering::AtomicExpansionKind 477 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override; 478 Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, 479 AtomicCmpXchgInst *CI, 480 Value *AlignedAddr, Value *CmpVal, 481 Value *NewVal, Value *Mask, 482 AtomicOrdering Ord) const override; 483 484 /// Returns true if the target allows unaligned memory accesses of the 485 /// specified type. 486 bool allowsMisalignedMemoryAccesses( 487 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1), 488 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 489 bool *Fast = nullptr) const override; 490 491 bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, 492 SDValue Val, SDValue *Parts, 493 unsigned NumParts, MVT PartVT, 494 Optional<CallingConv::ID> CC) const override; 495 496 SDValue 497 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, 498 const SDValue *Parts, unsigned NumParts, 499 MVT PartVT, EVT ValueVT, 500 Optional<CallingConv::ID> CC) const override; 501 502 static RISCVII::VLMUL getLMUL(MVT VT); 503 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul); 504 static unsigned getSubregIndexByMVT(MVT VT, unsigned Index); 505 static unsigned getRegClassIDForVecVT(MVT VT); 506 static std::pair<unsigned, unsigned> 507 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, 508 unsigned InsertExtractIdx, 509 const RISCVRegisterInfo *TRI); 510 MVT getContainerForFixedLengthVector(MVT VT) const; 511 512 bool shouldRemoveExtendFromGSIndex(EVT VT) const override; 513 514 bool isLegalElementTypeForRVV(Type *ScalarTy) const; 515 516 private: 517 /// RISCVCCAssignFn - This target-specific function extends the default 518 /// CCValAssign with additional information used to lower RISC-V calling 519 /// conventions. 520 typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI, 521 unsigned ValNo, MVT ValVT, MVT LocVT, 522 CCValAssign::LocInfo LocInfo, 523 ISD::ArgFlagsTy ArgFlags, CCState &State, 524 bool IsFixed, bool IsRet, Type *OrigTy, 525 const RISCVTargetLowering &TLI, 526 Optional<unsigned> FirstMaskArgument); 527 528 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, 529 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet, 530 RISCVCCAssignFn Fn) const; 531 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo, 532 const SmallVectorImpl<ISD::OutputArg> &Outs, 533 bool IsRet, CallLoweringInfo *CLI, 534 RISCVCCAssignFn Fn) const; 535 536 template <class NodeTy> 537 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const; 538 539 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, 540 bool UseGOT) const; 541 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const; 542 543 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 544 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 545 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 546 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 547 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 548 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 549 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 550 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 551 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 552 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 553 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 554 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; 555 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const; 556 SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const; 557 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, 558 int64_t ExtTrueVal) const; 559 SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const; 560 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 561 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 562 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 563 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 564 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 565 SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const; 566 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 567 SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG, 568 bool IsVP) const; 569 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 570 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 571 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 572 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const; 573 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const; 574 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const; 575 SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const; 576 SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const; 577 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op, 578 SelectionDAG &DAG) const; 579 SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const; 580 SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const; 581 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const; 582 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const; 583 SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const; 584 SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG, 585 unsigned MaskOpc, 586 unsigned VecOpc) const; 587 SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const; 588 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op, 589 SelectionDAG &DAG) const; 590 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc, 591 bool HasMask = true) const; 592 SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc) const; 593 SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG, 594 unsigned ExtendOpc) const; 595 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 596 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 597 598 SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const; 599 SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const; 600 601 bool isEligibleForTailCallOptimization( 602 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, 603 const SmallVector<CCValAssign, 16> &ArgLocs) const; 604 605 /// Generate error diagnostics if any register used by CC has been marked 606 /// reserved. 607 void validateCCReservedRegs( 608 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs, 609 MachineFunction &MF) const; 610 611 bool useRVVForFixedLengthVectorVT(MVT VT) const; 612 613 MVT getVPExplicitVectorLengthTy() const override; 614 615 /// RVV code generation for fixed length vectors does not lower all 616 /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to 617 /// merge. However, merging them creates a BUILD_VECTOR that is just as 618 /// illegal as the original, thus leading to an infinite legalisation loop. 619 /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types, 620 /// this override can be removed. 621 bool mergeStoresAfterLegalization(EVT VT) const override; 622 }; 623 624 namespace RISCV { 625 // We use 64 bits as the known part in the scalable vector types. 626 static constexpr unsigned RVVBitsPerBlock = 64; 627 } // namespace RISCV 628 629 namespace RISCVVIntrinsicsTable { 630 631 struct RISCVVIntrinsicInfo { 632 unsigned IntrinsicID; 633 uint8_t SplatOperand; 634 }; 635 636 using namespace RISCV; 637 638 #define GET_RISCVVIntrinsicsTable_DECL 639 #include "RISCVGenSearchableTables.inc" 640 641 } // end namespace RISCVVIntrinsicsTable 642 643 } // end namespace llvm 644 645 #endif 646