1; RUN: llc < %s -march=avr | FileCheck %s
2
3define i8 @and8_reg_reg(i8 %a, i8 %b) {
4; CHECK-LABEL: and8_reg_reg:
5; CHECK: and r24, r22
6    %result = and i8 %a, %b
7    ret i8 %result
8}
9
10define i8 @and8_reg_imm(i8 %a) {
11; CHECK-LABEL: and8_reg_imm:
12; CHECK: andi r24, 5
13    %result = and i8 %a, 5
14    ret i8 %result
15}
16
17define i16 @and16_reg_reg(i16 %a, i16 %b) {
18; CHECK-LABEL: and16_reg_reg:
19; CHECK: and r24, r22
20; CHECK: and r25, r23
21    %result = and i16 %a, %b
22    ret i16 %result
23}
24
25define i16 @and16_reg_imm(i16 %a) {
26; CHECK-LABEL: and16_reg_imm:
27; CHECK: andi r24, 210
28; CHECK: andi r25, 4
29    %result = and i16 %a, 1234
30    ret i16 %result
31}
32
33define i32 @and32_reg_reg(i32 %a, i32 %b) {
34; CHECK-LABEL: and32_reg_reg:
35; CHECK: and r22, r18
36; CHECK: and r23, r19
37; CHECK: and r24, r20
38; CHECK: and r25, r21
39    %result = and i32 %a, %b
40    ret i32 %result
41}
42
43define i32 @and32_reg_imm(i32 %a) {
44; CHECK-LABEL: and32_reg_imm:
45; CHECK: andi r22, 21
46; CHECK: andi r23, 205
47; CHECK: andi r24, 91
48; CHECK: andi r25, 7
49    %result = and i32 %a, 123456789
50    ret i32 %result
51}
52
53define i64 @and64_reg_reg(i64 %a, i64 %b) {
54; CHECK-LABEL: and64_reg_reg:
55; CHECK: and r18, r10
56; CHECK: and r19, r11
57; CHECK: and r20, r12
58; CHECK: and r21, r13
59; CHECK: and r22, r14
60; CHECK: and r23, r15
61; CHECK: and r24, r16
62; CHECK: and r25, r17
63    %result = and i64 %a, %b
64    ret i64 %result
65}
66
67define i64 @and64_reg_imm(i64 %a) {
68; CHECK-LABEL: and64_reg_imm:
69; CHECK: andi r18, 253
70; Per PR 31345, we optimize away ANDI Rd, 0xff
71; CHECK-NOT: andi r19, 255
72; CHECK: andi r20, 155
73; CHECK: andi r21, 88
74; CHECK: andi r22, 76
75; CHECK: andi r23, 73
76; CHECK: andi r24, 31
77; CHECK: andi r25, 242
78    %result = and i64 %a, 17446744073709551613
79    ret i64 %result
80}
81
82