1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32IF %s 4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefix=RV64IF %s 6 7define float @select_fcmp_false(float %a, float %b) nounwind { 8; RV32IF-LABEL: select_fcmp_false: 9; RV32IF: # %bb.0: 10; RV32IF-NEXT: mv a0, a1 11; RV32IF-NEXT: ret 12; 13; RV64IF-LABEL: select_fcmp_false: 14; RV64IF: # %bb.0: 15; RV64IF-NEXT: mv a0, a1 16; RV64IF-NEXT: ret 17 %1 = fcmp false float %a, %b 18 %2 = select i1 %1, float %a, float %b 19 ret float %2 20} 21 22define float @select_fcmp_oeq(float %a, float %b) nounwind { 23; RV32IF-LABEL: select_fcmp_oeq: 24; RV32IF: # %bb.0: 25; RV32IF-NEXT: fmv.w.x ft1, a1 26; RV32IF-NEXT: fmv.w.x ft0, a0 27; RV32IF-NEXT: feq.s a0, ft0, ft1 28; RV32IF-NEXT: bnez a0, .LBB1_2 29; RV32IF-NEXT: # %bb.1: 30; RV32IF-NEXT: fmv.s ft0, ft1 31; RV32IF-NEXT: .LBB1_2: 32; RV32IF-NEXT: fmv.x.w a0, ft0 33; RV32IF-NEXT: ret 34; 35; RV64IF-LABEL: select_fcmp_oeq: 36; RV64IF: # %bb.0: 37; RV64IF-NEXT: fmv.w.x ft1, a1 38; RV64IF-NEXT: fmv.w.x ft0, a0 39; RV64IF-NEXT: feq.s a0, ft0, ft1 40; RV64IF-NEXT: bnez a0, .LBB1_2 41; RV64IF-NEXT: # %bb.1: 42; RV64IF-NEXT: fmv.s ft0, ft1 43; RV64IF-NEXT: .LBB1_2: 44; RV64IF-NEXT: fmv.x.w a0, ft0 45; RV64IF-NEXT: ret 46 %1 = fcmp oeq float %a, %b 47 %2 = select i1 %1, float %a, float %b 48 ret float %2 49} 50 51define float @select_fcmp_ogt(float %a, float %b) nounwind { 52; RV32IF-LABEL: select_fcmp_ogt: 53; RV32IF: # %bb.0: 54; RV32IF-NEXT: fmv.w.x ft0, a0 55; RV32IF-NEXT: fmv.w.x ft1, a1 56; RV32IF-NEXT: flt.s a0, ft1, ft0 57; RV32IF-NEXT: bnez a0, .LBB2_2 58; RV32IF-NEXT: # %bb.1: 59; RV32IF-NEXT: fmv.s ft0, ft1 60; RV32IF-NEXT: .LBB2_2: 61; RV32IF-NEXT: fmv.x.w a0, ft0 62; RV32IF-NEXT: ret 63; 64; RV64IF-LABEL: select_fcmp_ogt: 65; RV64IF: # %bb.0: 66; RV64IF-NEXT: fmv.w.x ft0, a0 67; RV64IF-NEXT: fmv.w.x ft1, a1 68; RV64IF-NEXT: flt.s a0, ft1, ft0 69; RV64IF-NEXT: bnez a0, .LBB2_2 70; RV64IF-NEXT: # %bb.1: 71; RV64IF-NEXT: fmv.s ft0, ft1 72; RV64IF-NEXT: .LBB2_2: 73; RV64IF-NEXT: fmv.x.w a0, ft0 74; RV64IF-NEXT: ret 75 %1 = fcmp ogt float %a, %b 76 %2 = select i1 %1, float %a, float %b 77 ret float %2 78} 79 80define float @select_fcmp_oge(float %a, float %b) nounwind { 81; RV32IF-LABEL: select_fcmp_oge: 82; RV32IF: # %bb.0: 83; RV32IF-NEXT: fmv.w.x ft0, a0 84; RV32IF-NEXT: fmv.w.x ft1, a1 85; RV32IF-NEXT: fle.s a0, ft1, ft0 86; RV32IF-NEXT: bnez a0, .LBB3_2 87; RV32IF-NEXT: # %bb.1: 88; RV32IF-NEXT: fmv.s ft0, ft1 89; RV32IF-NEXT: .LBB3_2: 90; RV32IF-NEXT: fmv.x.w a0, ft0 91; RV32IF-NEXT: ret 92; 93; RV64IF-LABEL: select_fcmp_oge: 94; RV64IF: # %bb.0: 95; RV64IF-NEXT: fmv.w.x ft0, a0 96; RV64IF-NEXT: fmv.w.x ft1, a1 97; RV64IF-NEXT: fle.s a0, ft1, ft0 98; RV64IF-NEXT: bnez a0, .LBB3_2 99; RV64IF-NEXT: # %bb.1: 100; RV64IF-NEXT: fmv.s ft0, ft1 101; RV64IF-NEXT: .LBB3_2: 102; RV64IF-NEXT: fmv.x.w a0, ft0 103; RV64IF-NEXT: ret 104 %1 = fcmp oge float %a, %b 105 %2 = select i1 %1, float %a, float %b 106 ret float %2 107} 108 109define float @select_fcmp_olt(float %a, float %b) nounwind { 110; RV32IF-LABEL: select_fcmp_olt: 111; RV32IF: # %bb.0: 112; RV32IF-NEXT: fmv.w.x ft1, a1 113; RV32IF-NEXT: fmv.w.x ft0, a0 114; RV32IF-NEXT: flt.s a0, ft0, ft1 115; RV32IF-NEXT: bnez a0, .LBB4_2 116; RV32IF-NEXT: # %bb.1: 117; RV32IF-NEXT: fmv.s ft0, ft1 118; RV32IF-NEXT: .LBB4_2: 119; RV32IF-NEXT: fmv.x.w a0, ft0 120; RV32IF-NEXT: ret 121; 122; RV64IF-LABEL: select_fcmp_olt: 123; RV64IF: # %bb.0: 124; RV64IF-NEXT: fmv.w.x ft1, a1 125; RV64IF-NEXT: fmv.w.x ft0, a0 126; RV64IF-NEXT: flt.s a0, ft0, ft1 127; RV64IF-NEXT: bnez a0, .LBB4_2 128; RV64IF-NEXT: # %bb.1: 129; RV64IF-NEXT: fmv.s ft0, ft1 130; RV64IF-NEXT: .LBB4_2: 131; RV64IF-NEXT: fmv.x.w a0, ft0 132; RV64IF-NEXT: ret 133 %1 = fcmp olt float %a, %b 134 %2 = select i1 %1, float %a, float %b 135 ret float %2 136} 137 138define float @select_fcmp_ole(float %a, float %b) nounwind { 139; RV32IF-LABEL: select_fcmp_ole: 140; RV32IF: # %bb.0: 141; RV32IF-NEXT: fmv.w.x ft1, a1 142; RV32IF-NEXT: fmv.w.x ft0, a0 143; RV32IF-NEXT: fle.s a0, ft0, ft1 144; RV32IF-NEXT: bnez a0, .LBB5_2 145; RV32IF-NEXT: # %bb.1: 146; RV32IF-NEXT: fmv.s ft0, ft1 147; RV32IF-NEXT: .LBB5_2: 148; RV32IF-NEXT: fmv.x.w a0, ft0 149; RV32IF-NEXT: ret 150; 151; RV64IF-LABEL: select_fcmp_ole: 152; RV64IF: # %bb.0: 153; RV64IF-NEXT: fmv.w.x ft1, a1 154; RV64IF-NEXT: fmv.w.x ft0, a0 155; RV64IF-NEXT: fle.s a0, ft0, ft1 156; RV64IF-NEXT: bnez a0, .LBB5_2 157; RV64IF-NEXT: # %bb.1: 158; RV64IF-NEXT: fmv.s ft0, ft1 159; RV64IF-NEXT: .LBB5_2: 160; RV64IF-NEXT: fmv.x.w a0, ft0 161; RV64IF-NEXT: ret 162 %1 = fcmp ole float %a, %b 163 %2 = select i1 %1, float %a, float %b 164 ret float %2 165} 166 167define float @select_fcmp_one(float %a, float %b) nounwind { 168; RV32IF-LABEL: select_fcmp_one: 169; RV32IF: # %bb.0: 170; RV32IF-NEXT: fmv.w.x ft1, a1 171; RV32IF-NEXT: fmv.w.x ft0, a0 172; RV32IF-NEXT: flt.s a0, ft0, ft1 173; RV32IF-NEXT: flt.s a1, ft1, ft0 174; RV32IF-NEXT: or a0, a1, a0 175; RV32IF-NEXT: bnez a0, .LBB6_2 176; RV32IF-NEXT: # %bb.1: 177; RV32IF-NEXT: fmv.s ft0, ft1 178; RV32IF-NEXT: .LBB6_2: 179; RV32IF-NEXT: fmv.x.w a0, ft0 180; RV32IF-NEXT: ret 181; 182; RV64IF-LABEL: select_fcmp_one: 183; RV64IF: # %bb.0: 184; RV64IF-NEXT: fmv.w.x ft1, a1 185; RV64IF-NEXT: fmv.w.x ft0, a0 186; RV64IF-NEXT: flt.s a0, ft0, ft1 187; RV64IF-NEXT: flt.s a1, ft1, ft0 188; RV64IF-NEXT: or a0, a1, a0 189; RV64IF-NEXT: bnez a0, .LBB6_2 190; RV64IF-NEXT: # %bb.1: 191; RV64IF-NEXT: fmv.s ft0, ft1 192; RV64IF-NEXT: .LBB6_2: 193; RV64IF-NEXT: fmv.x.w a0, ft0 194; RV64IF-NEXT: ret 195 %1 = fcmp one float %a, %b 196 %2 = select i1 %1, float %a, float %b 197 ret float %2 198} 199 200define float @select_fcmp_ord(float %a, float %b) nounwind { 201; RV32IF-LABEL: select_fcmp_ord: 202; RV32IF: # %bb.0: 203; RV32IF-NEXT: fmv.w.x ft0, a0 204; RV32IF-NEXT: fmv.w.x ft1, a1 205; RV32IF-NEXT: feq.s a0, ft1, ft1 206; RV32IF-NEXT: feq.s a1, ft0, ft0 207; RV32IF-NEXT: and a0, a1, a0 208; RV32IF-NEXT: bnez a0, .LBB7_2 209; RV32IF-NEXT: # %bb.1: 210; RV32IF-NEXT: fmv.s ft0, ft1 211; RV32IF-NEXT: .LBB7_2: 212; RV32IF-NEXT: fmv.x.w a0, ft0 213; RV32IF-NEXT: ret 214; 215; RV64IF-LABEL: select_fcmp_ord: 216; RV64IF: # %bb.0: 217; RV64IF-NEXT: fmv.w.x ft0, a0 218; RV64IF-NEXT: fmv.w.x ft1, a1 219; RV64IF-NEXT: feq.s a0, ft1, ft1 220; RV64IF-NEXT: feq.s a1, ft0, ft0 221; RV64IF-NEXT: and a0, a1, a0 222; RV64IF-NEXT: bnez a0, .LBB7_2 223; RV64IF-NEXT: # %bb.1: 224; RV64IF-NEXT: fmv.s ft0, ft1 225; RV64IF-NEXT: .LBB7_2: 226; RV64IF-NEXT: fmv.x.w a0, ft0 227; RV64IF-NEXT: ret 228 %1 = fcmp ord float %a, %b 229 %2 = select i1 %1, float %a, float %b 230 ret float %2 231} 232 233define float @select_fcmp_ueq(float %a, float %b) nounwind { 234; RV32IF-LABEL: select_fcmp_ueq: 235; RV32IF: # %bb.0: 236; RV32IF-NEXT: fmv.w.x ft1, a1 237; RV32IF-NEXT: fmv.w.x ft0, a0 238; RV32IF-NEXT: flt.s a0, ft0, ft1 239; RV32IF-NEXT: flt.s a1, ft1, ft0 240; RV32IF-NEXT: or a0, a1, a0 241; RV32IF-NEXT: beqz a0, .LBB8_2 242; RV32IF-NEXT: # %bb.1: 243; RV32IF-NEXT: fmv.s ft0, ft1 244; RV32IF-NEXT: .LBB8_2: 245; RV32IF-NEXT: fmv.x.w a0, ft0 246; RV32IF-NEXT: ret 247; 248; RV64IF-LABEL: select_fcmp_ueq: 249; RV64IF: # %bb.0: 250; RV64IF-NEXT: fmv.w.x ft1, a1 251; RV64IF-NEXT: fmv.w.x ft0, a0 252; RV64IF-NEXT: flt.s a0, ft0, ft1 253; RV64IF-NEXT: flt.s a1, ft1, ft0 254; RV64IF-NEXT: or a0, a1, a0 255; RV64IF-NEXT: beqz a0, .LBB8_2 256; RV64IF-NEXT: # %bb.1: 257; RV64IF-NEXT: fmv.s ft0, ft1 258; RV64IF-NEXT: .LBB8_2: 259; RV64IF-NEXT: fmv.x.w a0, ft0 260; RV64IF-NEXT: ret 261 %1 = fcmp ueq float %a, %b 262 %2 = select i1 %1, float %a, float %b 263 ret float %2 264} 265 266define float @select_fcmp_ugt(float %a, float %b) nounwind { 267; RV32IF-LABEL: select_fcmp_ugt: 268; RV32IF: # %bb.0: 269; RV32IF-NEXT: fmv.w.x ft1, a1 270; RV32IF-NEXT: fmv.w.x ft0, a0 271; RV32IF-NEXT: fle.s a0, ft0, ft1 272; RV32IF-NEXT: beqz a0, .LBB9_2 273; RV32IF-NEXT: # %bb.1: 274; RV32IF-NEXT: fmv.s ft0, ft1 275; RV32IF-NEXT: .LBB9_2: 276; RV32IF-NEXT: fmv.x.w a0, ft0 277; RV32IF-NEXT: ret 278; 279; RV64IF-LABEL: select_fcmp_ugt: 280; RV64IF: # %bb.0: 281; RV64IF-NEXT: fmv.w.x ft1, a1 282; RV64IF-NEXT: fmv.w.x ft0, a0 283; RV64IF-NEXT: fle.s a0, ft0, ft1 284; RV64IF-NEXT: beqz a0, .LBB9_2 285; RV64IF-NEXT: # %bb.1: 286; RV64IF-NEXT: fmv.s ft0, ft1 287; RV64IF-NEXT: .LBB9_2: 288; RV64IF-NEXT: fmv.x.w a0, ft0 289; RV64IF-NEXT: ret 290 %1 = fcmp ugt float %a, %b 291 %2 = select i1 %1, float %a, float %b 292 ret float %2 293} 294 295define float @select_fcmp_uge(float %a, float %b) nounwind { 296; RV32IF-LABEL: select_fcmp_uge: 297; RV32IF: # %bb.0: 298; RV32IF-NEXT: fmv.w.x ft1, a1 299; RV32IF-NEXT: fmv.w.x ft0, a0 300; RV32IF-NEXT: flt.s a0, ft0, ft1 301; RV32IF-NEXT: beqz a0, .LBB10_2 302; RV32IF-NEXT: # %bb.1: 303; RV32IF-NEXT: fmv.s ft0, ft1 304; RV32IF-NEXT: .LBB10_2: 305; RV32IF-NEXT: fmv.x.w a0, ft0 306; RV32IF-NEXT: ret 307; 308; RV64IF-LABEL: select_fcmp_uge: 309; RV64IF: # %bb.0: 310; RV64IF-NEXT: fmv.w.x ft1, a1 311; RV64IF-NEXT: fmv.w.x ft0, a0 312; RV64IF-NEXT: flt.s a0, ft0, ft1 313; RV64IF-NEXT: beqz a0, .LBB10_2 314; RV64IF-NEXT: # %bb.1: 315; RV64IF-NEXT: fmv.s ft0, ft1 316; RV64IF-NEXT: .LBB10_2: 317; RV64IF-NEXT: fmv.x.w a0, ft0 318; RV64IF-NEXT: ret 319 %1 = fcmp uge float %a, %b 320 %2 = select i1 %1, float %a, float %b 321 ret float %2 322} 323 324define float @select_fcmp_ult(float %a, float %b) nounwind { 325; RV32IF-LABEL: select_fcmp_ult: 326; RV32IF: # %bb.0: 327; RV32IF-NEXT: fmv.w.x ft0, a0 328; RV32IF-NEXT: fmv.w.x ft1, a1 329; RV32IF-NEXT: fle.s a0, ft1, ft0 330; RV32IF-NEXT: beqz a0, .LBB11_2 331; RV32IF-NEXT: # %bb.1: 332; RV32IF-NEXT: fmv.s ft0, ft1 333; RV32IF-NEXT: .LBB11_2: 334; RV32IF-NEXT: fmv.x.w a0, ft0 335; RV32IF-NEXT: ret 336; 337; RV64IF-LABEL: select_fcmp_ult: 338; RV64IF: # %bb.0: 339; RV64IF-NEXT: fmv.w.x ft0, a0 340; RV64IF-NEXT: fmv.w.x ft1, a1 341; RV64IF-NEXT: fle.s a0, ft1, ft0 342; RV64IF-NEXT: beqz a0, .LBB11_2 343; RV64IF-NEXT: # %bb.1: 344; RV64IF-NEXT: fmv.s ft0, ft1 345; RV64IF-NEXT: .LBB11_2: 346; RV64IF-NEXT: fmv.x.w a0, ft0 347; RV64IF-NEXT: ret 348 %1 = fcmp ult float %a, %b 349 %2 = select i1 %1, float %a, float %b 350 ret float %2 351} 352 353define float @select_fcmp_ule(float %a, float %b) nounwind { 354; RV32IF-LABEL: select_fcmp_ule: 355; RV32IF: # %bb.0: 356; RV32IF-NEXT: fmv.w.x ft0, a0 357; RV32IF-NEXT: fmv.w.x ft1, a1 358; RV32IF-NEXT: flt.s a0, ft1, ft0 359; RV32IF-NEXT: beqz a0, .LBB12_2 360; RV32IF-NEXT: # %bb.1: 361; RV32IF-NEXT: fmv.s ft0, ft1 362; RV32IF-NEXT: .LBB12_2: 363; RV32IF-NEXT: fmv.x.w a0, ft0 364; RV32IF-NEXT: ret 365; 366; RV64IF-LABEL: select_fcmp_ule: 367; RV64IF: # %bb.0: 368; RV64IF-NEXT: fmv.w.x ft0, a0 369; RV64IF-NEXT: fmv.w.x ft1, a1 370; RV64IF-NEXT: flt.s a0, ft1, ft0 371; RV64IF-NEXT: beqz a0, .LBB12_2 372; RV64IF-NEXT: # %bb.1: 373; RV64IF-NEXT: fmv.s ft0, ft1 374; RV64IF-NEXT: .LBB12_2: 375; RV64IF-NEXT: fmv.x.w a0, ft0 376; RV64IF-NEXT: ret 377 %1 = fcmp ule float %a, %b 378 %2 = select i1 %1, float %a, float %b 379 ret float %2 380} 381 382define float @select_fcmp_une(float %a, float %b) nounwind { 383; RV32IF-LABEL: select_fcmp_une: 384; RV32IF: # %bb.0: 385; RV32IF-NEXT: fmv.w.x ft1, a1 386; RV32IF-NEXT: fmv.w.x ft0, a0 387; RV32IF-NEXT: feq.s a0, ft0, ft1 388; RV32IF-NEXT: beqz a0, .LBB13_2 389; RV32IF-NEXT: # %bb.1: 390; RV32IF-NEXT: fmv.s ft0, ft1 391; RV32IF-NEXT: .LBB13_2: 392; RV32IF-NEXT: fmv.x.w a0, ft0 393; RV32IF-NEXT: ret 394; 395; RV64IF-LABEL: select_fcmp_une: 396; RV64IF: # %bb.0: 397; RV64IF-NEXT: fmv.w.x ft1, a1 398; RV64IF-NEXT: fmv.w.x ft0, a0 399; RV64IF-NEXT: feq.s a0, ft0, ft1 400; RV64IF-NEXT: beqz a0, .LBB13_2 401; RV64IF-NEXT: # %bb.1: 402; RV64IF-NEXT: fmv.s ft0, ft1 403; RV64IF-NEXT: .LBB13_2: 404; RV64IF-NEXT: fmv.x.w a0, ft0 405; RV64IF-NEXT: ret 406 %1 = fcmp une float %a, %b 407 %2 = select i1 %1, float %a, float %b 408 ret float %2 409} 410 411define float @select_fcmp_uno(float %a, float %b) nounwind { 412; RV32IF-LABEL: select_fcmp_uno: 413; RV32IF: # %bb.0: 414; RV32IF-NEXT: fmv.w.x ft0, a0 415; RV32IF-NEXT: fmv.w.x ft1, a1 416; RV32IF-NEXT: feq.s a0, ft1, ft1 417; RV32IF-NEXT: feq.s a1, ft0, ft0 418; RV32IF-NEXT: and a0, a1, a0 419; RV32IF-NEXT: beqz a0, .LBB14_2 420; RV32IF-NEXT: # %bb.1: 421; RV32IF-NEXT: fmv.s ft0, ft1 422; RV32IF-NEXT: .LBB14_2: 423; RV32IF-NEXT: fmv.x.w a0, ft0 424; RV32IF-NEXT: ret 425; 426; RV64IF-LABEL: select_fcmp_uno: 427; RV64IF: # %bb.0: 428; RV64IF-NEXT: fmv.w.x ft0, a0 429; RV64IF-NEXT: fmv.w.x ft1, a1 430; RV64IF-NEXT: feq.s a0, ft1, ft1 431; RV64IF-NEXT: feq.s a1, ft0, ft0 432; RV64IF-NEXT: and a0, a1, a0 433; RV64IF-NEXT: beqz a0, .LBB14_2 434; RV64IF-NEXT: # %bb.1: 435; RV64IF-NEXT: fmv.s ft0, ft1 436; RV64IF-NEXT: .LBB14_2: 437; RV64IF-NEXT: fmv.x.w a0, ft0 438; RV64IF-NEXT: ret 439 %1 = fcmp uno float %a, %b 440 %2 = select i1 %1, float %a, float %b 441 ret float %2 442} 443 444define float @select_fcmp_true(float %a, float %b) nounwind { 445; RV32IF-LABEL: select_fcmp_true: 446; RV32IF: # %bb.0: 447; RV32IF-NEXT: ret 448; 449; RV64IF-LABEL: select_fcmp_true: 450; RV64IF: # %bb.0: 451; RV64IF-NEXT: ret 452 %1 = fcmp true float %a, %b 453 %2 = select i1 %1, float %a, float %b 454 ret float %2 455} 456 457; Ensure that ISel succeeds for a select+fcmp that has an i32 result type. 458define i32 @i32_select_fcmp_oeq(float %a, float %b, i32 %c, i32 %d) nounwind { 459; RV32IF-LABEL: i32_select_fcmp_oeq: 460; RV32IF: # %bb.0: 461; RV32IF-NEXT: fmv.w.x ft0, a1 462; RV32IF-NEXT: fmv.w.x ft1, a0 463; RV32IF-NEXT: feq.s a1, ft1, ft0 464; RV32IF-NEXT: mv a0, a2 465; RV32IF-NEXT: bnez a1, .LBB16_2 466; RV32IF-NEXT: # %bb.1: 467; RV32IF-NEXT: mv a0, a3 468; RV32IF-NEXT: .LBB16_2: 469; RV32IF-NEXT: ret 470; 471; RV64IF-LABEL: i32_select_fcmp_oeq: 472; RV64IF: # %bb.0: 473; RV64IF-NEXT: fmv.w.x ft0, a1 474; RV64IF-NEXT: fmv.w.x ft1, a0 475; RV64IF-NEXT: feq.s a1, ft1, ft0 476; RV64IF-NEXT: mv a0, a2 477; RV64IF-NEXT: bnez a1, .LBB16_2 478; RV64IF-NEXT: # %bb.1: 479; RV64IF-NEXT: mv a0, a3 480; RV64IF-NEXT: .LBB16_2: 481; RV64IF-NEXT: ret 482 %1 = fcmp oeq float %a, %b 483 %2 = select i1 %1, i32 %c, i32 %d 484 ret i32 %2 485} 486