1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=thumb-eabi -mattr=+v6 | FileCheck %s --check-prefixes=THUMBV6
3
4define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
5; THUMBV6-LABEL: muloti_test:
6; THUMBV6:       @ %bb.0: @ %start
7; THUMBV6-NEXT:    .save {r4, r5, r6, r7, lr}
8; THUMBV6-NEXT:    push {r4, r5, r6, r7, lr}
9; THUMBV6-NEXT:    .pad #60
10; THUMBV6-NEXT:    sub sp, #60
11; THUMBV6-NEXT:    mov r6, r3
12; THUMBV6-NEXT:    mov r1, r2
13; THUMBV6-NEXT:    str r2, [sp, #52] @ 4-byte Spill
14; THUMBV6-NEXT:    mov r4, r0
15; THUMBV6-NEXT:    str r0, [sp, #40] @ 4-byte Spill
16; THUMBV6-NEXT:    ldr r2, [sp, #88]
17; THUMBV6-NEXT:    str r2, [sp, #48] @ 4-byte Spill
18; THUMBV6-NEXT:    movs r5, #0
19; THUMBV6-NEXT:    mov r0, r1
20; THUMBV6-NEXT:    mov r1, r5
21; THUMBV6-NEXT:    mov r3, r5
22; THUMBV6-NEXT:    bl __aeabi_lmul
23; THUMBV6-NEXT:    str r1, [sp, #28] @ 4-byte Spill
24; THUMBV6-NEXT:    str r0, [r4]
25; THUMBV6-NEXT:    ldr r2, [sp, #96]
26; THUMBV6-NEXT:    str r2, [sp, #36] @ 4-byte Spill
27; THUMBV6-NEXT:    mov r4, r6
28; THUMBV6-NEXT:    str r6, [sp, #56] @ 4-byte Spill
29; THUMBV6-NEXT:    mov r0, r6
30; THUMBV6-NEXT:    mov r1, r5
31; THUMBV6-NEXT:    mov r3, r5
32; THUMBV6-NEXT:    bl __aeabi_lmul
33; THUMBV6-NEXT:    str r0, [sp, #44] @ 4-byte Spill
34; THUMBV6-NEXT:    mov r7, r1
35; THUMBV6-NEXT:    subs r0, r1, #1
36; THUMBV6-NEXT:    sbcs r7, r0
37; THUMBV6-NEXT:    ldr r0, [sp, #100]
38; THUMBV6-NEXT:    str r0, [sp, #32] @ 4-byte Spill
39; THUMBV6-NEXT:    mov r1, r5
40; THUMBV6-NEXT:    ldr r6, [sp, #52] @ 4-byte Reload
41; THUMBV6-NEXT:    mov r2, r6
42; THUMBV6-NEXT:    mov r3, r5
43; THUMBV6-NEXT:    bl __aeabi_lmul
44; THUMBV6-NEXT:    str r0, [sp, #24] @ 4-byte Spill
45; THUMBV6-NEXT:    subs r2, r1, #1
46; THUMBV6-NEXT:    sbcs r1, r2
47; THUMBV6-NEXT:    subs r2, r4, #1
48; THUMBV6-NEXT:    mov r3, r4
49; THUMBV6-NEXT:    sbcs r3, r2
50; THUMBV6-NEXT:    ldr r4, [sp, #32] @ 4-byte Reload
51; THUMBV6-NEXT:    subs r2, r4, #1
52; THUMBV6-NEXT:    sbcs r4, r2
53; THUMBV6-NEXT:    ands r4, r3
54; THUMBV6-NEXT:    orrs r4, r1
55; THUMBV6-NEXT:    orrs r4, r7
56; THUMBV6-NEXT:    ldr r0, [sp, #44] @ 4-byte Reload
57; THUMBV6-NEXT:    ldr r1, [sp, #24] @ 4-byte Reload
58; THUMBV6-NEXT:    adds r7, r1, r0
59; THUMBV6-NEXT:    ldr r0, [sp, #36] @ 4-byte Reload
60; THUMBV6-NEXT:    mov r1, r5
61; THUMBV6-NEXT:    mov r2, r6
62; THUMBV6-NEXT:    mov r3, r5
63; THUMBV6-NEXT:    bl __aeabi_lmul
64; THUMBV6-NEXT:    str r0, [sp, #24] @ 4-byte Spill
65; THUMBV6-NEXT:    adds r0, r1, r7
66; THUMBV6-NEXT:    str r0, [sp, #20] @ 4-byte Spill
67; THUMBV6-NEXT:    mov r0, r5
68; THUMBV6-NEXT:    adcs r0, r5
69; THUMBV6-NEXT:    orrs r0, r4
70; THUMBV6-NEXT:    str r0, [sp, #16] @ 4-byte Spill
71; THUMBV6-NEXT:    ldr r0, [sp, #92]
72; THUMBV6-NEXT:    str r0, [sp, #44] @ 4-byte Spill
73; THUMBV6-NEXT:    ldr r7, [sp, #80]
74; THUMBV6-NEXT:    mov r1, r5
75; THUMBV6-NEXT:    mov r2, r7
76; THUMBV6-NEXT:    mov r3, r5
77; THUMBV6-NEXT:    bl __aeabi_lmul
78; THUMBV6-NEXT:    str r0, [sp, #12] @ 4-byte Spill
79; THUMBV6-NEXT:    mov r4, r1
80; THUMBV6-NEXT:    subs r0, r1, #1
81; THUMBV6-NEXT:    sbcs r4, r0
82; THUMBV6-NEXT:    ldr r6, [sp, #84]
83; THUMBV6-NEXT:    mov r0, r6
84; THUMBV6-NEXT:    mov r1, r5
85; THUMBV6-NEXT:    ldr r2, [sp, #48] @ 4-byte Reload
86; THUMBV6-NEXT:    mov r3, r5
87; THUMBV6-NEXT:    bl __aeabi_lmul
88; THUMBV6-NEXT:    str r0, [sp, #4] @ 4-byte Spill
89; THUMBV6-NEXT:    subs r2, r1, #1
90; THUMBV6-NEXT:    sbcs r1, r2
91; THUMBV6-NEXT:    ldr r3, [sp, #44] @ 4-byte Reload
92; THUMBV6-NEXT:    subs r2, r3, #1
93; THUMBV6-NEXT:    sbcs r3, r2
94; THUMBV6-NEXT:    str r6, [sp, #8] @ 4-byte Spill
95; THUMBV6-NEXT:    subs r2, r6, #1
96; THUMBV6-NEXT:    sbcs r6, r2
97; THUMBV6-NEXT:    ands r6, r3
98; THUMBV6-NEXT:    orrs r6, r1
99; THUMBV6-NEXT:    orrs r6, r4
100; THUMBV6-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
101; THUMBV6-NEXT:    ldr r1, [sp, #4] @ 4-byte Reload
102; THUMBV6-NEXT:    adds r0, r1, r0
103; THUMBV6-NEXT:    str r0, [sp, #4] @ 4-byte Spill
104; THUMBV6-NEXT:    mov r0, r7
105; THUMBV6-NEXT:    mov r1, r5
106; THUMBV6-NEXT:    ldr r4, [sp, #48] @ 4-byte Reload
107; THUMBV6-NEXT:    mov r2, r4
108; THUMBV6-NEXT:    mov r3, r5
109; THUMBV6-NEXT:    bl __aeabi_lmul
110; THUMBV6-NEXT:    str r0, [sp, #12] @ 4-byte Spill
111; THUMBV6-NEXT:    ldr r0, [sp, #4] @ 4-byte Reload
112; THUMBV6-NEXT:    adds r0, r1, r0
113; THUMBV6-NEXT:    mov r1, r5
114; THUMBV6-NEXT:    adcs r1, r5
115; THUMBV6-NEXT:    orrs r1, r6
116; THUMBV6-NEXT:    ldr r3, [sp, #36] @ 4-byte Reload
117; THUMBV6-NEXT:    ldr r2, [sp, #32] @ 4-byte Reload
118; THUMBV6-NEXT:    orrs r3, r2
119; THUMBV6-NEXT:    subs r2, r3, #1
120; THUMBV6-NEXT:    sbcs r3, r2
121; THUMBV6-NEXT:    ldr r2, [sp, #8] @ 4-byte Reload
122; THUMBV6-NEXT:    orrs r7, r2
123; THUMBV6-NEXT:    subs r2, r7, #1
124; THUMBV6-NEXT:    sbcs r7, r2
125; THUMBV6-NEXT:    ands r7, r3
126; THUMBV6-NEXT:    orrs r7, r1
127; THUMBV6-NEXT:    ldr r1, [sp, #16] @ 4-byte Reload
128; THUMBV6-NEXT:    orrs r7, r1
129; THUMBV6-NEXT:    ldr r1, [sp, #24] @ 4-byte Reload
130; THUMBV6-NEXT:    ldr r2, [sp, #12] @ 4-byte Reload
131; THUMBV6-NEXT:    adds r1, r2, r1
132; THUMBV6-NEXT:    str r1, [sp, #32] @ 4-byte Spill
133; THUMBV6-NEXT:    ldr r1, [sp, #20] @ 4-byte Reload
134; THUMBV6-NEXT:    adcs r0, r1
135; THUMBV6-NEXT:    str r0, [sp, #36] @ 4-byte Spill
136; THUMBV6-NEXT:    ldr r0, [sp, #56] @ 4-byte Reload
137; THUMBV6-NEXT:    mov r1, r5
138; THUMBV6-NEXT:    mov r2, r4
139; THUMBV6-NEXT:    mov r3, r5
140; THUMBV6-NEXT:    bl __aeabi_lmul
141; THUMBV6-NEXT:    mov r4, r1
142; THUMBV6-NEXT:    ldr r1, [sp, #28] @ 4-byte Reload
143; THUMBV6-NEXT:    adds r6, r0, r1
144; THUMBV6-NEXT:    adcs r4, r5
145; THUMBV6-NEXT:    ldr r0, [sp, #52] @ 4-byte Reload
146; THUMBV6-NEXT:    mov r1, r5
147; THUMBV6-NEXT:    ldr r2, [sp, #44] @ 4-byte Reload
148; THUMBV6-NEXT:    mov r3, r5
149; THUMBV6-NEXT:    bl __aeabi_lmul
150; THUMBV6-NEXT:    adds r0, r0, r6
151; THUMBV6-NEXT:    ldr r2, [sp, #40] @ 4-byte Reload
152; THUMBV6-NEXT:    str r0, [r2, #4]
153; THUMBV6-NEXT:    adcs r1, r5
154; THUMBV6-NEXT:    adds r0, r4, r1
155; THUMBV6-NEXT:    str r0, [sp, #28] @ 4-byte Spill
156; THUMBV6-NEXT:    mov r6, r5
157; THUMBV6-NEXT:    adcs r6, r5
158; THUMBV6-NEXT:    ldr r0, [sp, #56] @ 4-byte Reload
159; THUMBV6-NEXT:    mov r1, r5
160; THUMBV6-NEXT:    ldr r4, [sp, #44] @ 4-byte Reload
161; THUMBV6-NEXT:    mov r2, r4
162; THUMBV6-NEXT:    mov r3, r5
163; THUMBV6-NEXT:    bl __aeabi_lmul
164; THUMBV6-NEXT:    ldr r2, [sp, #28] @ 4-byte Reload
165; THUMBV6-NEXT:    adds r0, r0, r2
166; THUMBV6-NEXT:    str r0, [sp, #28] @ 4-byte Spill
167; THUMBV6-NEXT:    adcs r1, r6
168; THUMBV6-NEXT:    str r1, [sp, #24] @ 4-byte Spill
169; THUMBV6-NEXT:    ldr r0, [sp, #48] @ 4-byte Reload
170; THUMBV6-NEXT:    mov r1, r4
171; THUMBV6-NEXT:    mov r2, r5
172; THUMBV6-NEXT:    mov r3, r5
173; THUMBV6-NEXT:    bl __aeabi_lmul
174; THUMBV6-NEXT:    mov r6, r0
175; THUMBV6-NEXT:    mov r4, r1
176; THUMBV6-NEXT:    ldr r0, [sp, #52] @ 4-byte Reload
177; THUMBV6-NEXT:    ldr r1, [sp, #56] @ 4-byte Reload
178; THUMBV6-NEXT:    mov r2, r5
179; THUMBV6-NEXT:    mov r3, r5
180; THUMBV6-NEXT:    bl __aeabi_lmul
181; THUMBV6-NEXT:    adds r0, r0, r6
182; THUMBV6-NEXT:    adcs r1, r4
183; THUMBV6-NEXT:    ldr r2, [sp, #28] @ 4-byte Reload
184; THUMBV6-NEXT:    adds r0, r2, r0
185; THUMBV6-NEXT:    ldr r2, [sp, #24] @ 4-byte Reload
186; THUMBV6-NEXT:    adcs r1, r2
187; THUMBV6-NEXT:    ldr r2, [sp, #32] @ 4-byte Reload
188; THUMBV6-NEXT:    adds r0, r0, r2
189; THUMBV6-NEXT:    ldr r2, [sp, #40] @ 4-byte Reload
190; THUMBV6-NEXT:    str r0, [r2, #8]
191; THUMBV6-NEXT:    ldr r0, [sp, #36] @ 4-byte Reload
192; THUMBV6-NEXT:    adcs r1, r0
193; THUMBV6-NEXT:    str r1, [r2, #12]
194; THUMBV6-NEXT:    adcs r5, r5
195; THUMBV6-NEXT:    orrs r5, r7
196; THUMBV6-NEXT:    movs r0, #1
197; THUMBV6-NEXT:    ands r0, r5
198; THUMBV6-NEXT:    strb r0, [r2, #16]
199; THUMBV6-NEXT:    add sp, #60
200; THUMBV6-NEXT:    pop {r4, r5, r6, r7, pc}
201start:
202  %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
203  %1 = extractvalue { i128, i1 } %0, 0
204  %2 = extractvalue { i128, i1 } %0, 1
205  %3 = zext i1 %2 to i8
206  %4 = insertvalue { i128, i8 } undef, i128 %1, 0
207  %5 = insertvalue { i128, i8 } %4, i8 %3, 1
208  ret { i128, i8 } %5
209}
210
211; Function Attrs: nounwind readnone speculatable
212declare { i128, i1 } @llvm.umul.with.overflow.i128(i128, i128) #1
213
214attributes #0 = { nounwind readnone uwtable }
215attributes #1 = { nounwind readnone speculatable }
216attributes #2 = { nounwind }
217