1//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9class DspMMRel;
10
11def Dsp2MicroMips : InstrMapping {
12  let FilterClass = "DspMMRel";
13  // Instructions with the same BaseOpcode and isNVStore values form a row.
14  let RowFields = ["BaseOpcode"];
15  // Instructions with the same predicate sense form a column.
16  let ColFields = ["Arch"];
17  // The key column is the unpredicated instructions.
18  let KeyCol = ["dsp"];
19  // Value columns are PredSense=true and PredSense=false
20  let ValueCols = [["dsp"], ["mmdsp"]];
21}
22
23def HasDSP : Predicate<"Subtarget->hasDSP()">,
24             AssemblerPredicate<"FeatureDSP">;
25def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
26               AssemblerPredicate<"FeatureDSPR2">;
27def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
28               AssemblerPredicate<"FeatureDSPR3">;
29
30class ISA_DSPR2 {
31  list<Predicate> ASEPredicate = [HasDSPR2];
32}
33
34class ISA_DSPR3 {
35  list<Predicate> ASEPredicate = [HasDSPR3];
36}
37
38// Fields.
39class Field6<bits<6> val> {
40  bits<6> V = val;
41}
42
43def SPECIAL3_OPCODE : Field6<0b011111>;
44def REGIMM_OPCODE : Field6<0b000001>;
45
46class DSPInst<string opstr = "">
47    : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
48  let ASEPredicate = [HasDSP];
49  string BaseOpcode = opstr;
50  string Arch = "dsp";
51}
52
53class PseudoDSP<dag outs, dag ins, list<dag> pattern,
54                InstrItinClass itin = IIPseudo>
55    : MipsPseudo<outs, ins, pattern, itin> {
56  let ASEPredicate = [HasDSP];
57}
58
59class DSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
60    : InstAlias<Asm, Result, Emit>, PredicateControl {
61  let ASEPredicate = [HasDSP];
62}
63
64// ADDU.QB sub-class format.
65class ADDU_QB_FMT<bits<5> op> : DSPInst {
66  bits<5> rd;
67  bits<5> rs;
68  bits<5> rt;
69
70  let Opcode = SPECIAL3_OPCODE.V;
71
72  let Inst{25-21} = rs;
73  let Inst{20-16} = rt;
74  let Inst{15-11} = rd;
75  let Inst{10-6}  = op;
76  let Inst{5-0}   = 0b010000;
77}
78
79class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
80  bits<5> rd;
81  bits<5> rs;
82
83  let Opcode = SPECIAL3_OPCODE.V;
84
85  let Inst{25-21} = rs;
86  let Inst{20-16} = 0;
87  let Inst{15-11} = rd;
88  let Inst{10-6}  = op;
89  let Inst{5-0}   = 0b010000;
90}
91
92// CMPU.EQ.QB sub-class format.
93class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
94  bits<5> rs;
95  bits<5> rt;
96
97  let Opcode = SPECIAL3_OPCODE.V;
98
99  let Inst{25-21} = rs;
100  let Inst{20-16} = rt;
101  let Inst{15-11} = 0;
102  let Inst{10-6}  = op;
103  let Inst{5-0}   = 0b010001;
104}
105
106class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
107  bits<5> rs;
108  bits<5> rt;
109  bits<5> rd;
110
111  let Opcode = SPECIAL3_OPCODE.V;
112
113  let Inst{25-21} = rs;
114  let Inst{20-16} = rt;
115  let Inst{15-11} = rd;
116  let Inst{10-6}  = op;
117  let Inst{5-0}   = 0b010001;
118}
119
120class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
121  bits<5> rs;
122  bits<5> rt;
123  bits<5> sa;
124
125  let Opcode = SPECIAL3_OPCODE.V;
126
127  let Inst{25-21} = rs;
128  let Inst{20-16} = rt;
129  let Inst{15-11} = sa;
130  let Inst{10-6}  = op;
131  let Inst{5-0}   = 0b010001;
132}
133
134// ABSQ_S.PH sub-class format.
135class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
136  bits<5> rd;
137  bits<5> rt;
138
139  let Opcode = SPECIAL3_OPCODE.V;
140
141  let Inst{25-21} = 0;
142  let Inst{20-16} = rt;
143  let Inst{15-11} = rd;
144  let Inst{10-6}  = op;
145  let Inst{5-0}   = 0b010010;
146}
147
148
149class REPL_FMT<bits<5> op> : DSPInst {
150  bits<5> rd;
151  bits<10> imm;
152
153  let Opcode = SPECIAL3_OPCODE.V;
154
155  let Inst{25-16} = imm;
156  let Inst{15-11} = rd;
157  let Inst{10-6}  = op;
158  let Inst{5-0}   = 0b010010;
159}
160
161// SHLL.QB sub-class format.
162class SHLL_QB_FMT<bits<5> op> : DSPInst {
163  bits<5> rd;
164  bits<5> rt;
165  bits<5> rs_sa;
166
167  let Opcode = SPECIAL3_OPCODE.V;
168
169  let Inst{25-21} = rs_sa;
170  let Inst{20-16} = rt;
171  let Inst{15-11} = rd;
172  let Inst{10-6}  = op;
173  let Inst{5-0}   = 0b010011;
174}
175
176// LX sub-class format.
177class LX_FMT<bits<5> op> : DSPInst {
178  bits<5> rd;
179  bits<5> base;
180  bits<5> index;
181
182  let Opcode = SPECIAL3_OPCODE.V;
183
184  let Inst{25-21} = base;
185  let Inst{20-16} = index;
186  let Inst{15-11} = rd;
187  let Inst{10-6}  = op;
188  let Inst{5-0} = 0b001010;
189}
190
191// ADDUH.QB sub-class format.
192class ADDUH_QB_FMT<bits<5> op> : DSPInst {
193  bits<5> rd;
194  bits<5> rs;
195  bits<5> rt;
196
197  let Opcode = SPECIAL3_OPCODE.V;
198
199  let Inst{25-21} = rs;
200  let Inst{20-16} = rt;
201  let Inst{15-11} = rd;
202  let Inst{10-6} = op;
203  let Inst{5-0} = 0b011000;
204}
205
206// APPEND sub-class format.
207class APPEND_FMT<bits<5> op> : DSPInst {
208  bits<5> rt;
209  bits<5> rs;
210  bits<5> sa;
211
212  let Opcode = SPECIAL3_OPCODE.V;
213
214  let Inst{25-21} = rs;
215  let Inst{20-16} = rt;
216  let Inst{15-11} = sa;
217  let Inst{10-6} = op;
218  let Inst{5-0} = 0b110001;
219}
220
221// DPA.W.PH sub-class format.
222class DPA_W_PH_FMT<bits<5> op> : DSPInst {
223  bits<2> ac;
224  bits<5> rs;
225  bits<5> rt;
226
227  let Opcode = SPECIAL3_OPCODE.V;
228
229  let Inst{25-21} = rs;
230  let Inst{20-16} = rt;
231  let Inst{15-13} = 0;
232  let Inst{12-11} = ac;
233  let Inst{10-6}  = op;
234  let Inst{5-0} = 0b110000;
235}
236
237// MULT sub-class format.
238class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
239  bits<2> ac;
240  bits<5> rs;
241  bits<5> rt;
242
243  let Opcode = opcode;
244
245  let Inst{25-21} = rs;
246  let Inst{20-16} = rt;
247  let Inst{15-13} = 0;
248  let Inst{12-11} = ac;
249  let Inst{10-6}  = 0;
250  let Inst{5-0} = funct;
251}
252
253// MFHI sub-class format.
254class MFHI_FMT<bits<6> funct> : DSPInst {
255  bits<5> rd;
256  bits<2> ac;
257
258  let Inst{31-26} = 0;
259  let Inst{25-23} = 0;
260  let Inst{22-21} = ac;
261  let Inst{20-16} = 0;
262  let Inst{15-11} = rd;
263  let Inst{10-6} = 0;
264  let Inst{5-0} = funct;
265}
266
267// MTHI sub-class format.
268class MTHI_FMT<bits<6> funct> : DSPInst {
269  bits<5> rs;
270  bits<2> ac;
271
272  let Inst{31-26} = 0;
273  let Inst{25-21} = rs;
274  let Inst{20-13} = 0;
275  let Inst{12-11} = ac;
276  let Inst{10-6} = 0;
277  let Inst{5-0} = funct;
278}
279
280// EXTR.W sub-class format (type 1).
281class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
282  bits<5> rt;
283  bits<2> ac;
284  bits<5> shift_rs;
285
286  let Opcode = SPECIAL3_OPCODE.V;
287
288  let Inst{25-21} = shift_rs;
289  let Inst{20-16} = rt;
290  let Inst{15-13} = 0;
291  let Inst{12-11} = ac;
292  let Inst{10-6} = op;
293  let Inst{5-0} = 0b111000;
294}
295
296// SHILO sub-class format.
297class SHILO_R1_FMT<bits<5> op> : DSPInst {
298  bits<2> ac;
299  bits<6> shift;
300
301  let Opcode = SPECIAL3_OPCODE.V;
302
303  let Inst{25-20} = shift;
304  let Inst{19-13} = 0;
305  let Inst{12-11} = ac;
306  let Inst{10-6} = op;
307  let Inst{5-0} = 0b111000;
308}
309
310class SHILO_R2_FMT<bits<5> op> : DSPInst {
311  bits<2> ac;
312  bits<5> rs;
313
314  let Opcode = SPECIAL3_OPCODE.V;
315
316  let Inst{25-21} = rs;
317  let Inst{20-13} = 0;
318  let Inst{12-11} = ac;
319  let Inst{10-6} = op;
320  let Inst{5-0} = 0b111000;
321}
322
323class RDDSP_FMT<bits<5> op> : DSPInst {
324  bits<5> rd;
325  bits<10> mask;
326
327  let Opcode = SPECIAL3_OPCODE.V;
328
329  let Inst{25-16} = mask;
330  let Inst{15-11} = rd;
331  let Inst{10-6} = op;
332  let Inst{5-0} = 0b111000;
333}
334
335class WRDSP_FMT<bits<5> op> : DSPInst {
336  bits<5> rs;
337  bits<10> mask;
338
339  let Opcode = SPECIAL3_OPCODE.V;
340
341  let Inst{25-21} = rs;
342  let Inst{20-11} = mask;
343  let Inst{10-6} = op;
344  let Inst{5-0} = 0b111000;
345}
346
347class BPOSGE32_FMT<bits<5> op> : DSPInst {
348  bits<16> offset;
349
350  let Opcode = REGIMM_OPCODE.V;
351
352  let Inst{25-21} = 0;
353  let Inst{20-16} = op;
354  let Inst{15-0} = offset;
355}
356
357// INSV sub-class format.
358class INSV_FMT<bits<6> op> : DSPInst {
359  bits<5> rt;
360  bits<5> rs;
361
362  let Opcode = SPECIAL3_OPCODE.V;
363
364  let Inst{25-21} = rs;
365  let Inst{20-16} = rt;
366  let Inst{15-6} = 0;
367  let Inst{5-0} = op;
368}
369