1; RUN: llc -march=hexagon -filetype=obj < %s -o - | llvm-objdump -d - | FileCheck %s
2
3; CHECK-LABEL: f0:
4; CHECK: r{{[1-9]}}:{{[0-9]}} = abs(r{{[1-9]}}:{{[0-9]}})
5define double @f0(double %a0) #0 {
6b0:
7  %v0 = alloca double, align 8
8  store double %a0, double* %v0, align 8
9  %v1 = load double, double* %v0, align 8
10  %v2 = fptosi double %v1 to i64
11  %v3 = call i64 @llvm.hexagon.A2.absp(i64 %v2)
12  %v4 = sitofp i64 %v3 to double
13  ret double %v4
14}
15
16declare i64 @llvm.hexagon.A2.absp(i64) #1
17
18; CHECK-LABEL: f1:
19; CHECK: r{{[1-9]}}:{{[0-9]}} = neg(r{{[1-9]}}:{{[0-9]}})
20define double @f1(double %a0) #0 {
21b0:
22  %v0 = alloca double, align 8
23  store double %a0, double* %v0, align 8
24  %v1 = load double, double* %v0, align 8
25  %v2 = fptosi double %v1 to i64
26  %v3 = call i64 @llvm.hexagon.A2.negp(i64 %v2)
27  %v4 = sitofp i64 %v3 to double
28  ret double %v4
29}
30
31declare i64 @llvm.hexagon.A2.negp(i64) #1
32
33; CHECK-LABEL: f2:
34; CHECK: r{{[1-9]}}:{{[0-9]}} = not(r{{[1-9]}}:{{[0-9]}})
35define double @f2(double %a0) #0 {
36b0:
37  %v0 = alloca double, align 8
38  store double %a0, double* %v0, align 8
39  %v1 = load double, double* %v0, align 8
40  %v2 = fptosi double %v1 to i64
41  %v3 = call i64 @llvm.hexagon.A2.notp(i64 %v2)
42  %v4 = sitofp i64 %v3 to double
43  ret double %v4
44}
45
46declare i64 @llvm.hexagon.A2.notp(i64) #1
47
48; CHECK-LABEL: f3:
49; CHECK: r{{[1-9]}}:{{[0-9]}} = interleave(r{{[1-9]}}:{{[0-9]}})
50define double @f3(double %a0) #0 {
51b0:
52  %v0 = alloca double, align 8
53  store double %a0, double* %v0, align 8
54  %v1 = load double, double* %v0, align 8
55  %v2 = fptosi double %v1 to i64
56  %v3 = call i64 @llvm.hexagon.S2.interleave(i64 %v2)
57  %v4 = sitofp i64 %v3 to double
58  ret double %v4
59}
60
61declare i64 @llvm.hexagon.S2.interleave(i64) #1
62
63; CHECK-LABEL: f4:
64; CHECK: r{{[1-9]}}:{{[0-9]}} = deinterleave(r{{[1-9]}}:{{[0-9]}})
65define double @f4(double %a0) #0 {
66b0:
67  %v0 = alloca double, align 8
68  store double %a0, double* %v0, align 8
69  %v1 = load double, double* %v0, align 8
70  %v2 = fptosi double %v1 to i64
71  %v3 = call i64 @llvm.hexagon.S2.deinterleave(i64 %v2)
72  %v4 = sitofp i64 %v3 to double
73  ret double %v4
74}
75
76declare i64 @llvm.hexagon.S2.deinterleave(i64) #1
77
78; CHECK-LABEL: f5:
79; CHECK: r{{[1-9]}}:{{[0-9]}} = vconj(r{{[1-9]}}:{{[0-9]}}):sat
80define double @f5(double %a0) #0 {
81b0:
82  %v0 = alloca double, align 8
83  store double %a0, double* %v0, align 8
84  %v1 = load double, double* %v0, align 8
85  %v2 = fptosi double %v1 to i64
86  %v3 = call i64 @llvm.hexagon.A2.vconj(i64 %v2)
87  %v4 = sitofp i64 %v3 to double
88  ret double %v4
89}
90
91declare i64 @llvm.hexagon.A2.vconj(i64) #1
92
93; CHECK-LABEL: f6:
94; CHECK: r{{[1-9]}}:{{[0-9]}} = vsathb(r{{[1-9]}}:{{[0-9]}})
95define double @f6(double %a0) #0 {
96b0:
97  %v0 = alloca double, align 8
98  store double %a0, double* %v0, align 8
99  %v1 = load double, double* %v0, align 8
100  %v2 = fptosi double %v1 to i64
101  %v3 = call i64 @llvm.hexagon.S2.vsathb.nopack(i64 %v2)
102  %v4 = sitofp i64 %v3 to double
103  ret double %v4
104}
105
106declare i64 @llvm.hexagon.S2.vsathb.nopack(i64) #1
107
108; CHECK-LABEL: f7:
109; CHECK: r{{[1-9]}}:{{[0-9]}} = vsathub(r{{[1-9]}}:{{[0-9]}})
110define double @f7(double %a0) #0 {
111b0:
112  %v0 = alloca double, align 8
113  store double %a0, double* %v0, align 8
114  %v1 = load double, double* %v0, align 8
115  %v2 = fptosi double %v1 to i64
116  %v3 = call i64 @llvm.hexagon.S2.vsathub.nopack(i64 %v2)
117  %v4 = sitofp i64 %v3 to double
118  ret double %v4
119}
120
121declare i64 @llvm.hexagon.S2.vsathub.nopack(i64) #1
122
123; CHECK-LABEL: f8:
124; CHECK: r{{[1-9]}}:{{[0-9]}} = vsatwh(r{{[1-9]}}:{{[0-9]}})
125define double @f8(double %a0) #0 {
126b0:
127  %v0 = alloca double, align 8
128  store double %a0, double* %v0, align 8
129  %v1 = load double, double* %v0, align 8
130  %v2 = fptosi double %v1 to i64
131  %v3 = call i64 @llvm.hexagon.S2.vsatwh.nopack(i64 %v2)
132  %v4 = sitofp i64 %v3 to double
133  ret double %v4
134}
135
136declare i64 @llvm.hexagon.S2.vsatwh.nopack(i64) #1
137
138; CHECK-LABEL: f9:
139; CHECK: r{{[1-9]}}:{{[0-9]}} = vsatwuh(r{{[1-9]}}:{{[0-9]}})
140define double @f9(double %a0) #0 {
141b0:
142  %v0 = alloca double, align 8
143  store double %a0, double* %v0, align 8
144  %v1 = load double, double* %v0, align 8
145  %v2 = fptosi double %v1 to i64
146  %v3 = call i64 @llvm.hexagon.S2.vsatwuh.nopack(i64 %v2)
147  %v4 = sitofp i64 %v3 to double
148  ret double %v4
149}
150
151declare i64 @llvm.hexagon.S2.vsatwuh.nopack(i64) #1
152
153; CHECK-LABEL: f10:
154; CHECK: r{{[1-9]}}:{{[0-9]}} = asr(r{{[1-9]}}:{{[0-9]}},#1)
155define double @f10(double %a0) #0 {
156b0:
157  %v0 = alloca double, align 8
158  store double %a0, double* %v0, align 8
159  %v1 = load double, double* %v0, align 8
160  %v2 = fptosi double %v1 to i64
161  %v3 = call i64 @llvm.hexagon.S2.asr.i.p(i64 %v2, i32 1)
162  %v4 = sitofp i64 %v3 to double
163  ret double %v4
164}
165
166declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32) #1
167
168; CHECK-LABEL: f11:
169; CHECK: r{{[1-9]}}:{{[0-9]}} = lsr(r{{[1-9]}}:{{[0-9]}},#1)
170define double @f11(double %a0) #0 {
171b0:
172  %v0 = alloca double, align 8
173  store double %a0, double* %v0, align 8
174  %v1 = load double, double* %v0, align 8
175  %v2 = fptosi double %v1 to i64
176  %v3 = call i64 @llvm.hexagon.S2.lsr.i.p(i64 %v2, i32 1)
177  %v4 = sitofp i64 %v3 to double
178  ret double %v4
179}
180
181declare i64 @llvm.hexagon.S2.lsr.i.p(i64, i32) #1
182
183; CHECK-LABEL: f12:
184; CHECK: r{{[1-9]}}:{{[0-9]}} = asl(r{{[1-9]}}:{{[0-9]}},#1)
185define double @f12(double %a0) #0 {
186b0:
187  %v0 = alloca double, align 8
188  store double %a0, double* %v0, align 8
189  %v1 = load double, double* %v0, align 8
190  %v2 = fptosi double %v1 to i64
191  %v3 = call i64 @llvm.hexagon.S2.asl.i.p(i64 %v2, i32 1)
192  %v4 = sitofp i64 %v3 to double
193  ret double %v4
194}
195
196declare i64 @llvm.hexagon.S2.asl.i.p(i64, i32) #1
197
198; CHECK-LABEL: f13:
199; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsh(r{{[1-9]}}:{{[0-9]}})
200define double @f13(double %a0) #0 {
201b0:
202  %v0 = alloca double, align 8
203  store double %a0, double* %v0, align 8
204  %v1 = load double, double* %v0, align 8
205  %v2 = fptosi double %v1 to i64
206  %v3 = call i64 @llvm.hexagon.A2.vabsh(i64 %v2)
207  %v4 = sitofp i64 %v3 to double
208  ret double %v4
209}
210
211declare i64 @llvm.hexagon.A2.vabsh(i64) #1
212
213; CHECK-LABEL: f14:
214; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsh(r{{[1-9]}}:{{[0-9]}}):sat
215define double @f14(double %a0) #0 {
216b0:
217  %v0 = alloca double, align 8
218  store double %a0, double* %v0, align 8
219  %v1 = load double, double* %v0, align 8
220  %v2 = fptosi double %v1 to i64
221  %v3 = call i64 @llvm.hexagon.A2.vabshsat(i64 %v2)
222  %v4 = sitofp i64 %v3 to double
223  ret double %v4
224}
225
226declare i64 @llvm.hexagon.A2.vabshsat(i64) #1
227
228; CHECK-LABEL: f15:
229; CHECK: r{{[0-9]}}:{{[0-9]}} = vasrh(r{{[1-9]}}:{{[0-9]}},#1)
230define double @f15(double %a0) #0 {
231b0:
232  %v0 = alloca double, align 8
233  store double %a0, double* %v0, align 8
234  %v1 = load double, double* %v0, align 8
235  %v2 = fptosi double %v1 to i64
236  %v3 = call i64 @llvm.hexagon.S2.asr.i.vh(i64 %v2, i32 1)
237  %v4 = sitofp i64 %v3 to double
238  ret double %v4
239}
240
241declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32) #1
242
243; CHECK-LABEL: f16:
244; CHECK: r{{[1-9]}}:{{[0-9]}} = vlsrh(r{{[1-9]}}:{{[0-9]}},#1)
245define double @f16(double %a0) #0 {
246b0:
247  %v0 = alloca double, align 8
248  store double %a0, double* %v0, align 8
249  %v1 = load double, double* %v0, align 8
250  %v2 = fptosi double %v1 to i64
251  %v3 = call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %v2, i32 1)
252  %v4 = sitofp i64 %v3 to double
253  ret double %v4
254}
255
256declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32) #1
257
258; CHECK-LABEL: f17:
259; CHECK: r{{[1-9]}}:{{[0-9]}} = vaslh(r{{[1-9]}}:{{[0-9]}},#1)
260define double @f17(double %a0) #0 {
261b0:
262  %v0 = alloca double, align 8
263  store double %a0, double* %v0, align 8
264  %v1 = load double, double* %v0, align 8
265  %v2 = fptosi double %v1 to i64
266  %v3 = call i64 @llvm.hexagon.S2.asl.i.vh(i64 %v2, i32 1)
267  %v4 = sitofp i64 %v3 to double
268  ret double %v4
269}
270
271declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) #1
272
273; CHECK-LABEL: f18:
274; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsw(r{{[1-9]}}:{{[0-9]}})
275define double @f18(double %a0) #0 {
276b0:
277  %v0 = alloca double, align 8
278  store double %a0, double* %v0, align 8
279  %v1 = load double, double* %v0, align 8
280  %v2 = fptosi double %v1 to i64
281  %v3 = call i64 @llvm.hexagon.A2.vabsw(i64 %v2)
282  %v4 = sitofp i64 %v3 to double
283  ret double %v4
284}
285
286declare i64 @llvm.hexagon.A2.vabsw(i64) #1
287
288; CHECK-LABEL: f19:
289; CHECK: r{{[1-9]}}:{{[0-9]}} = vabsw(r{{[1-9]}}:{{[0-9]}}):sat
290define double @f19(double %a0) #0 {
291b0:
292  %v0 = alloca double, align 8
293  store double %a0, double* %v0, align 8
294  %v1 = load double, double* %v0, align 8
295  %v2 = fptosi double %v1 to i64
296  %v3 = call i64 @llvm.hexagon.A2.vabswsat(i64 %v2)
297  %v4 = sitofp i64 %v3 to double
298  ret double %v4
299}
300
301declare i64 @llvm.hexagon.A2.vabswsat(i64) #1
302
303; CHECK-LABEL: f20:
304; CHECK: r{{[1-9]}}:{{[0-9]}} = vasrw(r{{[1-9]}}:{{[0-9]}},#1)
305define double @f20(double %a0) #0 {
306b0:
307  %v0 = alloca double, align 8
308  store double %a0, double* %v0, align 8
309  %v1 = load double, double* %v0, align 8
310  %v2 = fptosi double %v1 to i64
311  %v3 = call i64 @llvm.hexagon.S2.asr.i.vw(i64 %v2, i32 1)
312  %v4 = sitofp i64 %v3 to double
313  ret double %v4
314}
315
316declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) #1
317
318; CHECK-LABEL: f21:
319; CHECK: r{{[1-9]}}:{{[0-9]}} = vlsrw(r{{[1-9]}}:{{[0-9]}},#1)
320define double @f21(double %a0) #0 {
321b0:
322  %v0 = alloca double, align 8
323  store double %a0, double* %v0, align 8
324  %v1 = load double, double* %v0, align 8
325  %v2 = fptosi double %v1 to i64
326  %v3 = call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %v2, i32 1)
327  %v4 = sitofp i64 %v3 to double
328  ret double %v4
329}
330
331declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32) #1
332
333; CHECK-LABEL: f22:
334; CHECK: r{{[1-9]}}:{{[0-9]}} = vaslw(r{{[1-9]}}:{{[0-9]}},#1)
335define double @f22(double %a0) #0 {
336b0:
337  %v0 = alloca double, align 8
338  store double %a0, double* %v0, align 8
339  %v1 = load double, double* %v0, align 8
340  %v2 = fptosi double %v1 to i64
341  %v3 = call i64 @llvm.hexagon.S2.asl.i.vw(i64 %v2, i32 1)
342  %v4 = sitofp i64 %v3 to double
343  ret double %v4
344}
345
346declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) #1
347
348; CHECK-LABEL: f23:
349; CHECK: r{{[1-9]}}:{{[0-9]}} = brev(r{{[1-9]}}:{{[0-9]}})
350define double @f23(double %a0) #0 {
351b0:
352  %v0 = alloca double, align 8
353  store double %a0, double* %v0, align 8
354  %v1 = load double, double* %v0, align 8
355  %v2 = fptosi double %v1 to i64
356  %v3 = call i64 @llvm.hexagon.S2.brevp(i64 %v2)
357  %v4 = sitofp i64 %v3 to double
358  ret double %v4
359}
360
361declare i64 @llvm.hexagon.S2.brevp(i64) #1
362
363attributes #0 = { nounwind }
364attributes #1 = { nounwind readnone }
365