1; RUN: llc -march=hexagon -enable-pipeliner -verify-machineinstrs < %s
2; REQUIRES: asserts
3
4; This test fails in the machine verifier because the verifier thinks the
5; return register is undefined, and because there is a basic block that
6; ends with an unconditional branch that is not marked as a barrier.
7;
8; Enabling SWP exposes these bugs because the live variable analysis is
9; performed earlier than the process implicit def pass.  This ordering
10; causes the JMPR machine instruction to contain two R0 operands, one
11; with an undef and one with a kill flag.
12
13@g0 = common global i32 0, align 4
14
15; Function Attrs: nounwind
16define i32 @f0(i32 %a0) #0 {
17b0:
18  %v0 = icmp eq i32 %a0, 0
19  br i1 %v0, label %b2, label %b1
20
21b1:                                               ; preds = %b0
22  %v1 = tail call i32 bitcast (i32 (...)* @f1 to i32 (i32)*)(i32 %a0) #0
23  br label %b3
24
25b2:                                               ; preds = %b0
26  store i32 0, i32* @g0, align 4
27  br label %b3
28
29b3:                                               ; preds = %b2, %b1
30  ret i32 undef
31}
32
33declare i32 @f1(...)
34
35attributes #0 = { nounwind }
36