1; RUN: llc -relocation-model=static -verify-machineinstrs -O0 -mcpu=pwr7 -code-model=medium -filetype=obj -fast-isel=false %s -o - | \
2; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM %s
3; RUN: llc -relocation-model=static -verify-machineinstrs -O0 -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \
4; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE %s
5
6; Run jump table test separately since jump tables aren't generated at -O0.
7; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -code-model=medium -filetype=obj -fast-isel=false %s -o - | \
8; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM-JT %s
9; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \
10; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE-JT %s
11
12; FIXME: When asm-parse is available, could make this an assembly test.
13
14target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
15target triple = "powerpc64-unknown-linux-gnu"
16
17@ei = external global i32
18
19define signext i32 @test_external() nounwind {
20entry:
21  %0 = load i32, i32* @ei, align 4
22  %inc = add nsw i32 %0, 1
23  store i32 %inc, i32* @ei, align 4
24  ret i32 %0
25}
26
27; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
28; accessing external variable ei.
29;
30; MEDIUM:      Relocations [
31; MEDIUM:        Section {{.*}} .rela.text {
32; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]]
33; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]]
34;
35; LARGE:       Relocations [
36; LARGE:         Section {{.*}} .rela.text {
37; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]]
38; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]]
39
40@test_fn_static.si = internal global i32 0, align 4
41
42define signext i32 @test_fn_static() nounwind {
43entry:
44  %0 = load i32, i32* @test_fn_static.si, align 4
45  %inc = add nsw i32 %0, 1
46  store i32 %inc, i32* @test_fn_static.si, align 4
47  ret i32 %0
48}
49
50; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
51; accessing function-scoped variable si.
52;
53; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]]
54; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]]
55;
56; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
57; accessing function-scoped variable si.
58;
59; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]]
60; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM2]]
61
62@gi = global i32 5, align 4
63
64define signext i32 @test_file_static() nounwind {
65entry:
66  %0 = load i32, i32* @gi, align 4
67  %inc = add nsw i32 %0, 1
68  store i32 %inc, i32* @gi, align 4
69  ret i32 %0
70}
71
72; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
73; accessing file-scope variable gi.
74;
75; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]]
76; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM3]]
77;
78; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
79; accessing file-scope variable gi.
80;
81; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]]
82; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM3]]
83
84define double @test_double_const() nounwind {
85entry:
86  ret double 0x3F4FD4920B498CF0
87}
88
89; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
90; accessing a constant.
91;
92; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
93; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM4]]
94;
95; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
96; accessing a constant.
97;
98; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
99; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM4]]
100
101@ti = common global i32 0, align 4
102
103define signext i32 @test_tentative() nounwind {
104entry:
105  %0 = load i32, i32* @ti, align 4
106  %inc = add nsw i32 %0, 1
107  store i32 %inc, i32* @ti, align 4
108  ret i32 %0
109}
110
111; Verify generation of relocations foraccessing variable ti.
112;
113; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
114; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM6]]
115;
116; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
117; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
118
119define i8* @test_fnaddr() nounwind {
120entry:
121  %func = alloca i32 (i32)*, align 8
122  store i32 (i32)* @foo, i32 (i32)** %func, align 8
123  %0 = load i32 (i32)*, i32 (i32)** %func, align 8
124  %1 = bitcast i32 (i32)* %0 to i8*
125  ret i8* %1
126}
127
128declare signext i32 @foo(i32 signext)
129
130; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
131; accessing function address foo.
132;
133; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
134; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
135;
136; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
137; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
138
139
140define signext i32 @test_jump_table(i32 signext %i) nounwind {
141entry:
142  %i.addr = alloca i32, align 4
143  store i32 %i, i32* %i.addr, align 4
144  %0 = load i32, i32* %i.addr, align 4
145  switch i32 %0, label %sw.default [
146    i32 3, label %sw.bb
147    i32 4, label %sw.bb1
148    i32 5, label %sw.bb2
149    i32 6, label %sw.bb3
150  ]
151
152sw.default:                                       ; preds = %entry
153  br label %sw.epilog
154
155sw.bb:                                            ; preds = %entry
156  %1 = load i32, i32* %i.addr, align 4
157  %mul = mul nsw i32 %1, 7
158  store i32 %mul, i32* %i.addr, align 4
159  br label %sw.bb1
160
161sw.bb1:                                           ; preds = %entry, %sw.bb
162  %2 = load i32, i32* %i.addr, align 4
163  %dec = add nsw i32 %2, -1
164  store i32 %dec, i32* %i.addr, align 4
165  br label %sw.bb2
166
167sw.bb2:                                           ; preds = %entry, %sw.bb1
168  %3 = load i32, i32* %i.addr, align 4
169  %add = add nsw i32 %3, 3
170  store i32 %add, i32* %i.addr, align 4
171  br label %sw.bb3
172
173sw.bb3:                                           ; preds = %entry, %sw.bb2
174  %4 = load i32, i32* %i.addr, align 4
175  %shl = shl i32 %4, 1
176  store i32 %shl, i32* %i.addr, align 4
177  br label %sw.epilog
178
179sw.epilog:                                        ; preds = %sw.bb3, %sw.default
180  %5 = load i32, i32* %i.addr, align 4
181  ret i32 %5
182}
183
184; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
185; accessing a jump table address.
186;
187; MEDIUM-JT:      Relocations [
188; MEDIUM-JT:        Section ({{.*}}) .rela.text {
189; MEDIUM-JT-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM:[^ ]+]]
190; MEDIUM-JT-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM]]
191;
192; LARGE-JT:       Relocations [
193; LARGE-JT:         Section ({{.*}}) .rela.text {
194; LARGE-JT-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM:[^ ]+]]
195; LARGE-JT-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM]]
196