1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -mattr=+avx512cd,+avx512vl | FileCheck %s --check-prefixes=CHECK,X86 3; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512cd,+avx512vl | FileCheck %s --check-prefixes=CHECK,X64 4 5define <2 x i64> @test_mm_broadcastmb_epi64(<2 x i64> %a, <2 x i64> %b) { 6; X86-LABEL: test_mm_broadcastmb_epi64: 7; X86: # %bb.0: # %entry 8; X86-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 9; X86-NEXT: kmovw %k0, %eax 10; X86-NEXT: vmovd %eax, %xmm0 11; X86-NEXT: vpbroadcastq %xmm0, %xmm0 12; X86-NEXT: retl 13; 14; X64-LABEL: test_mm_broadcastmb_epi64: 15; X64: # %bb.0: # %entry 16; X64-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 17; X64-NEXT: vpbroadcastmb2q %k0, %xmm0 18; X64-NEXT: retq 19entry: 20 %0 = bitcast <2 x i64> %a to <4 x i32> 21 %1 = bitcast <2 x i64> %b to <4 x i32> 22 %2 = icmp eq <4 x i32> %0, %1 23 %3 = shufflevector <4 x i1> %2, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 24 %4 = bitcast <8 x i1> %3 to i8 25 %conv.i = zext i8 %4 to i64 26 %vecinit.i.i = insertelement <2 x i64> undef, i64 %conv.i, i32 0 27 %vecinit1.i.i = shufflevector <2 x i64> %vecinit.i.i, <2 x i64> undef, <2 x i32> zeroinitializer 28 ret <2 x i64> %vecinit1.i.i 29} 30 31define <4 x i64> @test_mm256_broadcastmb_epi64(<4 x i64> %a, <4 x i64> %b) { 32; X86-LABEL: test_mm256_broadcastmb_epi64: 33; X86: # %bb.0: # %entry 34; X86-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 35; X86-NEXT: kmovw %k0, %eax 36; X86-NEXT: vmovd %eax, %xmm0 37; X86-NEXT: vpbroadcastq %xmm0, %ymm0 38; X86-NEXT: retl 39; 40; X64-LABEL: test_mm256_broadcastmb_epi64: 41; X64: # %bb.0: # %entry 42; X64-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 43; X64-NEXT: vpbroadcastmb2q %k0, %ymm0 44; X64-NEXT: retq 45entry: 46 %0 = icmp eq <4 x i64> %a, %b 47 %1 = shufflevector <4 x i1> %0, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 48 %2 = bitcast <8 x i1> %1 to i8 49 %conv.i = zext i8 %2 to i64 50 %vecinit.i.i = insertelement <4 x i64> undef, i64 %conv.i, i32 0 51 %vecinit3.i.i = shufflevector <4 x i64> %vecinit.i.i, <4 x i64> undef, <4 x i32> zeroinitializer 52 ret <4 x i64> %vecinit3.i.i 53} 54 55define <2 x i64> @test_mm_broadcastmw_epi32(<8 x i64> %a, <8 x i64> %b) { 56; CHECK-LABEL: test_mm_broadcastmw_epi32: 57; CHECK: # %bb.0: # %entry 58; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 59; CHECK-NEXT: vpbroadcastmw2d %k0, %xmm0 60; CHECK-NEXT: vzeroupper 61; CHECK-NEXT: ret{{[l|q]}} 62entry: 63 %0 = bitcast <8 x i64> %a to <16 x i32> 64 %1 = bitcast <8 x i64> %b to <16 x i32> 65 %2 = icmp eq <16 x i32> %0, %1 66 %3 = bitcast <16 x i1> %2 to i16 67 %conv.i = zext i16 %3 to i32 68 %vecinit.i.i = insertelement <4 x i32> undef, i32 %conv.i, i32 0 69 %vecinit3.i.i = shufflevector <4 x i32> %vecinit.i.i, <4 x i32> undef, <4 x i32> zeroinitializer 70 %4 = bitcast <4 x i32> %vecinit3.i.i to <2 x i64> 71 ret <2 x i64> %4 72} 73 74define <4 x i64> @test_mm256_broadcastmw_epi32(<8 x i64> %a, <8 x i64> %b) { 75; CHECK-LABEL: test_mm256_broadcastmw_epi32: 76; CHECK: # %bb.0: # %entry 77; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 78; CHECK-NEXT: vpbroadcastmw2d %k0, %ymm0 79; CHECK-NEXT: ret{{[l|q]}} 80entry: 81 %0 = bitcast <8 x i64> %a to <16 x i32> 82 %1 = bitcast <8 x i64> %b to <16 x i32> 83 %2 = icmp eq <16 x i32> %0, %1 84 %3 = bitcast <16 x i1> %2 to i16 85 %conv.i = zext i16 %3 to i32 86 %vecinit.i.i = insertelement <8 x i32> undef, i32 %conv.i, i32 0 87 %vecinit7.i.i = shufflevector <8 x i32> %vecinit.i.i, <8 x i32> undef, <8 x i32> zeroinitializer 88 %4 = bitcast <8 x i32> %vecinit7.i.i to <4 x i64> 89 ret <4 x i64> %4 90} 91 92 93