1; RUN: llc -march=hexagon < %s | FileCheck %s
2; REQUIRES: asserts
3
4; Hexagon early if-conversion used to crash on this testcase due to not
5; recognizing vector predicate registers.
6
7target triple = "hexagon"
8
9; Check that the early if-conversion has not happened.
10
11; CHECK-LABEL: fred
12; CHECK: q{{[0-3]}} = not
13; CHECK: LBB
14; CHECK: if (q{{[0-3]}}) vmem
15define void @fred(i32 %a0) #0 {
16b1:
17  %v2 = tail call <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32 %a0) #2
18  br i1 undef, label %b3, label %b5
19
20b3:                                               ; preds = %b1
21  %v4 = tail call <128 x i1> @llvm.hexagon.V6.pred.not.128B(<128 x i1> %v2) #2
22  br label %b5
23
24b5:                                               ; preds = %b3, %b1
25  %v6 = phi <128 x i1> [ %v4, %b3 ], [ %v2, %b1 ]
26  tail call void asm sideeffect "if ($0) vmem($1) = $2;", "q,r,v,~{memory}"(<128 x i1> %v6, <32 x i32>* undef, <32 x i32> undef) #2
27  ret void
28}
29
30declare <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1
31declare <128 x i1> @llvm.hexagon.V6.pred.not.128B(<128 x i1>) #1
32
33attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
34attributes #1 = { nounwind readnone }
35attributes #2 = { nounwind }
36
37