1; RUN: llc -march=hexagon < %s | FileCheck %s
2;
3; Check that we do not generate v0 = vand(v1,v1)
4
5; CHECK-NOT: v{{[0-9]+}} = vand(v{{[0-9]+}},v{{[0-9]+}})
6
7; Function Attrs: nounwind
8define void @f0(i8* nocapture readonly %a0, i8* nocapture readonly %a1, i32 %a2, i8* nocapture %a3, i32 %a4, i32 %a5) #0 {
9b0:
10  %v0 = bitcast i8* %a1 to i64*
11  %v1 = load i64, i64* %v0, align 8, !tbaa !0
12  %v2 = shl i64 %v1, 8
13  %v3 = trunc i64 %v2 to i32
14  %v4 = trunc i64 %v1 to i32
15  %v5 = and i32 %v4, 16777215
16  %v6 = bitcast i8* %a0 to <16 x i32>*
17  %v7 = load <16 x i32>, <16 x i32>* %v6, align 64, !tbaa !4
18  %v8 = getelementptr inbounds i8, i8* %a0, i32 32
19  %v9 = bitcast i8* %v8 to <16 x i32>*
20  %v10 = load <16 x i32>, <16 x i32>* %v9, align 64, !tbaa !4
21  %v11 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v10, <16 x i32> %v7)
22  %v12 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 %v5, i32 0)
23  %v13 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 %v3, i32 0)
24  %v14 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v12)
25  %v15 = tail call <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32> %v14, <16 x i32> %v14, i32 %a2)
26  %v16 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v13)
27  %v17 = tail call <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32> %v16, <16 x i32> %v16, i32 %a2)
28  %v18 = getelementptr inbounds i8, i8* %a3, i32 32
29  %v19 = bitcast i8* %v18 to <16 x i32>*
30  store <16 x i32> %v15, <16 x i32>* %v19, align 64, !tbaa !4
31  %v20 = bitcast i8* %a3 to <16 x i32>*
32  store <16 x i32> %v17, <16 x i32>* %v20, align 64, !tbaa !4
33  ret void
34}
35
36; Function Attrs: nounwind readnone
37declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
38
39; Function Attrs: nounwind readnone
40declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #1
41
42; Function Attrs: nounwind readnone
43declare <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32>, <16 x i32>, i32) #1
44
45; Function Attrs: nounwind readnone
46declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
47
48; Function Attrs: nounwind readnone
49declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
50
51; Function Attrs: nounwind readnone
52define i32 @f1() #2 {
53b0:
54  ret i32 0
55}
56
57attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
58attributes #1 = { nounwind readnone }
59attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
60
61!0 = !{!1, !1, i64 0}
62!1 = !{!"long long", !2, i64 0}
63!2 = !{!"omnipotent char", !3, i64 0}
64!3 = !{!"Simple C/C++ TBAA"}
65!4 = !{!2, !2, i64 0}
66