1; RUN: llc -march=hexagon -O3 -hexagon-small-data-threshold=0 < %s | FileCheck %s
2; Check that absolute loads are generated for 64-bit
3
4target triple = "hexagon-unknown--elf"
5
6@g0 = external global i8, align 8
7@g1 = external global i16, align 8
8@g2 = external global i32, align 8
9@g3 = external global i64, align 8
10
11; CHECK-LABEL: f0:
12; CHECK: = memd(##441656)
13define i64 @f0() #0 {
14b0:
15  %v0 = load volatile i64, i64* inttoptr (i32 441656 to i64*)
16  ret i64 %v0
17}
18
19; CHECK-LABEL: f1:
20; CHECK: = memw(##441656)
21define i64 @f1() #0 {
22b0:
23  %v0 = load volatile i32, i32* inttoptr (i32 441656 to i32*)
24  %v1 = sext i32 %v0 to i64
25  ret i64 %v1
26}
27
28; CHECK-LABEL: f2:
29; CHECK: = memw(##441656)
30define i64 @f2() #0 {
31b0:
32  %v0 = load volatile i32, i32* inttoptr (i32 441656 to i32*)
33  %v1 = zext i32 %v0 to i64
34  ret i64 %v1
35}
36
37; CHECK-LABEL: f3:
38; CHECK: = memh(##441656)
39define i64 @f3() #0 {
40b0:
41  %v0 = load volatile i16, i16* inttoptr (i32 441656 to i16*)
42  %v1 = sext i16 %v0 to i64
43  ret i64 %v1
44}
45
46; CHECK-LABEL: f4:
47; CHECK: = memuh(##441656)
48define i64 @f4() #0 {
49b0:
50  %v0 = load volatile i16, i16* inttoptr (i32 441656 to i16*)
51  %v1 = zext i16 %v0 to i64
52  ret i64 %v1
53}
54
55; CHECK-LABEL: f5:
56; CHECK: = memb(##441656)
57define i64 @f5() #0 {
58b0:
59  %v0 = load volatile i8, i8* inttoptr (i32 441656 to i8*)
60  %v1 = sext i8 %v0 to i64
61  ret i64 %v1
62}
63
64; CHECK-LABEL: f6:
65; CHECK: = memub(##441656)
66define i64 @f6() #0 {
67b0:
68  %v0 = load volatile i8, i8* inttoptr (i32 441656 to i8*)
69  %v1 = zext i8 %v0 to i64
70  ret i64 %v1
71}
72
73; CHECK-LABEL: f7:
74; CHECK: = memd(##g3)
75define i64 @f7() #0 {
76b0:
77  %v0 = load volatile i64, i64* @g3
78  ret i64 %v0
79}
80
81; CHECK-LABEL: f8:
82; CHECK: = memw(##g2)
83define i64 @f8() #0 {
84b0:
85  %v0 = load volatile i32, i32* @g2
86  %v1 = sext i32 %v0 to i64
87  ret i64 %v1
88}
89
90; CHECK-LABEL: f9:
91; CHECK: = memw(##g2)
92define i64 @f9() #0 {
93b0:
94  %v0 = load volatile i32, i32* @g2
95  %v1 = zext i32 %v0 to i64
96  ret i64 %v1
97}
98
99; CHECK-LABEL: f10:
100; CHECK: = memh(##g1)
101define i64 @f10() #0 {
102b0:
103  %v0 = load volatile i16, i16* @g1
104  %v1 = sext i16 %v0 to i64
105  ret i64 %v1
106}
107
108; CHECK-LABEL: f11:
109; CHECK: = memuh(##g1)
110define i64 @f11() #0 {
111b0:
112  %v0 = load volatile i16, i16* @g1
113  %v1 = zext i16 %v0 to i64
114  ret i64 %v1
115}
116
117; CHECK-LABEL: f12:
118; CHECK: = memb(##g0)
119define i64 @f12() #0 {
120b0:
121  %v0 = load volatile i8, i8* @g0
122  %v1 = sext i8 %v0 to i64
123  ret i64 %v1
124}
125
126; CHECK-LABEL: f13:
127; CHECK: = memub(##g0)
128define i64 @f13() #0 {
129b0:
130  %v0 = load volatile i8, i8* @g0
131  %v1 = zext i8 %v0 to i64
132  ret i64 %v1
133}
134
135attributes #0 = { nounwind }
136