1; RUN: llc -march=hexagon -enable-pipeliner < %s
2; REQUIRES: asserts
3
4; Function Attrs: nounwind
5define void @f0() #0 {
6b0:
7  br i1 undef, label %b1, label %b4
8
9b1:                                               ; preds = %b0
10  br label %b2
11
12b2:                                               ; preds = %b2, %b1
13  %v0 = phi i32 [ undef, %b1 ], [ %v13, %b2 ]
14  %v1 = phi i32 [ 0, %b1 ], [ %v20, %b2 ]
15  %v2 = zext i32 %v0 to i64
16  %v3 = or i64 0, %v2
17  %v4 = tail call i64 @llvm.hexagon.S2.lsl.r.vh(i64 %v3, i32 4)
18  %v5 = or i64 %v4, -9223231297218904064
19  %v6 = lshr i64 %v5, 32
20  %v7 = trunc i64 %v6 to i32
21  %v8 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v7)
22  %v9 = lshr i64 %v8, 32
23  %v10 = trunc i64 %v9 to i32
24  %v11 = tail call i32 @llvm.hexagon.S2.lsr.r.r(i32 %v10, i32 undef)
25  %v12 = load i64, i64* undef, align 8, !tbaa !0
26  %v13 = trunc i64 %v12 to i32
27  %v14 = lshr i64 %v12, 32
28  %v15 = trunc i64 %v14 to i32
29  %v16 = zext i32 %v11 to i64
30  %v17 = shl nuw i64 %v16, 32
31  %v18 = or i64 %v17, 0
32  %v19 = tail call i32 @llvm.hexagon.S2.vsatwuh(i64 %v18)
33  %v20 = add nsw i32 %v1, 1
34  %v21 = icmp eq i32 %v20, undef
35  br i1 %v21, label %b3, label %b2
36
37b3:                                               ; preds = %b2
38  br label %b4
39
40b4:                                               ; preds = %b3, %b0
41  %v22 = phi i32 [ %v19, %b3 ], [ undef, %b0 ]
42  %v23 = phi i32 [ %v15, %b3 ], [ undef, %b0 ]
43  %v24 = zext i32 %v22 to i64
44  %v25 = shl nuw i64 %v24, 32
45  %v26 = or i64 %v25, 0
46  store i64 %v26, i64* undef, align 8, !tbaa !0
47  ret void
48}
49
50; Function Attrs: nounwind readnone
51declare i64 @llvm.hexagon.S2.lsl.r.vh(i64, i32) #1
52
53; Function Attrs: nounwind readnone
54declare i64 @llvm.hexagon.S2.vzxthw(i32) #1
55
56; Function Attrs: nounwind readnone
57declare i32 @llvm.hexagon.S2.lsr.r.r(i32, i32) #1
58
59; Function Attrs: nounwind readnone
60declare i32 @llvm.hexagon.S2.vsatwuh(i64) #1
61
62attributes #0 = { nounwind "target-cpu"="hexagonv55" }
63attributes #1 = { nounwind readnone }
64
65!0 = !{!1, !1, i64 0}
66!1 = !{!"long long", !2}
67!2 = !{!"omnipotent char", !3}
68!3 = !{!"Simple C/C++ TBAA"}
69