1; RUN: llc -march=hexagon -O2 -enable-pipeliner=false < %s | FileCheck %s
2; RUN: llc -march=hexagon -O2 -debug-only=pipeliner < %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SWP
3; REQUIRES: asserts
4
5; CHECK: {
6; CHECK-DAG: v{{[0-9]*}} = vmem(r{{[0-9]*}}++#1)
7; CHECK-DAG: vmem(r{{[0-9]*}}++#1) = v{{[0-9]*}}.new
8; CHECK: }{{[ \t]*}}:endloop0
9
10; CHECK-SWP: Schedule Found? 1
11; CHECK-SWP: {
12; CHECK-DAG-SWP: v{{[0-9]*}}.cur = vmem(r{{[0-9]*}}++#1)
13; CHECK-DAG-SWP: vmem(r{{[0-9]*}}++#1) = v{{[0-9]*}}.new
14; CHECK-SWP: }{{[ \t]*}}:endloop0
15
16target triple = "hexagon"
17
18; Function Attrs: nounwind
19define void @f0(i16* nocapture readonly %a0, i32 %a1, i32 %a2, i16* nocapture %a3) #0 {
20b0:
21  %v0 = mul i32 %a2, -2
22  %v1 = add i32 %v0, 64
23  %v2 = tail call <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32> undef, <16 x i32> undef)
24  %v3 = bitcast i16* %a3 to <16 x i32>*
25  %v4 = sdiv i32 %a1, 32
26  %v5 = icmp sgt i32 %a1, 31
27  br i1 %v5, label %b1, label %b4
28
29b1:                                               ; preds = %b0
30  %v6 = bitcast i16* %a0 to <16 x i32>*
31  %v7 = icmp sgt i32 %a1, 63
32  %v8 = mul i32 %v4, 32
33  %v9 = select i1 %v7, i32 %v8, i32 32
34  %v10 = getelementptr i16, i16* %a3, i32 %v9
35  br label %b2
36
37b2:                                               ; preds = %b2, %b1
38  %v11 = phi i32 [ 0, %b1 ], [ %v19, %b2 ]
39  %v12 = phi <16 x i32> [ %v2, %b1 ], [ %v16, %b2 ]
40  %v13 = phi <16 x i32>* [ %v3, %b1 ], [ %v18, %b2 ]
41  %v14 = phi <16 x i32>* [ %v6, %b1 ], [ %v15, %b2 ]
42  %v15 = getelementptr inbounds <16 x i32>, <16 x i32>* %v14, i32 1
43  %v16 = load <16 x i32>, <16 x i32>* %v14, align 64, !tbaa !0
44  %v17 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v16, <16 x i32> %v12, i32 %v1)
45  %v18 = getelementptr inbounds <16 x i32>, <16 x i32>* %v13, i32 1
46  store <16 x i32> %v17, <16 x i32>* %v13, align 64, !tbaa !0
47  %v19 = add nsw i32 %v11, 1
48  %v20 = icmp slt i32 %v19, %v4
49  br i1 %v20, label %b2, label %b3
50
51b3:                                               ; preds = %b2
52  %v21 = bitcast i16* %v10 to <16 x i32>*
53  br label %b4
54
55b4:                                               ; preds = %b3, %b0
56  %v22 = phi <16 x i32> [ %v16, %b3 ], [ %v2, %b0 ]
57  %v23 = phi <16 x i32>* [ %v21, %b3 ], [ %v3, %b0 ]
58  %v24 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v2, <16 x i32> %v22, i32 %v1)
59  store <16 x i32> %v24, <16 x i32>* %v23, align 64, !tbaa !0
60  ret void
61}
62
63; Function Attrs: nounwind readnone
64declare <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32>, <16 x i32>) #1
65
66; Function Attrs: nounwind readnone
67declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1
68
69attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
70attributes #1 = { nounwind readnone }
71
72!0 = !{!1, !1, i64 0}
73!1 = !{!"omnipotent char", !2, i64 0}
74!2 = !{!"Simple C/C++ TBAA"}
75