1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32IFD %s 4; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefix=RV64IFD %s 6 7define double @fld(double *%a) nounwind { 8; RV32IFD-LABEL: fld: 9; RV32IFD: # %bb.0: 10; RV32IFD-NEXT: addi sp, sp, -16 11; RV32IFD-NEXT: fld ft0, 0(a0) 12; RV32IFD-NEXT: fld ft1, 24(a0) 13; RV32IFD-NEXT: fadd.d ft0, ft0, ft1 14; RV32IFD-NEXT: fsd ft0, 8(sp) 15; RV32IFD-NEXT: lw a0, 8(sp) 16; RV32IFD-NEXT: lw a1, 12(sp) 17; RV32IFD-NEXT: addi sp, sp, 16 18; RV32IFD-NEXT: ret 19; 20; RV64IFD-LABEL: fld: 21; RV64IFD: # %bb.0: 22; RV64IFD-NEXT: fld ft0, 0(a0) 23; RV64IFD-NEXT: fld ft1, 24(a0) 24; RV64IFD-NEXT: fadd.d ft0, ft0, ft1 25; RV64IFD-NEXT: fmv.x.d a0, ft0 26; RV64IFD-NEXT: ret 27 %1 = load double, double* %a 28 %2 = getelementptr double, double* %a, i32 3 29 %3 = load double, double* %2 30; Use both loaded values in an FP op to ensure an fld is used, even for the 31; soft float ABI 32 %4 = fadd double %1, %3 33 ret double %4 34} 35 36define void @fsd(double *%a, double %b, double %c) nounwind { 37; RV32IFD-LABEL: fsd: 38; RV32IFD: # %bb.0: 39; RV32IFD-NEXT: addi sp, sp, -16 40; RV32IFD-NEXT: sw a3, 8(sp) 41; RV32IFD-NEXT: sw a4, 12(sp) 42; RV32IFD-NEXT: fld ft0, 8(sp) 43; RV32IFD-NEXT: sw a1, 8(sp) 44; RV32IFD-NEXT: sw a2, 12(sp) 45; RV32IFD-NEXT: fld ft1, 8(sp) 46; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 47; RV32IFD-NEXT: fsd ft0, 0(a0) 48; RV32IFD-NEXT: fsd ft0, 64(a0) 49; RV32IFD-NEXT: addi sp, sp, 16 50; RV32IFD-NEXT: ret 51; 52; RV64IFD-LABEL: fsd: 53; RV64IFD: # %bb.0: 54; RV64IFD-NEXT: fmv.d.x ft0, a2 55; RV64IFD-NEXT: fmv.d.x ft1, a1 56; RV64IFD-NEXT: fadd.d ft0, ft1, ft0 57; RV64IFD-NEXT: fsd ft0, 0(a0) 58; RV64IFD-NEXT: fsd ft0, 64(a0) 59; RV64IFD-NEXT: ret 60; Use %b and %c in an FP op to ensure floating point registers are used, even 61; for the soft float ABI 62 %1 = fadd double %b, %c 63 store double %1, double* %a 64 %2 = getelementptr double, double* %a, i32 8 65 store double %1, double* %2 66 ret void 67} 68 69; Check load and store to a global 70@G = global double 0.0 71 72define double @fld_fsd_global(double %a, double %b) nounwind { 73; RV32IFD-LABEL: fld_fsd_global: 74; RV32IFD: # %bb.0: 75; RV32IFD-NEXT: addi sp, sp, -16 76; RV32IFD-NEXT: sw a2, 8(sp) 77; RV32IFD-NEXT: sw a3, 12(sp) 78; RV32IFD-NEXT: fld ft0, 8(sp) 79; RV32IFD-NEXT: sw a0, 8(sp) 80; RV32IFD-NEXT: sw a1, 12(sp) 81; RV32IFD-NEXT: fld ft1, 8(sp) 82; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 83; RV32IFD-NEXT: lui a0, %hi(G) 84; RV32IFD-NEXT: fld ft1, %lo(G)(a0) 85; RV32IFD-NEXT: fsd ft0, %lo(G)(a0) 86; RV32IFD-NEXT: addi a0, a0, %lo(G) 87; RV32IFD-NEXT: fld ft1, 72(a0) 88; RV32IFD-NEXT: fsd ft0, 72(a0) 89; RV32IFD-NEXT: fsd ft0, 8(sp) 90; RV32IFD-NEXT: lw a0, 8(sp) 91; RV32IFD-NEXT: lw a1, 12(sp) 92; RV32IFD-NEXT: addi sp, sp, 16 93; RV32IFD-NEXT: ret 94; 95; RV64IFD-LABEL: fld_fsd_global: 96; RV64IFD: # %bb.0: 97; RV64IFD-NEXT: fmv.d.x ft0, a1 98; RV64IFD-NEXT: fmv.d.x ft1, a0 99; RV64IFD-NEXT: fadd.d ft0, ft1, ft0 100; RV64IFD-NEXT: lui a0, %hi(G) 101; RV64IFD-NEXT: fld ft1, %lo(G)(a0) 102; RV64IFD-NEXT: fsd ft0, %lo(G)(a0) 103; RV64IFD-NEXT: addi a1, a0, %lo(G) 104; RV64IFD-NEXT: fld ft1, 72(a1) 105; RV64IFD-NEXT: fmv.x.d a0, ft0 106; RV64IFD-NEXT: fsd ft0, 72(a1) 107; RV64IFD-NEXT: ret 108; Use %a and %b in an FP op to ensure floating point registers are used, even 109; for the soft float ABI 110 %1 = fadd double %a, %b 111 %2 = load volatile double, double* @G 112 store double %1, double* @G 113 %3 = getelementptr double, double* @G, i32 9 114 %4 = load volatile double, double* %3 115 store double %1, double* %3 116 ret double %1 117} 118 119; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1 120define double @fld_fsd_constant(double %a) nounwind { 121; RV32IFD-LABEL: fld_fsd_constant: 122; RV32IFD: # %bb.0: 123; RV32IFD-NEXT: addi sp, sp, -16 124; RV32IFD-NEXT: sw a0, 8(sp) 125; RV32IFD-NEXT: sw a1, 12(sp) 126; RV32IFD-NEXT: fld ft0, 8(sp) 127; RV32IFD-NEXT: lui a0, 912092 128; RV32IFD-NEXT: fld ft1, -273(a0) 129; RV32IFD-NEXT: fadd.d ft0, ft0, ft1 130; RV32IFD-NEXT: fsd ft0, -273(a0) 131; RV32IFD-NEXT: fsd ft0, 8(sp) 132; RV32IFD-NEXT: lw a0, 8(sp) 133; RV32IFD-NEXT: lw a1, 12(sp) 134; RV32IFD-NEXT: addi sp, sp, 16 135; RV32IFD-NEXT: ret 136; 137; RV64IFD-LABEL: fld_fsd_constant: 138; RV64IFD: # %bb.0: 139; RV64IFD-NEXT: lui a1, 56 140; RV64IFD-NEXT: addiw a1, a1, -1353 141; RV64IFD-NEXT: slli a1, a1, 14 142; RV64IFD-NEXT: fld ft0, -273(a1) 143; RV64IFD-NEXT: fmv.d.x ft1, a0 144; RV64IFD-NEXT: fadd.d ft0, ft1, ft0 145; RV64IFD-NEXT: fmv.x.d a0, ft0 146; RV64IFD-NEXT: fsd ft0, -273(a1) 147; RV64IFD-NEXT: ret 148 %1 = inttoptr i32 3735928559 to double* 149 %2 = load volatile double, double* %1 150 %3 = fadd double %a, %2 151 store double %3, double* %1 152 ret double %3 153} 154 155declare void @notdead(i8*) 156 157define double @fld_stack(double %a) nounwind { 158; RV32IFD-LABEL: fld_stack: 159; RV32IFD: # %bb.0: 160; RV32IFD-NEXT: addi sp, sp, -32 161; RV32IFD-NEXT: sw ra, 28(sp) 162; RV32IFD-NEXT: sw a0, 8(sp) 163; RV32IFD-NEXT: sw a1, 12(sp) 164; RV32IFD-NEXT: fld ft0, 8(sp) 165; RV32IFD-NEXT: fsd ft0, 0(sp) 166; RV32IFD-NEXT: addi a0, sp, 16 167; RV32IFD-NEXT: call notdead 168; RV32IFD-NEXT: fld ft0, 16(sp) 169; RV32IFD-NEXT: fld ft1, 0(sp) 170; RV32IFD-NEXT: fadd.d ft0, ft0, ft1 171; RV32IFD-NEXT: fsd ft0, 8(sp) 172; RV32IFD-NEXT: lw a0, 8(sp) 173; RV32IFD-NEXT: lw a1, 12(sp) 174; RV32IFD-NEXT: lw ra, 28(sp) 175; RV32IFD-NEXT: addi sp, sp, 32 176; RV32IFD-NEXT: ret 177; 178; RV64IFD-LABEL: fld_stack: 179; RV64IFD: # %bb.0: 180; RV64IFD-NEXT: addi sp, sp, -32 181; RV64IFD-NEXT: sd ra, 24(sp) 182; RV64IFD-NEXT: fmv.d.x ft0, a0 183; RV64IFD-NEXT: fsd ft0, 8(sp) 184; RV64IFD-NEXT: addi a0, sp, 16 185; RV64IFD-NEXT: call notdead 186; RV64IFD-NEXT: fld ft0, 16(sp) 187; RV64IFD-NEXT: fld ft1, 8(sp) 188; RV64IFD-NEXT: fadd.d ft0, ft0, ft1 189; RV64IFD-NEXT: fmv.x.d a0, ft0 190; RV64IFD-NEXT: ld ra, 24(sp) 191; RV64IFD-NEXT: addi sp, sp, 32 192; RV64IFD-NEXT: ret 193 %1 = alloca double, align 8 194 %2 = bitcast double* %1 to i8* 195 call void @notdead(i8* %2) 196 %3 = load double, double* %1 197 %4 = fadd double %3, %a ; force load in to FPR64 198 ret double %4 199} 200 201define void @fsd_stack(double %a, double %b) nounwind { 202; RV32IFD-LABEL: fsd_stack: 203; RV32IFD: # %bb.0: 204; RV32IFD-NEXT: addi sp, sp, -32 205; RV32IFD-NEXT: sw ra, 28(sp) 206; RV32IFD-NEXT: sw a2, 8(sp) 207; RV32IFD-NEXT: sw a3, 12(sp) 208; RV32IFD-NEXT: fld ft0, 8(sp) 209; RV32IFD-NEXT: sw a0, 8(sp) 210; RV32IFD-NEXT: sw a1, 12(sp) 211; RV32IFD-NEXT: fld ft1, 8(sp) 212; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 213; RV32IFD-NEXT: fsd ft0, 16(sp) 214; RV32IFD-NEXT: addi a0, sp, 16 215; RV32IFD-NEXT: call notdead 216; RV32IFD-NEXT: lw ra, 28(sp) 217; RV32IFD-NEXT: addi sp, sp, 32 218; RV32IFD-NEXT: ret 219; 220; RV64IFD-LABEL: fsd_stack: 221; RV64IFD: # %bb.0: 222; RV64IFD-NEXT: addi sp, sp, -16 223; RV64IFD-NEXT: sd ra, 8(sp) 224; RV64IFD-NEXT: fmv.d.x ft0, a1 225; RV64IFD-NEXT: fmv.d.x ft1, a0 226; RV64IFD-NEXT: fadd.d ft0, ft1, ft0 227; RV64IFD-NEXT: fsd ft0, 0(sp) 228; RV64IFD-NEXT: mv a0, sp 229; RV64IFD-NEXT: call notdead 230; RV64IFD-NEXT: ld ra, 8(sp) 231; RV64IFD-NEXT: addi sp, sp, 16 232; RV64IFD-NEXT: ret 233 %1 = fadd double %a, %b ; force store from FPR64 234 %2 = alloca double, align 8 235 store double %1, double* %2 236 %3 = bitcast double* %2 to i8* 237 call void @notdead(i8* %3) 238 ret void 239} 240 241; Test selection of store<ST4[%a], trunc to f32>, .. 242define void @fsd_trunc(float* %a, double %b) nounwind noinline optnone { 243; RV32IFD-LABEL: fsd_trunc: 244; RV32IFD: # %bb.0: 245; RV32IFD-NEXT: addi sp, sp, -16 246; RV32IFD-NEXT: sw a1, 8(sp) 247; RV32IFD-NEXT: sw a2, 12(sp) 248; RV32IFD-NEXT: fld ft0, 8(sp) 249; RV32IFD-NEXT: fcvt.s.d ft0, ft0 250; RV32IFD-NEXT: fsw ft0, 0(a0) 251; RV32IFD-NEXT: addi sp, sp, 16 252; RV32IFD-NEXT: ret 253; 254; RV64IFD-LABEL: fsd_trunc: 255; RV64IFD: # %bb.0: 256; RV64IFD-NEXT: fmv.d.x ft0, a1 257; RV64IFD-NEXT: fcvt.s.d ft0, ft0 258; RV64IFD-NEXT: fsw ft0, 0(a0) 259; RV64IFD-NEXT: ret 260 %1 = fptrunc double %b to float 261 store float %1, float* %a, align 4 262 ret void 263} 264