1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32IF %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64IF %s
6
7define i32 @fcmp_false(float %a, float %b) nounwind {
8; RV32IF-LABEL: fcmp_false:
9; RV32IF:       # %bb.0:
10; RV32IF-NEXT:    mv a0, zero
11; RV32IF-NEXT:    ret
12;
13; RV64IF-LABEL: fcmp_false:
14; RV64IF:       # %bb.0:
15; RV64IF-NEXT:    mv a0, zero
16; RV64IF-NEXT:    ret
17  %1 = fcmp false float %a, %b
18  %2 = zext i1 %1 to i32
19  ret i32 %2
20}
21
22define i32 @fcmp_oeq(float %a, float %b) nounwind {
23; RV32IF-LABEL: fcmp_oeq:
24; RV32IF:       # %bb.0:
25; RV32IF-NEXT:    fmv.w.x ft0, a1
26; RV32IF-NEXT:    fmv.w.x ft1, a0
27; RV32IF-NEXT:    feq.s a0, ft1, ft0
28; RV32IF-NEXT:    ret
29;
30; RV64IF-LABEL: fcmp_oeq:
31; RV64IF:       # %bb.0:
32; RV64IF-NEXT:    fmv.w.x ft0, a1
33; RV64IF-NEXT:    fmv.w.x ft1, a0
34; RV64IF-NEXT:    feq.s a0, ft1, ft0
35; RV64IF-NEXT:    ret
36  %1 = fcmp oeq float %a, %b
37  %2 = zext i1 %1 to i32
38  ret i32 %2
39}
40
41define i32 @fcmp_ogt(float %a, float %b) nounwind {
42; RV32IF-LABEL: fcmp_ogt:
43; RV32IF:       # %bb.0:
44; RV32IF-NEXT:    fmv.w.x ft0, a0
45; RV32IF-NEXT:    fmv.w.x ft1, a1
46; RV32IF-NEXT:    flt.s a0, ft1, ft0
47; RV32IF-NEXT:    ret
48;
49; RV64IF-LABEL: fcmp_ogt:
50; RV64IF:       # %bb.0:
51; RV64IF-NEXT:    fmv.w.x ft0, a0
52; RV64IF-NEXT:    fmv.w.x ft1, a1
53; RV64IF-NEXT:    flt.s a0, ft1, ft0
54; RV64IF-NEXT:    ret
55  %1 = fcmp ogt float %a, %b
56  %2 = zext i1 %1 to i32
57  ret i32 %2
58}
59
60define i32 @fcmp_oge(float %a, float %b) nounwind {
61; RV32IF-LABEL: fcmp_oge:
62; RV32IF:       # %bb.0:
63; RV32IF-NEXT:    fmv.w.x ft0, a0
64; RV32IF-NEXT:    fmv.w.x ft1, a1
65; RV32IF-NEXT:    fle.s a0, ft1, ft0
66; RV32IF-NEXT:    ret
67;
68; RV64IF-LABEL: fcmp_oge:
69; RV64IF:       # %bb.0:
70; RV64IF-NEXT:    fmv.w.x ft0, a0
71; RV64IF-NEXT:    fmv.w.x ft1, a1
72; RV64IF-NEXT:    fle.s a0, ft1, ft0
73; RV64IF-NEXT:    ret
74  %1 = fcmp oge float %a, %b
75  %2 = zext i1 %1 to i32
76  ret i32 %2
77}
78
79define i32 @fcmp_olt(float %a, float %b) nounwind {
80; RV32IF-LABEL: fcmp_olt:
81; RV32IF:       # %bb.0:
82; RV32IF-NEXT:    fmv.w.x ft0, a1
83; RV32IF-NEXT:    fmv.w.x ft1, a0
84; RV32IF-NEXT:    flt.s a0, ft1, ft0
85; RV32IF-NEXT:    ret
86;
87; RV64IF-LABEL: fcmp_olt:
88; RV64IF:       # %bb.0:
89; RV64IF-NEXT:    fmv.w.x ft0, a1
90; RV64IF-NEXT:    fmv.w.x ft1, a0
91; RV64IF-NEXT:    flt.s a0, ft1, ft0
92; RV64IF-NEXT:    ret
93  %1 = fcmp olt float %a, %b
94  %2 = zext i1 %1 to i32
95  ret i32 %2
96}
97
98define i32 @fcmp_ole(float %a, float %b) nounwind {
99; RV32IF-LABEL: fcmp_ole:
100; RV32IF:       # %bb.0:
101; RV32IF-NEXT:    fmv.w.x ft0, a1
102; RV32IF-NEXT:    fmv.w.x ft1, a0
103; RV32IF-NEXT:    fle.s a0, ft1, ft0
104; RV32IF-NEXT:    ret
105;
106; RV64IF-LABEL: fcmp_ole:
107; RV64IF:       # %bb.0:
108; RV64IF-NEXT:    fmv.w.x ft0, a1
109; RV64IF-NEXT:    fmv.w.x ft1, a0
110; RV64IF-NEXT:    fle.s a0, ft1, ft0
111; RV64IF-NEXT:    ret
112  %1 = fcmp ole float %a, %b
113  %2 = zext i1 %1 to i32
114  ret i32 %2
115}
116
117define i32 @fcmp_one(float %a, float %b) nounwind {
118; RV32IF-LABEL: fcmp_one:
119; RV32IF:       # %bb.0:
120; RV32IF-NEXT:    fmv.w.x ft0, a0
121; RV32IF-NEXT:    fmv.w.x ft1, a1
122; RV32IF-NEXT:    feq.s a0, ft1, ft1
123; RV32IF-NEXT:    feq.s a1, ft0, ft0
124; RV32IF-NEXT:    and a0, a1, a0
125; RV32IF-NEXT:    feq.s a1, ft0, ft1
126; RV32IF-NEXT:    not a1, a1
127; RV32IF-NEXT:    and a0, a1, a0
128; RV32IF-NEXT:    ret
129;
130; RV64IF-LABEL: fcmp_one:
131; RV64IF:       # %bb.0:
132; RV64IF-NEXT:    fmv.w.x ft0, a0
133; RV64IF-NEXT:    fmv.w.x ft1, a1
134; RV64IF-NEXT:    feq.s a0, ft1, ft1
135; RV64IF-NEXT:    feq.s a1, ft0, ft0
136; RV64IF-NEXT:    and a0, a1, a0
137; RV64IF-NEXT:    feq.s a1, ft0, ft1
138; RV64IF-NEXT:    not a1, a1
139; RV64IF-NEXT:    and a0, a1, a0
140; RV64IF-NEXT:    ret
141  %1 = fcmp one float %a, %b
142  %2 = zext i1 %1 to i32
143  ret i32 %2
144}
145
146define i32 @fcmp_ord(float %a, float %b) nounwind {
147; RV32IF-LABEL: fcmp_ord:
148; RV32IF:       # %bb.0:
149; RV32IF-NEXT:    fmv.w.x ft0, a0
150; RV32IF-NEXT:    fmv.w.x ft1, a1
151; RV32IF-NEXT:    feq.s a0, ft1, ft1
152; RV32IF-NEXT:    feq.s a1, ft0, ft0
153; RV32IF-NEXT:    and a0, a1, a0
154; RV32IF-NEXT:    ret
155;
156; RV64IF-LABEL: fcmp_ord:
157; RV64IF:       # %bb.0:
158; RV64IF-NEXT:    fmv.w.x ft0, a0
159; RV64IF-NEXT:    fmv.w.x ft1, a1
160; RV64IF-NEXT:    feq.s a0, ft1, ft1
161; RV64IF-NEXT:    feq.s a1, ft0, ft0
162; RV64IF-NEXT:    and a0, a1, a0
163; RV64IF-NEXT:    ret
164  %1 = fcmp ord float %a, %b
165  %2 = zext i1 %1 to i32
166  ret i32 %2
167}
168
169define i32 @fcmp_ueq(float %a, float %b) nounwind {
170; RV32IF-LABEL: fcmp_ueq:
171; RV32IF:       # %bb.0:
172; RV32IF-NEXT:    fmv.w.x ft0, a1
173; RV32IF-NEXT:    fmv.w.x ft1, a0
174; RV32IF-NEXT:    feq.s a0, ft1, ft0
175; RV32IF-NEXT:    feq.s a1, ft0, ft0
176; RV32IF-NEXT:    feq.s a2, ft1, ft1
177; RV32IF-NEXT:    and a1, a2, a1
178; RV32IF-NEXT:    seqz a1, a1
179; RV32IF-NEXT:    or a0, a0, a1
180; RV32IF-NEXT:    ret
181;
182; RV64IF-LABEL: fcmp_ueq:
183; RV64IF:       # %bb.0:
184; RV64IF-NEXT:    fmv.w.x ft0, a1
185; RV64IF-NEXT:    fmv.w.x ft1, a0
186; RV64IF-NEXT:    feq.s a0, ft1, ft0
187; RV64IF-NEXT:    feq.s a1, ft0, ft0
188; RV64IF-NEXT:    feq.s a2, ft1, ft1
189; RV64IF-NEXT:    and a1, a2, a1
190; RV64IF-NEXT:    seqz a1, a1
191; RV64IF-NEXT:    or a0, a0, a1
192; RV64IF-NEXT:    ret
193  %1 = fcmp ueq float %a, %b
194  %2 = zext i1 %1 to i32
195  ret i32 %2
196}
197
198define i32 @fcmp_ugt(float %a, float %b) nounwind {
199; RV32IF-LABEL: fcmp_ugt:
200; RV32IF:       # %bb.0:
201; RV32IF-NEXT:    fmv.w.x ft0, a1
202; RV32IF-NEXT:    fmv.w.x ft1, a0
203; RV32IF-NEXT:    fle.s a0, ft1, ft0
204; RV32IF-NEXT:    xori a0, a0, 1
205; RV32IF-NEXT:    ret
206;
207; RV64IF-LABEL: fcmp_ugt:
208; RV64IF:       # %bb.0:
209; RV64IF-NEXT:    fmv.w.x ft0, a1
210; RV64IF-NEXT:    fmv.w.x ft1, a0
211; RV64IF-NEXT:    fle.s a0, ft1, ft0
212; RV64IF-NEXT:    xori a0, a0, 1
213; RV64IF-NEXT:    ret
214  %1 = fcmp ugt float %a, %b
215  %2 = zext i1 %1 to i32
216  ret i32 %2
217}
218
219define i32 @fcmp_uge(float %a, float %b) nounwind {
220; RV32IF-LABEL: fcmp_uge:
221; RV32IF:       # %bb.0:
222; RV32IF-NEXT:    fmv.w.x ft0, a1
223; RV32IF-NEXT:    fmv.w.x ft1, a0
224; RV32IF-NEXT:    flt.s a0, ft1, ft0
225; RV32IF-NEXT:    xori a0, a0, 1
226; RV32IF-NEXT:    ret
227;
228; RV64IF-LABEL: fcmp_uge:
229; RV64IF:       # %bb.0:
230; RV64IF-NEXT:    fmv.w.x ft0, a1
231; RV64IF-NEXT:    fmv.w.x ft1, a0
232; RV64IF-NEXT:    flt.s a0, ft1, ft0
233; RV64IF-NEXT:    xori a0, a0, 1
234; RV64IF-NEXT:    ret
235  %1 = fcmp uge float %a, %b
236  %2 = zext i1 %1 to i32
237  ret i32 %2
238}
239
240define i32 @fcmp_ult(float %a, float %b) nounwind {
241; RV32IF-LABEL: fcmp_ult:
242; RV32IF:       # %bb.0:
243; RV32IF-NEXT:    fmv.w.x ft0, a0
244; RV32IF-NEXT:    fmv.w.x ft1, a1
245; RV32IF-NEXT:    fle.s a0, ft1, ft0
246; RV32IF-NEXT:    xori a0, a0, 1
247; RV32IF-NEXT:    ret
248;
249; RV64IF-LABEL: fcmp_ult:
250; RV64IF:       # %bb.0:
251; RV64IF-NEXT:    fmv.w.x ft0, a0
252; RV64IF-NEXT:    fmv.w.x ft1, a1
253; RV64IF-NEXT:    fle.s a0, ft1, ft0
254; RV64IF-NEXT:    xori a0, a0, 1
255; RV64IF-NEXT:    ret
256  %1 = fcmp ult float %a, %b
257  %2 = zext i1 %1 to i32
258  ret i32 %2
259}
260
261define i32 @fcmp_ule(float %a, float %b) nounwind {
262; RV32IF-LABEL: fcmp_ule:
263; RV32IF:       # %bb.0:
264; RV32IF-NEXT:    fmv.w.x ft0, a0
265; RV32IF-NEXT:    fmv.w.x ft1, a1
266; RV32IF-NEXT:    flt.s a0, ft1, ft0
267; RV32IF-NEXT:    xori a0, a0, 1
268; RV32IF-NEXT:    ret
269;
270; RV64IF-LABEL: fcmp_ule:
271; RV64IF:       # %bb.0:
272; RV64IF-NEXT:    fmv.w.x ft0, a0
273; RV64IF-NEXT:    fmv.w.x ft1, a1
274; RV64IF-NEXT:    flt.s a0, ft1, ft0
275; RV64IF-NEXT:    xori a0, a0, 1
276; RV64IF-NEXT:    ret
277  %1 = fcmp ule float %a, %b
278  %2 = zext i1 %1 to i32
279  ret i32 %2
280}
281
282define i32 @fcmp_une(float %a, float %b) nounwind {
283; RV32IF-LABEL: fcmp_une:
284; RV32IF:       # %bb.0:
285; RV32IF-NEXT:    fmv.w.x ft0, a1
286; RV32IF-NEXT:    fmv.w.x ft1, a0
287; RV32IF-NEXT:    feq.s a0, ft1, ft0
288; RV32IF-NEXT:    xori a0, a0, 1
289; RV32IF-NEXT:    ret
290;
291; RV64IF-LABEL: fcmp_une:
292; RV64IF:       # %bb.0:
293; RV64IF-NEXT:    fmv.w.x ft0, a1
294; RV64IF-NEXT:    fmv.w.x ft1, a0
295; RV64IF-NEXT:    feq.s a0, ft1, ft0
296; RV64IF-NEXT:    xori a0, a0, 1
297; RV64IF-NEXT:    ret
298  %1 = fcmp une float %a, %b
299  %2 = zext i1 %1 to i32
300  ret i32 %2
301}
302
303define i32 @fcmp_uno(float %a, float %b) nounwind {
304; RV32IF-LABEL: fcmp_uno:
305; RV32IF:       # %bb.0:
306; RV32IF-NEXT:    fmv.w.x ft0, a0
307; RV32IF-NEXT:    fmv.w.x ft1, a1
308; RV32IF-NEXT:    feq.s a0, ft1, ft1
309; RV32IF-NEXT:    feq.s a1, ft0, ft0
310; RV32IF-NEXT:    and a0, a1, a0
311; RV32IF-NEXT:    seqz a0, a0
312; RV32IF-NEXT:    ret
313;
314; RV64IF-LABEL: fcmp_uno:
315; RV64IF:       # %bb.0:
316; RV64IF-NEXT:    fmv.w.x ft0, a0
317; RV64IF-NEXT:    fmv.w.x ft1, a1
318; RV64IF-NEXT:    feq.s a0, ft1, ft1
319; RV64IF-NEXT:    feq.s a1, ft0, ft0
320; RV64IF-NEXT:    and a0, a1, a0
321; RV64IF-NEXT:    seqz a0, a0
322; RV64IF-NEXT:    ret
323  %1 = fcmp uno float %a, %b
324  %2 = zext i1 %1 to i32
325  ret i32 %2
326}
327
328define i32 @fcmp_true(float %a, float %b) nounwind {
329; RV32IF-LABEL: fcmp_true:
330; RV32IF:       # %bb.0:
331; RV32IF-NEXT:    addi a0, zero, 1
332; RV32IF-NEXT:    ret
333;
334; RV64IF-LABEL: fcmp_true:
335; RV64IF:       # %bb.0:
336; RV64IF-NEXT:    addi a0, zero, 1
337; RV64IF-NEXT:    ret
338  %1 = fcmp true float %a, %b
339  %2 = zext i1 %1 to i32
340  ret i32 %2
341}
342