1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+f < %s \
3; RUN:     | FileCheck --check-prefix=RV32F %s
4; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+f,+d < %s \
5; RUN:     | FileCheck --check-prefix=RV32D %s
6; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+f < %s \
7; RUN:     | FileCheck --check-prefix=RV64F %s
8; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+f,+d < %s \
9; RUN:     | FileCheck --check-prefix=RV64D %s
10
11define float @f32_positive_zero(float *%pf) nounwind {
12; RV32F-LABEL: f32_positive_zero:
13; RV32F:       # %bb.0:
14; RV32F-NEXT:    fmv.w.x fa0, zero
15; RV32F-NEXT:    ret
16;
17; RV32D-LABEL: f32_positive_zero:
18; RV32D:       # %bb.0:
19; RV32D-NEXT:    fmv.w.x fa0, zero
20; RV32D-NEXT:    ret
21;
22; RV64F-LABEL: f32_positive_zero:
23; RV64F:       # %bb.0:
24; RV64F-NEXT:    fmv.w.x fa0, zero
25; RV64F-NEXT:    ret
26;
27; RV64D-LABEL: f32_positive_zero:
28; RV64D:       # %bb.0:
29; RV64D-NEXT:    fmv.w.x fa0, zero
30; RV64D-NEXT:    ret
31  ret float 0.0
32}
33
34define float @f32_negative_zero(float *%pf) nounwind {
35; RV32F-LABEL: f32_negative_zero:
36; RV32F:       # %bb.0:
37; RV32F-NEXT:    lui a0, %hi(.LCPI1_0)
38; RV32F-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
39; RV32F-NEXT:    ret
40;
41; RV32D-LABEL: f32_negative_zero:
42; RV32D:       # %bb.0:
43; RV32D-NEXT:    lui a0, %hi(.LCPI1_0)
44; RV32D-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
45; RV32D-NEXT:    ret
46;
47; RV64F-LABEL: f32_negative_zero:
48; RV64F:       # %bb.0:
49; RV64F-NEXT:    lui a0, %hi(.LCPI1_0)
50; RV64F-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
51; RV64F-NEXT:    ret
52;
53; RV64D-LABEL: f32_negative_zero:
54; RV64D:       # %bb.0:
55; RV64D-NEXT:    lui a0, %hi(.LCPI1_0)
56; RV64D-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
57; RV64D-NEXT:    ret
58  ret float -0.0
59}
60
61define double @f64_positive_zero(double *%pd) nounwind {
62; RV32F-LABEL: f64_positive_zero:
63; RV32F:       # %bb.0:
64; RV32F-NEXT:    mv a0, zero
65; RV32F-NEXT:    mv a1, zero
66; RV32F-NEXT:    ret
67;
68; RV32D-LABEL: f64_positive_zero:
69; RV32D:       # %bb.0:
70; RV32D-NEXT:    fcvt.d.w fa0, zero
71; RV32D-NEXT:    ret
72;
73; RV64F-LABEL: f64_positive_zero:
74; RV64F:       # %bb.0:
75; RV64F-NEXT:    mv a0, zero
76; RV64F-NEXT:    ret
77;
78; RV64D-LABEL: f64_positive_zero:
79; RV64D:       # %bb.0:
80; RV64D-NEXT:    fmv.d.x fa0, zero
81; RV64D-NEXT:    ret
82  ret double 0.0
83}
84
85define double @f64_negative_zero(double *%pd) nounwind {
86; RV32F-LABEL: f64_negative_zero:
87; RV32F:       # %bb.0:
88; RV32F-NEXT:    lui a1, 524288
89; RV32F-NEXT:    mv a0, zero
90; RV32F-NEXT:    ret
91;
92; RV32D-LABEL: f64_negative_zero:
93; RV32D:       # %bb.0:
94; RV32D-NEXT:    lui a0, %hi(.LCPI3_0)
95; RV32D-NEXT:    fld fa0, %lo(.LCPI3_0)(a0)
96; RV32D-NEXT:    ret
97;
98; RV64F-LABEL: f64_negative_zero:
99; RV64F:       # %bb.0:
100; RV64F-NEXT:    addi a0, zero, -1
101; RV64F-NEXT:    slli a0, a0, 63
102; RV64F-NEXT:    ret
103;
104; RV64D-LABEL: f64_negative_zero:
105; RV64D:       # %bb.0:
106; RV64D-NEXT:    lui a0, %hi(.LCPI3_0)
107; RV64D-NEXT:    fld fa0, %lo(.LCPI3_0)(a0)
108; RV64D-NEXT:    ret
109  ret double -0.0
110}
111