1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32IF %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64IF %s
6
7; These test that we can use both the architectural names (x*) and the ABI names
8; (a*, s*, t* etc) to refer to registers in inline asm constraint lists. In each
9; case, the named register should be used for the source register of the `addi`.
10; It is very likely that `a0` will be chosen as the designation register, but
11; this is left to the compiler to choose.
12;
13; The inline assembly will, by default, contain the ABI names for the registers.
14;
15; Parenthesised registers in comments are the other aliases for this register.
16
17
18define i32 @explicit_register_f0(float %a) nounwind {
19; RV32IF-LABEL: explicit_register_f0:
20; RV32IF:       # %bb.0:
21; RV32IF-NEXT:    fmv.s ft0, fa0
22; RV32IF-NEXT:    #APP
23; RV32IF-NEXT:    fcvt.w.s a0, ft0
24; RV32IF-NEXT:    #NO_APP
25; RV32IF-NEXT:    ret
26;
27; RV64IF-LABEL: explicit_register_f0:
28; RV64IF:       # %bb.0:
29; RV64IF-NEXT:    fmv.s ft0, fa0
30; RV64IF-NEXT:    #APP
31; RV64IF-NEXT:    fcvt.w.s a0, ft0
32; RV64IF-NEXT:    #NO_APP
33; RV64IF-NEXT:    ret
34  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f0}"(float %a)
35  ret i32 %1
36}
37
38define i32 @explicit_register_ft0(float %a) nounwind {
39; RV32IF-LABEL: explicit_register_ft0:
40; RV32IF:       # %bb.0:
41; RV32IF-NEXT:    fmv.s ft0, fa0
42; RV32IF-NEXT:    #APP
43; RV32IF-NEXT:    fcvt.w.s a0, ft0
44; RV32IF-NEXT:    #NO_APP
45; RV32IF-NEXT:    ret
46;
47; RV64IF-LABEL: explicit_register_ft0:
48; RV64IF:       # %bb.0:
49; RV64IF-NEXT:    fmv.s ft0, fa0
50; RV64IF-NEXT:    #APP
51; RV64IF-NEXT:    fcvt.w.s a0, ft0
52; RV64IF-NEXT:    #NO_APP
53; RV64IF-NEXT:    ret
54  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft0}"(float %a)
55  ret i32 %1
56}
57
58define i32 @explicit_register_f1(float %a) nounwind {
59; RV32IF-LABEL: explicit_register_f1:
60; RV32IF:       # %bb.0:
61; RV32IF-NEXT:    fmv.s ft1, fa0
62; RV32IF-NEXT:    #APP
63; RV32IF-NEXT:    fcvt.w.s a0, ft1
64; RV32IF-NEXT:    #NO_APP
65; RV32IF-NEXT:    ret
66;
67; RV64IF-LABEL: explicit_register_f1:
68; RV64IF:       # %bb.0:
69; RV64IF-NEXT:    fmv.s ft1, fa0
70; RV64IF-NEXT:    #APP
71; RV64IF-NEXT:    fcvt.w.s a0, ft1
72; RV64IF-NEXT:    #NO_APP
73; RV64IF-NEXT:    ret
74  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f1}"(float %a)
75  ret i32 %1
76}
77
78define i32 @explicit_register_ft1(float %a) nounwind {
79; RV32IF-LABEL: explicit_register_ft1:
80; RV32IF:       # %bb.0:
81; RV32IF-NEXT:    fmv.s ft1, fa0
82; RV32IF-NEXT:    #APP
83; RV32IF-NEXT:    fcvt.w.s a0, ft1
84; RV32IF-NEXT:    #NO_APP
85; RV32IF-NEXT:    ret
86;
87; RV64IF-LABEL: explicit_register_ft1:
88; RV64IF:       # %bb.0:
89; RV64IF-NEXT:    fmv.s ft1, fa0
90; RV64IF-NEXT:    #APP
91; RV64IF-NEXT:    fcvt.w.s a0, ft1
92; RV64IF-NEXT:    #NO_APP
93; RV64IF-NEXT:    ret
94  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft1}"(float %a)
95  ret i32 %1
96}
97
98define i32 @explicit_register_f2(float %a) nounwind {
99; RV32IF-LABEL: explicit_register_f2:
100; RV32IF:       # %bb.0:
101; RV32IF-NEXT:    fmv.s ft2, fa0
102; RV32IF-NEXT:    #APP
103; RV32IF-NEXT:    fcvt.w.s a0, ft2
104; RV32IF-NEXT:    #NO_APP
105; RV32IF-NEXT:    ret
106;
107; RV64IF-LABEL: explicit_register_f2:
108; RV64IF:       # %bb.0:
109; RV64IF-NEXT:    fmv.s ft2, fa0
110; RV64IF-NEXT:    #APP
111; RV64IF-NEXT:    fcvt.w.s a0, ft2
112; RV64IF-NEXT:    #NO_APP
113; RV64IF-NEXT:    ret
114  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f2}"(float %a)
115  ret i32 %1
116}
117
118define i32 @explicit_register_ft2(float %a) nounwind {
119; RV32IF-LABEL: explicit_register_ft2:
120; RV32IF:       # %bb.0:
121; RV32IF-NEXT:    fmv.s ft2, fa0
122; RV32IF-NEXT:    #APP
123; RV32IF-NEXT:    fcvt.w.s a0, ft2
124; RV32IF-NEXT:    #NO_APP
125; RV32IF-NEXT:    ret
126;
127; RV64IF-LABEL: explicit_register_ft2:
128; RV64IF:       # %bb.0:
129; RV64IF-NEXT:    fmv.s ft2, fa0
130; RV64IF-NEXT:    #APP
131; RV64IF-NEXT:    fcvt.w.s a0, ft2
132; RV64IF-NEXT:    #NO_APP
133; RV64IF-NEXT:    ret
134  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft2}"(float %a)
135  ret i32 %1
136}
137
138define i32 @explicit_register_f3(float %a) nounwind {
139; RV32IF-LABEL: explicit_register_f3:
140; RV32IF:       # %bb.0:
141; RV32IF-NEXT:    fmv.s ft3, fa0
142; RV32IF-NEXT:    #APP
143; RV32IF-NEXT:    fcvt.w.s a0, ft3
144; RV32IF-NEXT:    #NO_APP
145; RV32IF-NEXT:    ret
146;
147; RV64IF-LABEL: explicit_register_f3:
148; RV64IF:       # %bb.0:
149; RV64IF-NEXT:    fmv.s ft3, fa0
150; RV64IF-NEXT:    #APP
151; RV64IF-NEXT:    fcvt.w.s a0, ft3
152; RV64IF-NEXT:    #NO_APP
153; RV64IF-NEXT:    ret
154  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f3}"(float %a)
155  ret i32 %1
156}
157
158define i32 @explicit_register_ft3(float %a) nounwind {
159; RV32IF-LABEL: explicit_register_ft3:
160; RV32IF:       # %bb.0:
161; RV32IF-NEXT:    fmv.s ft3, fa0
162; RV32IF-NEXT:    #APP
163; RV32IF-NEXT:    fcvt.w.s a0, ft3
164; RV32IF-NEXT:    #NO_APP
165; RV32IF-NEXT:    ret
166;
167; RV64IF-LABEL: explicit_register_ft3:
168; RV64IF:       # %bb.0:
169; RV64IF-NEXT:    fmv.s ft3, fa0
170; RV64IF-NEXT:    #APP
171; RV64IF-NEXT:    fcvt.w.s a0, ft3
172; RV64IF-NEXT:    #NO_APP
173; RV64IF-NEXT:    ret
174  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft3}"(float %a)
175  ret i32 %1
176}
177
178define i32 @explicit_register_f4(float %a) nounwind {
179; RV32IF-LABEL: explicit_register_f4:
180; RV32IF:       # %bb.0:
181; RV32IF-NEXT:    fmv.s ft4, fa0
182; RV32IF-NEXT:    #APP
183; RV32IF-NEXT:    fcvt.w.s a0, ft4
184; RV32IF-NEXT:    #NO_APP
185; RV32IF-NEXT:    ret
186;
187; RV64IF-LABEL: explicit_register_f4:
188; RV64IF:       # %bb.0:
189; RV64IF-NEXT:    fmv.s ft4, fa0
190; RV64IF-NEXT:    #APP
191; RV64IF-NEXT:    fcvt.w.s a0, ft4
192; RV64IF-NEXT:    #NO_APP
193; RV64IF-NEXT:    ret
194  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f4}"(float %a)
195  ret i32 %1
196}
197
198define i32 @explicit_register_ft4(float %a) nounwind {
199; RV32IF-LABEL: explicit_register_ft4:
200; RV32IF:       # %bb.0:
201; RV32IF-NEXT:    fmv.s ft4, fa0
202; RV32IF-NEXT:    #APP
203; RV32IF-NEXT:    fcvt.w.s a0, ft4
204; RV32IF-NEXT:    #NO_APP
205; RV32IF-NEXT:    ret
206;
207; RV64IF-LABEL: explicit_register_ft4:
208; RV64IF:       # %bb.0:
209; RV64IF-NEXT:    fmv.s ft4, fa0
210; RV64IF-NEXT:    #APP
211; RV64IF-NEXT:    fcvt.w.s a0, ft4
212; RV64IF-NEXT:    #NO_APP
213; RV64IF-NEXT:    ret
214  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft4}"(float %a)
215  ret i32 %1
216}
217
218define i32 @explicit_register_f5(float %a) nounwind {
219; RV32IF-LABEL: explicit_register_f5:
220; RV32IF:       # %bb.0:
221; RV32IF-NEXT:    fmv.s ft5, fa0
222; RV32IF-NEXT:    #APP
223; RV32IF-NEXT:    fcvt.w.s a0, ft5
224; RV32IF-NEXT:    #NO_APP
225; RV32IF-NEXT:    ret
226;
227; RV64IF-LABEL: explicit_register_f5:
228; RV64IF:       # %bb.0:
229; RV64IF-NEXT:    fmv.s ft5, fa0
230; RV64IF-NEXT:    #APP
231; RV64IF-NEXT:    fcvt.w.s a0, ft5
232; RV64IF-NEXT:    #NO_APP
233; RV64IF-NEXT:    ret
234  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f5}"(float %a)
235  ret i32 %1
236}
237
238define i32 @explicit_register_ft5(float %a) nounwind {
239; RV32IF-LABEL: explicit_register_ft5:
240; RV32IF:       # %bb.0:
241; RV32IF-NEXT:    fmv.s ft5, fa0
242; RV32IF-NEXT:    #APP
243; RV32IF-NEXT:    fcvt.w.s a0, ft5
244; RV32IF-NEXT:    #NO_APP
245; RV32IF-NEXT:    ret
246;
247; RV64IF-LABEL: explicit_register_ft5:
248; RV64IF:       # %bb.0:
249; RV64IF-NEXT:    fmv.s ft5, fa0
250; RV64IF-NEXT:    #APP
251; RV64IF-NEXT:    fcvt.w.s a0, ft5
252; RV64IF-NEXT:    #NO_APP
253; RV64IF-NEXT:    ret
254  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft5}"(float %a)
255  ret i32 %1
256}
257
258define i32 @explicit_register_f6(float %a) nounwind {
259; RV32IF-LABEL: explicit_register_f6:
260; RV32IF:       # %bb.0:
261; RV32IF-NEXT:    fmv.s ft6, fa0
262; RV32IF-NEXT:    #APP
263; RV32IF-NEXT:    fcvt.w.s a0, ft6
264; RV32IF-NEXT:    #NO_APP
265; RV32IF-NEXT:    ret
266;
267; RV64IF-LABEL: explicit_register_f6:
268; RV64IF:       # %bb.0:
269; RV64IF-NEXT:    fmv.s ft6, fa0
270; RV64IF-NEXT:    #APP
271; RV64IF-NEXT:    fcvt.w.s a0, ft6
272; RV64IF-NEXT:    #NO_APP
273; RV64IF-NEXT:    ret
274  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f6}"(float %a)
275  ret i32 %1
276}
277
278define i32 @explicit_register_ft6(float %a) nounwind {
279; RV32IF-LABEL: explicit_register_ft6:
280; RV32IF:       # %bb.0:
281; RV32IF-NEXT:    fmv.s ft6, fa0
282; RV32IF-NEXT:    #APP
283; RV32IF-NEXT:    fcvt.w.s a0, ft6
284; RV32IF-NEXT:    #NO_APP
285; RV32IF-NEXT:    ret
286;
287; RV64IF-LABEL: explicit_register_ft6:
288; RV64IF:       # %bb.0:
289; RV64IF-NEXT:    fmv.s ft6, fa0
290; RV64IF-NEXT:    #APP
291; RV64IF-NEXT:    fcvt.w.s a0, ft6
292; RV64IF-NEXT:    #NO_APP
293; RV64IF-NEXT:    ret
294  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft6}"(float %a)
295  ret i32 %1
296}
297
298define i32 @explicit_register_f7(float %a) nounwind {
299; RV32IF-LABEL: explicit_register_f7:
300; RV32IF:       # %bb.0:
301; RV32IF-NEXT:    fmv.s ft7, fa0
302; RV32IF-NEXT:    #APP
303; RV32IF-NEXT:    fcvt.w.s a0, ft7
304; RV32IF-NEXT:    #NO_APP
305; RV32IF-NEXT:    ret
306;
307; RV64IF-LABEL: explicit_register_f7:
308; RV64IF:       # %bb.0:
309; RV64IF-NEXT:    fmv.s ft7, fa0
310; RV64IF-NEXT:    #APP
311; RV64IF-NEXT:    fcvt.w.s a0, ft7
312; RV64IF-NEXT:    #NO_APP
313; RV64IF-NEXT:    ret
314  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f7}"(float %a)
315  ret i32 %1
316}
317
318define i32 @explicit_register_ft7(float %a) nounwind {
319; RV32IF-LABEL: explicit_register_ft7:
320; RV32IF:       # %bb.0:
321; RV32IF-NEXT:    fmv.s ft7, fa0
322; RV32IF-NEXT:    #APP
323; RV32IF-NEXT:    fcvt.w.s a0, ft7
324; RV32IF-NEXT:    #NO_APP
325; RV32IF-NEXT:    ret
326;
327; RV64IF-LABEL: explicit_register_ft7:
328; RV64IF:       # %bb.0:
329; RV64IF-NEXT:    fmv.s ft7, fa0
330; RV64IF-NEXT:    #APP
331; RV64IF-NEXT:    fcvt.w.s a0, ft7
332; RV64IF-NEXT:    #NO_APP
333; RV64IF-NEXT:    ret
334  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft7}"(float %a)
335  ret i32 %1
336}
337
338
339; NOTE: This test uses `f8` (`fs0`) as an input, so it should be saved.
340define i32 @explicit_register_f8(float %a) nounwind {
341; RV32IF-LABEL: explicit_register_f8:
342; RV32IF:       # %bb.0:
343; RV32IF-NEXT:    addi sp, sp, -16
344; RV32IF-NEXT:    fsw fs0, 12(sp)
345; RV32IF-NEXT:    fmv.s fs0, fa0
346; RV32IF-NEXT:    #APP
347; RV32IF-NEXT:    fcvt.w.s a0, fs0
348; RV32IF-NEXT:    #NO_APP
349; RV32IF-NEXT:    flw fs0, 12(sp)
350; RV32IF-NEXT:    addi sp, sp, 16
351; RV32IF-NEXT:    ret
352;
353; RV64IF-LABEL: explicit_register_f8:
354; RV64IF:       # %bb.0:
355; RV64IF-NEXT:    addi sp, sp, -16
356; RV64IF-NEXT:    fsw fs0, 12(sp)
357; RV64IF-NEXT:    fmv.s fs0, fa0
358; RV64IF-NEXT:    #APP
359; RV64IF-NEXT:    fcvt.w.s a0, fs0
360; RV64IF-NEXT:    #NO_APP
361; RV64IF-NEXT:    flw fs0, 12(sp)
362; RV64IF-NEXT:    addi sp, sp, 16
363; RV64IF-NEXT:    ret
364  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f8}"(float %a)
365  ret i32 %1
366}
367
368; NOTE: This test uses `fs0` (`f8`) as an input, so it should be saved.
369define i32 @explicit_register_fs0(float %a) nounwind {
370; RV32IF-LABEL: explicit_register_fs0:
371; RV32IF:       # %bb.0:
372; RV32IF-NEXT:    addi sp, sp, -16
373; RV32IF-NEXT:    fsw fs0, 12(sp)
374; RV32IF-NEXT:    fmv.s fs0, fa0
375; RV32IF-NEXT:    #APP
376; RV32IF-NEXT:    fcvt.w.s a0, fs0
377; RV32IF-NEXT:    #NO_APP
378; RV32IF-NEXT:    flw fs0, 12(sp)
379; RV32IF-NEXT:    addi sp, sp, 16
380; RV32IF-NEXT:    ret
381;
382; RV64IF-LABEL: explicit_register_fs0:
383; RV64IF:       # %bb.0:
384; RV64IF-NEXT:    addi sp, sp, -16
385; RV64IF-NEXT:    fsw fs0, 12(sp)
386; RV64IF-NEXT:    fmv.s fs0, fa0
387; RV64IF-NEXT:    #APP
388; RV64IF-NEXT:    fcvt.w.s a0, fs0
389; RV64IF-NEXT:    #NO_APP
390; RV64IF-NEXT:    flw fs0, 12(sp)
391; RV64IF-NEXT:    addi sp, sp, 16
392; RV64IF-NEXT:    ret
393  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs0}"(float %a)
394  ret i32 %1
395}
396
397; NOTE: This test uses `f9` (`fs1`) as an input, so it should be saved.
398define i32 @explicit_register_f9(float %a) nounwind {
399; RV32IF-LABEL: explicit_register_f9:
400; RV32IF:       # %bb.0:
401; RV32IF-NEXT:    addi sp, sp, -16
402; RV32IF-NEXT:    fsw fs1, 12(sp)
403; RV32IF-NEXT:    fmv.s fs1, fa0
404; RV32IF-NEXT:    #APP
405; RV32IF-NEXT:    fcvt.w.s a0, fs1
406; RV32IF-NEXT:    #NO_APP
407; RV32IF-NEXT:    flw fs1, 12(sp)
408; RV32IF-NEXT:    addi sp, sp, 16
409; RV32IF-NEXT:    ret
410;
411; RV64IF-LABEL: explicit_register_f9:
412; RV64IF:       # %bb.0:
413; RV64IF-NEXT:    addi sp, sp, -16
414; RV64IF-NEXT:    fsw fs1, 12(sp)
415; RV64IF-NEXT:    fmv.s fs1, fa0
416; RV64IF-NEXT:    #APP
417; RV64IF-NEXT:    fcvt.w.s a0, fs1
418; RV64IF-NEXT:    #NO_APP
419; RV64IF-NEXT:    flw fs1, 12(sp)
420; RV64IF-NEXT:    addi sp, sp, 16
421; RV64IF-NEXT:    ret
422  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f9}"(float %a)
423  ret i32 %1
424}
425
426; NOTE: This test uses `fs1` (`f9`) as an input, so it should be saved.
427define i32 @explicit_register_fs1(float %a) nounwind {
428; RV32IF-LABEL: explicit_register_fs1:
429; RV32IF:       # %bb.0:
430; RV32IF-NEXT:    addi sp, sp, -16
431; RV32IF-NEXT:    fsw fs1, 12(sp)
432; RV32IF-NEXT:    fmv.s fs1, fa0
433; RV32IF-NEXT:    #APP
434; RV32IF-NEXT:    fcvt.w.s a0, fs1
435; RV32IF-NEXT:    #NO_APP
436; RV32IF-NEXT:    flw fs1, 12(sp)
437; RV32IF-NEXT:    addi sp, sp, 16
438; RV32IF-NEXT:    ret
439;
440; RV64IF-LABEL: explicit_register_fs1:
441; RV64IF:       # %bb.0:
442; RV64IF-NEXT:    addi sp, sp, -16
443; RV64IF-NEXT:    fsw fs1, 12(sp)
444; RV64IF-NEXT:    fmv.s fs1, fa0
445; RV64IF-NEXT:    #APP
446; RV64IF-NEXT:    fcvt.w.s a0, fs1
447; RV64IF-NEXT:    #NO_APP
448; RV64IF-NEXT:    flw fs1, 12(sp)
449; RV64IF-NEXT:    addi sp, sp, 16
450; RV64IF-NEXT:    ret
451  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs1}"(float %a)
452  ret i32 %1
453}
454
455define i32 @explicit_register_f10(float %a) nounwind {
456; RV32IF-LABEL: explicit_register_f10:
457; RV32IF:       # %bb.0:
458; RV32IF-NEXT:    #APP
459; RV32IF-NEXT:    fcvt.w.s a0, fa0
460; RV32IF-NEXT:    #NO_APP
461; RV32IF-NEXT:    ret
462;
463; RV64IF-LABEL: explicit_register_f10:
464; RV64IF:       # %bb.0:
465; RV64IF-NEXT:    #APP
466; RV64IF-NEXT:    fcvt.w.s a0, fa0
467; RV64IF-NEXT:    #NO_APP
468; RV64IF-NEXT:    ret
469  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f10}"(float %a)
470  ret i32 %1
471}
472
473define i32 @explicit_register_fa0(float %a) nounwind {
474; RV32IF-LABEL: explicit_register_fa0:
475; RV32IF:       # %bb.0:
476; RV32IF-NEXT:    #APP
477; RV32IF-NEXT:    fcvt.w.s a0, fa0
478; RV32IF-NEXT:    #NO_APP
479; RV32IF-NEXT:    ret
480;
481; RV64IF-LABEL: explicit_register_fa0:
482; RV64IF:       # %bb.0:
483; RV64IF-NEXT:    #APP
484; RV64IF-NEXT:    fcvt.w.s a0, fa0
485; RV64IF-NEXT:    #NO_APP
486; RV64IF-NEXT:    ret
487  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa0}"(float %a)
488  ret i32 %1
489}
490
491define i32 @explicit_register_f11(float %a) nounwind {
492; RV32IF-LABEL: explicit_register_f11:
493; RV32IF:       # %bb.0:
494; RV32IF-NEXT:    fmv.s fa1, fa0
495; RV32IF-NEXT:    #APP
496; RV32IF-NEXT:    fcvt.w.s a0, fa1
497; RV32IF-NEXT:    #NO_APP
498; RV32IF-NEXT:    ret
499;
500; RV64IF-LABEL: explicit_register_f11:
501; RV64IF:       # %bb.0:
502; RV64IF-NEXT:    fmv.s fa1, fa0
503; RV64IF-NEXT:    #APP
504; RV64IF-NEXT:    fcvt.w.s a0, fa1
505; RV64IF-NEXT:    #NO_APP
506; RV64IF-NEXT:    ret
507  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f11}"(float %a)
508  ret i32 %1
509}
510
511define i32 @explicit_register_fa1(float %a) nounwind {
512; RV32IF-LABEL: explicit_register_fa1:
513; RV32IF:       # %bb.0:
514; RV32IF-NEXT:    fmv.s fa1, fa0
515; RV32IF-NEXT:    #APP
516; RV32IF-NEXT:    fcvt.w.s a0, fa1
517; RV32IF-NEXT:    #NO_APP
518; RV32IF-NEXT:    ret
519;
520; RV64IF-LABEL: explicit_register_fa1:
521; RV64IF:       # %bb.0:
522; RV64IF-NEXT:    fmv.s fa1, fa0
523; RV64IF-NEXT:    #APP
524; RV64IF-NEXT:    fcvt.w.s a0, fa1
525; RV64IF-NEXT:    #NO_APP
526; RV64IF-NEXT:    ret
527  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa1}"(float %a)
528  ret i32 %1
529}
530
531define i32 @explicit_register_f12(float %a) nounwind {
532; RV32IF-LABEL: explicit_register_f12:
533; RV32IF:       # %bb.0:
534; RV32IF-NEXT:    fmv.s fa2, fa0
535; RV32IF-NEXT:    #APP
536; RV32IF-NEXT:    fcvt.w.s a0, fa2
537; RV32IF-NEXT:    #NO_APP
538; RV32IF-NEXT:    ret
539;
540; RV64IF-LABEL: explicit_register_f12:
541; RV64IF:       # %bb.0:
542; RV64IF-NEXT:    fmv.s fa2, fa0
543; RV64IF-NEXT:    #APP
544; RV64IF-NEXT:    fcvt.w.s a0, fa2
545; RV64IF-NEXT:    #NO_APP
546; RV64IF-NEXT:    ret
547  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f12}"(float %a)
548  ret i32 %1
549}
550
551define i32 @explicit_register_fa2(float %a) nounwind {
552; RV32IF-LABEL: explicit_register_fa2:
553; RV32IF:       # %bb.0:
554; RV32IF-NEXT:    fmv.s fa2, fa0
555; RV32IF-NEXT:    #APP
556; RV32IF-NEXT:    fcvt.w.s a0, fa2
557; RV32IF-NEXT:    #NO_APP
558; RV32IF-NEXT:    ret
559;
560; RV64IF-LABEL: explicit_register_fa2:
561; RV64IF:       # %bb.0:
562; RV64IF-NEXT:    fmv.s fa2, fa0
563; RV64IF-NEXT:    #APP
564; RV64IF-NEXT:    fcvt.w.s a0, fa2
565; RV64IF-NEXT:    #NO_APP
566; RV64IF-NEXT:    ret
567  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa2}"(float %a)
568  ret i32 %1
569}
570
571define i32 @explicit_register_f13(float %a) nounwind {
572; RV32IF-LABEL: explicit_register_f13:
573; RV32IF:       # %bb.0:
574; RV32IF-NEXT:    fmv.s fa3, fa0
575; RV32IF-NEXT:    #APP
576; RV32IF-NEXT:    fcvt.w.s a0, fa3
577; RV32IF-NEXT:    #NO_APP
578; RV32IF-NEXT:    ret
579;
580; RV64IF-LABEL: explicit_register_f13:
581; RV64IF:       # %bb.0:
582; RV64IF-NEXT:    fmv.s fa3, fa0
583; RV64IF-NEXT:    #APP
584; RV64IF-NEXT:    fcvt.w.s a0, fa3
585; RV64IF-NEXT:    #NO_APP
586; RV64IF-NEXT:    ret
587  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f13}"(float %a)
588  ret i32 %1
589}
590
591define i32 @explicit_register_fa3(float %a) nounwind {
592; RV32IF-LABEL: explicit_register_fa3:
593; RV32IF:       # %bb.0:
594; RV32IF-NEXT:    fmv.s fa3, fa0
595; RV32IF-NEXT:    #APP
596; RV32IF-NEXT:    fcvt.w.s a0, fa3
597; RV32IF-NEXT:    #NO_APP
598; RV32IF-NEXT:    ret
599;
600; RV64IF-LABEL: explicit_register_fa3:
601; RV64IF:       # %bb.0:
602; RV64IF-NEXT:    fmv.s fa3, fa0
603; RV64IF-NEXT:    #APP
604; RV64IF-NEXT:    fcvt.w.s a0, fa3
605; RV64IF-NEXT:    #NO_APP
606; RV64IF-NEXT:    ret
607  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa3}"(float %a)
608  ret i32 %1
609}
610
611define i32 @explicit_register_f14(float %a) nounwind {
612; RV32IF-LABEL: explicit_register_f14:
613; RV32IF:       # %bb.0:
614; RV32IF-NEXT:    fmv.s fa4, fa0
615; RV32IF-NEXT:    #APP
616; RV32IF-NEXT:    fcvt.w.s a0, fa4
617; RV32IF-NEXT:    #NO_APP
618; RV32IF-NEXT:    ret
619;
620; RV64IF-LABEL: explicit_register_f14:
621; RV64IF:       # %bb.0:
622; RV64IF-NEXT:    fmv.s fa4, fa0
623; RV64IF-NEXT:    #APP
624; RV64IF-NEXT:    fcvt.w.s a0, fa4
625; RV64IF-NEXT:    #NO_APP
626; RV64IF-NEXT:    ret
627  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f14}"(float %a)
628  ret i32 %1
629}
630
631define i32 @explicit_register_fa4(float %a) nounwind {
632; RV32IF-LABEL: explicit_register_fa4:
633; RV32IF:       # %bb.0:
634; RV32IF-NEXT:    fmv.s fa4, fa0
635; RV32IF-NEXT:    #APP
636; RV32IF-NEXT:    fcvt.w.s a0, fa4
637; RV32IF-NEXT:    #NO_APP
638; RV32IF-NEXT:    ret
639;
640; RV64IF-LABEL: explicit_register_fa4:
641; RV64IF:       # %bb.0:
642; RV64IF-NEXT:    fmv.s fa4, fa0
643; RV64IF-NEXT:    #APP
644; RV64IF-NEXT:    fcvt.w.s a0, fa4
645; RV64IF-NEXT:    #NO_APP
646; RV64IF-NEXT:    ret
647  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa4}"(float %a)
648  ret i32 %1
649}
650
651define i32 @explicit_register_f15(float %a) nounwind {
652; RV32IF-LABEL: explicit_register_f15:
653; RV32IF:       # %bb.0:
654; RV32IF-NEXT:    fmv.s fa5, fa0
655; RV32IF-NEXT:    #APP
656; RV32IF-NEXT:    fcvt.w.s a0, fa5
657; RV32IF-NEXT:    #NO_APP
658; RV32IF-NEXT:    ret
659;
660; RV64IF-LABEL: explicit_register_f15:
661; RV64IF:       # %bb.0:
662; RV64IF-NEXT:    fmv.s fa5, fa0
663; RV64IF-NEXT:    #APP
664; RV64IF-NEXT:    fcvt.w.s a0, fa5
665; RV64IF-NEXT:    #NO_APP
666; RV64IF-NEXT:    ret
667  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f15}"(float %a)
668  ret i32 %1
669}
670
671define i32 @explicit_register_fa5(float %a) nounwind {
672; RV32IF-LABEL: explicit_register_fa5:
673; RV32IF:       # %bb.0:
674; RV32IF-NEXT:    fmv.s fa5, fa0
675; RV32IF-NEXT:    #APP
676; RV32IF-NEXT:    fcvt.w.s a0, fa5
677; RV32IF-NEXT:    #NO_APP
678; RV32IF-NEXT:    ret
679;
680; RV64IF-LABEL: explicit_register_fa5:
681; RV64IF:       # %bb.0:
682; RV64IF-NEXT:    fmv.s fa5, fa0
683; RV64IF-NEXT:    #APP
684; RV64IF-NEXT:    fcvt.w.s a0, fa5
685; RV64IF-NEXT:    #NO_APP
686; RV64IF-NEXT:    ret
687  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa5}"(float %a)
688  ret i32 %1
689}
690
691define i32 @explicit_register_f16(float %a) nounwind {
692; RV32IF-LABEL: explicit_register_f16:
693; RV32IF:       # %bb.0:
694; RV32IF-NEXT:    fmv.s fa6, fa0
695; RV32IF-NEXT:    #APP
696; RV32IF-NEXT:    fcvt.w.s a0, fa6
697; RV32IF-NEXT:    #NO_APP
698; RV32IF-NEXT:    ret
699;
700; RV64IF-LABEL: explicit_register_f16:
701; RV64IF:       # %bb.0:
702; RV64IF-NEXT:    fmv.s fa6, fa0
703; RV64IF-NEXT:    #APP
704; RV64IF-NEXT:    fcvt.w.s a0, fa6
705; RV64IF-NEXT:    #NO_APP
706; RV64IF-NEXT:    ret
707  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f16}"(float %a)
708  ret i32 %1
709}
710
711define i32 @explicit_register_fa6(float %a) nounwind {
712; RV32IF-LABEL: explicit_register_fa6:
713; RV32IF:       # %bb.0:
714; RV32IF-NEXT:    fmv.s fa6, fa0
715; RV32IF-NEXT:    #APP
716; RV32IF-NEXT:    fcvt.w.s a0, fa6
717; RV32IF-NEXT:    #NO_APP
718; RV32IF-NEXT:    ret
719;
720; RV64IF-LABEL: explicit_register_fa6:
721; RV64IF:       # %bb.0:
722; RV64IF-NEXT:    fmv.s fa6, fa0
723; RV64IF-NEXT:    #APP
724; RV64IF-NEXT:    fcvt.w.s a0, fa6
725; RV64IF-NEXT:    #NO_APP
726; RV64IF-NEXT:    ret
727  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa6}"(float %a)
728  ret i32 %1
729}
730
731define i32 @explicit_register_f17(float %a) nounwind {
732; RV32IF-LABEL: explicit_register_f17:
733; RV32IF:       # %bb.0:
734; RV32IF-NEXT:    fmv.s fa7, fa0
735; RV32IF-NEXT:    #APP
736; RV32IF-NEXT:    fcvt.w.s a0, fa7
737; RV32IF-NEXT:    #NO_APP
738; RV32IF-NEXT:    ret
739;
740; RV64IF-LABEL: explicit_register_f17:
741; RV64IF:       # %bb.0:
742; RV64IF-NEXT:    fmv.s fa7, fa0
743; RV64IF-NEXT:    #APP
744; RV64IF-NEXT:    fcvt.w.s a0, fa7
745; RV64IF-NEXT:    #NO_APP
746; RV64IF-NEXT:    ret
747  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f17}"(float %a)
748  ret i32 %1
749}
750
751define i32 @explicit_register_fa7(float %a) nounwind {
752; RV32IF-LABEL: explicit_register_fa7:
753; RV32IF:       # %bb.0:
754; RV32IF-NEXT:    fmv.s fa7, fa0
755; RV32IF-NEXT:    #APP
756; RV32IF-NEXT:    fcvt.w.s a0, fa7
757; RV32IF-NEXT:    #NO_APP
758; RV32IF-NEXT:    ret
759;
760; RV64IF-LABEL: explicit_register_fa7:
761; RV64IF:       # %bb.0:
762; RV64IF-NEXT:    fmv.s fa7, fa0
763; RV64IF-NEXT:    #APP
764; RV64IF-NEXT:    fcvt.w.s a0, fa7
765; RV64IF-NEXT:    #NO_APP
766; RV64IF-NEXT:    ret
767  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa7}"(float %a)
768  ret i32 %1
769}
770
771; NOTE: This test uses `f18` (`fs2`) as an input, so it should be saved.
772define i32 @explicit_register_f18(float %a) nounwind {
773; RV32IF-LABEL: explicit_register_f18:
774; RV32IF:       # %bb.0:
775; RV32IF-NEXT:    addi sp, sp, -16
776; RV32IF-NEXT:    fsw fs2, 12(sp)
777; RV32IF-NEXT:    fmv.s fs2, fa0
778; RV32IF-NEXT:    #APP
779; RV32IF-NEXT:    fcvt.w.s a0, fs2
780; RV32IF-NEXT:    #NO_APP
781; RV32IF-NEXT:    flw fs2, 12(sp)
782; RV32IF-NEXT:    addi sp, sp, 16
783; RV32IF-NEXT:    ret
784;
785; RV64IF-LABEL: explicit_register_f18:
786; RV64IF:       # %bb.0:
787; RV64IF-NEXT:    addi sp, sp, -16
788; RV64IF-NEXT:    fsw fs2, 12(sp)
789; RV64IF-NEXT:    fmv.s fs2, fa0
790; RV64IF-NEXT:    #APP
791; RV64IF-NEXT:    fcvt.w.s a0, fs2
792; RV64IF-NEXT:    #NO_APP
793; RV64IF-NEXT:    flw fs2, 12(sp)
794; RV64IF-NEXT:    addi sp, sp, 16
795; RV64IF-NEXT:    ret
796  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f18}"(float %a)
797  ret i32 %1
798}
799
800; NOTE: This test uses `fs2` (`f18`) as an input, so it should be saved.
801define i32 @explicit_register_fs2(float %a) nounwind {
802; RV32IF-LABEL: explicit_register_fs2:
803; RV32IF:       # %bb.0:
804; RV32IF-NEXT:    addi sp, sp, -16
805; RV32IF-NEXT:    fsw fs2, 12(sp)
806; RV32IF-NEXT:    fmv.s fs2, fa0
807; RV32IF-NEXT:    #APP
808; RV32IF-NEXT:    fcvt.w.s a0, fs2
809; RV32IF-NEXT:    #NO_APP
810; RV32IF-NEXT:    flw fs2, 12(sp)
811; RV32IF-NEXT:    addi sp, sp, 16
812; RV32IF-NEXT:    ret
813;
814; RV64IF-LABEL: explicit_register_fs2:
815; RV64IF:       # %bb.0:
816; RV64IF-NEXT:    addi sp, sp, -16
817; RV64IF-NEXT:    fsw fs2, 12(sp)
818; RV64IF-NEXT:    fmv.s fs2, fa0
819; RV64IF-NEXT:    #APP
820; RV64IF-NEXT:    fcvt.w.s a0, fs2
821; RV64IF-NEXT:    #NO_APP
822; RV64IF-NEXT:    flw fs2, 12(sp)
823; RV64IF-NEXT:    addi sp, sp, 16
824; RV64IF-NEXT:    ret
825  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs2}"(float %a)
826  ret i32 %1
827}
828
829; NOTE: This test uses `f19` (`fs3`) as an input, so it should be saved.
830define i32 @explicit_register_f19(float %a) nounwind {
831; RV32IF-LABEL: explicit_register_f19:
832; RV32IF:       # %bb.0:
833; RV32IF-NEXT:    addi sp, sp, -16
834; RV32IF-NEXT:    fsw fs3, 12(sp)
835; RV32IF-NEXT:    fmv.s fs3, fa0
836; RV32IF-NEXT:    #APP
837; RV32IF-NEXT:    fcvt.w.s a0, fs3
838; RV32IF-NEXT:    #NO_APP
839; RV32IF-NEXT:    flw fs3, 12(sp)
840; RV32IF-NEXT:    addi sp, sp, 16
841; RV32IF-NEXT:    ret
842;
843; RV64IF-LABEL: explicit_register_f19:
844; RV64IF:       # %bb.0:
845; RV64IF-NEXT:    addi sp, sp, -16
846; RV64IF-NEXT:    fsw fs3, 12(sp)
847; RV64IF-NEXT:    fmv.s fs3, fa0
848; RV64IF-NEXT:    #APP
849; RV64IF-NEXT:    fcvt.w.s a0, fs3
850; RV64IF-NEXT:    #NO_APP
851; RV64IF-NEXT:    flw fs3, 12(sp)
852; RV64IF-NEXT:    addi sp, sp, 16
853; RV64IF-NEXT:    ret
854  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f19}"(float %a)
855  ret i32 %1
856}
857
858; NOTE: This test uses `fs3` (`f19`) as an input, so it should be saved.
859define i32 @explicit_register_fs3(float %a) nounwind {
860; RV32IF-LABEL: explicit_register_fs3:
861; RV32IF:       # %bb.0:
862; RV32IF-NEXT:    addi sp, sp, -16
863; RV32IF-NEXT:    fsw fs3, 12(sp)
864; RV32IF-NEXT:    fmv.s fs3, fa0
865; RV32IF-NEXT:    #APP
866; RV32IF-NEXT:    fcvt.w.s a0, fs3
867; RV32IF-NEXT:    #NO_APP
868; RV32IF-NEXT:    flw fs3, 12(sp)
869; RV32IF-NEXT:    addi sp, sp, 16
870; RV32IF-NEXT:    ret
871;
872; RV64IF-LABEL: explicit_register_fs3:
873; RV64IF:       # %bb.0:
874; RV64IF-NEXT:    addi sp, sp, -16
875; RV64IF-NEXT:    fsw fs3, 12(sp)
876; RV64IF-NEXT:    fmv.s fs3, fa0
877; RV64IF-NEXT:    #APP
878; RV64IF-NEXT:    fcvt.w.s a0, fs3
879; RV64IF-NEXT:    #NO_APP
880; RV64IF-NEXT:    flw fs3, 12(sp)
881; RV64IF-NEXT:    addi sp, sp, 16
882; RV64IF-NEXT:    ret
883  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs3}"(float %a)
884  ret i32 %1
885}
886
887; NOTE: This test uses `f20` (`fs4`) as an input, so it should be saved.
888define i32 @explicit_register_f20(float %a) nounwind {
889; RV32IF-LABEL: explicit_register_f20:
890; RV32IF:       # %bb.0:
891; RV32IF-NEXT:    addi sp, sp, -16
892; RV32IF-NEXT:    fsw fs4, 12(sp)
893; RV32IF-NEXT:    fmv.s fs4, fa0
894; RV32IF-NEXT:    #APP
895; RV32IF-NEXT:    fcvt.w.s a0, fs4
896; RV32IF-NEXT:    #NO_APP
897; RV32IF-NEXT:    flw fs4, 12(sp)
898; RV32IF-NEXT:    addi sp, sp, 16
899; RV32IF-NEXT:    ret
900;
901; RV64IF-LABEL: explicit_register_f20:
902; RV64IF:       # %bb.0:
903; RV64IF-NEXT:    addi sp, sp, -16
904; RV64IF-NEXT:    fsw fs4, 12(sp)
905; RV64IF-NEXT:    fmv.s fs4, fa0
906; RV64IF-NEXT:    #APP
907; RV64IF-NEXT:    fcvt.w.s a0, fs4
908; RV64IF-NEXT:    #NO_APP
909; RV64IF-NEXT:    flw fs4, 12(sp)
910; RV64IF-NEXT:    addi sp, sp, 16
911; RV64IF-NEXT:    ret
912  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f20}"(float %a)
913  ret i32 %1
914}
915
916; NOTE: This test uses `fs4` (`f20`) as an input, so it should be saved.
917define i32 @explicit_register_fs4(float %a) nounwind {
918; RV32IF-LABEL: explicit_register_fs4:
919; RV32IF:       # %bb.0:
920; RV32IF-NEXT:    addi sp, sp, -16
921; RV32IF-NEXT:    fsw fs4, 12(sp)
922; RV32IF-NEXT:    fmv.s fs4, fa0
923; RV32IF-NEXT:    #APP
924; RV32IF-NEXT:    fcvt.w.s a0, fs4
925; RV32IF-NEXT:    #NO_APP
926; RV32IF-NEXT:    flw fs4, 12(sp)
927; RV32IF-NEXT:    addi sp, sp, 16
928; RV32IF-NEXT:    ret
929;
930; RV64IF-LABEL: explicit_register_fs4:
931; RV64IF:       # %bb.0:
932; RV64IF-NEXT:    addi sp, sp, -16
933; RV64IF-NEXT:    fsw fs4, 12(sp)
934; RV64IF-NEXT:    fmv.s fs4, fa0
935; RV64IF-NEXT:    #APP
936; RV64IF-NEXT:    fcvt.w.s a0, fs4
937; RV64IF-NEXT:    #NO_APP
938; RV64IF-NEXT:    flw fs4, 12(sp)
939; RV64IF-NEXT:    addi sp, sp, 16
940; RV64IF-NEXT:    ret
941  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs4}"(float %a)
942  ret i32 %1
943}
944
945; NOTE: This test uses `f21` (`fs5`) as an input, so it should be saved.
946define i32 @explicit_register_f21(float %a) nounwind {
947; RV32IF-LABEL: explicit_register_f21:
948; RV32IF:       # %bb.0:
949; RV32IF-NEXT:    addi sp, sp, -16
950; RV32IF-NEXT:    fsw fs5, 12(sp)
951; RV32IF-NEXT:    fmv.s fs5, fa0
952; RV32IF-NEXT:    #APP
953; RV32IF-NEXT:    fcvt.w.s a0, fs5
954; RV32IF-NEXT:    #NO_APP
955; RV32IF-NEXT:    flw fs5, 12(sp)
956; RV32IF-NEXT:    addi sp, sp, 16
957; RV32IF-NEXT:    ret
958;
959; RV64IF-LABEL: explicit_register_f21:
960; RV64IF:       # %bb.0:
961; RV64IF-NEXT:    addi sp, sp, -16
962; RV64IF-NEXT:    fsw fs5, 12(sp)
963; RV64IF-NEXT:    fmv.s fs5, fa0
964; RV64IF-NEXT:    #APP
965; RV64IF-NEXT:    fcvt.w.s a0, fs5
966; RV64IF-NEXT:    #NO_APP
967; RV64IF-NEXT:    flw fs5, 12(sp)
968; RV64IF-NEXT:    addi sp, sp, 16
969; RV64IF-NEXT:    ret
970  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f21}"(float %a)
971  ret i32 %1
972}
973
974; NOTE: This test uses `fs5` (`f21`) as an input, so it should be saved.
975define i32 @explicit_register_fs5(float %a) nounwind {
976; RV32IF-LABEL: explicit_register_fs5:
977; RV32IF:       # %bb.0:
978; RV32IF-NEXT:    addi sp, sp, -16
979; RV32IF-NEXT:    fsw fs5, 12(sp)
980; RV32IF-NEXT:    fmv.s fs5, fa0
981; RV32IF-NEXT:    #APP
982; RV32IF-NEXT:    fcvt.w.s a0, fs5
983; RV32IF-NEXT:    #NO_APP
984; RV32IF-NEXT:    flw fs5, 12(sp)
985; RV32IF-NEXT:    addi sp, sp, 16
986; RV32IF-NEXT:    ret
987;
988; RV64IF-LABEL: explicit_register_fs5:
989; RV64IF:       # %bb.0:
990; RV64IF-NEXT:    addi sp, sp, -16
991; RV64IF-NEXT:    fsw fs5, 12(sp)
992; RV64IF-NEXT:    fmv.s fs5, fa0
993; RV64IF-NEXT:    #APP
994; RV64IF-NEXT:    fcvt.w.s a0, fs5
995; RV64IF-NEXT:    #NO_APP
996; RV64IF-NEXT:    flw fs5, 12(sp)
997; RV64IF-NEXT:    addi sp, sp, 16
998; RV64IF-NEXT:    ret
999  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs5}"(float %a)
1000  ret i32 %1
1001}
1002
1003; NOTE: This test uses `f22` (`fs6`) as an input, so it should be saved.
1004define i32 @explicit_register_f22(float %a) nounwind {
1005; RV32IF-LABEL: explicit_register_f22:
1006; RV32IF:       # %bb.0:
1007; RV32IF-NEXT:    addi sp, sp, -16
1008; RV32IF-NEXT:    fsw fs6, 12(sp)
1009; RV32IF-NEXT:    fmv.s fs6, fa0
1010; RV32IF-NEXT:    #APP
1011; RV32IF-NEXT:    fcvt.w.s a0, fs6
1012; RV32IF-NEXT:    #NO_APP
1013; RV32IF-NEXT:    flw fs6, 12(sp)
1014; RV32IF-NEXT:    addi sp, sp, 16
1015; RV32IF-NEXT:    ret
1016;
1017; RV64IF-LABEL: explicit_register_f22:
1018; RV64IF:       # %bb.0:
1019; RV64IF-NEXT:    addi sp, sp, -16
1020; RV64IF-NEXT:    fsw fs6, 12(sp)
1021; RV64IF-NEXT:    fmv.s fs6, fa0
1022; RV64IF-NEXT:    #APP
1023; RV64IF-NEXT:    fcvt.w.s a0, fs6
1024; RV64IF-NEXT:    #NO_APP
1025; RV64IF-NEXT:    flw fs6, 12(sp)
1026; RV64IF-NEXT:    addi sp, sp, 16
1027; RV64IF-NEXT:    ret
1028  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f22}"(float %a)
1029  ret i32 %1
1030}
1031
1032; NOTE: This test uses `fs6` (`f22`) as an input, so it should be saved.
1033define i32 @explicit_register_fs6(float %a) nounwind {
1034; RV32IF-LABEL: explicit_register_fs6:
1035; RV32IF:       # %bb.0:
1036; RV32IF-NEXT:    addi sp, sp, -16
1037; RV32IF-NEXT:    fsw fs6, 12(sp)
1038; RV32IF-NEXT:    fmv.s fs6, fa0
1039; RV32IF-NEXT:    #APP
1040; RV32IF-NEXT:    fcvt.w.s a0, fs6
1041; RV32IF-NEXT:    #NO_APP
1042; RV32IF-NEXT:    flw fs6, 12(sp)
1043; RV32IF-NEXT:    addi sp, sp, 16
1044; RV32IF-NEXT:    ret
1045;
1046; RV64IF-LABEL: explicit_register_fs6:
1047; RV64IF:       # %bb.0:
1048; RV64IF-NEXT:    addi sp, sp, -16
1049; RV64IF-NEXT:    fsw fs6, 12(sp)
1050; RV64IF-NEXT:    fmv.s fs6, fa0
1051; RV64IF-NEXT:    #APP
1052; RV64IF-NEXT:    fcvt.w.s a0, fs6
1053; RV64IF-NEXT:    #NO_APP
1054; RV64IF-NEXT:    flw fs6, 12(sp)
1055; RV64IF-NEXT:    addi sp, sp, 16
1056; RV64IF-NEXT:    ret
1057  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs6}"(float %a)
1058  ret i32 %1
1059}
1060
1061; NOTE: This test uses `f23` (`fs7`) as an input, so it should be saved.
1062define i32 @explicit_register_f23(float %a) nounwind {
1063; RV32IF-LABEL: explicit_register_f23:
1064; RV32IF:       # %bb.0:
1065; RV32IF-NEXT:    addi sp, sp, -16
1066; RV32IF-NEXT:    fsw fs7, 12(sp)
1067; RV32IF-NEXT:    fmv.s fs7, fa0
1068; RV32IF-NEXT:    #APP
1069; RV32IF-NEXT:    fcvt.w.s a0, fs7
1070; RV32IF-NEXT:    #NO_APP
1071; RV32IF-NEXT:    flw fs7, 12(sp)
1072; RV32IF-NEXT:    addi sp, sp, 16
1073; RV32IF-NEXT:    ret
1074;
1075; RV64IF-LABEL: explicit_register_f23:
1076; RV64IF:       # %bb.0:
1077; RV64IF-NEXT:    addi sp, sp, -16
1078; RV64IF-NEXT:    fsw fs7, 12(sp)
1079; RV64IF-NEXT:    fmv.s fs7, fa0
1080; RV64IF-NEXT:    #APP
1081; RV64IF-NEXT:    fcvt.w.s a0, fs7
1082; RV64IF-NEXT:    #NO_APP
1083; RV64IF-NEXT:    flw fs7, 12(sp)
1084; RV64IF-NEXT:    addi sp, sp, 16
1085; RV64IF-NEXT:    ret
1086  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f23}"(float %a)
1087  ret i32 %1
1088}
1089
1090; NOTE: This test uses `fs7` (`f23`) as an input, so it should be saved.
1091define i32 @explicit_register_fs7(float %a) nounwind {
1092; RV32IF-LABEL: explicit_register_fs7:
1093; RV32IF:       # %bb.0:
1094; RV32IF-NEXT:    addi sp, sp, -16
1095; RV32IF-NEXT:    fsw fs7, 12(sp)
1096; RV32IF-NEXT:    fmv.s fs7, fa0
1097; RV32IF-NEXT:    #APP
1098; RV32IF-NEXT:    fcvt.w.s a0, fs7
1099; RV32IF-NEXT:    #NO_APP
1100; RV32IF-NEXT:    flw fs7, 12(sp)
1101; RV32IF-NEXT:    addi sp, sp, 16
1102; RV32IF-NEXT:    ret
1103;
1104; RV64IF-LABEL: explicit_register_fs7:
1105; RV64IF:       # %bb.0:
1106; RV64IF-NEXT:    addi sp, sp, -16
1107; RV64IF-NEXT:    fsw fs7, 12(sp)
1108; RV64IF-NEXT:    fmv.s fs7, fa0
1109; RV64IF-NEXT:    #APP
1110; RV64IF-NEXT:    fcvt.w.s a0, fs7
1111; RV64IF-NEXT:    #NO_APP
1112; RV64IF-NEXT:    flw fs7, 12(sp)
1113; RV64IF-NEXT:    addi sp, sp, 16
1114; RV64IF-NEXT:    ret
1115  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs7}"(float %a)
1116  ret i32 %1
1117}
1118
1119; NOTE: This test uses `f24` (`fs8`) as an input, so it should be saved.
1120define i32 @explicit_register_f24(float %a) nounwind {
1121; RV32IF-LABEL: explicit_register_f24:
1122; RV32IF:       # %bb.0:
1123; RV32IF-NEXT:    addi sp, sp, -16
1124; RV32IF-NEXT:    fsw fs8, 12(sp)
1125; RV32IF-NEXT:    fmv.s fs8, fa0
1126; RV32IF-NEXT:    #APP
1127; RV32IF-NEXT:    fcvt.w.s a0, fs8
1128; RV32IF-NEXT:    #NO_APP
1129; RV32IF-NEXT:    flw fs8, 12(sp)
1130; RV32IF-NEXT:    addi sp, sp, 16
1131; RV32IF-NEXT:    ret
1132;
1133; RV64IF-LABEL: explicit_register_f24:
1134; RV64IF:       # %bb.0:
1135; RV64IF-NEXT:    addi sp, sp, -16
1136; RV64IF-NEXT:    fsw fs8, 12(sp)
1137; RV64IF-NEXT:    fmv.s fs8, fa0
1138; RV64IF-NEXT:    #APP
1139; RV64IF-NEXT:    fcvt.w.s a0, fs8
1140; RV64IF-NEXT:    #NO_APP
1141; RV64IF-NEXT:    flw fs8, 12(sp)
1142; RV64IF-NEXT:    addi sp, sp, 16
1143; RV64IF-NEXT:    ret
1144  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f24}"(float %a)
1145  ret i32 %1
1146}
1147
1148; NOTE: This test uses `fs8` (`f24`) as an input, so it should be saved.
1149define i32 @explicit_register_fs8(float %a) nounwind {
1150; RV32IF-LABEL: explicit_register_fs8:
1151; RV32IF:       # %bb.0:
1152; RV32IF-NEXT:    addi sp, sp, -16
1153; RV32IF-NEXT:    fsw fs8, 12(sp)
1154; RV32IF-NEXT:    fmv.s fs8, fa0
1155; RV32IF-NEXT:    #APP
1156; RV32IF-NEXT:    fcvt.w.s a0, fs8
1157; RV32IF-NEXT:    #NO_APP
1158; RV32IF-NEXT:    flw fs8, 12(sp)
1159; RV32IF-NEXT:    addi sp, sp, 16
1160; RV32IF-NEXT:    ret
1161;
1162; RV64IF-LABEL: explicit_register_fs8:
1163; RV64IF:       # %bb.0:
1164; RV64IF-NEXT:    addi sp, sp, -16
1165; RV64IF-NEXT:    fsw fs8, 12(sp)
1166; RV64IF-NEXT:    fmv.s fs8, fa0
1167; RV64IF-NEXT:    #APP
1168; RV64IF-NEXT:    fcvt.w.s a0, fs8
1169; RV64IF-NEXT:    #NO_APP
1170; RV64IF-NEXT:    flw fs8, 12(sp)
1171; RV64IF-NEXT:    addi sp, sp, 16
1172; RV64IF-NEXT:    ret
1173  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs8}"(float %a)
1174  ret i32 %1
1175}
1176
1177; NOTE: This test uses `f25` (`fs9`) as an input, so it should be saved.
1178define i32 @explicit_register_f25(float %a) nounwind {
1179; RV32IF-LABEL: explicit_register_f25:
1180; RV32IF:       # %bb.0:
1181; RV32IF-NEXT:    addi sp, sp, -16
1182; RV32IF-NEXT:    fsw fs9, 12(sp)
1183; RV32IF-NEXT:    fmv.s fs9, fa0
1184; RV32IF-NEXT:    #APP
1185; RV32IF-NEXT:    fcvt.w.s a0, fs9
1186; RV32IF-NEXT:    #NO_APP
1187; RV32IF-NEXT:    flw fs9, 12(sp)
1188; RV32IF-NEXT:    addi sp, sp, 16
1189; RV32IF-NEXT:    ret
1190;
1191; RV64IF-LABEL: explicit_register_f25:
1192; RV64IF:       # %bb.0:
1193; RV64IF-NEXT:    addi sp, sp, -16
1194; RV64IF-NEXT:    fsw fs9, 12(sp)
1195; RV64IF-NEXT:    fmv.s fs9, fa0
1196; RV64IF-NEXT:    #APP
1197; RV64IF-NEXT:    fcvt.w.s a0, fs9
1198; RV64IF-NEXT:    #NO_APP
1199; RV64IF-NEXT:    flw fs9, 12(sp)
1200; RV64IF-NEXT:    addi sp, sp, 16
1201; RV64IF-NEXT:    ret
1202  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f25}"(float %a)
1203  ret i32 %1
1204}
1205
1206; NOTE: This test uses `fs9` (`f25`) as an input, so it should be saved.
1207define i32 @explicit_register_fs9(float %a) nounwind {
1208; RV32IF-LABEL: explicit_register_fs9:
1209; RV32IF:       # %bb.0:
1210; RV32IF-NEXT:    addi sp, sp, -16
1211; RV32IF-NEXT:    fsw fs9, 12(sp)
1212; RV32IF-NEXT:    fmv.s fs9, fa0
1213; RV32IF-NEXT:    #APP
1214; RV32IF-NEXT:    fcvt.w.s a0, fs9
1215; RV32IF-NEXT:    #NO_APP
1216; RV32IF-NEXT:    flw fs9, 12(sp)
1217; RV32IF-NEXT:    addi sp, sp, 16
1218; RV32IF-NEXT:    ret
1219;
1220; RV64IF-LABEL: explicit_register_fs9:
1221; RV64IF:       # %bb.0:
1222; RV64IF-NEXT:    addi sp, sp, -16
1223; RV64IF-NEXT:    fsw fs9, 12(sp)
1224; RV64IF-NEXT:    fmv.s fs9, fa0
1225; RV64IF-NEXT:    #APP
1226; RV64IF-NEXT:    fcvt.w.s a0, fs9
1227; RV64IF-NEXT:    #NO_APP
1228; RV64IF-NEXT:    flw fs9, 12(sp)
1229; RV64IF-NEXT:    addi sp, sp, 16
1230; RV64IF-NEXT:    ret
1231  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs9}"(float %a)
1232  ret i32 %1
1233}
1234
1235; NOTE: This test uses `f26` (`fs10`) as an input, so it should be saved.
1236define i32 @explicit_register_f26(float %a) nounwind {
1237; RV32IF-LABEL: explicit_register_f26:
1238; RV32IF:       # %bb.0:
1239; RV32IF-NEXT:    addi sp, sp, -16
1240; RV32IF-NEXT:    fsw fs10, 12(sp)
1241; RV32IF-NEXT:    fmv.s fs10, fa0
1242; RV32IF-NEXT:    #APP
1243; RV32IF-NEXT:    fcvt.w.s a0, fs10
1244; RV32IF-NEXT:    #NO_APP
1245; RV32IF-NEXT:    flw fs10, 12(sp)
1246; RV32IF-NEXT:    addi sp, sp, 16
1247; RV32IF-NEXT:    ret
1248;
1249; RV64IF-LABEL: explicit_register_f26:
1250; RV64IF:       # %bb.0:
1251; RV64IF-NEXT:    addi sp, sp, -16
1252; RV64IF-NEXT:    fsw fs10, 12(sp)
1253; RV64IF-NEXT:    fmv.s fs10, fa0
1254; RV64IF-NEXT:    #APP
1255; RV64IF-NEXT:    fcvt.w.s a0, fs10
1256; RV64IF-NEXT:    #NO_APP
1257; RV64IF-NEXT:    flw fs10, 12(sp)
1258; RV64IF-NEXT:    addi sp, sp, 16
1259; RV64IF-NEXT:    ret
1260  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f26}"(float %a)
1261  ret i32 %1
1262}
1263
1264; NOTE: This test uses `fs10` (`f26`) as an input, so it should be saved.
1265define i32 @explicit_register_fs10(float %a) nounwind {
1266; RV32IF-LABEL: explicit_register_fs10:
1267; RV32IF:       # %bb.0:
1268; RV32IF-NEXT:    addi sp, sp, -16
1269; RV32IF-NEXT:    fsw fs10, 12(sp)
1270; RV32IF-NEXT:    fmv.s fs10, fa0
1271; RV32IF-NEXT:    #APP
1272; RV32IF-NEXT:    fcvt.w.s a0, fs10
1273; RV32IF-NEXT:    #NO_APP
1274; RV32IF-NEXT:    flw fs10, 12(sp)
1275; RV32IF-NEXT:    addi sp, sp, 16
1276; RV32IF-NEXT:    ret
1277;
1278; RV64IF-LABEL: explicit_register_fs10:
1279; RV64IF:       # %bb.0:
1280; RV64IF-NEXT:    addi sp, sp, -16
1281; RV64IF-NEXT:    fsw fs10, 12(sp)
1282; RV64IF-NEXT:    fmv.s fs10, fa0
1283; RV64IF-NEXT:    #APP
1284; RV64IF-NEXT:    fcvt.w.s a0, fs10
1285; RV64IF-NEXT:    #NO_APP
1286; RV64IF-NEXT:    flw fs10, 12(sp)
1287; RV64IF-NEXT:    addi sp, sp, 16
1288; RV64IF-NEXT:    ret
1289  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs10}"(float %a)
1290  ret i32 %1
1291}
1292
1293; NOTE: This test uses `f27` (`fs11`) as an input, so it should be saved.
1294define i32 @explicit_register_f27(float %a) nounwind {
1295; RV32IF-LABEL: explicit_register_f27:
1296; RV32IF:       # %bb.0:
1297; RV32IF-NEXT:    addi sp, sp, -16
1298; RV32IF-NEXT:    fsw fs11, 12(sp)
1299; RV32IF-NEXT:    fmv.s fs11, fa0
1300; RV32IF-NEXT:    #APP
1301; RV32IF-NEXT:    fcvt.w.s a0, fs11
1302; RV32IF-NEXT:    #NO_APP
1303; RV32IF-NEXT:    flw fs11, 12(sp)
1304; RV32IF-NEXT:    addi sp, sp, 16
1305; RV32IF-NEXT:    ret
1306;
1307; RV64IF-LABEL: explicit_register_f27:
1308; RV64IF:       # %bb.0:
1309; RV64IF-NEXT:    addi sp, sp, -16
1310; RV64IF-NEXT:    fsw fs11, 12(sp)
1311; RV64IF-NEXT:    fmv.s fs11, fa0
1312; RV64IF-NEXT:    #APP
1313; RV64IF-NEXT:    fcvt.w.s a0, fs11
1314; RV64IF-NEXT:    #NO_APP
1315; RV64IF-NEXT:    flw fs11, 12(sp)
1316; RV64IF-NEXT:    addi sp, sp, 16
1317; RV64IF-NEXT:    ret
1318  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f27}"(float %a)
1319  ret i32 %1
1320}
1321
1322; NOTE: This test uses `fs11` (`f27`) as an input, so it should be saved.
1323define i32 @explicit_register_fs11(float %a) nounwind {
1324; RV32IF-LABEL: explicit_register_fs11:
1325; RV32IF:       # %bb.0:
1326; RV32IF-NEXT:    addi sp, sp, -16
1327; RV32IF-NEXT:    fsw fs11, 12(sp)
1328; RV32IF-NEXT:    fmv.s fs11, fa0
1329; RV32IF-NEXT:    #APP
1330; RV32IF-NEXT:    fcvt.w.s a0, fs11
1331; RV32IF-NEXT:    #NO_APP
1332; RV32IF-NEXT:    flw fs11, 12(sp)
1333; RV32IF-NEXT:    addi sp, sp, 16
1334; RV32IF-NEXT:    ret
1335;
1336; RV64IF-LABEL: explicit_register_fs11:
1337; RV64IF:       # %bb.0:
1338; RV64IF-NEXT:    addi sp, sp, -16
1339; RV64IF-NEXT:    fsw fs11, 12(sp)
1340; RV64IF-NEXT:    fmv.s fs11, fa0
1341; RV64IF-NEXT:    #APP
1342; RV64IF-NEXT:    fcvt.w.s a0, fs11
1343; RV64IF-NEXT:    #NO_APP
1344; RV64IF-NEXT:    flw fs11, 12(sp)
1345; RV64IF-NEXT:    addi sp, sp, 16
1346; RV64IF-NEXT:    ret
1347  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs11}"(float %a)
1348  ret i32 %1
1349}
1350
1351define i32 @explicit_register_f28(float %a) nounwind {
1352; RV32IF-LABEL: explicit_register_f28:
1353; RV32IF:       # %bb.0:
1354; RV32IF-NEXT:    fmv.s ft8, fa0
1355; RV32IF-NEXT:    #APP
1356; RV32IF-NEXT:    fcvt.w.s a0, ft8
1357; RV32IF-NEXT:    #NO_APP
1358; RV32IF-NEXT:    ret
1359;
1360; RV64IF-LABEL: explicit_register_f28:
1361; RV64IF:       # %bb.0:
1362; RV64IF-NEXT:    fmv.s ft8, fa0
1363; RV64IF-NEXT:    #APP
1364; RV64IF-NEXT:    fcvt.w.s a0, ft8
1365; RV64IF-NEXT:    #NO_APP
1366; RV64IF-NEXT:    ret
1367  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f28}"(float %a)
1368  ret i32 %1
1369}
1370
1371define i32 @explicit_register_ft8(float %a) nounwind {
1372; RV32IF-LABEL: explicit_register_ft8:
1373; RV32IF:       # %bb.0:
1374; RV32IF-NEXT:    fmv.s ft8, fa0
1375; RV32IF-NEXT:    #APP
1376; RV32IF-NEXT:    fcvt.w.s a0, ft8
1377; RV32IF-NEXT:    #NO_APP
1378; RV32IF-NEXT:    ret
1379;
1380; RV64IF-LABEL: explicit_register_ft8:
1381; RV64IF:       # %bb.0:
1382; RV64IF-NEXT:    fmv.s ft8, fa0
1383; RV64IF-NEXT:    #APP
1384; RV64IF-NEXT:    fcvt.w.s a0, ft8
1385; RV64IF-NEXT:    #NO_APP
1386; RV64IF-NEXT:    ret
1387  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft8}"(float %a)
1388  ret i32 %1
1389}
1390
1391define i32 @explicit_register_f29(float %a) nounwind {
1392; RV32IF-LABEL: explicit_register_f29:
1393; RV32IF:       # %bb.0:
1394; RV32IF-NEXT:    fmv.s ft9, fa0
1395; RV32IF-NEXT:    #APP
1396; RV32IF-NEXT:    fcvt.w.s a0, ft9
1397; RV32IF-NEXT:    #NO_APP
1398; RV32IF-NEXT:    ret
1399;
1400; RV64IF-LABEL: explicit_register_f29:
1401; RV64IF:       # %bb.0:
1402; RV64IF-NEXT:    fmv.s ft9, fa0
1403; RV64IF-NEXT:    #APP
1404; RV64IF-NEXT:    fcvt.w.s a0, ft9
1405; RV64IF-NEXT:    #NO_APP
1406; RV64IF-NEXT:    ret
1407  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f29}"(float %a)
1408  ret i32 %1
1409}
1410
1411define i32 @explicit_register_ft9(float %a) nounwind {
1412; RV32IF-LABEL: explicit_register_ft9:
1413; RV32IF:       # %bb.0:
1414; RV32IF-NEXT:    fmv.s ft9, fa0
1415; RV32IF-NEXT:    #APP
1416; RV32IF-NEXT:    fcvt.w.s a0, ft9
1417; RV32IF-NEXT:    #NO_APP
1418; RV32IF-NEXT:    ret
1419;
1420; RV64IF-LABEL: explicit_register_ft9:
1421; RV64IF:       # %bb.0:
1422; RV64IF-NEXT:    fmv.s ft9, fa0
1423; RV64IF-NEXT:    #APP
1424; RV64IF-NEXT:    fcvt.w.s a0, ft9
1425; RV64IF-NEXT:    #NO_APP
1426; RV64IF-NEXT:    ret
1427  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft9}"(float %a)
1428  ret i32 %1
1429}
1430
1431define i32 @explicit_register_f30(float %a) nounwind {
1432; RV32IF-LABEL: explicit_register_f30:
1433; RV32IF:       # %bb.0:
1434; RV32IF-NEXT:    fmv.s ft10, fa0
1435; RV32IF-NEXT:    #APP
1436; RV32IF-NEXT:    fcvt.w.s a0, ft10
1437; RV32IF-NEXT:    #NO_APP
1438; RV32IF-NEXT:    ret
1439;
1440; RV64IF-LABEL: explicit_register_f30:
1441; RV64IF:       # %bb.0:
1442; RV64IF-NEXT:    fmv.s ft10, fa0
1443; RV64IF-NEXT:    #APP
1444; RV64IF-NEXT:    fcvt.w.s a0, ft10
1445; RV64IF-NEXT:    #NO_APP
1446; RV64IF-NEXT:    ret
1447  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f30}"(float %a)
1448  ret i32 %1
1449}
1450
1451define i32 @explicit_register_ft10(float %a) nounwind {
1452; RV32IF-LABEL: explicit_register_ft10:
1453; RV32IF:       # %bb.0:
1454; RV32IF-NEXT:    fmv.s ft10, fa0
1455; RV32IF-NEXT:    #APP
1456; RV32IF-NEXT:    fcvt.w.s a0, ft10
1457; RV32IF-NEXT:    #NO_APP
1458; RV32IF-NEXT:    ret
1459;
1460; RV64IF-LABEL: explicit_register_ft10:
1461; RV64IF:       # %bb.0:
1462; RV64IF-NEXT:    fmv.s ft10, fa0
1463; RV64IF-NEXT:    #APP
1464; RV64IF-NEXT:    fcvt.w.s a0, ft10
1465; RV64IF-NEXT:    #NO_APP
1466; RV64IF-NEXT:    ret
1467  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft10}"(float %a)
1468  ret i32 %1
1469}
1470
1471define i32 @explicit_register_f31(float %a) nounwind {
1472; RV32IF-LABEL: explicit_register_f31:
1473; RV32IF:       # %bb.0:
1474; RV32IF-NEXT:    fmv.s ft11, fa0
1475; RV32IF-NEXT:    #APP
1476; RV32IF-NEXT:    fcvt.w.s a0, ft11
1477; RV32IF-NEXT:    #NO_APP
1478; RV32IF-NEXT:    ret
1479;
1480; RV64IF-LABEL: explicit_register_f31:
1481; RV64IF:       # %bb.0:
1482; RV64IF-NEXT:    fmv.s ft11, fa0
1483; RV64IF-NEXT:    #APP
1484; RV64IF-NEXT:    fcvt.w.s a0, ft11
1485; RV64IF-NEXT:    #NO_APP
1486; RV64IF-NEXT:    ret
1487  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f31}"(float %a)
1488  ret i32 %1
1489}
1490
1491define i32 @explicit_register_ft11(float %a) nounwind {
1492; RV32IF-LABEL: explicit_register_ft11:
1493; RV32IF:       # %bb.0:
1494; RV32IF-NEXT:    fmv.s ft11, fa0
1495; RV32IF-NEXT:    #APP
1496; RV32IF-NEXT:    fcvt.w.s a0, ft11
1497; RV32IF-NEXT:    #NO_APP
1498; RV32IF-NEXT:    ret
1499;
1500; RV64IF-LABEL: explicit_register_ft11:
1501; RV64IF:       # %bb.0:
1502; RV64IF-NEXT:    fmv.s ft11, fa0
1503; RV64IF-NEXT:    #APP
1504; RV64IF-NEXT:    fcvt.w.s a0, ft11
1505; RV64IF-NEXT:    #NO_APP
1506; RV64IF-NEXT:    ret
1507  %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft11}"(float %a)
1508  ret i32 %1
1509}
1510