1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64IM
4
5; The patterns for the 'W' suffixed RV64M instructions have the potential of
6; missing cases. This file checks all the variants of
7; sign-extended/zero-extended/any-extended inputs and outputs.
8
9define i32 @aext_mulw_aext_aext(i32 %a, i32 %b) nounwind {
10; RV64IM-LABEL: aext_mulw_aext_aext:
11; RV64IM:       # %bb.0:
12; RV64IM-NEXT:    mulw a0, a0, a1
13; RV64IM-NEXT:    ret
14  %1 = mul i32 %a, %b
15  ret i32 %1
16}
17
18define i32 @aext_mulw_aext_sext(i32 %a, i32 signext %b) nounwind {
19; RV64IM-LABEL: aext_mulw_aext_sext:
20; RV64IM:       # %bb.0:
21; RV64IM-NEXT:    mulw a0, a0, a1
22; RV64IM-NEXT:    ret
23  %1 = mul i32 %a, %b
24  ret i32 %1
25}
26
27define i32 @aext_mulw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
28; RV64IM-LABEL: aext_mulw_aext_zext:
29; RV64IM:       # %bb.0:
30; RV64IM-NEXT:    mulw a0, a0, a1
31; RV64IM-NEXT:    ret
32  %1 = mul i32 %a, %b
33  ret i32 %1
34}
35
36define i32 @aext_mulw_sext_aext(i32 signext %a, i32 %b) nounwind {
37; RV64IM-LABEL: aext_mulw_sext_aext:
38; RV64IM:       # %bb.0:
39; RV64IM-NEXT:    mulw a0, a0, a1
40; RV64IM-NEXT:    ret
41  %1 = mul i32 %a, %b
42  ret i32 %1
43}
44
45define i32 @aext_mulw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
46; RV64IM-LABEL: aext_mulw_sext_sext:
47; RV64IM:       # %bb.0:
48; RV64IM-NEXT:    mulw a0, a0, a1
49; RV64IM-NEXT:    ret
50  %1 = mul i32 %a, %b
51  ret i32 %1
52}
53
54define i32 @aext_mulw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
55; RV64IM-LABEL: aext_mulw_sext_zext:
56; RV64IM:       # %bb.0:
57; RV64IM-NEXT:    mulw a0, a0, a1
58; RV64IM-NEXT:    ret
59  %1 = mul i32 %a, %b
60  ret i32 %1
61}
62
63define i32 @aext_mulw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
64; RV64IM-LABEL: aext_mulw_zext_aext:
65; RV64IM:       # %bb.0:
66; RV64IM-NEXT:    mulw a0, a0, a1
67; RV64IM-NEXT:    ret
68  %1 = mul i32 %a, %b
69  ret i32 %1
70}
71
72define i32 @aext_mulw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
73; RV64IM-LABEL: aext_mulw_zext_sext:
74; RV64IM:       # %bb.0:
75; RV64IM-NEXT:    mulw a0, a0, a1
76; RV64IM-NEXT:    ret
77  %1 = mul i32 %a, %b
78  ret i32 %1
79}
80
81define i32 @aext_mulw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
82; RV64IM-LABEL: aext_mulw_zext_zext:
83; RV64IM:       # %bb.0:
84; RV64IM-NEXT:    mulw a0, a0, a1
85; RV64IM-NEXT:    ret
86  %1 = mul i32 %a, %b
87  ret i32 %1
88}
89
90define signext i32 @sext_mulw_aext_aext(i32 %a, i32 %b) nounwind {
91; RV64IM-LABEL: sext_mulw_aext_aext:
92; RV64IM:       # %bb.0:
93; RV64IM-NEXT:    mulw a0, a0, a1
94; RV64IM-NEXT:    ret
95  %1 = mul i32 %a, %b
96  ret i32 %1
97}
98
99define signext i32 @sext_mulw_aext_sext(i32 %a, i32 signext %b) nounwind {
100; RV64IM-LABEL: sext_mulw_aext_sext:
101; RV64IM:       # %bb.0:
102; RV64IM-NEXT:    mulw a0, a0, a1
103; RV64IM-NEXT:    ret
104  %1 = mul i32 %a, %b
105  ret i32 %1
106}
107
108define signext i32 @sext_mulw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
109; RV64IM-LABEL: sext_mulw_aext_zext:
110; RV64IM:       # %bb.0:
111; RV64IM-NEXT:    mulw a0, a0, a1
112; RV64IM-NEXT:    ret
113  %1 = mul i32 %a, %b
114  ret i32 %1
115}
116
117define signext i32 @sext_mulw_sext_aext(i32 signext %a, i32 %b) nounwind {
118; RV64IM-LABEL: sext_mulw_sext_aext:
119; RV64IM:       # %bb.0:
120; RV64IM-NEXT:    mulw a0, a0, a1
121; RV64IM-NEXT:    ret
122  %1 = mul i32 %a, %b
123  ret i32 %1
124}
125
126define signext i32 @sext_mulw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
127; RV64IM-LABEL: sext_mulw_sext_sext:
128; RV64IM:       # %bb.0:
129; RV64IM-NEXT:    mulw a0, a0, a1
130; RV64IM-NEXT:    ret
131  %1 = mul i32 %a, %b
132  ret i32 %1
133}
134
135define signext i32 @sext_mulw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
136; RV64IM-LABEL: sext_mulw_sext_zext:
137; RV64IM:       # %bb.0:
138; RV64IM-NEXT:    mulw a0, a0, a1
139; RV64IM-NEXT:    ret
140  %1 = mul i32 %a, %b
141  ret i32 %1
142}
143
144define signext i32 @sext_mulw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
145; RV64IM-LABEL: sext_mulw_zext_aext:
146; RV64IM:       # %bb.0:
147; RV64IM-NEXT:    mulw a0, a0, a1
148; RV64IM-NEXT:    ret
149  %1 = mul i32 %a, %b
150  ret i32 %1
151}
152
153define signext i32 @sext_mulw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
154; RV64IM-LABEL: sext_mulw_zext_sext:
155; RV64IM:       # %bb.0:
156; RV64IM-NEXT:    mulw a0, a0, a1
157; RV64IM-NEXT:    ret
158  %1 = mul i32 %a, %b
159  ret i32 %1
160}
161
162define signext i32 @sext_mulw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
163; RV64IM-LABEL: sext_mulw_zext_zext:
164; RV64IM:       # %bb.0:
165; RV64IM-NEXT:    mulw a0, a0, a1
166; RV64IM-NEXT:    ret
167  %1 = mul i32 %a, %b
168  ret i32 %1
169}
170
171define zeroext i32 @zext_mulw_aext_aext(i32 %a, i32 %b) nounwind {
172; RV64IM-LABEL: zext_mulw_aext_aext:
173; RV64IM:       # %bb.0:
174; RV64IM-NEXT:    mul a0, a0, a1
175; RV64IM-NEXT:    slli a0, a0, 32
176; RV64IM-NEXT:    srli a0, a0, 32
177; RV64IM-NEXT:    ret
178  %1 = mul i32 %a, %b
179  ret i32 %1
180}
181
182define zeroext i32 @zext_mulw_aext_sext(i32 %a, i32 signext %b) nounwind {
183; RV64IM-LABEL: zext_mulw_aext_sext:
184; RV64IM:       # %bb.0:
185; RV64IM-NEXT:    mul a0, a0, a1
186; RV64IM-NEXT:    slli a0, a0, 32
187; RV64IM-NEXT:    srli a0, a0, 32
188; RV64IM-NEXT:    ret
189  %1 = mul i32 %a, %b
190  ret i32 %1
191}
192
193define zeroext i32 @zext_mulw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
194; RV64IM-LABEL: zext_mulw_aext_zext:
195; RV64IM:       # %bb.0:
196; RV64IM-NEXT:    mul a0, a0, a1
197; RV64IM-NEXT:    slli a0, a0, 32
198; RV64IM-NEXT:    srli a0, a0, 32
199; RV64IM-NEXT:    ret
200  %1 = mul i32 %a, %b
201  ret i32 %1
202}
203
204define zeroext i32 @zext_mulw_sext_aext(i32 signext %a, i32 %b) nounwind {
205; RV64IM-LABEL: zext_mulw_sext_aext:
206; RV64IM:       # %bb.0:
207; RV64IM-NEXT:    mul a0, a0, a1
208; RV64IM-NEXT:    slli a0, a0, 32
209; RV64IM-NEXT:    srli a0, a0, 32
210; RV64IM-NEXT:    ret
211  %1 = mul i32 %a, %b
212  ret i32 %1
213}
214
215define zeroext i32 @zext_mulw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
216; RV64IM-LABEL: zext_mulw_sext_sext:
217; RV64IM:       # %bb.0:
218; RV64IM-NEXT:    mul a0, a0, a1
219; RV64IM-NEXT:    slli a0, a0, 32
220; RV64IM-NEXT:    srli a0, a0, 32
221; RV64IM-NEXT:    ret
222  %1 = mul i32 %a, %b
223  ret i32 %1
224}
225
226define zeroext i32 @zext_mulw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
227; RV64IM-LABEL: zext_mulw_sext_zext:
228; RV64IM:       # %bb.0:
229; RV64IM-NEXT:    mul a0, a0, a1
230; RV64IM-NEXT:    slli a0, a0, 32
231; RV64IM-NEXT:    srli a0, a0, 32
232; RV64IM-NEXT:    ret
233  %1 = mul i32 %a, %b
234  ret i32 %1
235}
236
237define zeroext i32 @zext_mulw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
238; RV64IM-LABEL: zext_mulw_zext_aext:
239; RV64IM:       # %bb.0:
240; RV64IM-NEXT:    mul a0, a0, a1
241; RV64IM-NEXT:    slli a0, a0, 32
242; RV64IM-NEXT:    srli a0, a0, 32
243; RV64IM-NEXT:    ret
244  %1 = mul i32 %a, %b
245  ret i32 %1
246}
247
248define zeroext i32 @zext_mulw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
249; RV64IM-LABEL: zext_mulw_zext_sext:
250; RV64IM:       # %bb.0:
251; RV64IM-NEXT:    mul a0, a0, a1
252; RV64IM-NEXT:    slli a0, a0, 32
253; RV64IM-NEXT:    srli a0, a0, 32
254; RV64IM-NEXT:    ret
255  %1 = mul i32 %a, %b
256  ret i32 %1
257}
258
259define zeroext i32 @zext_mulw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
260; RV64IM-LABEL: zext_mulw_zext_zext:
261; RV64IM:       # %bb.0:
262; RV64IM-NEXT:    mul a0, a0, a1
263; RV64IM-NEXT:    slli a0, a0, 32
264; RV64IM-NEXT:    srli a0, a0, 32
265; RV64IM-NEXT:    ret
266  %1 = mul i32 %a, %b
267  ret i32 %1
268}
269
270define i32 @aext_divuw_aext_aext(i32 %a, i32 %b) nounwind {
271; RV64IM-LABEL: aext_divuw_aext_aext:
272; RV64IM:       # %bb.0:
273; RV64IM-NEXT:    divuw a0, a0, a1
274; RV64IM-NEXT:    ret
275  %1 = udiv i32 %a, %b
276  ret i32 %1
277}
278
279define i32 @aext_divuw_aext_sext(i32 %a, i32 signext %b) nounwind {
280; RV64IM-LABEL: aext_divuw_aext_sext:
281; RV64IM:       # %bb.0:
282; RV64IM-NEXT:    divuw a0, a0, a1
283; RV64IM-NEXT:    ret
284  %1 = udiv i32 %a, %b
285  ret i32 %1
286}
287
288define i32 @aext_divuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
289; RV64IM-LABEL: aext_divuw_aext_zext:
290; RV64IM:       # %bb.0:
291; RV64IM-NEXT:    divuw a0, a0, a1
292; RV64IM-NEXT:    ret
293  %1 = udiv i32 %a, %b
294  ret i32 %1
295}
296
297define i32 @aext_divuw_sext_aext(i32 signext %a, i32 %b) nounwind {
298; RV64IM-LABEL: aext_divuw_sext_aext:
299; RV64IM:       # %bb.0:
300; RV64IM-NEXT:    divuw a0, a0, a1
301; RV64IM-NEXT:    ret
302  %1 = udiv i32 %a, %b
303  ret i32 %1
304}
305
306define i32 @aext_divuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
307; RV64IM-LABEL: aext_divuw_sext_sext:
308; RV64IM:       # %bb.0:
309; RV64IM-NEXT:    divuw a0, a0, a1
310; RV64IM-NEXT:    ret
311  %1 = udiv i32 %a, %b
312  ret i32 %1
313}
314
315define i32 @aext_divuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
316; RV64IM-LABEL: aext_divuw_sext_zext:
317; RV64IM:       # %bb.0:
318; RV64IM-NEXT:    divuw a0, a0, a1
319; RV64IM-NEXT:    ret
320  %1 = udiv i32 %a, %b
321  ret i32 %1
322}
323
324define i32 @aext_divuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
325; RV64IM-LABEL: aext_divuw_zext_aext:
326; RV64IM:       # %bb.0:
327; RV64IM-NEXT:    divuw a0, a0, a1
328; RV64IM-NEXT:    ret
329  %1 = udiv i32 %a, %b
330  ret i32 %1
331}
332
333define i32 @aext_divuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
334; RV64IM-LABEL: aext_divuw_zext_sext:
335; RV64IM:       # %bb.0:
336; RV64IM-NEXT:    divuw a0, a0, a1
337; RV64IM-NEXT:    ret
338  %1 = udiv i32 %a, %b
339  ret i32 %1
340}
341
342define i32 @aext_divuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
343; RV64IM-LABEL: aext_divuw_zext_zext:
344; RV64IM:       # %bb.0:
345; RV64IM-NEXT:    divuw a0, a0, a1
346; RV64IM-NEXT:    ret
347  %1 = udiv i32 %a, %b
348  ret i32 %1
349}
350
351define signext i32 @sext_divuw_aext_aext(i32 %a, i32 %b) nounwind {
352; RV64IM-LABEL: sext_divuw_aext_aext:
353; RV64IM:       # %bb.0:
354; RV64IM-NEXT:    divuw a0, a0, a1
355; RV64IM-NEXT:    ret
356  %1 = udiv i32 %a, %b
357  ret i32 %1
358}
359
360define signext i32 @sext_divuw_aext_sext(i32 %a, i32 signext %b) nounwind {
361; RV64IM-LABEL: sext_divuw_aext_sext:
362; RV64IM:       # %bb.0:
363; RV64IM-NEXT:    divuw a0, a0, a1
364; RV64IM-NEXT:    ret
365  %1 = udiv i32 %a, %b
366  ret i32 %1
367}
368
369define signext i32 @sext_divuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
370; RV64IM-LABEL: sext_divuw_aext_zext:
371; RV64IM:       # %bb.0:
372; RV64IM-NEXT:    divuw a0, a0, a1
373; RV64IM-NEXT:    ret
374  %1 = udiv i32 %a, %b
375  ret i32 %1
376}
377
378define signext i32 @sext_divuw_sext_aext(i32 signext %a, i32 %b) nounwind {
379; RV64IM-LABEL: sext_divuw_sext_aext:
380; RV64IM:       # %bb.0:
381; RV64IM-NEXT:    divuw a0, a0, a1
382; RV64IM-NEXT:    ret
383  %1 = udiv i32 %a, %b
384  ret i32 %1
385}
386
387define signext i32 @sext_divuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
388; RV64IM-LABEL: sext_divuw_sext_sext:
389; RV64IM:       # %bb.0:
390; RV64IM-NEXT:    divuw a0, a0, a1
391; RV64IM-NEXT:    ret
392  %1 = udiv i32 %a, %b
393  ret i32 %1
394}
395
396define signext i32 @sext_divuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
397; RV64IM-LABEL: sext_divuw_sext_zext:
398; RV64IM:       # %bb.0:
399; RV64IM-NEXT:    divuw a0, a0, a1
400; RV64IM-NEXT:    ret
401  %1 = udiv i32 %a, %b
402  ret i32 %1
403}
404
405define signext i32 @sext_divuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
406; RV64IM-LABEL: sext_divuw_zext_aext:
407; RV64IM:       # %bb.0:
408; RV64IM-NEXT:    divuw a0, a0, a1
409; RV64IM-NEXT:    ret
410  %1 = udiv i32 %a, %b
411  ret i32 %1
412}
413
414define signext i32 @sext_divuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
415; RV64IM-LABEL: sext_divuw_zext_sext:
416; RV64IM:       # %bb.0:
417; RV64IM-NEXT:    divuw a0, a0, a1
418; RV64IM-NEXT:    ret
419  %1 = udiv i32 %a, %b
420  ret i32 %1
421}
422
423define signext i32 @sext_divuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
424; RV64IM-LABEL: sext_divuw_zext_zext:
425; RV64IM:       # %bb.0:
426; RV64IM-NEXT:    divuw a0, a0, a1
427; RV64IM-NEXT:    ret
428  %1 = udiv i32 %a, %b
429  ret i32 %1
430}
431
432define zeroext i32 @zext_divuw_aext_aext(i32 %a, i32 %b) nounwind {
433; RV64IM-LABEL: zext_divuw_aext_aext:
434; RV64IM:       # %bb.0:
435; RV64IM-NEXT:    divuw a0, a0, a1
436; RV64IM-NEXT:    slli a0, a0, 32
437; RV64IM-NEXT:    srli a0, a0, 32
438; RV64IM-NEXT:    ret
439  %1 = udiv i32 %a, %b
440  ret i32 %1
441}
442
443define zeroext i32 @zext_divuw_aext_sext(i32 %a, i32 signext %b) nounwind {
444; RV64IM-LABEL: zext_divuw_aext_sext:
445; RV64IM:       # %bb.0:
446; RV64IM-NEXT:    divuw a0, a0, a1
447; RV64IM-NEXT:    slli a0, a0, 32
448; RV64IM-NEXT:    srli a0, a0, 32
449; RV64IM-NEXT:    ret
450  %1 = udiv i32 %a, %b
451  ret i32 %1
452}
453
454define zeroext i32 @zext_divuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
455; RV64IM-LABEL: zext_divuw_aext_zext:
456; RV64IM:       # %bb.0:
457; RV64IM-NEXT:    divuw a0, a0, a1
458; RV64IM-NEXT:    slli a0, a0, 32
459; RV64IM-NEXT:    srli a0, a0, 32
460; RV64IM-NEXT:    ret
461  %1 = udiv i32 %a, %b
462  ret i32 %1
463}
464
465define zeroext i32 @zext_divuw_sext_aext(i32 signext %a, i32 %b) nounwind {
466; RV64IM-LABEL: zext_divuw_sext_aext:
467; RV64IM:       # %bb.0:
468; RV64IM-NEXT:    divuw a0, a0, a1
469; RV64IM-NEXT:    slli a0, a0, 32
470; RV64IM-NEXT:    srli a0, a0, 32
471; RV64IM-NEXT:    ret
472  %1 = udiv i32 %a, %b
473  ret i32 %1
474}
475
476define zeroext i32 @zext_divuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
477; RV64IM-LABEL: zext_divuw_sext_sext:
478; RV64IM:       # %bb.0:
479; RV64IM-NEXT:    divuw a0, a0, a1
480; RV64IM-NEXT:    slli a0, a0, 32
481; RV64IM-NEXT:    srli a0, a0, 32
482; RV64IM-NEXT:    ret
483  %1 = udiv i32 %a, %b
484  ret i32 %1
485}
486
487define zeroext i32 @zext_divuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
488; RV64IM-LABEL: zext_divuw_sext_zext:
489; RV64IM:       # %bb.0:
490; RV64IM-NEXT:    divuw a0, a0, a1
491; RV64IM-NEXT:    slli a0, a0, 32
492; RV64IM-NEXT:    srli a0, a0, 32
493; RV64IM-NEXT:    ret
494  %1 = udiv i32 %a, %b
495  ret i32 %1
496}
497
498define zeroext i32 @zext_divuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
499; RV64IM-LABEL: zext_divuw_zext_aext:
500; RV64IM:       # %bb.0:
501; RV64IM-NEXT:    divuw a0, a0, a1
502; RV64IM-NEXT:    slli a0, a0, 32
503; RV64IM-NEXT:    srli a0, a0, 32
504; RV64IM-NEXT:    ret
505  %1 = udiv i32 %a, %b
506  ret i32 %1
507}
508
509define zeroext i32 @zext_divuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
510; RV64IM-LABEL: zext_divuw_zext_sext:
511; RV64IM:       # %bb.0:
512; RV64IM-NEXT:    divuw a0, a0, a1
513; RV64IM-NEXT:    slli a0, a0, 32
514; RV64IM-NEXT:    srli a0, a0, 32
515; RV64IM-NEXT:    ret
516  %1 = udiv i32 %a, %b
517  ret i32 %1
518}
519
520define zeroext i32 @zext_divuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
521; RV64IM-LABEL: zext_divuw_zext_zext:
522; RV64IM:       # %bb.0:
523; RV64IM-NEXT:    divu a0, a0, a1
524; RV64IM-NEXT:    ret
525  %1 = udiv i32 %a, %b
526  ret i32 %1
527}
528
529define i32 @aext_divw_aext_aext(i32 %a, i32 %b) nounwind {
530; RV64IM-LABEL: aext_divw_aext_aext:
531; RV64IM:       # %bb.0:
532; RV64IM-NEXT:    divw a0, a0, a1
533; RV64IM-NEXT:    ret
534  %1 = sdiv i32 %a, %b
535  ret i32 %1
536}
537
538define i32 @aext_divw_aext_sext(i32 %a, i32 signext %b) nounwind {
539; RV64IM-LABEL: aext_divw_aext_sext:
540; RV64IM:       # %bb.0:
541; RV64IM-NEXT:    divw a0, a0, a1
542; RV64IM-NEXT:    ret
543  %1 = sdiv i32 %a, %b
544  ret i32 %1
545}
546
547define i32 @aext_divw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
548; RV64IM-LABEL: aext_divw_aext_zext:
549; RV64IM:       # %bb.0:
550; RV64IM-NEXT:    divw a0, a0, a1
551; RV64IM-NEXT:    ret
552  %1 = sdiv i32 %a, %b
553  ret i32 %1
554}
555
556define i32 @aext_divw_sext_aext(i32 signext %a, i32 %b) nounwind {
557; RV64IM-LABEL: aext_divw_sext_aext:
558; RV64IM:       # %bb.0:
559; RV64IM-NEXT:    divw a0, a0, a1
560; RV64IM-NEXT:    ret
561  %1 = sdiv i32 %a, %b
562  ret i32 %1
563}
564
565define i32 @aext_divw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
566; RV64IM-LABEL: aext_divw_sext_sext:
567; RV64IM:       # %bb.0:
568; RV64IM-NEXT:    divw a0, a0, a1
569; RV64IM-NEXT:    ret
570  %1 = sdiv i32 %a, %b
571  ret i32 %1
572}
573
574define i32 @aext_divw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
575; RV64IM-LABEL: aext_divw_sext_zext:
576; RV64IM:       # %bb.0:
577; RV64IM-NEXT:    divw a0, a0, a1
578; RV64IM-NEXT:    ret
579  %1 = sdiv i32 %a, %b
580  ret i32 %1
581}
582
583define i32 @aext_divw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
584; RV64IM-LABEL: aext_divw_zext_aext:
585; RV64IM:       # %bb.0:
586; RV64IM-NEXT:    divw a0, a0, a1
587; RV64IM-NEXT:    ret
588  %1 = sdiv i32 %a, %b
589  ret i32 %1
590}
591
592define i32 @aext_divw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
593; RV64IM-LABEL: aext_divw_zext_sext:
594; RV64IM:       # %bb.0:
595; RV64IM-NEXT:    divw a0, a0, a1
596; RV64IM-NEXT:    ret
597  %1 = sdiv i32 %a, %b
598  ret i32 %1
599}
600
601define i32 @aext_divw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
602; RV64IM-LABEL: aext_divw_zext_zext:
603; RV64IM:       # %bb.0:
604; RV64IM-NEXT:    divw a0, a0, a1
605; RV64IM-NEXT:    ret
606  %1 = sdiv i32 %a, %b
607  ret i32 %1
608}
609
610define signext i32 @sext_divw_aext_aext(i32 %a, i32 %b) nounwind {
611; RV64IM-LABEL: sext_divw_aext_aext:
612; RV64IM:       # %bb.0:
613; RV64IM-NEXT:    divw a0, a0, a1
614; RV64IM-NEXT:    ret
615  %1 = sdiv i32 %a, %b
616  ret i32 %1
617}
618
619define signext i32 @sext_divw_aext_sext(i32 %a, i32 signext %b) nounwind {
620; RV64IM-LABEL: sext_divw_aext_sext:
621; RV64IM:       # %bb.0:
622; RV64IM-NEXT:    divw a0, a0, a1
623; RV64IM-NEXT:    ret
624  %1 = sdiv i32 %a, %b
625  ret i32 %1
626}
627
628define signext i32 @sext_divw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
629; RV64IM-LABEL: sext_divw_aext_zext:
630; RV64IM:       # %bb.0:
631; RV64IM-NEXT:    divw a0, a0, a1
632; RV64IM-NEXT:    ret
633  %1 = sdiv i32 %a, %b
634  ret i32 %1
635}
636
637define signext i32 @sext_divw_sext_aext(i32 signext %a, i32 %b) nounwind {
638; RV64IM-LABEL: sext_divw_sext_aext:
639; RV64IM:       # %bb.0:
640; RV64IM-NEXT:    divw a0, a0, a1
641; RV64IM-NEXT:    ret
642  %1 = sdiv i32 %a, %b
643  ret i32 %1
644}
645
646define signext i32 @sext_divw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
647; RV64IM-LABEL: sext_divw_sext_sext:
648; RV64IM:       # %bb.0:
649; RV64IM-NEXT:    divw a0, a0, a1
650; RV64IM-NEXT:    ret
651  %1 = sdiv i32 %a, %b
652  ret i32 %1
653}
654
655define signext i32 @sext_divw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
656; RV64IM-LABEL: sext_divw_sext_zext:
657; RV64IM:       # %bb.0:
658; RV64IM-NEXT:    divw a0, a0, a1
659; RV64IM-NEXT:    ret
660  %1 = sdiv i32 %a, %b
661  ret i32 %1
662}
663
664define signext i32 @sext_divw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
665; RV64IM-LABEL: sext_divw_zext_aext:
666; RV64IM:       # %bb.0:
667; RV64IM-NEXT:    divw a0, a0, a1
668; RV64IM-NEXT:    ret
669  %1 = sdiv i32 %a, %b
670  ret i32 %1
671}
672
673define signext i32 @sext_divw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
674; RV64IM-LABEL: sext_divw_zext_sext:
675; RV64IM:       # %bb.0:
676; RV64IM-NEXT:    divw a0, a0, a1
677; RV64IM-NEXT:    ret
678  %1 = sdiv i32 %a, %b
679  ret i32 %1
680}
681
682define signext i32 @sext_divw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
683; RV64IM-LABEL: sext_divw_zext_zext:
684; RV64IM:       # %bb.0:
685; RV64IM-NEXT:    divw a0, a0, a1
686; RV64IM-NEXT:    ret
687  %1 = sdiv i32 %a, %b
688  ret i32 %1
689}
690
691define zeroext i32 @zext_divw_aext_aext(i32 %a, i32 %b) nounwind {
692; RV64IM-LABEL: zext_divw_aext_aext:
693; RV64IM:       # %bb.0:
694; RV64IM-NEXT:    divw a0, a0, a1
695; RV64IM-NEXT:    slli a0, a0, 32
696; RV64IM-NEXT:    srli a0, a0, 32
697; RV64IM-NEXT:    ret
698  %1 = sdiv i32 %a, %b
699  ret i32 %1
700}
701
702define zeroext i32 @zext_divw_aext_sext(i32 %a, i32 signext %b) nounwind {
703; RV64IM-LABEL: zext_divw_aext_sext:
704; RV64IM:       # %bb.0:
705; RV64IM-NEXT:    divw a0, a0, a1
706; RV64IM-NEXT:    slli a0, a0, 32
707; RV64IM-NEXT:    srli a0, a0, 32
708; RV64IM-NEXT:    ret
709  %1 = sdiv i32 %a, %b
710  ret i32 %1
711}
712
713define zeroext i32 @zext_divw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
714; RV64IM-LABEL: zext_divw_aext_zext:
715; RV64IM:       # %bb.0:
716; RV64IM-NEXT:    divw a0, a0, a1
717; RV64IM-NEXT:    slli a0, a0, 32
718; RV64IM-NEXT:    srli a0, a0, 32
719; RV64IM-NEXT:    ret
720  %1 = sdiv i32 %a, %b
721  ret i32 %1
722}
723
724define zeroext i32 @zext_divw_sext_aext(i32 signext %a, i32 %b) nounwind {
725; RV64IM-LABEL: zext_divw_sext_aext:
726; RV64IM:       # %bb.0:
727; RV64IM-NEXT:    divw a0, a0, a1
728; RV64IM-NEXT:    slli a0, a0, 32
729; RV64IM-NEXT:    srli a0, a0, 32
730; RV64IM-NEXT:    ret
731  %1 = sdiv i32 %a, %b
732  ret i32 %1
733}
734
735define zeroext i32 @zext_divw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
736; RV64IM-LABEL: zext_divw_sext_sext:
737; RV64IM:       # %bb.0:
738; RV64IM-NEXT:    divw a0, a0, a1
739; RV64IM-NEXT:    slli a0, a0, 32
740; RV64IM-NEXT:    srli a0, a0, 32
741; RV64IM-NEXT:    ret
742  %1 = sdiv i32 %a, %b
743  ret i32 %1
744}
745
746define zeroext i32 @zext_divw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
747; RV64IM-LABEL: zext_divw_sext_zext:
748; RV64IM:       # %bb.0:
749; RV64IM-NEXT:    divw a0, a0, a1
750; RV64IM-NEXT:    slli a0, a0, 32
751; RV64IM-NEXT:    srli a0, a0, 32
752; RV64IM-NEXT:    ret
753  %1 = sdiv i32 %a, %b
754  ret i32 %1
755}
756
757define zeroext i32 @zext_divw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
758; RV64IM-LABEL: zext_divw_zext_aext:
759; RV64IM:       # %bb.0:
760; RV64IM-NEXT:    divw a0, a0, a1
761; RV64IM-NEXT:    slli a0, a0, 32
762; RV64IM-NEXT:    srli a0, a0, 32
763; RV64IM-NEXT:    ret
764  %1 = sdiv i32 %a, %b
765  ret i32 %1
766}
767
768define zeroext i32 @zext_divw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
769; RV64IM-LABEL: zext_divw_zext_sext:
770; RV64IM:       # %bb.0:
771; RV64IM-NEXT:    divw a0, a0, a1
772; RV64IM-NEXT:    slli a0, a0, 32
773; RV64IM-NEXT:    srli a0, a0, 32
774; RV64IM-NEXT:    ret
775  %1 = sdiv i32 %a, %b
776  ret i32 %1
777}
778
779define zeroext i32 @zext_divw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
780; RV64IM-LABEL: zext_divw_zext_zext:
781; RV64IM:       # %bb.0:
782; RV64IM-NEXT:    divw a0, a0, a1
783; RV64IM-NEXT:    slli a0, a0, 32
784; RV64IM-NEXT:    srli a0, a0, 32
785; RV64IM-NEXT:    ret
786  %1 = sdiv i32 %a, %b
787  ret i32 %1
788}
789
790define i32 @aext_remw_aext_aext(i32 %a, i32 %b) nounwind {
791; RV64IM-LABEL: aext_remw_aext_aext:
792; RV64IM:       # %bb.0:
793; RV64IM-NEXT:    remw a0, a0, a1
794; RV64IM-NEXT:    ret
795  %1 = srem i32 %a, %b
796  ret i32 %1
797}
798
799define i32 @aext_remw_aext_sext(i32 %a, i32 signext %b) nounwind {
800; RV64IM-LABEL: aext_remw_aext_sext:
801; RV64IM:       # %bb.0:
802; RV64IM-NEXT:    remw a0, a0, a1
803; RV64IM-NEXT:    ret
804  %1 = srem i32 %a, %b
805  ret i32 %1
806}
807
808define i32 @aext_remw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
809; RV64IM-LABEL: aext_remw_aext_zext:
810; RV64IM:       # %bb.0:
811; RV64IM-NEXT:    remw a0, a0, a1
812; RV64IM-NEXT:    ret
813  %1 = srem i32 %a, %b
814  ret i32 %1
815}
816
817define i32 @aext_remw_sext_aext(i32 signext %a, i32 %b) nounwind {
818; RV64IM-LABEL: aext_remw_sext_aext:
819; RV64IM:       # %bb.0:
820; RV64IM-NEXT:    remw a0, a0, a1
821; RV64IM-NEXT:    ret
822  %1 = srem i32 %a, %b
823  ret i32 %1
824}
825
826define i32 @aext_remw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
827; RV64IM-LABEL: aext_remw_sext_sext:
828; RV64IM:       # %bb.0:
829; RV64IM-NEXT:    remw a0, a0, a1
830; RV64IM-NEXT:    ret
831  %1 = srem i32 %a, %b
832  ret i32 %1
833}
834
835define i32 @aext_remw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
836; RV64IM-LABEL: aext_remw_sext_zext:
837; RV64IM:       # %bb.0:
838; RV64IM-NEXT:    remw a0, a0, a1
839; RV64IM-NEXT:    ret
840  %1 = srem i32 %a, %b
841  ret i32 %1
842}
843
844define i32 @aext_remw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
845; RV64IM-LABEL: aext_remw_zext_aext:
846; RV64IM:       # %bb.0:
847; RV64IM-NEXT:    remw a0, a0, a1
848; RV64IM-NEXT:    ret
849  %1 = srem i32 %a, %b
850  ret i32 %1
851}
852
853define i32 @aext_remw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
854; RV64IM-LABEL: aext_remw_zext_sext:
855; RV64IM:       # %bb.0:
856; RV64IM-NEXT:    remw a0, a0, a1
857; RV64IM-NEXT:    ret
858  %1 = srem i32 %a, %b
859  ret i32 %1
860}
861
862define i32 @aext_remw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
863; RV64IM-LABEL: aext_remw_zext_zext:
864; RV64IM:       # %bb.0:
865; RV64IM-NEXT:    remw a0, a0, a1
866; RV64IM-NEXT:    ret
867  %1 = srem i32 %a, %b
868  ret i32 %1
869}
870
871define signext i32 @sext_remw_aext_aext(i32 %a, i32 %b) nounwind {
872; RV64IM-LABEL: sext_remw_aext_aext:
873; RV64IM:       # %bb.0:
874; RV64IM-NEXT:    remw a0, a0, a1
875; RV64IM-NEXT:    ret
876  %1 = srem i32 %a, %b
877  ret i32 %1
878}
879
880define signext i32 @sext_remw_aext_sext(i32 %a, i32 signext %b) nounwind {
881; RV64IM-LABEL: sext_remw_aext_sext:
882; RV64IM:       # %bb.0:
883; RV64IM-NEXT:    remw a0, a0, a1
884; RV64IM-NEXT:    ret
885  %1 = srem i32 %a, %b
886  ret i32 %1
887}
888
889define signext i32 @sext_remw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
890; RV64IM-LABEL: sext_remw_aext_zext:
891; RV64IM:       # %bb.0:
892; RV64IM-NEXT:    remw a0, a0, a1
893; RV64IM-NEXT:    ret
894  %1 = srem i32 %a, %b
895  ret i32 %1
896}
897
898define signext i32 @sext_remw_sext_aext(i32 signext %a, i32 %b) nounwind {
899; RV64IM-LABEL: sext_remw_sext_aext:
900; RV64IM:       # %bb.0:
901; RV64IM-NEXT:    remw a0, a0, a1
902; RV64IM-NEXT:    ret
903  %1 = srem i32 %a, %b
904  ret i32 %1
905}
906
907define signext i32 @sext_remw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
908; RV64IM-LABEL: sext_remw_sext_sext:
909; RV64IM:       # %bb.0:
910; RV64IM-NEXT:    remw a0, a0, a1
911; RV64IM-NEXT:    ret
912  %1 = srem i32 %a, %b
913  ret i32 %1
914}
915
916define signext i32 @sext_remw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
917; RV64IM-LABEL: sext_remw_sext_zext:
918; RV64IM:       # %bb.0:
919; RV64IM-NEXT:    remw a0, a0, a1
920; RV64IM-NEXT:    ret
921  %1 = srem i32 %a, %b
922  ret i32 %1
923}
924
925define signext i32 @sext_remw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
926; RV64IM-LABEL: sext_remw_zext_aext:
927; RV64IM:       # %bb.0:
928; RV64IM-NEXT:    remw a0, a0, a1
929; RV64IM-NEXT:    ret
930  %1 = srem i32 %a, %b
931  ret i32 %1
932}
933
934define signext i32 @sext_remw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
935; RV64IM-LABEL: sext_remw_zext_sext:
936; RV64IM:       # %bb.0:
937; RV64IM-NEXT:    remw a0, a0, a1
938; RV64IM-NEXT:    ret
939  %1 = srem i32 %a, %b
940  ret i32 %1
941}
942
943define signext i32 @sext_remw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
944; RV64IM-LABEL: sext_remw_zext_zext:
945; RV64IM:       # %bb.0:
946; RV64IM-NEXT:    remw a0, a0, a1
947; RV64IM-NEXT:    ret
948  %1 = srem i32 %a, %b
949  ret i32 %1
950}
951
952define zeroext i32 @zext_remw_aext_aext(i32 %a, i32 %b) nounwind {
953; RV64IM-LABEL: zext_remw_aext_aext:
954; RV64IM:       # %bb.0:
955; RV64IM-NEXT:    remw a0, a0, a1
956; RV64IM-NEXT:    slli a0, a0, 32
957; RV64IM-NEXT:    srli a0, a0, 32
958; RV64IM-NEXT:    ret
959  %1 = srem i32 %a, %b
960  ret i32 %1
961}
962
963define zeroext i32 @zext_remw_aext_sext(i32 %a, i32 signext %b) nounwind {
964; RV64IM-LABEL: zext_remw_aext_sext:
965; RV64IM:       # %bb.0:
966; RV64IM-NEXT:    remw a0, a0, a1
967; RV64IM-NEXT:    slli a0, a0, 32
968; RV64IM-NEXT:    srli a0, a0, 32
969; RV64IM-NEXT:    ret
970  %1 = srem i32 %a, %b
971  ret i32 %1
972}
973
974define zeroext i32 @zext_remw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
975; RV64IM-LABEL: zext_remw_aext_zext:
976; RV64IM:       # %bb.0:
977; RV64IM-NEXT:    remw a0, a0, a1
978; RV64IM-NEXT:    slli a0, a0, 32
979; RV64IM-NEXT:    srli a0, a0, 32
980; RV64IM-NEXT:    ret
981  %1 = srem i32 %a, %b
982  ret i32 %1
983}
984
985define zeroext i32 @zext_remw_sext_aext(i32 signext %a, i32 %b) nounwind {
986; RV64IM-LABEL: zext_remw_sext_aext:
987; RV64IM:       # %bb.0:
988; RV64IM-NEXT:    remw a0, a0, a1
989; RV64IM-NEXT:    slli a0, a0, 32
990; RV64IM-NEXT:    srli a0, a0, 32
991; RV64IM-NEXT:    ret
992  %1 = srem i32 %a, %b
993  ret i32 %1
994}
995
996define zeroext i32 @zext_remw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
997; RV64IM-LABEL: zext_remw_sext_sext:
998; RV64IM:       # %bb.0:
999; RV64IM-NEXT:    remw a0, a0, a1
1000; RV64IM-NEXT:    slli a0, a0, 32
1001; RV64IM-NEXT:    srli a0, a0, 32
1002; RV64IM-NEXT:    ret
1003  %1 = srem i32 %a, %b
1004  ret i32 %1
1005}
1006
1007define zeroext i32 @zext_remw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1008; RV64IM-LABEL: zext_remw_sext_zext:
1009; RV64IM:       # %bb.0:
1010; RV64IM-NEXT:    remw a0, a0, a1
1011; RV64IM-NEXT:    slli a0, a0, 32
1012; RV64IM-NEXT:    srli a0, a0, 32
1013; RV64IM-NEXT:    ret
1014  %1 = srem i32 %a, %b
1015  ret i32 %1
1016}
1017
1018define zeroext i32 @zext_remw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1019; RV64IM-LABEL: zext_remw_zext_aext:
1020; RV64IM:       # %bb.0:
1021; RV64IM-NEXT:    remw a0, a0, a1
1022; RV64IM-NEXT:    slli a0, a0, 32
1023; RV64IM-NEXT:    srli a0, a0, 32
1024; RV64IM-NEXT:    ret
1025  %1 = srem i32 %a, %b
1026  ret i32 %1
1027}
1028
1029define zeroext i32 @zext_remw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1030; RV64IM-LABEL: zext_remw_zext_sext:
1031; RV64IM:       # %bb.0:
1032; RV64IM-NEXT:    remw a0, a0, a1
1033; RV64IM-NEXT:    slli a0, a0, 32
1034; RV64IM-NEXT:    srli a0, a0, 32
1035; RV64IM-NEXT:    ret
1036  %1 = srem i32 %a, %b
1037  ret i32 %1
1038}
1039
1040define zeroext i32 @zext_remw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1041; RV64IM-LABEL: zext_remw_zext_zext:
1042; RV64IM:       # %bb.0:
1043; RV64IM-NEXT:    remw a0, a0, a1
1044; RV64IM-NEXT:    slli a0, a0, 32
1045; RV64IM-NEXT:    srli a0, a0, 32
1046; RV64IM-NEXT:    ret
1047  %1 = srem i32 %a, %b
1048  ret i32 %1
1049}
1050
1051define i32 @aext_remuw_aext_aext(i32 %a, i32 %b) nounwind {
1052; RV64IM-LABEL: aext_remuw_aext_aext:
1053; RV64IM:       # %bb.0:
1054; RV64IM-NEXT:    remuw a0, a0, a1
1055; RV64IM-NEXT:    ret
1056  %1 = urem i32 %a, %b
1057  ret i32 %1
1058}
1059
1060define i32 @aext_remuw_aext_sext(i32 %a, i32 signext %b) nounwind {
1061; RV64IM-LABEL: aext_remuw_aext_sext:
1062; RV64IM:       # %bb.0:
1063; RV64IM-NEXT:    remuw a0, a0, a1
1064; RV64IM-NEXT:    ret
1065  %1 = urem i32 %a, %b
1066  ret i32 %1
1067}
1068
1069define i32 @aext_remuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1070; RV64IM-LABEL: aext_remuw_aext_zext:
1071; RV64IM:       # %bb.0:
1072; RV64IM-NEXT:    remuw a0, a0, a1
1073; RV64IM-NEXT:    ret
1074  %1 = urem i32 %a, %b
1075  ret i32 %1
1076}
1077
1078define i32 @aext_remuw_sext_aext(i32 signext %a, i32 %b) nounwind {
1079; RV64IM-LABEL: aext_remuw_sext_aext:
1080; RV64IM:       # %bb.0:
1081; RV64IM-NEXT:    remuw a0, a0, a1
1082; RV64IM-NEXT:    ret
1083  %1 = urem i32 %a, %b
1084  ret i32 %1
1085}
1086
1087define i32 @aext_remuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1088; RV64IM-LABEL: aext_remuw_sext_sext:
1089; RV64IM:       # %bb.0:
1090; RV64IM-NEXT:    remuw a0, a0, a1
1091; RV64IM-NEXT:    ret
1092  %1 = urem i32 %a, %b
1093  ret i32 %1
1094}
1095
1096define i32 @aext_remuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1097; RV64IM-LABEL: aext_remuw_sext_zext:
1098; RV64IM:       # %bb.0:
1099; RV64IM-NEXT:    remuw a0, a0, a1
1100; RV64IM-NEXT:    ret
1101  %1 = urem i32 %a, %b
1102  ret i32 %1
1103}
1104
1105define i32 @aext_remuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1106; RV64IM-LABEL: aext_remuw_zext_aext:
1107; RV64IM:       # %bb.0:
1108; RV64IM-NEXT:    remuw a0, a0, a1
1109; RV64IM-NEXT:    ret
1110  %1 = urem i32 %a, %b
1111  ret i32 %1
1112}
1113
1114define i32 @aext_remuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1115; RV64IM-LABEL: aext_remuw_zext_sext:
1116; RV64IM:       # %bb.0:
1117; RV64IM-NEXT:    remuw a0, a0, a1
1118; RV64IM-NEXT:    ret
1119  %1 = urem i32 %a, %b
1120  ret i32 %1
1121}
1122
1123define i32 @aext_remuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1124; RV64IM-LABEL: aext_remuw_zext_zext:
1125; RV64IM:       # %bb.0:
1126; RV64IM-NEXT:    remuw a0, a0, a1
1127; RV64IM-NEXT:    ret
1128  %1 = urem i32 %a, %b
1129  ret i32 %1
1130}
1131
1132define signext i32 @sext_remuw_aext_aext(i32 %a, i32 %b) nounwind {
1133; RV64IM-LABEL: sext_remuw_aext_aext:
1134; RV64IM:       # %bb.0:
1135; RV64IM-NEXT:    remuw a0, a0, a1
1136; RV64IM-NEXT:    ret
1137  %1 = urem i32 %a, %b
1138  ret i32 %1
1139}
1140
1141define signext i32 @sext_remuw_aext_sext(i32 %a, i32 signext %b) nounwind {
1142; RV64IM-LABEL: sext_remuw_aext_sext:
1143; RV64IM:       # %bb.0:
1144; RV64IM-NEXT:    remuw a0, a0, a1
1145; RV64IM-NEXT:    ret
1146  %1 = urem i32 %a, %b
1147  ret i32 %1
1148}
1149
1150define signext i32 @sext_remuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1151; RV64IM-LABEL: sext_remuw_aext_zext:
1152; RV64IM:       # %bb.0:
1153; RV64IM-NEXT:    remuw a0, a0, a1
1154; RV64IM-NEXT:    ret
1155  %1 = urem i32 %a, %b
1156  ret i32 %1
1157}
1158
1159define signext i32 @sext_remuw_sext_aext(i32 signext %a, i32 %b) nounwind {
1160; RV64IM-LABEL: sext_remuw_sext_aext:
1161; RV64IM:       # %bb.0:
1162; RV64IM-NEXT:    remuw a0, a0, a1
1163; RV64IM-NEXT:    ret
1164  %1 = urem i32 %a, %b
1165  ret i32 %1
1166}
1167
1168define signext i32 @sext_remuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1169; RV64IM-LABEL: sext_remuw_sext_sext:
1170; RV64IM:       # %bb.0:
1171; RV64IM-NEXT:    remuw a0, a0, a1
1172; RV64IM-NEXT:    ret
1173  %1 = urem i32 %a, %b
1174  ret i32 %1
1175}
1176
1177define signext i32 @sext_remuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1178; RV64IM-LABEL: sext_remuw_sext_zext:
1179; RV64IM:       # %bb.0:
1180; RV64IM-NEXT:    remuw a0, a0, a1
1181; RV64IM-NEXT:    ret
1182  %1 = urem i32 %a, %b
1183  ret i32 %1
1184}
1185
1186define signext i32 @sext_remuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1187; RV64IM-LABEL: sext_remuw_zext_aext:
1188; RV64IM:       # %bb.0:
1189; RV64IM-NEXT:    remuw a0, a0, a1
1190; RV64IM-NEXT:    ret
1191  %1 = urem i32 %a, %b
1192  ret i32 %1
1193}
1194
1195define signext i32 @sext_remuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1196; RV64IM-LABEL: sext_remuw_zext_sext:
1197; RV64IM:       # %bb.0:
1198; RV64IM-NEXT:    remuw a0, a0, a1
1199; RV64IM-NEXT:    ret
1200  %1 = urem i32 %a, %b
1201  ret i32 %1
1202}
1203
1204define signext i32 @sext_remuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1205; RV64IM-LABEL: sext_remuw_zext_zext:
1206; RV64IM:       # %bb.0:
1207; RV64IM-NEXT:    remuw a0, a0, a1
1208; RV64IM-NEXT:    ret
1209  %1 = urem i32 %a, %b
1210  ret i32 %1
1211}
1212
1213define zeroext i32 @zext_remuw_aext_aext(i32 %a, i32 %b) nounwind {
1214; RV64IM-LABEL: zext_remuw_aext_aext:
1215; RV64IM:       # %bb.0:
1216; RV64IM-NEXT:    remuw a0, a0, a1
1217; RV64IM-NEXT:    slli a0, a0, 32
1218; RV64IM-NEXT:    srli a0, a0, 32
1219; RV64IM-NEXT:    ret
1220  %1 = urem i32 %a, %b
1221  ret i32 %1
1222}
1223
1224define zeroext i32 @zext_remuw_aext_sext(i32 %a, i32 signext %b) nounwind {
1225; RV64IM-LABEL: zext_remuw_aext_sext:
1226; RV64IM:       # %bb.0:
1227; RV64IM-NEXT:    remuw a0, a0, a1
1228; RV64IM-NEXT:    slli a0, a0, 32
1229; RV64IM-NEXT:    srli a0, a0, 32
1230; RV64IM-NEXT:    ret
1231  %1 = urem i32 %a, %b
1232  ret i32 %1
1233}
1234
1235define zeroext i32 @zext_remuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1236; RV64IM-LABEL: zext_remuw_aext_zext:
1237; RV64IM:       # %bb.0:
1238; RV64IM-NEXT:    remuw a0, a0, a1
1239; RV64IM-NEXT:    slli a0, a0, 32
1240; RV64IM-NEXT:    srli a0, a0, 32
1241; RV64IM-NEXT:    ret
1242  %1 = urem i32 %a, %b
1243  ret i32 %1
1244}
1245
1246define zeroext i32 @zext_remuw_sext_aext(i32 signext %a, i32 %b) nounwind {
1247; RV64IM-LABEL: zext_remuw_sext_aext:
1248; RV64IM:       # %bb.0:
1249; RV64IM-NEXT:    remuw a0, a0, a1
1250; RV64IM-NEXT:    slli a0, a0, 32
1251; RV64IM-NEXT:    srli a0, a0, 32
1252; RV64IM-NEXT:    ret
1253  %1 = urem i32 %a, %b
1254  ret i32 %1
1255}
1256
1257define zeroext i32 @zext_remuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1258; RV64IM-LABEL: zext_remuw_sext_sext:
1259; RV64IM:       # %bb.0:
1260; RV64IM-NEXT:    remuw a0, a0, a1
1261; RV64IM-NEXT:    slli a0, a0, 32
1262; RV64IM-NEXT:    srli a0, a0, 32
1263; RV64IM-NEXT:    ret
1264  %1 = urem i32 %a, %b
1265  ret i32 %1
1266}
1267
1268define zeroext i32 @zext_remuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1269; RV64IM-LABEL: zext_remuw_sext_zext:
1270; RV64IM:       # %bb.0:
1271; RV64IM-NEXT:    remuw a0, a0, a1
1272; RV64IM-NEXT:    slli a0, a0, 32
1273; RV64IM-NEXT:    srli a0, a0, 32
1274; RV64IM-NEXT:    ret
1275  %1 = urem i32 %a, %b
1276  ret i32 %1
1277}
1278
1279define zeroext i32 @zext_remuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1280; RV64IM-LABEL: zext_remuw_zext_aext:
1281; RV64IM:       # %bb.0:
1282; RV64IM-NEXT:    remuw a0, a0, a1
1283; RV64IM-NEXT:    slli a0, a0, 32
1284; RV64IM-NEXT:    srli a0, a0, 32
1285; RV64IM-NEXT:    ret
1286  %1 = urem i32 %a, %b
1287  ret i32 %1
1288}
1289
1290define zeroext i32 @zext_remuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1291; RV64IM-LABEL: zext_remuw_zext_sext:
1292; RV64IM:       # %bb.0:
1293; RV64IM-NEXT:    remuw a0, a0, a1
1294; RV64IM-NEXT:    slli a0, a0, 32
1295; RV64IM-NEXT:    srli a0, a0, 32
1296; RV64IM-NEXT:    ret
1297  %1 = urem i32 %a, %b
1298  ret i32 %1
1299}
1300
1301define zeroext i32 @zext_remuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1302; RV64IM-LABEL: zext_remuw_zext_zext:
1303; RV64IM:       # %bb.0:
1304; RV64IM-NEXT:    remu a0, a0, a1
1305; RV64IM-NEXT:    ret
1306  %1 = urem i32 %a, %b
1307  ret i32 %1
1308}
1309