1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // MachineScheduler schedules machine instructions after phi elimination. It
10 // preserves LiveIntervals so it can be invoked before register allocation.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "llvm/CodeGen/MachineScheduler.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/PriorityQueue.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/ADT/iterator_range.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/LiveInterval.h"
25 #include "llvm/CodeGen/LiveIntervals.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineDominators.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineLoopInfo.h"
32 #include "llvm/CodeGen/MachineOperand.h"
33 #include "llvm/CodeGen/MachinePassRegistry.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/RegisterClassInfo.h"
37 #include "llvm/CodeGen/RegisterPressure.h"
38 #include "llvm/CodeGen/ScheduleDAG.h"
39 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
40 #include "llvm/CodeGen/ScheduleDAGMutation.h"
41 #include "llvm/CodeGen/ScheduleDFS.h"
42 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
43 #include "llvm/CodeGen/SlotIndexes.h"
44 #include "llvm/CodeGen/TargetFrameLowering.h"
45 #include "llvm/CodeGen/TargetInstrInfo.h"
46 #include "llvm/CodeGen/TargetLowering.h"
47 #include "llvm/CodeGen/TargetPassConfig.h"
48 #include "llvm/CodeGen/TargetRegisterInfo.h"
49 #include "llvm/CodeGen/TargetSchedule.h"
50 #include "llvm/CodeGen/TargetSubtargetInfo.h"
51 #include "llvm/Config/llvm-config.h"
52 #include "llvm/InitializePasses.h"
53 #include "llvm/MC/LaneBitmask.h"
54 #include "llvm/Pass.h"
55 #include "llvm/Support/CommandLine.h"
56 #include "llvm/Support/Compiler.h"
57 #include "llvm/Support/Debug.h"
58 #include "llvm/Support/ErrorHandling.h"
59 #include "llvm/Support/GraphWriter.h"
60 #include "llvm/Support/MachineValueType.h"
61 #include "llvm/Support/raw_ostream.h"
62 #include <algorithm>
63 #include <cassert>
64 #include <cstdint>
65 #include <iterator>
66 #include <limits>
67 #include <memory>
68 #include <string>
69 #include <tuple>
70 #include <utility>
71 #include <vector>
72
73 using namespace llvm;
74
75 #define DEBUG_TYPE "machine-scheduler"
76
77 STATISTIC(NumClustered, "Number of load/store pairs clustered");
78
79 namespace llvm {
80
81 cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
82 cl::desc("Force top-down list scheduling"));
83 cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
84 cl::desc("Force bottom-up list scheduling"));
85 cl::opt<bool>
86 DumpCriticalPathLength("misched-dcpl", cl::Hidden,
87 cl::desc("Print critical path length to stdout"));
88
89 cl::opt<bool> VerifyScheduling(
90 "verify-misched", cl::Hidden,
91 cl::desc("Verify machine instrs before and after machine scheduling"));
92
93 } // end namespace llvm
94
95 #ifndef NDEBUG
96 static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
97 cl::desc("Pop up a window to show MISched dags after they are processed"));
98
99 /// In some situations a few uninteresting nodes depend on nearly all other
100 /// nodes in the graph, provide a cutoff to hide them.
101 static cl::opt<unsigned> ViewMISchedCutoff("view-misched-cutoff", cl::Hidden,
102 cl::desc("Hide nodes with more predecessor/successor than cutoff"));
103
104 static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
105 cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
106
107 static cl::opt<std::string> SchedOnlyFunc("misched-only-func", cl::Hidden,
108 cl::desc("Only schedule this function"));
109 static cl::opt<unsigned> SchedOnlyBlock("misched-only-block", cl::Hidden,
110 cl::desc("Only schedule this MBB#"));
111 static cl::opt<bool> PrintDAGs("misched-print-dags", cl::Hidden,
112 cl::desc("Print schedule DAGs"));
113 #else
114 static const bool ViewMISchedDAGs = false;
115 static const bool PrintDAGs = false;
116 #endif // NDEBUG
117
118 /// Avoid quadratic complexity in unusually large basic blocks by limiting the
119 /// size of the ready lists.
120 static cl::opt<unsigned> ReadyListLimit("misched-limit", cl::Hidden,
121 cl::desc("Limit ready list to N instructions"), cl::init(256));
122
123 static cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden,
124 cl::desc("Enable register pressure scheduling."), cl::init(true));
125
126 static cl::opt<bool> EnableCyclicPath("misched-cyclicpath", cl::Hidden,
127 cl::desc("Enable cyclic critical path analysis."), cl::init(true));
128
129 static cl::opt<bool> EnableMemOpCluster("misched-cluster", cl::Hidden,
130 cl::desc("Enable memop clustering."),
131 cl::init(true));
132 static cl::opt<bool>
133 ForceFastCluster("force-fast-cluster", cl::Hidden,
134 cl::desc("Switch to fast cluster algorithm with the lost "
135 "of some fusion opportunities"),
136 cl::init(false));
137 static cl::opt<unsigned>
138 FastClusterThreshold("fast-cluster-threshold", cl::Hidden,
139 cl::desc("The threshold for fast cluster"),
140 cl::init(1000));
141
142 // DAG subtrees must have at least this many nodes.
143 static const unsigned MinSubtreeSize = 8;
144
145 // Pin the vtables to this file.
anchor()146 void MachineSchedStrategy::anchor() {}
147
anchor()148 void ScheduleDAGMutation::anchor() {}
149
150 //===----------------------------------------------------------------------===//
151 // Machine Instruction Scheduling Pass and Registry
152 //===----------------------------------------------------------------------===//
153
MachineSchedContext()154 MachineSchedContext::MachineSchedContext() {
155 RegClassInfo = new RegisterClassInfo();
156 }
157
~MachineSchedContext()158 MachineSchedContext::~MachineSchedContext() {
159 delete RegClassInfo;
160 }
161
162 namespace {
163
164 /// Base class for a machine scheduler class that can run at any point.
165 class MachineSchedulerBase : public MachineSchedContext,
166 public MachineFunctionPass {
167 public:
MachineSchedulerBase(char & ID)168 MachineSchedulerBase(char &ID): MachineFunctionPass(ID) {}
169
170 void print(raw_ostream &O, const Module* = nullptr) const override;
171
172 protected:
173 void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags);
174 };
175
176 /// MachineScheduler runs after coalescing and before register allocation.
177 class MachineScheduler : public MachineSchedulerBase {
178 public:
179 MachineScheduler();
180
181 void getAnalysisUsage(AnalysisUsage &AU) const override;
182
183 bool runOnMachineFunction(MachineFunction&) override;
184
185 static char ID; // Class identification, replacement for typeinfo
186
187 protected:
188 ScheduleDAGInstrs *createMachineScheduler();
189 };
190
191 /// PostMachineScheduler runs after shortly before code emission.
192 class PostMachineScheduler : public MachineSchedulerBase {
193 public:
194 PostMachineScheduler();
195
196 void getAnalysisUsage(AnalysisUsage &AU) const override;
197
198 bool runOnMachineFunction(MachineFunction&) override;
199
200 static char ID; // Class identification, replacement for typeinfo
201
202 protected:
203 ScheduleDAGInstrs *createPostMachineScheduler();
204 };
205
206 } // end anonymous namespace
207
208 char MachineScheduler::ID = 0;
209
210 char &llvm::MachineSchedulerID = MachineScheduler::ID;
211
212 INITIALIZE_PASS_BEGIN(MachineScheduler, DEBUG_TYPE,
213 "Machine Instruction Scheduler", false, false)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)214 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
215 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
216 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
217 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
218 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
219 INITIALIZE_PASS_END(MachineScheduler, DEBUG_TYPE,
220 "Machine Instruction Scheduler", false, false)
221
222 MachineScheduler::MachineScheduler() : MachineSchedulerBase(ID) {
223 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
224 }
225
getAnalysisUsage(AnalysisUsage & AU) const226 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
227 AU.setPreservesCFG();
228 AU.addRequired<MachineDominatorTree>();
229 AU.addRequired<MachineLoopInfo>();
230 AU.addRequired<AAResultsWrapperPass>();
231 AU.addRequired<TargetPassConfig>();
232 AU.addRequired<SlotIndexes>();
233 AU.addPreserved<SlotIndexes>();
234 AU.addRequired<LiveIntervals>();
235 AU.addPreserved<LiveIntervals>();
236 MachineFunctionPass::getAnalysisUsage(AU);
237 }
238
239 char PostMachineScheduler::ID = 0;
240
241 char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID;
242
243 INITIALIZE_PASS_BEGIN(PostMachineScheduler, "postmisched",
244 "PostRA Machine Instruction Scheduler", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)245 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
246 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
247 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
248 INITIALIZE_PASS_END(PostMachineScheduler, "postmisched",
249 "PostRA Machine Instruction Scheduler", false, false)
250
251 PostMachineScheduler::PostMachineScheduler() : MachineSchedulerBase(ID) {
252 initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry());
253 }
254
getAnalysisUsage(AnalysisUsage & AU) const255 void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
256 AU.setPreservesCFG();
257 AU.addRequired<MachineDominatorTree>();
258 AU.addRequired<MachineLoopInfo>();
259 AU.addRequired<AAResultsWrapperPass>();
260 AU.addRequired<TargetPassConfig>();
261 MachineFunctionPass::getAnalysisUsage(AU);
262 }
263
264 MachinePassRegistry<MachineSchedRegistry::ScheduleDAGCtor>
265 MachineSchedRegistry::Registry;
266
267 /// A dummy default scheduler factory indicates whether the scheduler
268 /// is overridden on the command line.
useDefaultMachineSched(MachineSchedContext * C)269 static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
270 return nullptr;
271 }
272
273 /// MachineSchedOpt allows command line selection of the scheduler.
274 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
275 RegisterPassParser<MachineSchedRegistry>>
276 MachineSchedOpt("misched",
277 cl::init(&useDefaultMachineSched), cl::Hidden,
278 cl::desc("Machine instruction scheduler to use"));
279
280 static MachineSchedRegistry
281 DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
282 useDefaultMachineSched);
283
284 static cl::opt<bool> EnableMachineSched(
285 "enable-misched",
286 cl::desc("Enable the machine instruction scheduling pass."), cl::init(true),
287 cl::Hidden);
288
289 static cl::opt<bool> EnablePostRAMachineSched(
290 "enable-post-misched",
291 cl::desc("Enable the post-ra machine instruction scheduling pass."),
292 cl::init(true), cl::Hidden);
293
294 /// Decrement this iterator until reaching the top or a non-debug instr.
295 static MachineBasicBlock::const_iterator
priorNonDebug(MachineBasicBlock::const_iterator I,MachineBasicBlock::const_iterator Beg)296 priorNonDebug(MachineBasicBlock::const_iterator I,
297 MachineBasicBlock::const_iterator Beg) {
298 assert(I != Beg && "reached the top of the region, cannot decrement");
299 while (--I != Beg) {
300 if (!I->isDebugInstr())
301 break;
302 }
303 return I;
304 }
305
306 /// Non-const version.
307 static MachineBasicBlock::iterator
priorNonDebug(MachineBasicBlock::iterator I,MachineBasicBlock::const_iterator Beg)308 priorNonDebug(MachineBasicBlock::iterator I,
309 MachineBasicBlock::const_iterator Beg) {
310 return priorNonDebug(MachineBasicBlock::const_iterator(I), Beg)
311 .getNonConstIterator();
312 }
313
314 /// If this iterator is a debug value, increment until reaching the End or a
315 /// non-debug instruction.
316 static MachineBasicBlock::const_iterator
nextIfDebug(MachineBasicBlock::const_iterator I,MachineBasicBlock::const_iterator End)317 nextIfDebug(MachineBasicBlock::const_iterator I,
318 MachineBasicBlock::const_iterator End) {
319 for(; I != End; ++I) {
320 if (!I->isDebugInstr())
321 break;
322 }
323 return I;
324 }
325
326 /// Non-const version.
327 static MachineBasicBlock::iterator
nextIfDebug(MachineBasicBlock::iterator I,MachineBasicBlock::const_iterator End)328 nextIfDebug(MachineBasicBlock::iterator I,
329 MachineBasicBlock::const_iterator End) {
330 return nextIfDebug(MachineBasicBlock::const_iterator(I), End)
331 .getNonConstIterator();
332 }
333
334 /// Instantiate a ScheduleDAGInstrs that will be owned by the caller.
createMachineScheduler()335 ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
336 // Select the scheduler, or set the default.
337 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
338 if (Ctor != useDefaultMachineSched)
339 return Ctor(this);
340
341 // Get the default scheduler set by the target for this function.
342 ScheduleDAGInstrs *Scheduler = PassConfig->createMachineScheduler(this);
343 if (Scheduler)
344 return Scheduler;
345
346 // Default to GenericScheduler.
347 return createGenericSchedLive(this);
348 }
349
350 /// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
351 /// the caller. We don't have a command line option to override the postRA
352 /// scheduler. The Target must configure it.
createPostMachineScheduler()353 ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
354 // Get the postRA scheduler set by the target for this function.
355 ScheduleDAGInstrs *Scheduler = PassConfig->createPostMachineScheduler(this);
356 if (Scheduler)
357 return Scheduler;
358
359 // Default to GenericScheduler.
360 return createGenericSchedPostRA(this);
361 }
362
363 /// Top-level MachineScheduler pass driver.
364 ///
365 /// Visit blocks in function order. Divide each block into scheduling regions
366 /// and visit them bottom-up. Visiting regions bottom-up is not required, but is
367 /// consistent with the DAG builder, which traverses the interior of the
368 /// scheduling regions bottom-up.
369 ///
370 /// This design avoids exposing scheduling boundaries to the DAG builder,
371 /// simplifying the DAG builder's support for "special" target instructions.
372 /// At the same time the design allows target schedulers to operate across
373 /// scheduling boundaries, for example to bundle the boundary instructions
374 /// without reordering them. This creates complexity, because the target
375 /// scheduler must update the RegionBegin and RegionEnd positions cached by
376 /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
377 /// design would be to split blocks at scheduling boundaries, but LLVM has a
378 /// general bias against block splitting purely for implementation simplicity.
runOnMachineFunction(MachineFunction & mf)379 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
380 if (skipFunction(mf.getFunction()))
381 return false;
382
383 if (EnableMachineSched.getNumOccurrences()) {
384 if (!EnableMachineSched)
385 return false;
386 } else if (!mf.getSubtarget().enableMachineScheduler())
387 return false;
388
389 LLVM_DEBUG(dbgs() << "Before MISched:\n"; mf.print(dbgs()));
390
391 // Initialize the context of the pass.
392 MF = &mf;
393 MLI = &getAnalysis<MachineLoopInfo>();
394 MDT = &getAnalysis<MachineDominatorTree>();
395 PassConfig = &getAnalysis<TargetPassConfig>();
396 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
397
398 LIS = &getAnalysis<LiveIntervals>();
399
400 if (VerifyScheduling) {
401 LLVM_DEBUG(LIS->dump());
402 MF->verify(this, "Before machine scheduling.");
403 }
404 RegClassInfo->runOnMachineFunction(*MF);
405
406 // Instantiate the selected scheduler for this target, function, and
407 // optimization level.
408 std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
409 scheduleRegions(*Scheduler, false);
410
411 LLVM_DEBUG(LIS->dump());
412 if (VerifyScheduling)
413 MF->verify(this, "After machine scheduling.");
414 return true;
415 }
416
runOnMachineFunction(MachineFunction & mf)417 bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
418 if (skipFunction(mf.getFunction()))
419 return false;
420
421 if (EnablePostRAMachineSched.getNumOccurrences()) {
422 if (!EnablePostRAMachineSched)
423 return false;
424 } else if (!mf.getSubtarget().enablePostRAMachineScheduler()) {
425 LLVM_DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
426 return false;
427 }
428 LLVM_DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs()));
429
430 // Initialize the context of the pass.
431 MF = &mf;
432 MLI = &getAnalysis<MachineLoopInfo>();
433 PassConfig = &getAnalysis<TargetPassConfig>();
434 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
435
436 if (VerifyScheduling)
437 MF->verify(this, "Before post machine scheduling.");
438
439 // Instantiate the selected scheduler for this target, function, and
440 // optimization level.
441 std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler());
442 scheduleRegions(*Scheduler, true);
443
444 if (VerifyScheduling)
445 MF->verify(this, "After post machine scheduling.");
446 return true;
447 }
448
449 /// Return true of the given instruction should not be included in a scheduling
450 /// region.
451 ///
452 /// MachineScheduler does not currently support scheduling across calls. To
453 /// handle calls, the DAG builder needs to be modified to create register
454 /// anti/output dependencies on the registers clobbered by the call's regmask
455 /// operand. In PreRA scheduling, the stack pointer adjustment already prevents
456 /// scheduling across calls. In PostRA scheduling, we need the isCall to enforce
457 /// the boundary, but there would be no benefit to postRA scheduling across
458 /// calls this late anyway.
isSchedBoundary(MachineBasicBlock::iterator MI,MachineBasicBlock * MBB,MachineFunction * MF,const TargetInstrInfo * TII)459 static bool isSchedBoundary(MachineBasicBlock::iterator MI,
460 MachineBasicBlock *MBB,
461 MachineFunction *MF,
462 const TargetInstrInfo *TII) {
463 return MI->isCall() || TII->isSchedulingBoundary(*MI, MBB, *MF);
464 }
465
466 /// A region of an MBB for scheduling.
467 namespace {
468 struct SchedRegion {
469 /// RegionBegin is the first instruction in the scheduling region, and
470 /// RegionEnd is either MBB->end() or the scheduling boundary after the
471 /// last instruction in the scheduling region. These iterators cannot refer
472 /// to instructions outside of the identified scheduling region because
473 /// those may be reordered before scheduling this region.
474 MachineBasicBlock::iterator RegionBegin;
475 MachineBasicBlock::iterator RegionEnd;
476 unsigned NumRegionInstrs;
477
SchedRegion__anon2c8d5d400211::SchedRegion478 SchedRegion(MachineBasicBlock::iterator B, MachineBasicBlock::iterator E,
479 unsigned N) :
480 RegionBegin(B), RegionEnd(E), NumRegionInstrs(N) {}
481 };
482 } // end anonymous namespace
483
484 using MBBRegionsVector = SmallVector<SchedRegion, 16>;
485
486 static void
getSchedRegions(MachineBasicBlock * MBB,MBBRegionsVector & Regions,bool RegionsTopDown)487 getSchedRegions(MachineBasicBlock *MBB,
488 MBBRegionsVector &Regions,
489 bool RegionsTopDown) {
490 MachineFunction *MF = MBB->getParent();
491 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
492
493 MachineBasicBlock::iterator I = nullptr;
494 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
495 RegionEnd != MBB->begin(); RegionEnd = I) {
496
497 // Avoid decrementing RegionEnd for blocks with no terminator.
498 if (RegionEnd != MBB->end() ||
499 isSchedBoundary(&*std::prev(RegionEnd), &*MBB, MF, TII)) {
500 --RegionEnd;
501 }
502
503 // The next region starts above the previous region. Look backward in the
504 // instruction stream until we find the nearest boundary.
505 unsigned NumRegionInstrs = 0;
506 I = RegionEnd;
507 for (;I != MBB->begin(); --I) {
508 MachineInstr &MI = *std::prev(I);
509 if (isSchedBoundary(&MI, &*MBB, MF, TII))
510 break;
511 if (!MI.isDebugInstr()) {
512 // MBB::size() uses instr_iterator to count. Here we need a bundle to
513 // count as a single instruction.
514 ++NumRegionInstrs;
515 }
516 }
517
518 // It's possible we found a scheduling region that only has debug
519 // instructions. Don't bother scheduling these.
520 if (NumRegionInstrs != 0)
521 Regions.push_back(SchedRegion(I, RegionEnd, NumRegionInstrs));
522 }
523
524 if (RegionsTopDown)
525 std::reverse(Regions.begin(), Regions.end());
526 }
527
528 /// Main driver for both MachineScheduler and PostMachineScheduler.
scheduleRegions(ScheduleDAGInstrs & Scheduler,bool FixKillFlags)529 void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
530 bool FixKillFlags) {
531 // Visit all machine basic blocks.
532 //
533 // TODO: Visit blocks in global postorder or postorder within the bottom-up
534 // loop tree. Then we can optionally compute global RegPressure.
535 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
536 MBB != MBBEnd; ++MBB) {
537
538 Scheduler.startBlock(&*MBB);
539
540 #ifndef NDEBUG
541 if (SchedOnlyFunc.getNumOccurrences() && SchedOnlyFunc != MF->getName())
542 continue;
543 if (SchedOnlyBlock.getNumOccurrences()
544 && (int)SchedOnlyBlock != MBB->getNumber())
545 continue;
546 #endif
547
548 // Break the block into scheduling regions [I, RegionEnd). RegionEnd
549 // points to the scheduling boundary at the bottom of the region. The DAG
550 // does not include RegionEnd, but the region does (i.e. the next
551 // RegionEnd is above the previous RegionBegin). If the current block has
552 // no terminator then RegionEnd == MBB->end() for the bottom region.
553 //
554 // All the regions of MBB are first found and stored in MBBRegions, which
555 // will be processed (MBB) top-down if initialized with true.
556 //
557 // The Scheduler may insert instructions during either schedule() or
558 // exitRegion(), even for empty regions. So the local iterators 'I' and
559 // 'RegionEnd' are invalid across these calls. Instructions must not be
560 // added to other regions than the current one without updating MBBRegions.
561
562 MBBRegionsVector MBBRegions;
563 getSchedRegions(&*MBB, MBBRegions, Scheduler.doMBBSchedRegionsTopDown());
564 for (MBBRegionsVector::iterator R = MBBRegions.begin();
565 R != MBBRegions.end(); ++R) {
566 MachineBasicBlock::iterator I = R->RegionBegin;
567 MachineBasicBlock::iterator RegionEnd = R->RegionEnd;
568 unsigned NumRegionInstrs = R->NumRegionInstrs;
569
570 // Notify the scheduler of the region, even if we may skip scheduling
571 // it. Perhaps it still needs to be bundled.
572 Scheduler.enterRegion(&*MBB, I, RegionEnd, NumRegionInstrs);
573
574 // Skip empty scheduling regions (0 or 1 schedulable instructions).
575 if (I == RegionEnd || I == std::prev(RegionEnd)) {
576 // Close the current region. Bundle the terminator if needed.
577 // This invalidates 'RegionEnd' and 'I'.
578 Scheduler.exitRegion();
579 continue;
580 }
581 LLVM_DEBUG(dbgs() << "********** MI Scheduling **********\n");
582 LLVM_DEBUG(dbgs() << MF->getName() << ":" << printMBBReference(*MBB)
583 << " " << MBB->getName() << "\n From: " << *I
584 << " To: ";
585 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
586 else dbgs() << "End";
587 dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n');
588 if (DumpCriticalPathLength) {
589 errs() << MF->getName();
590 errs() << ":%bb. " << MBB->getNumber();
591 errs() << " " << MBB->getName() << " \n";
592 }
593
594 // Schedule a region: possibly reorder instructions.
595 // This invalidates the original region iterators.
596 Scheduler.schedule();
597
598 // Close the current region.
599 Scheduler.exitRegion();
600 }
601 Scheduler.finishBlock();
602 // FIXME: Ideally, no further passes should rely on kill flags. However,
603 // thumb2 size reduction is currently an exception, so the PostMIScheduler
604 // needs to do this.
605 if (FixKillFlags)
606 Scheduler.fixupKills(*MBB);
607 }
608 Scheduler.finalizeSchedule();
609 }
610
print(raw_ostream & O,const Module * m) const611 void MachineSchedulerBase::print(raw_ostream &O, const Module* m) const {
612 // unimplemented
613 }
614
615 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
dump() const616 LLVM_DUMP_METHOD void ReadyQueue::dump() const {
617 dbgs() << "Queue " << Name << ": ";
618 for (const SUnit *SU : Queue)
619 dbgs() << SU->NodeNum << " ";
620 dbgs() << "\n";
621 }
622 #endif
623
624 //===----------------------------------------------------------------------===//
625 // ScheduleDAGMI - Basic machine instruction scheduling. This is
626 // independent of PreRA/PostRA scheduling and involves no extra book-keeping for
627 // virtual registers.
628 // ===----------------------------------------------------------------------===/
629
630 // Provide a vtable anchor.
631 ScheduleDAGMI::~ScheduleDAGMI() = default;
632
633 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
634 /// NumPredsLeft reaches zero, release the successor node.
635 ///
636 /// FIXME: Adjust SuccSU height based on MinLatency.
releaseSucc(SUnit * SU,SDep * SuccEdge)637 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
638 SUnit *SuccSU = SuccEdge->getSUnit();
639
640 if (SuccEdge->isWeak()) {
641 --SuccSU->WeakPredsLeft;
642 if (SuccEdge->isCluster())
643 NextClusterSucc = SuccSU;
644 return;
645 }
646 #ifndef NDEBUG
647 if (SuccSU->NumPredsLeft == 0) {
648 dbgs() << "*** Scheduling failed! ***\n";
649 dumpNode(*SuccSU);
650 dbgs() << " has been released too many times!\n";
651 llvm_unreachable(nullptr);
652 }
653 #endif
654 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However,
655 // CurrCycle may have advanced since then.
656 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency())
657 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency();
658
659 --SuccSU->NumPredsLeft;
660 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
661 SchedImpl->releaseTopNode(SuccSU);
662 }
663
664 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
releaseSuccessors(SUnit * SU)665 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
666 for (SDep &Succ : SU->Succs)
667 releaseSucc(SU, &Succ);
668 }
669
670 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
671 /// NumSuccsLeft reaches zero, release the predecessor node.
672 ///
673 /// FIXME: Adjust PredSU height based on MinLatency.
releasePred(SUnit * SU,SDep * PredEdge)674 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
675 SUnit *PredSU = PredEdge->getSUnit();
676
677 if (PredEdge->isWeak()) {
678 --PredSU->WeakSuccsLeft;
679 if (PredEdge->isCluster())
680 NextClusterPred = PredSU;
681 return;
682 }
683 #ifndef NDEBUG
684 if (PredSU->NumSuccsLeft == 0) {
685 dbgs() << "*** Scheduling failed! ***\n";
686 dumpNode(*PredSU);
687 dbgs() << " has been released too many times!\n";
688 llvm_unreachable(nullptr);
689 }
690 #endif
691 // SU->BotReadyCycle was set to CurrCycle when it was scheduled. However,
692 // CurrCycle may have advanced since then.
693 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency())
694 PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency();
695
696 --PredSU->NumSuccsLeft;
697 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
698 SchedImpl->releaseBottomNode(PredSU);
699 }
700
701 /// releasePredecessors - Call releasePred on each of SU's predecessors.
releasePredecessors(SUnit * SU)702 void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
703 for (SDep &Pred : SU->Preds)
704 releasePred(SU, &Pred);
705 }
706
startBlock(MachineBasicBlock * bb)707 void ScheduleDAGMI::startBlock(MachineBasicBlock *bb) {
708 ScheduleDAGInstrs::startBlock(bb);
709 SchedImpl->enterMBB(bb);
710 }
711
finishBlock()712 void ScheduleDAGMI::finishBlock() {
713 SchedImpl->leaveMBB();
714 ScheduleDAGInstrs::finishBlock();
715 }
716
717 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
718 /// crossing a scheduling boundary. [begin, end) includes all instructions in
719 /// the region, including the boundary itself and single-instruction regions
720 /// that don't get scheduled.
enterRegion(MachineBasicBlock * bb,MachineBasicBlock::iterator begin,MachineBasicBlock::iterator end,unsigned regioninstrs)721 void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
722 MachineBasicBlock::iterator begin,
723 MachineBasicBlock::iterator end,
724 unsigned regioninstrs)
725 {
726 ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
727
728 SchedImpl->initPolicy(begin, end, regioninstrs);
729 }
730
731 /// This is normally called from the main scheduler loop but may also be invoked
732 /// by the scheduling strategy to perform additional code motion.
moveInstruction(MachineInstr * MI,MachineBasicBlock::iterator InsertPos)733 void ScheduleDAGMI::moveInstruction(
734 MachineInstr *MI, MachineBasicBlock::iterator InsertPos) {
735 // Advance RegionBegin if the first instruction moves down.
736 if (&*RegionBegin == MI)
737 ++RegionBegin;
738
739 // Update the instruction stream.
740 BB->splice(InsertPos, BB, MI);
741
742 // Update LiveIntervals
743 if (LIS)
744 LIS->handleMove(*MI, /*UpdateFlags=*/true);
745
746 // Recede RegionBegin if an instruction moves above the first.
747 if (RegionBegin == InsertPos)
748 RegionBegin = MI;
749 }
750
checkSchedLimit()751 bool ScheduleDAGMI::checkSchedLimit() {
752 #ifndef NDEBUG
753 if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
754 CurrentTop = CurrentBottom;
755 return false;
756 }
757 ++NumInstrsScheduled;
758 #endif
759 return true;
760 }
761
762 /// Per-region scheduling driver, called back from
763 /// MachineScheduler::runOnMachineFunction. This is a simplified driver that
764 /// does not consider liveness or register pressure. It is useful for PostRA
765 /// scheduling and potentially other custom schedulers.
schedule()766 void ScheduleDAGMI::schedule() {
767 LLVM_DEBUG(dbgs() << "ScheduleDAGMI::schedule starting\n");
768 LLVM_DEBUG(SchedImpl->dumpPolicy());
769
770 // Build the DAG.
771 buildSchedGraph(AA);
772
773 postprocessDAG();
774
775 SmallVector<SUnit*, 8> TopRoots, BotRoots;
776 findRootsAndBiasEdges(TopRoots, BotRoots);
777
778 LLVM_DEBUG(dump());
779 if (PrintDAGs) dump();
780 if (ViewMISchedDAGs) viewGraph();
781
782 // Initialize the strategy before modifying the DAG.
783 // This may initialize a DFSResult to be used for queue priority.
784 SchedImpl->initialize(this);
785
786 // Initialize ready queues now that the DAG and priority data are finalized.
787 initQueues(TopRoots, BotRoots);
788
789 bool IsTopNode = false;
790 while (true) {
791 LLVM_DEBUG(dbgs() << "** ScheduleDAGMI::schedule picking next node\n");
792 SUnit *SU = SchedImpl->pickNode(IsTopNode);
793 if (!SU) break;
794
795 assert(!SU->isScheduled && "Node already scheduled");
796 if (!checkSchedLimit())
797 break;
798
799 MachineInstr *MI = SU->getInstr();
800 if (IsTopNode) {
801 assert(SU->isTopReady() && "node still has unscheduled dependencies");
802 if (&*CurrentTop == MI)
803 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
804 else
805 moveInstruction(MI, CurrentTop);
806 } else {
807 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
808 MachineBasicBlock::iterator priorII =
809 priorNonDebug(CurrentBottom, CurrentTop);
810 if (&*priorII == MI)
811 CurrentBottom = priorII;
812 else {
813 if (&*CurrentTop == MI)
814 CurrentTop = nextIfDebug(++CurrentTop, priorII);
815 moveInstruction(MI, CurrentBottom);
816 CurrentBottom = MI;
817 }
818 }
819 // Notify the scheduling strategy before updating the DAG.
820 // This sets the scheduled node's ReadyCycle to CurrCycle. When updateQueues
821 // runs, it can then use the accurate ReadyCycle time to determine whether
822 // newly released nodes can move to the readyQ.
823 SchedImpl->schedNode(SU, IsTopNode);
824
825 updateQueues(SU, IsTopNode);
826 }
827 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
828
829 placeDebugValues();
830
831 LLVM_DEBUG({
832 dbgs() << "*** Final schedule for "
833 << printMBBReference(*begin()->getParent()) << " ***\n";
834 dumpSchedule();
835 dbgs() << '\n';
836 });
837 }
838
839 /// Apply each ScheduleDAGMutation step in order.
postprocessDAG()840 void ScheduleDAGMI::postprocessDAG() {
841 for (auto &m : Mutations)
842 m->apply(this);
843 }
844
845 void ScheduleDAGMI::
findRootsAndBiasEdges(SmallVectorImpl<SUnit * > & TopRoots,SmallVectorImpl<SUnit * > & BotRoots)846 findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
847 SmallVectorImpl<SUnit*> &BotRoots) {
848 for (SUnit &SU : SUnits) {
849 assert(!SU.isBoundaryNode() && "Boundary node should not be in SUnits");
850
851 // Order predecessors so DFSResult follows the critical path.
852 SU.biasCriticalPath();
853
854 // A SUnit is ready to top schedule if it has no predecessors.
855 if (!SU.NumPredsLeft)
856 TopRoots.push_back(&SU);
857 // A SUnit is ready to bottom schedule if it has no successors.
858 if (!SU.NumSuccsLeft)
859 BotRoots.push_back(&SU);
860 }
861 ExitSU.biasCriticalPath();
862 }
863
864 /// Identify DAG roots and setup scheduler queues.
initQueues(ArrayRef<SUnit * > TopRoots,ArrayRef<SUnit * > BotRoots)865 void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots,
866 ArrayRef<SUnit*> BotRoots) {
867 NextClusterSucc = nullptr;
868 NextClusterPred = nullptr;
869
870 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
871 //
872 // Nodes with unreleased weak edges can still be roots.
873 // Release top roots in forward order.
874 for (SUnit *SU : TopRoots)
875 SchedImpl->releaseTopNode(SU);
876
877 // Release bottom roots in reverse order so the higher priority nodes appear
878 // first. This is more natural and slightly more efficient.
879 for (SmallVectorImpl<SUnit*>::const_reverse_iterator
880 I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I) {
881 SchedImpl->releaseBottomNode(*I);
882 }
883
884 releaseSuccessors(&EntrySU);
885 releasePredecessors(&ExitSU);
886
887 SchedImpl->registerRoots();
888
889 // Advance past initial DebugValues.
890 CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
891 CurrentBottom = RegionEnd;
892 }
893
894 /// Update scheduler queues after scheduling an instruction.
updateQueues(SUnit * SU,bool IsTopNode)895 void ScheduleDAGMI::updateQueues(SUnit *SU, bool IsTopNode) {
896 // Release dependent instructions for scheduling.
897 if (IsTopNode)
898 releaseSuccessors(SU);
899 else
900 releasePredecessors(SU);
901
902 SU->isScheduled = true;
903 }
904
905 /// Reinsert any remaining debug_values, just like the PostRA scheduler.
placeDebugValues()906 void ScheduleDAGMI::placeDebugValues() {
907 // If first instruction was a DBG_VALUE then put it back.
908 if (FirstDbgValue) {
909 BB->splice(RegionBegin, BB, FirstDbgValue);
910 RegionBegin = FirstDbgValue;
911 }
912
913 for (std::vector<std::pair<MachineInstr *, MachineInstr *>>::iterator
914 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
915 std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
916 MachineInstr *DbgValue = P.first;
917 MachineBasicBlock::iterator OrigPrevMI = P.second;
918 if (&*RegionBegin == DbgValue)
919 ++RegionBegin;
920 BB->splice(++OrigPrevMI, BB, DbgValue);
921 if (OrigPrevMI == std::prev(RegionEnd))
922 RegionEnd = DbgValue;
923 }
924 DbgValues.clear();
925 FirstDbgValue = nullptr;
926 }
927
928 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
dumpSchedule() const929 LLVM_DUMP_METHOD void ScheduleDAGMI::dumpSchedule() const {
930 for (MachineBasicBlock::iterator MI = begin(), ME = end(); MI != ME; ++MI) {
931 if (SUnit *SU = getSUnit(&(*MI)))
932 dumpNode(*SU);
933 else
934 dbgs() << "Missing SUnit\n";
935 }
936 }
937 #endif
938
939 //===----------------------------------------------------------------------===//
940 // ScheduleDAGMILive - Base class for MachineInstr scheduling with LiveIntervals
941 // preservation.
942 //===----------------------------------------------------------------------===//
943
~ScheduleDAGMILive()944 ScheduleDAGMILive::~ScheduleDAGMILive() {
945 delete DFSResult;
946 }
947
collectVRegUses(SUnit & SU)948 void ScheduleDAGMILive::collectVRegUses(SUnit &SU) {
949 const MachineInstr &MI = *SU.getInstr();
950 for (const MachineOperand &MO : MI.operands()) {
951 if (!MO.isReg())
952 continue;
953 if (!MO.readsReg())
954 continue;
955 if (TrackLaneMasks && !MO.isUse())
956 continue;
957
958 Register Reg = MO.getReg();
959 if (!Register::isVirtualRegister(Reg))
960 continue;
961
962 // Ignore re-defs.
963 if (TrackLaneMasks) {
964 bool FoundDef = false;
965 for (const MachineOperand &MO2 : MI.operands()) {
966 if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
967 FoundDef = true;
968 break;
969 }
970 }
971 if (FoundDef)
972 continue;
973 }
974
975 // Record this local VReg use.
976 VReg2SUnitMultiMap::iterator UI = VRegUses.find(Reg);
977 for (; UI != VRegUses.end(); ++UI) {
978 if (UI->SU == &SU)
979 break;
980 }
981 if (UI == VRegUses.end())
982 VRegUses.insert(VReg2SUnit(Reg, LaneBitmask::getNone(), &SU));
983 }
984 }
985
986 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
987 /// crossing a scheduling boundary. [begin, end) includes all instructions in
988 /// the region, including the boundary itself and single-instruction regions
989 /// that don't get scheduled.
enterRegion(MachineBasicBlock * bb,MachineBasicBlock::iterator begin,MachineBasicBlock::iterator end,unsigned regioninstrs)990 void ScheduleDAGMILive::enterRegion(MachineBasicBlock *bb,
991 MachineBasicBlock::iterator begin,
992 MachineBasicBlock::iterator end,
993 unsigned regioninstrs)
994 {
995 // ScheduleDAGMI initializes SchedImpl's per-region policy.
996 ScheduleDAGMI::enterRegion(bb, begin, end, regioninstrs);
997
998 // For convenience remember the end of the liveness region.
999 LiveRegionEnd = (RegionEnd == bb->end()) ? RegionEnd : std::next(RegionEnd);
1000
1001 SUPressureDiffs.clear();
1002
1003 ShouldTrackPressure = SchedImpl->shouldTrackPressure();
1004 ShouldTrackLaneMasks = SchedImpl->shouldTrackLaneMasks();
1005
1006 assert((!ShouldTrackLaneMasks || ShouldTrackPressure) &&
1007 "ShouldTrackLaneMasks requires ShouldTrackPressure");
1008 }
1009
1010 // Setup the register pressure trackers for the top scheduled and bottom
1011 // scheduled regions.
initRegPressure()1012 void ScheduleDAGMILive::initRegPressure() {
1013 VRegUses.clear();
1014 VRegUses.setUniverse(MRI.getNumVirtRegs());
1015 for (SUnit &SU : SUnits)
1016 collectVRegUses(SU);
1017
1018 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin,
1019 ShouldTrackLaneMasks, false);
1020 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
1021 ShouldTrackLaneMasks, false);
1022
1023 // Close the RPTracker to finalize live ins.
1024 RPTracker.closeRegion();
1025
1026 LLVM_DEBUG(RPTracker.dump());
1027
1028 // Initialize the live ins and live outs.
1029 TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs);
1030 BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs);
1031
1032 // Close one end of the tracker so we can call
1033 // getMaxUpward/DownwardPressureDelta before advancing across any
1034 // instructions. This converts currently live regs into live ins/outs.
1035 TopRPTracker.closeTop();
1036 BotRPTracker.closeBottom();
1037
1038 BotRPTracker.initLiveThru(RPTracker);
1039 if (!BotRPTracker.getLiveThru().empty()) {
1040 TopRPTracker.initLiveThru(BotRPTracker.getLiveThru());
1041 LLVM_DEBUG(dbgs() << "Live Thru: ";
1042 dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
1043 };
1044
1045 // For each live out vreg reduce the pressure change associated with other
1046 // uses of the same vreg below the live-out reaching def.
1047 updatePressureDiffs(RPTracker.getPressure().LiveOutRegs);
1048
1049 // Account for liveness generated by the region boundary.
1050 if (LiveRegionEnd != RegionEnd) {
1051 SmallVector<RegisterMaskPair, 8> LiveUses;
1052 BotRPTracker.recede(&LiveUses);
1053 updatePressureDiffs(LiveUses);
1054 }
1055
1056 LLVM_DEBUG(dbgs() << "Top Pressure:\n";
1057 dumpRegSetPressure(TopRPTracker.getRegSetPressureAtPos(), TRI);
1058 dbgs() << "Bottom Pressure:\n";
1059 dumpRegSetPressure(BotRPTracker.getRegSetPressureAtPos(), TRI););
1060
1061 assert((BotRPTracker.getPos() == RegionEnd ||
1062 (RegionEnd->isDebugInstr() &&
1063 BotRPTracker.getPos() == priorNonDebug(RegionEnd, RegionBegin))) &&
1064 "Can't find the region bottom");
1065
1066 // Cache the list of excess pressure sets in this region. This will also track
1067 // the max pressure in the scheduled code for these sets.
1068 RegionCriticalPSets.clear();
1069 const std::vector<unsigned> &RegionPressure =
1070 RPTracker.getPressure().MaxSetPressure;
1071 for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
1072 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
1073 if (RegionPressure[i] > Limit) {
1074 LLVM_DEBUG(dbgs() << TRI->getRegPressureSetName(i) << " Limit " << Limit
1075 << " Actual " << RegionPressure[i] << "\n");
1076 RegionCriticalPSets.push_back(PressureChange(i));
1077 }
1078 }
1079 LLVM_DEBUG(dbgs() << "Excess PSets: ";
1080 for (const PressureChange &RCPS
1081 : RegionCriticalPSets) dbgs()
1082 << TRI->getRegPressureSetName(RCPS.getPSet()) << " ";
1083 dbgs() << "\n");
1084 }
1085
1086 void ScheduleDAGMILive::
updateScheduledPressure(const SUnit * SU,const std::vector<unsigned> & NewMaxPressure)1087 updateScheduledPressure(const SUnit *SU,
1088 const std::vector<unsigned> &NewMaxPressure) {
1089 const PressureDiff &PDiff = getPressureDiff(SU);
1090 unsigned CritIdx = 0, CritEnd = RegionCriticalPSets.size();
1091 for (const PressureChange &PC : PDiff) {
1092 if (!PC.isValid())
1093 break;
1094 unsigned ID = PC.getPSet();
1095 while (CritIdx != CritEnd && RegionCriticalPSets[CritIdx].getPSet() < ID)
1096 ++CritIdx;
1097 if (CritIdx != CritEnd && RegionCriticalPSets[CritIdx].getPSet() == ID) {
1098 if ((int)NewMaxPressure[ID] > RegionCriticalPSets[CritIdx].getUnitInc()
1099 && NewMaxPressure[ID] <= (unsigned)std::numeric_limits<int16_t>::max())
1100 RegionCriticalPSets[CritIdx].setUnitInc(NewMaxPressure[ID]);
1101 }
1102 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID);
1103 if (NewMaxPressure[ID] >= Limit - 2) {
1104 LLVM_DEBUG(dbgs() << " " << TRI->getRegPressureSetName(ID) << ": "
1105 << NewMaxPressure[ID]
1106 << ((NewMaxPressure[ID] > Limit) ? " > " : " <= ")
1107 << Limit << "(+ " << BotRPTracker.getLiveThru()[ID]
1108 << " livethru)\n");
1109 }
1110 }
1111 }
1112
1113 /// Update the PressureDiff array for liveness after scheduling this
1114 /// instruction.
updatePressureDiffs(ArrayRef<RegisterMaskPair> LiveUses)1115 void ScheduleDAGMILive::updatePressureDiffs(
1116 ArrayRef<RegisterMaskPair> LiveUses) {
1117 for (const RegisterMaskPair &P : LiveUses) {
1118 Register Reg = P.RegUnit;
1119 /// FIXME: Currently assuming single-use physregs.
1120 if (!Register::isVirtualRegister(Reg))
1121 continue;
1122
1123 if (ShouldTrackLaneMasks) {
1124 // If the register has just become live then other uses won't change
1125 // this fact anymore => decrement pressure.
1126 // If the register has just become dead then other uses make it come
1127 // back to life => increment pressure.
1128 bool Decrement = P.LaneMask.any();
1129
1130 for (const VReg2SUnit &V2SU
1131 : make_range(VRegUses.find(Reg), VRegUses.end())) {
1132 SUnit &SU = *V2SU.SU;
1133 if (SU.isScheduled || &SU == &ExitSU)
1134 continue;
1135
1136 PressureDiff &PDiff = getPressureDiff(&SU);
1137 PDiff.addPressureChange(Reg, Decrement, &MRI);
1138 LLVM_DEBUG(dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") "
1139 << printReg(Reg, TRI) << ':'
1140 << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr();
1141 dbgs() << " to "; PDiff.dump(*TRI););
1142 }
1143 } else {
1144 assert(P.LaneMask.any());
1145 LLVM_DEBUG(dbgs() << " LiveReg: " << printVRegOrUnit(Reg, TRI) << "\n");
1146 // This may be called before CurrentBottom has been initialized. However,
1147 // BotRPTracker must have a valid position. We want the value live into the
1148 // instruction or live out of the block, so ask for the previous
1149 // instruction's live-out.
1150 const LiveInterval &LI = LIS->getInterval(Reg);
1151 VNInfo *VNI;
1152 MachineBasicBlock::const_iterator I =
1153 nextIfDebug(BotRPTracker.getPos(), BB->end());
1154 if (I == BB->end())
1155 VNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
1156 else {
1157 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*I));
1158 VNI = LRQ.valueIn();
1159 }
1160 // RegisterPressureTracker guarantees that readsReg is true for LiveUses.
1161 assert(VNI && "No live value at use.");
1162 for (const VReg2SUnit &V2SU
1163 : make_range(VRegUses.find(Reg), VRegUses.end())) {
1164 SUnit *SU = V2SU.SU;
1165 // If this use comes before the reaching def, it cannot be a last use,
1166 // so decrease its pressure change.
1167 if (!SU->isScheduled && SU != &ExitSU) {
1168 LiveQueryResult LRQ =
1169 LI.Query(LIS->getInstructionIndex(*SU->getInstr()));
1170 if (LRQ.valueIn() == VNI) {
1171 PressureDiff &PDiff = getPressureDiff(SU);
1172 PDiff.addPressureChange(Reg, true, &MRI);
1173 LLVM_DEBUG(dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "
1174 << *SU->getInstr();
1175 dbgs() << " to "; PDiff.dump(*TRI););
1176 }
1177 }
1178 }
1179 }
1180 }
1181 }
1182
dump() const1183 void ScheduleDAGMILive::dump() const {
1184 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1185 if (EntrySU.getInstr() != nullptr)
1186 dumpNodeAll(EntrySU);
1187 for (const SUnit &SU : SUnits) {
1188 dumpNodeAll(SU);
1189 if (ShouldTrackPressure) {
1190 dbgs() << " Pressure Diff : ";
1191 getPressureDiff(&SU).dump(*TRI);
1192 }
1193 dbgs() << " Single Issue : ";
1194 if (SchedModel.mustBeginGroup(SU.getInstr()) &&
1195 SchedModel.mustEndGroup(SU.getInstr()))
1196 dbgs() << "true;";
1197 else
1198 dbgs() << "false;";
1199 dbgs() << '\n';
1200 }
1201 if (ExitSU.getInstr() != nullptr)
1202 dumpNodeAll(ExitSU);
1203 #endif
1204 }
1205
1206 /// schedule - Called back from MachineScheduler::runOnMachineFunction
1207 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
1208 /// only includes instructions that have DAG nodes, not scheduling boundaries.
1209 ///
1210 /// This is a skeletal driver, with all the functionality pushed into helpers,
1211 /// so that it can be easily extended by experimental schedulers. Generally,
1212 /// implementing MachineSchedStrategy should be sufficient to implement a new
1213 /// scheduling algorithm. However, if a scheduler further subclasses
1214 /// ScheduleDAGMILive then it will want to override this virtual method in order
1215 /// to update any specialized state.
schedule()1216 void ScheduleDAGMILive::schedule() {
1217 LLVM_DEBUG(dbgs() << "ScheduleDAGMILive::schedule starting\n");
1218 LLVM_DEBUG(SchedImpl->dumpPolicy());
1219 buildDAGWithRegPressure();
1220
1221 postprocessDAG();
1222
1223 SmallVector<SUnit*, 8> TopRoots, BotRoots;
1224 findRootsAndBiasEdges(TopRoots, BotRoots);
1225
1226 // Initialize the strategy before modifying the DAG.
1227 // This may initialize a DFSResult to be used for queue priority.
1228 SchedImpl->initialize(this);
1229
1230 LLVM_DEBUG(dump());
1231 if (PrintDAGs) dump();
1232 if (ViewMISchedDAGs) viewGraph();
1233
1234 // Initialize ready queues now that the DAG and priority data are finalized.
1235 initQueues(TopRoots, BotRoots);
1236
1237 bool IsTopNode = false;
1238 while (true) {
1239 LLVM_DEBUG(dbgs() << "** ScheduleDAGMILive::schedule picking next node\n");
1240 SUnit *SU = SchedImpl->pickNode(IsTopNode);
1241 if (!SU) break;
1242
1243 assert(!SU->isScheduled && "Node already scheduled");
1244 if (!checkSchedLimit())
1245 break;
1246
1247 scheduleMI(SU, IsTopNode);
1248
1249 if (DFSResult) {
1250 unsigned SubtreeID = DFSResult->getSubtreeID(SU);
1251 if (!ScheduledTrees.test(SubtreeID)) {
1252 ScheduledTrees.set(SubtreeID);
1253 DFSResult->scheduleTree(SubtreeID);
1254 SchedImpl->scheduleTree(SubtreeID);
1255 }
1256 }
1257
1258 // Notify the scheduling strategy after updating the DAG.
1259 SchedImpl->schedNode(SU, IsTopNode);
1260
1261 updateQueues(SU, IsTopNode);
1262 }
1263 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
1264
1265 placeDebugValues();
1266
1267 LLVM_DEBUG({
1268 dbgs() << "*** Final schedule for "
1269 << printMBBReference(*begin()->getParent()) << " ***\n";
1270 dumpSchedule();
1271 dbgs() << '\n';
1272 });
1273 }
1274
1275 /// Build the DAG and setup three register pressure trackers.
buildDAGWithRegPressure()1276 void ScheduleDAGMILive::buildDAGWithRegPressure() {
1277 if (!ShouldTrackPressure) {
1278 RPTracker.reset();
1279 RegionCriticalPSets.clear();
1280 buildSchedGraph(AA);
1281 return;
1282 }
1283
1284 // Initialize the register pressure tracker used by buildSchedGraph.
1285 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
1286 ShouldTrackLaneMasks, /*TrackUntiedDefs=*/true);
1287
1288 // Account for liveness generate by the region boundary.
1289 if (LiveRegionEnd != RegionEnd)
1290 RPTracker.recede();
1291
1292 // Build the DAG, and compute current register pressure.
1293 buildSchedGraph(AA, &RPTracker, &SUPressureDiffs, LIS, ShouldTrackLaneMasks);
1294
1295 // Initialize top/bottom trackers after computing region pressure.
1296 initRegPressure();
1297 }
1298
computeDFSResult()1299 void ScheduleDAGMILive::computeDFSResult() {
1300 if (!DFSResult)
1301 DFSResult = new SchedDFSResult(/*BottomU*/true, MinSubtreeSize);
1302 DFSResult->clear();
1303 ScheduledTrees.clear();
1304 DFSResult->resize(SUnits.size());
1305 DFSResult->compute(SUnits);
1306 ScheduledTrees.resize(DFSResult->getNumSubtrees());
1307 }
1308
1309 /// Compute the max cyclic critical path through the DAG. The scheduling DAG
1310 /// only provides the critical path for single block loops. To handle loops that
1311 /// span blocks, we could use the vreg path latencies provided by
1312 /// MachineTraceMetrics instead. However, MachineTraceMetrics is not currently
1313 /// available for use in the scheduler.
1314 ///
1315 /// The cyclic path estimation identifies a def-use pair that crosses the back
1316 /// edge and considers the depth and height of the nodes. For example, consider
1317 /// the following instruction sequence where each instruction has unit latency
1318 /// and defines an eponymous virtual register:
1319 ///
1320 /// a->b(a,c)->c(b)->d(c)->exit
1321 ///
1322 /// The cyclic critical path is a two cycles: b->c->b
1323 /// The acyclic critical path is four cycles: a->b->c->d->exit
1324 /// LiveOutHeight = height(c) = len(c->d->exit) = 2
1325 /// LiveOutDepth = depth(c) + 1 = len(a->b->c) + 1 = 3
1326 /// LiveInHeight = height(b) + 1 = len(b->c->d->exit) + 1 = 4
1327 /// LiveInDepth = depth(b) = len(a->b) = 1
1328 ///
1329 /// LiveOutDepth - LiveInDepth = 3 - 1 = 2
1330 /// LiveInHeight - LiveOutHeight = 4 - 2 = 2
1331 /// CyclicCriticalPath = min(2, 2) = 2
1332 ///
1333 /// This could be relevant to PostRA scheduling, but is currently implemented
1334 /// assuming LiveIntervals.
computeCyclicCriticalPath()1335 unsigned ScheduleDAGMILive::computeCyclicCriticalPath() {
1336 // This only applies to single block loop.
1337 if (!BB->isSuccessor(BB))
1338 return 0;
1339
1340 unsigned MaxCyclicLatency = 0;
1341 // Visit each live out vreg def to find def/use pairs that cross iterations.
1342 for (const RegisterMaskPair &P : RPTracker.getPressure().LiveOutRegs) {
1343 Register Reg = P.RegUnit;
1344 if (!Register::isVirtualRegister(Reg))
1345 continue;
1346 const LiveInterval &LI = LIS->getInterval(Reg);
1347 const VNInfo *DefVNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
1348 if (!DefVNI)
1349 continue;
1350
1351 MachineInstr *DefMI = LIS->getInstructionFromIndex(DefVNI->def);
1352 const SUnit *DefSU = getSUnit(DefMI);
1353 if (!DefSU)
1354 continue;
1355
1356 unsigned LiveOutHeight = DefSU->getHeight();
1357 unsigned LiveOutDepth = DefSU->getDepth() + DefSU->Latency;
1358 // Visit all local users of the vreg def.
1359 for (const VReg2SUnit &V2SU
1360 : make_range(VRegUses.find(Reg), VRegUses.end())) {
1361 SUnit *SU = V2SU.SU;
1362 if (SU == &ExitSU)
1363 continue;
1364
1365 // Only consider uses of the phi.
1366 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*SU->getInstr()));
1367 if (!LRQ.valueIn()->isPHIDef())
1368 continue;
1369
1370 // Assume that a path spanning two iterations is a cycle, which could
1371 // overestimate in strange cases. This allows cyclic latency to be
1372 // estimated as the minimum slack of the vreg's depth or height.
1373 unsigned CyclicLatency = 0;
1374 if (LiveOutDepth > SU->getDepth())
1375 CyclicLatency = LiveOutDepth - SU->getDepth();
1376
1377 unsigned LiveInHeight = SU->getHeight() + DefSU->Latency;
1378 if (LiveInHeight > LiveOutHeight) {
1379 if (LiveInHeight - LiveOutHeight < CyclicLatency)
1380 CyclicLatency = LiveInHeight - LiveOutHeight;
1381 } else
1382 CyclicLatency = 0;
1383
1384 LLVM_DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU("
1385 << SU->NodeNum << ") = " << CyclicLatency << "c\n");
1386 if (CyclicLatency > MaxCyclicLatency)
1387 MaxCyclicLatency = CyclicLatency;
1388 }
1389 }
1390 LLVM_DEBUG(dbgs() << "Cyclic Critical Path: " << MaxCyclicLatency << "c\n");
1391 return MaxCyclicLatency;
1392 }
1393
1394 /// Release ExitSU predecessors and setup scheduler queues. Re-position
1395 /// the Top RP tracker in case the region beginning has changed.
initQueues(ArrayRef<SUnit * > TopRoots,ArrayRef<SUnit * > BotRoots)1396 void ScheduleDAGMILive::initQueues(ArrayRef<SUnit*> TopRoots,
1397 ArrayRef<SUnit*> BotRoots) {
1398 ScheduleDAGMI::initQueues(TopRoots, BotRoots);
1399 if (ShouldTrackPressure) {
1400 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
1401 TopRPTracker.setPos(CurrentTop);
1402 }
1403 }
1404
1405 /// Move an instruction and update register pressure.
scheduleMI(SUnit * SU,bool IsTopNode)1406 void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
1407 // Move the instruction to its new location in the instruction stream.
1408 MachineInstr *MI = SU->getInstr();
1409
1410 if (IsTopNode) {
1411 assert(SU->isTopReady() && "node still has unscheduled dependencies");
1412 if (&*CurrentTop == MI)
1413 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
1414 else {
1415 moveInstruction(MI, CurrentTop);
1416 TopRPTracker.setPos(MI);
1417 }
1418
1419 if (ShouldTrackPressure) {
1420 // Update top scheduled pressure.
1421 RegisterOperands RegOpers;
1422 RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
1423 if (ShouldTrackLaneMasks) {
1424 // Adjust liveness and add missing dead+read-undef flags.
1425 SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
1426 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
1427 } else {
1428 // Adjust for missing dead-def flags.
1429 RegOpers.detectDeadDefs(*MI, *LIS);
1430 }
1431
1432 TopRPTracker.advance(RegOpers);
1433 assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
1434 LLVM_DEBUG(dbgs() << "Top Pressure:\n"; dumpRegSetPressure(
1435 TopRPTracker.getRegSetPressureAtPos(), TRI););
1436
1437 updateScheduledPressure(SU, TopRPTracker.getPressure().MaxSetPressure);
1438 }
1439 } else {
1440 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
1441 MachineBasicBlock::iterator priorII =
1442 priorNonDebug(CurrentBottom, CurrentTop);
1443 if (&*priorII == MI)
1444 CurrentBottom = priorII;
1445 else {
1446 if (&*CurrentTop == MI) {
1447 CurrentTop = nextIfDebug(++CurrentTop, priorII);
1448 TopRPTracker.setPos(CurrentTop);
1449 }
1450 moveInstruction(MI, CurrentBottom);
1451 CurrentBottom = MI;
1452 BotRPTracker.setPos(CurrentBottom);
1453 }
1454 if (ShouldTrackPressure) {
1455 RegisterOperands RegOpers;
1456 RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
1457 if (ShouldTrackLaneMasks) {
1458 // Adjust liveness and add missing dead+read-undef flags.
1459 SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
1460 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
1461 } else {
1462 // Adjust for missing dead-def flags.
1463 RegOpers.detectDeadDefs(*MI, *LIS);
1464 }
1465
1466 if (BotRPTracker.getPos() != CurrentBottom)
1467 BotRPTracker.recedeSkipDebugValues();
1468 SmallVector<RegisterMaskPair, 8> LiveUses;
1469 BotRPTracker.recede(RegOpers, &LiveUses);
1470 assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
1471 LLVM_DEBUG(dbgs() << "Bottom Pressure:\n"; dumpRegSetPressure(
1472 BotRPTracker.getRegSetPressureAtPos(), TRI););
1473
1474 updateScheduledPressure(SU, BotRPTracker.getPressure().MaxSetPressure);
1475 updatePressureDiffs(LiveUses);
1476 }
1477 }
1478 }
1479
1480 //===----------------------------------------------------------------------===//
1481 // BaseMemOpClusterMutation - DAG post-processing to cluster loads or stores.
1482 //===----------------------------------------------------------------------===//
1483
1484 namespace {
1485
1486 /// Post-process the DAG to create cluster edges between neighboring
1487 /// loads or between neighboring stores.
1488 class BaseMemOpClusterMutation : public ScheduleDAGMutation {
1489 struct MemOpInfo {
1490 SUnit *SU;
1491 SmallVector<const MachineOperand *, 4> BaseOps;
1492 int64_t Offset;
1493 unsigned Width;
1494
MemOpInfo__anon2c8d5d400311::BaseMemOpClusterMutation::MemOpInfo1495 MemOpInfo(SUnit *SU, ArrayRef<const MachineOperand *> BaseOps,
1496 int64_t Offset, unsigned Width)
1497 : SU(SU), BaseOps(BaseOps.begin(), BaseOps.end()), Offset(Offset),
1498 Width(Width) {}
1499
Compare__anon2c8d5d400311::BaseMemOpClusterMutation::MemOpInfo1500 static bool Compare(const MachineOperand *const &A,
1501 const MachineOperand *const &B) {
1502 if (A->getType() != B->getType())
1503 return A->getType() < B->getType();
1504 if (A->isReg())
1505 return A->getReg() < B->getReg();
1506 if (A->isFI()) {
1507 const MachineFunction &MF = *A->getParent()->getParent()->getParent();
1508 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
1509 bool StackGrowsDown = TFI.getStackGrowthDirection() ==
1510 TargetFrameLowering::StackGrowsDown;
1511 return StackGrowsDown ? A->getIndex() > B->getIndex()
1512 : A->getIndex() < B->getIndex();
1513 }
1514
1515 llvm_unreachable("MemOpClusterMutation only supports register or frame "
1516 "index bases.");
1517 }
1518
operator <__anon2c8d5d400311::BaseMemOpClusterMutation::MemOpInfo1519 bool operator<(const MemOpInfo &RHS) const {
1520 // FIXME: Don't compare everything twice. Maybe use C++20 three way
1521 // comparison instead when it's available.
1522 if (std::lexicographical_compare(BaseOps.begin(), BaseOps.end(),
1523 RHS.BaseOps.begin(), RHS.BaseOps.end(),
1524 Compare))
1525 return true;
1526 if (std::lexicographical_compare(RHS.BaseOps.begin(), RHS.BaseOps.end(),
1527 BaseOps.begin(), BaseOps.end(), Compare))
1528 return false;
1529 if (Offset != RHS.Offset)
1530 return Offset < RHS.Offset;
1531 return SU->NodeNum < RHS.SU->NodeNum;
1532 }
1533 };
1534
1535 const TargetInstrInfo *TII;
1536 const TargetRegisterInfo *TRI;
1537 bool IsLoad;
1538
1539 public:
BaseMemOpClusterMutation(const TargetInstrInfo * tii,const TargetRegisterInfo * tri,bool IsLoad)1540 BaseMemOpClusterMutation(const TargetInstrInfo *tii,
1541 const TargetRegisterInfo *tri, bool IsLoad)
1542 : TII(tii), TRI(tri), IsLoad(IsLoad) {}
1543
1544 void apply(ScheduleDAGInstrs *DAGInstrs) override;
1545
1546 protected:
1547 void clusterNeighboringMemOps(ArrayRef<MemOpInfo> MemOps, bool FastCluster,
1548 ScheduleDAGInstrs *DAG);
1549 void collectMemOpRecords(std::vector<SUnit> &SUnits,
1550 SmallVectorImpl<MemOpInfo> &MemOpRecords);
1551 bool groupMemOps(ArrayRef<MemOpInfo> MemOps, ScheduleDAGInstrs *DAG,
1552 DenseMap<unsigned, SmallVector<MemOpInfo, 32>> &Groups);
1553 };
1554
1555 class StoreClusterMutation : public BaseMemOpClusterMutation {
1556 public:
StoreClusterMutation(const TargetInstrInfo * tii,const TargetRegisterInfo * tri)1557 StoreClusterMutation(const TargetInstrInfo *tii,
1558 const TargetRegisterInfo *tri)
1559 : BaseMemOpClusterMutation(tii, tri, false) {}
1560 };
1561
1562 class LoadClusterMutation : public BaseMemOpClusterMutation {
1563 public:
LoadClusterMutation(const TargetInstrInfo * tii,const TargetRegisterInfo * tri)1564 LoadClusterMutation(const TargetInstrInfo *tii, const TargetRegisterInfo *tri)
1565 : BaseMemOpClusterMutation(tii, tri, true) {}
1566 };
1567
1568 } // end anonymous namespace
1569
1570 namespace llvm {
1571
1572 std::unique_ptr<ScheduleDAGMutation>
createLoadClusterDAGMutation(const TargetInstrInfo * TII,const TargetRegisterInfo * TRI)1573 createLoadClusterDAGMutation(const TargetInstrInfo *TII,
1574 const TargetRegisterInfo *TRI) {
1575 return EnableMemOpCluster ? std::make_unique<LoadClusterMutation>(TII, TRI)
1576 : nullptr;
1577 }
1578
1579 std::unique_ptr<ScheduleDAGMutation>
createStoreClusterDAGMutation(const TargetInstrInfo * TII,const TargetRegisterInfo * TRI)1580 createStoreClusterDAGMutation(const TargetInstrInfo *TII,
1581 const TargetRegisterInfo *TRI) {
1582 return EnableMemOpCluster ? std::make_unique<StoreClusterMutation>(TII, TRI)
1583 : nullptr;
1584 }
1585
1586 } // end namespace llvm
1587
1588 // Sorting all the loads/stores first, then for each load/store, checking the
1589 // following load/store one by one, until reach the first non-dependent one and
1590 // call target hook to see if they can cluster.
1591 // If FastCluster is enabled, we assume that, all the loads/stores have been
1592 // preprocessed and now, they didn't have dependencies on each other.
clusterNeighboringMemOps(ArrayRef<MemOpInfo> MemOpRecords,bool FastCluster,ScheduleDAGInstrs * DAG)1593 void BaseMemOpClusterMutation::clusterNeighboringMemOps(
1594 ArrayRef<MemOpInfo> MemOpRecords, bool FastCluster,
1595 ScheduleDAGInstrs *DAG) {
1596 // Keep track of the current cluster length and bytes for each SUnit.
1597 DenseMap<unsigned, std::pair<unsigned, unsigned>> SUnit2ClusterInfo;
1598
1599 // At this point, `MemOpRecords` array must hold atleast two mem ops. Try to
1600 // cluster mem ops collected within `MemOpRecords` array.
1601 for (unsigned Idx = 0, End = MemOpRecords.size(); Idx < (End - 1); ++Idx) {
1602 // Decision to cluster mem ops is taken based on target dependent logic
1603 auto MemOpa = MemOpRecords[Idx];
1604
1605 // Seek for the next load/store to do the cluster.
1606 unsigned NextIdx = Idx + 1;
1607 for (; NextIdx < End; ++NextIdx)
1608 // Skip if MemOpb has been clustered already or has dependency with
1609 // MemOpa.
1610 if (!SUnit2ClusterInfo.count(MemOpRecords[NextIdx].SU->NodeNum) &&
1611 (FastCluster ||
1612 (!DAG->IsReachable(MemOpRecords[NextIdx].SU, MemOpa.SU) &&
1613 !DAG->IsReachable(MemOpa.SU, MemOpRecords[NextIdx].SU))))
1614 break;
1615 if (NextIdx == End)
1616 continue;
1617
1618 auto MemOpb = MemOpRecords[NextIdx];
1619 unsigned ClusterLength = 2;
1620 unsigned CurrentClusterBytes = MemOpa.Width + MemOpb.Width;
1621 if (SUnit2ClusterInfo.count(MemOpa.SU->NodeNum)) {
1622 ClusterLength = SUnit2ClusterInfo[MemOpa.SU->NodeNum].first + 1;
1623 CurrentClusterBytes =
1624 SUnit2ClusterInfo[MemOpa.SU->NodeNum].second + MemOpb.Width;
1625 }
1626
1627 if (!TII->shouldClusterMemOps(MemOpa.BaseOps, MemOpb.BaseOps, ClusterLength,
1628 CurrentClusterBytes))
1629 continue;
1630
1631 SUnit *SUa = MemOpa.SU;
1632 SUnit *SUb = MemOpb.SU;
1633 if (SUa->NodeNum > SUb->NodeNum)
1634 std::swap(SUa, SUb);
1635
1636 // FIXME: Is this check really required?
1637 if (!DAG->addEdge(SUb, SDep(SUa, SDep::Cluster)))
1638 continue;
1639
1640 LLVM_DEBUG(dbgs() << "Cluster ld/st SU(" << SUa->NodeNum << ") - SU("
1641 << SUb->NodeNum << ")\n");
1642 ++NumClustered;
1643
1644 if (IsLoad) {
1645 // Copy successor edges from SUa to SUb. Interleaving computation
1646 // dependent on SUa can prevent load combining due to register reuse.
1647 // Predecessor edges do not need to be copied from SUb to SUa since
1648 // nearby loads should have effectively the same inputs.
1649 for (const SDep &Succ : SUa->Succs) {
1650 if (Succ.getSUnit() == SUb)
1651 continue;
1652 LLVM_DEBUG(dbgs() << " Copy Succ SU(" << Succ.getSUnit()->NodeNum
1653 << ")\n");
1654 DAG->addEdge(Succ.getSUnit(), SDep(SUb, SDep::Artificial));
1655 }
1656 } else {
1657 // Copy predecessor edges from SUb to SUa to avoid the SUnits that
1658 // SUb dependent on scheduled in-between SUb and SUa. Successor edges
1659 // do not need to be copied from SUa to SUb since no one will depend
1660 // on stores.
1661 // Notice that, we don't need to care about the memory dependency as
1662 // we won't try to cluster them if they have any memory dependency.
1663 for (const SDep &Pred : SUb->Preds) {
1664 if (Pred.getSUnit() == SUa)
1665 continue;
1666 LLVM_DEBUG(dbgs() << " Copy Pred SU(" << Pred.getSUnit()->NodeNum
1667 << ")\n");
1668 DAG->addEdge(SUa, SDep(Pred.getSUnit(), SDep::Artificial));
1669 }
1670 }
1671
1672 SUnit2ClusterInfo[MemOpb.SU->NodeNum] = {ClusterLength,
1673 CurrentClusterBytes};
1674
1675 LLVM_DEBUG(dbgs() << " Curr cluster length: " << ClusterLength
1676 << ", Curr cluster bytes: " << CurrentClusterBytes
1677 << "\n");
1678 }
1679 }
1680
collectMemOpRecords(std::vector<SUnit> & SUnits,SmallVectorImpl<MemOpInfo> & MemOpRecords)1681 void BaseMemOpClusterMutation::collectMemOpRecords(
1682 std::vector<SUnit> &SUnits, SmallVectorImpl<MemOpInfo> &MemOpRecords) {
1683 for (auto &SU : SUnits) {
1684 if ((IsLoad && !SU.getInstr()->mayLoad()) ||
1685 (!IsLoad && !SU.getInstr()->mayStore()))
1686 continue;
1687
1688 const MachineInstr &MI = *SU.getInstr();
1689 SmallVector<const MachineOperand *, 4> BaseOps;
1690 int64_t Offset;
1691 bool OffsetIsScalable;
1692 unsigned Width;
1693 if (TII->getMemOperandsWithOffsetWidth(MI, BaseOps, Offset,
1694 OffsetIsScalable, Width, TRI)) {
1695 MemOpRecords.push_back(MemOpInfo(&SU, BaseOps, Offset, Width));
1696
1697 LLVM_DEBUG(dbgs() << "Num BaseOps: " << BaseOps.size() << ", Offset: "
1698 << Offset << ", OffsetIsScalable: " << OffsetIsScalable
1699 << ", Width: " << Width << "\n");
1700 }
1701 #ifndef NDEBUG
1702 for (auto *Op : BaseOps)
1703 assert(Op);
1704 #endif
1705 }
1706 }
1707
groupMemOps(ArrayRef<MemOpInfo> MemOps,ScheduleDAGInstrs * DAG,DenseMap<unsigned,SmallVector<MemOpInfo,32>> & Groups)1708 bool BaseMemOpClusterMutation::groupMemOps(
1709 ArrayRef<MemOpInfo> MemOps, ScheduleDAGInstrs *DAG,
1710 DenseMap<unsigned, SmallVector<MemOpInfo, 32>> &Groups) {
1711 bool FastCluster =
1712 ForceFastCluster ||
1713 MemOps.size() * DAG->SUnits.size() / 1000 > FastClusterThreshold;
1714
1715 for (const auto &MemOp : MemOps) {
1716 unsigned ChainPredID = DAG->SUnits.size();
1717 if (FastCluster) {
1718 for (const SDep &Pred : MemOp.SU->Preds) {
1719 // We only want to cluster the mem ops that have the same ctrl(non-data)
1720 // pred so that they didn't have ctrl dependency for each other. But for
1721 // store instrs, we can still cluster them if the pred is load instr.
1722 if ((Pred.isCtrl() &&
1723 (IsLoad ||
1724 (Pred.getSUnit() && Pred.getSUnit()->getInstr()->mayStore()))) &&
1725 !Pred.isArtificial()) {
1726 ChainPredID = Pred.getSUnit()->NodeNum;
1727 break;
1728 }
1729 }
1730 } else
1731 ChainPredID = 0;
1732
1733 Groups[ChainPredID].push_back(MemOp);
1734 }
1735 return FastCluster;
1736 }
1737
1738 /// Callback from DAG postProcessing to create cluster edges for loads/stores.
apply(ScheduleDAGInstrs * DAG)1739 void BaseMemOpClusterMutation::apply(ScheduleDAGInstrs *DAG) {
1740 // Collect all the clusterable loads/stores
1741 SmallVector<MemOpInfo, 32> MemOpRecords;
1742 collectMemOpRecords(DAG->SUnits, MemOpRecords);
1743
1744 if (MemOpRecords.size() < 2)
1745 return;
1746
1747 // Put the loads/stores without dependency into the same group with some
1748 // heuristic if the DAG is too complex to avoid compiling time blow up.
1749 // Notice that, some fusion pair could be lost with this.
1750 DenseMap<unsigned, SmallVector<MemOpInfo, 32>> Groups;
1751 bool FastCluster = groupMemOps(MemOpRecords, DAG, Groups);
1752
1753 for (auto &Group : Groups) {
1754 // Sorting the loads/stores, so that, we can stop the cluster as early as
1755 // possible.
1756 llvm::sort(Group.second);
1757
1758 // Trying to cluster all the neighboring loads/stores.
1759 clusterNeighboringMemOps(Group.second, FastCluster, DAG);
1760 }
1761 }
1762
1763 //===----------------------------------------------------------------------===//
1764 // CopyConstrain - DAG post-processing to encourage copy elimination.
1765 //===----------------------------------------------------------------------===//
1766
1767 namespace {
1768
1769 /// Post-process the DAG to create weak edges from all uses of a copy to
1770 /// the one use that defines the copy's source vreg, most likely an induction
1771 /// variable increment.
1772 class CopyConstrain : public ScheduleDAGMutation {
1773 // Transient state.
1774 SlotIndex RegionBeginIdx;
1775
1776 // RegionEndIdx is the slot index of the last non-debug instruction in the
1777 // scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
1778 SlotIndex RegionEndIdx;
1779
1780 public:
CopyConstrain(const TargetInstrInfo *,const TargetRegisterInfo *)1781 CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
1782
1783 void apply(ScheduleDAGInstrs *DAGInstrs) override;
1784
1785 protected:
1786 void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG);
1787 };
1788
1789 } // end anonymous namespace
1790
1791 namespace llvm {
1792
1793 std::unique_ptr<ScheduleDAGMutation>
createCopyConstrainDAGMutation(const TargetInstrInfo * TII,const TargetRegisterInfo * TRI)1794 createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
1795 const TargetRegisterInfo *TRI) {
1796 return std::make_unique<CopyConstrain>(TII, TRI);
1797 }
1798
1799 } // end namespace llvm
1800
1801 /// constrainLocalCopy handles two possibilities:
1802 /// 1) Local src:
1803 /// I0: = dst
1804 /// I1: src = ...
1805 /// I2: = dst
1806 /// I3: dst = src (copy)
1807 /// (create pred->succ edges I0->I1, I2->I1)
1808 ///
1809 /// 2) Local copy:
1810 /// I0: dst = src (copy)
1811 /// I1: = dst
1812 /// I2: src = ...
1813 /// I3: = dst
1814 /// (create pred->succ edges I1->I2, I3->I2)
1815 ///
1816 /// Although the MachineScheduler is currently constrained to single blocks,
1817 /// this algorithm should handle extended blocks. An EBB is a set of
1818 /// contiguously numbered blocks such that the previous block in the EBB is
1819 /// always the single predecessor.
constrainLocalCopy(SUnit * CopySU,ScheduleDAGMILive * DAG)1820 void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG) {
1821 LiveIntervals *LIS = DAG->getLIS();
1822 MachineInstr *Copy = CopySU->getInstr();
1823
1824 // Check for pure vreg copies.
1825 const MachineOperand &SrcOp = Copy->getOperand(1);
1826 Register SrcReg = SrcOp.getReg();
1827 if (!Register::isVirtualRegister(SrcReg) || !SrcOp.readsReg())
1828 return;
1829
1830 const MachineOperand &DstOp = Copy->getOperand(0);
1831 Register DstReg = DstOp.getReg();
1832 if (!Register::isVirtualRegister(DstReg) || DstOp.isDead())
1833 return;
1834
1835 // Check if either the dest or source is local. If it's live across a back
1836 // edge, it's not local. Note that if both vregs are live across the back
1837 // edge, we cannot successfully contrain the copy without cyclic scheduling.
1838 // If both the copy's source and dest are local live intervals, then we
1839 // should treat the dest as the global for the purpose of adding
1840 // constraints. This adds edges from source's other uses to the copy.
1841 unsigned LocalReg = SrcReg;
1842 unsigned GlobalReg = DstReg;
1843 LiveInterval *LocalLI = &LIS->getInterval(LocalReg);
1844 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx)) {
1845 LocalReg = DstReg;
1846 GlobalReg = SrcReg;
1847 LocalLI = &LIS->getInterval(LocalReg);
1848 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx))
1849 return;
1850 }
1851 LiveInterval *GlobalLI = &LIS->getInterval(GlobalReg);
1852
1853 // Find the global segment after the start of the local LI.
1854 LiveInterval::iterator GlobalSegment = GlobalLI->find(LocalLI->beginIndex());
1855 // If GlobalLI does not overlap LocalLI->start, then a copy directly feeds a
1856 // local live range. We could create edges from other global uses to the local
1857 // start, but the coalescer should have already eliminated these cases, so
1858 // don't bother dealing with it.
1859 if (GlobalSegment == GlobalLI->end())
1860 return;
1861
1862 // If GlobalSegment is killed at the LocalLI->start, the call to find()
1863 // returned the next global segment. But if GlobalSegment overlaps with
1864 // LocalLI->start, then advance to the next segment. If a hole in GlobalLI
1865 // exists in LocalLI's vicinity, GlobalSegment will be the end of the hole.
1866 if (GlobalSegment->contains(LocalLI->beginIndex()))
1867 ++GlobalSegment;
1868
1869 if (GlobalSegment == GlobalLI->end())
1870 return;
1871
1872 // Check if GlobalLI contains a hole in the vicinity of LocalLI.
1873 if (GlobalSegment != GlobalLI->begin()) {
1874 // Two address defs have no hole.
1875 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->end,
1876 GlobalSegment->start)) {
1877 return;
1878 }
1879 // If the prior global segment may be defined by the same two-address
1880 // instruction that also defines LocalLI, then can't make a hole here.
1881 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->start,
1882 LocalLI->beginIndex())) {
1883 return;
1884 }
1885 // If GlobalLI has a prior segment, it must be live into the EBB. Otherwise
1886 // it would be a disconnected component in the live range.
1887 assert(std::prev(GlobalSegment)->start < LocalLI->beginIndex() &&
1888 "Disconnected LRG within the scheduling region.");
1889 }
1890 MachineInstr *GlobalDef = LIS->getInstructionFromIndex(GlobalSegment->start);
1891 if (!GlobalDef)
1892 return;
1893
1894 SUnit *GlobalSU = DAG->getSUnit(GlobalDef);
1895 if (!GlobalSU)
1896 return;
1897
1898 // GlobalDef is the bottom of the GlobalLI hole. Open the hole by
1899 // constraining the uses of the last local def to precede GlobalDef.
1900 SmallVector<SUnit*,8> LocalUses;
1901 const VNInfo *LastLocalVN = LocalLI->getVNInfoBefore(LocalLI->endIndex());
1902 MachineInstr *LastLocalDef = LIS->getInstructionFromIndex(LastLocalVN->def);
1903 SUnit *LastLocalSU = DAG->getSUnit(LastLocalDef);
1904 for (const SDep &Succ : LastLocalSU->Succs) {
1905 if (Succ.getKind() != SDep::Data || Succ.getReg() != LocalReg)
1906 continue;
1907 if (Succ.getSUnit() == GlobalSU)
1908 continue;
1909 if (!DAG->canAddEdge(GlobalSU, Succ.getSUnit()))
1910 return;
1911 LocalUses.push_back(Succ.getSUnit());
1912 }
1913 // Open the top of the GlobalLI hole by constraining any earlier global uses
1914 // to precede the start of LocalLI.
1915 SmallVector<SUnit*,8> GlobalUses;
1916 MachineInstr *FirstLocalDef =
1917 LIS->getInstructionFromIndex(LocalLI->beginIndex());
1918 SUnit *FirstLocalSU = DAG->getSUnit(FirstLocalDef);
1919 for (const SDep &Pred : GlobalSU->Preds) {
1920 if (Pred.getKind() != SDep::Anti || Pred.getReg() != GlobalReg)
1921 continue;
1922 if (Pred.getSUnit() == FirstLocalSU)
1923 continue;
1924 if (!DAG->canAddEdge(FirstLocalSU, Pred.getSUnit()))
1925 return;
1926 GlobalUses.push_back(Pred.getSUnit());
1927 }
1928 LLVM_DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n");
1929 // Add the weak edges.
1930 for (SmallVectorImpl<SUnit*>::const_iterator
1931 I = LocalUses.begin(), E = LocalUses.end(); I != E; ++I) {
1932 LLVM_DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU("
1933 << GlobalSU->NodeNum << ")\n");
1934 DAG->addEdge(GlobalSU, SDep(*I, SDep::Weak));
1935 }
1936 for (SmallVectorImpl<SUnit*>::const_iterator
1937 I = GlobalUses.begin(), E = GlobalUses.end(); I != E; ++I) {
1938 LLVM_DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU("
1939 << FirstLocalSU->NodeNum << ")\n");
1940 DAG->addEdge(FirstLocalSU, SDep(*I, SDep::Weak));
1941 }
1942 }
1943
1944 /// Callback from DAG postProcessing to create weak edges to encourage
1945 /// copy elimination.
apply(ScheduleDAGInstrs * DAGInstrs)1946 void CopyConstrain::apply(ScheduleDAGInstrs *DAGInstrs) {
1947 ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
1948 assert(DAG->hasVRegLiveness() && "Expect VRegs with LiveIntervals");
1949
1950 MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
1951 if (FirstPos == DAG->end())
1952 return;
1953 RegionBeginIdx = DAG->getLIS()->getInstructionIndex(*FirstPos);
1954 RegionEndIdx = DAG->getLIS()->getInstructionIndex(
1955 *priorNonDebug(DAG->end(), DAG->begin()));
1956
1957 for (SUnit &SU : DAG->SUnits) {
1958 if (!SU.getInstr()->isCopy())
1959 continue;
1960
1961 constrainLocalCopy(&SU, static_cast<ScheduleDAGMILive*>(DAG));
1962 }
1963 }
1964
1965 //===----------------------------------------------------------------------===//
1966 // MachineSchedStrategy helpers used by GenericScheduler, GenericPostScheduler
1967 // and possibly other custom schedulers.
1968 //===----------------------------------------------------------------------===//
1969
1970 static const unsigned InvalidCycle = ~0U;
1971
~SchedBoundary()1972 SchedBoundary::~SchedBoundary() { delete HazardRec; }
1973
1974 /// Given a Count of resource usage and a Latency value, return true if a
1975 /// SchedBoundary becomes resource limited.
1976 /// If we are checking after scheduling a node, we should return true when
1977 /// we just reach the resource limit.
checkResourceLimit(unsigned LFactor,unsigned Count,unsigned Latency,bool AfterSchedNode)1978 static bool checkResourceLimit(unsigned LFactor, unsigned Count,
1979 unsigned Latency, bool AfterSchedNode) {
1980 int ResCntFactor = (int)(Count - (Latency * LFactor));
1981 if (AfterSchedNode)
1982 return ResCntFactor >= (int)LFactor;
1983 else
1984 return ResCntFactor > (int)LFactor;
1985 }
1986
reset()1987 void SchedBoundary::reset() {
1988 // A new HazardRec is created for each DAG and owned by SchedBoundary.
1989 // Destroying and reconstructing it is very expensive though. So keep
1990 // invalid, placeholder HazardRecs.
1991 if (HazardRec && HazardRec->isEnabled()) {
1992 delete HazardRec;
1993 HazardRec = nullptr;
1994 }
1995 Available.clear();
1996 Pending.clear();
1997 CheckPending = false;
1998 CurrCycle = 0;
1999 CurrMOps = 0;
2000 MinReadyCycle = std::numeric_limits<unsigned>::max();
2001 ExpectedLatency = 0;
2002 DependentLatency = 0;
2003 RetiredMOps = 0;
2004 MaxExecutedResCount = 0;
2005 ZoneCritResIdx = 0;
2006 IsResourceLimited = false;
2007 ReservedCycles.clear();
2008 ReservedCyclesIndex.clear();
2009 #ifndef NDEBUG
2010 // Track the maximum number of stall cycles that could arise either from the
2011 // latency of a DAG edge or the number of cycles that a processor resource is
2012 // reserved (SchedBoundary::ReservedCycles).
2013 MaxObservedStall = 0;
2014 #endif
2015 // Reserve a zero-count for invalid CritResIdx.
2016 ExecutedResCounts.resize(1);
2017 assert(!ExecutedResCounts[0] && "nonzero count for bad resource");
2018 }
2019
2020 void SchedRemainder::
init(ScheduleDAGMI * DAG,const TargetSchedModel * SchedModel)2021 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
2022 reset();
2023 if (!SchedModel->hasInstrSchedModel())
2024 return;
2025 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
2026 for (SUnit &SU : DAG->SUnits) {
2027 const MCSchedClassDesc *SC = DAG->getSchedClass(&SU);
2028 RemIssueCount += SchedModel->getNumMicroOps(SU.getInstr(), SC)
2029 * SchedModel->getMicroOpFactor();
2030 for (TargetSchedModel::ProcResIter
2031 PI = SchedModel->getWriteProcResBegin(SC),
2032 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2033 unsigned PIdx = PI->ProcResourceIdx;
2034 unsigned Factor = SchedModel->getResourceFactor(PIdx);
2035 RemainingCounts[PIdx] += (Factor * PI->Cycles);
2036 }
2037 }
2038 }
2039
2040 void SchedBoundary::
init(ScheduleDAGMI * dag,const TargetSchedModel * smodel,SchedRemainder * rem)2041 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) {
2042 reset();
2043 DAG = dag;
2044 SchedModel = smodel;
2045 Rem = rem;
2046 if (SchedModel->hasInstrSchedModel()) {
2047 unsigned ResourceCount = SchedModel->getNumProcResourceKinds();
2048 ReservedCyclesIndex.resize(ResourceCount);
2049 ExecutedResCounts.resize(ResourceCount);
2050 unsigned NumUnits = 0;
2051
2052 for (unsigned i = 0; i < ResourceCount; ++i) {
2053 ReservedCyclesIndex[i] = NumUnits;
2054 NumUnits += SchedModel->getProcResource(i)->NumUnits;
2055 }
2056
2057 ReservedCycles.resize(NumUnits, InvalidCycle);
2058 }
2059 }
2060
2061 /// Compute the stall cycles based on this SUnit's ready time. Heuristics treat
2062 /// these "soft stalls" differently than the hard stall cycles based on CPU
2063 /// resources and computed by checkHazard(). A fully in-order model
2064 /// (MicroOpBufferSize==0) will not make use of this since instructions are not
2065 /// available for scheduling until they are ready. However, a weaker in-order
2066 /// model may use this for heuristics. For example, if a processor has in-order
2067 /// behavior when reading certain resources, this may come into play.
getLatencyStallCycles(SUnit * SU)2068 unsigned SchedBoundary::getLatencyStallCycles(SUnit *SU) {
2069 if (!SU->isUnbuffered)
2070 return 0;
2071
2072 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
2073 if (ReadyCycle > CurrCycle)
2074 return ReadyCycle - CurrCycle;
2075 return 0;
2076 }
2077
2078 /// Compute the next cycle at which the given processor resource unit
2079 /// can be scheduled.
getNextResourceCycleByInstance(unsigned InstanceIdx,unsigned Cycles)2080 unsigned SchedBoundary::getNextResourceCycleByInstance(unsigned InstanceIdx,
2081 unsigned Cycles) {
2082 unsigned NextUnreserved = ReservedCycles[InstanceIdx];
2083 // If this resource has never been used, always return cycle zero.
2084 if (NextUnreserved == InvalidCycle)
2085 return 0;
2086 // For bottom-up scheduling add the cycles needed for the current operation.
2087 if (!isTop())
2088 NextUnreserved += Cycles;
2089 return NextUnreserved;
2090 }
2091
2092 /// Compute the next cycle at which the given processor resource can be
2093 /// scheduled. Returns the next cycle and the index of the processor resource
2094 /// instance in the reserved cycles vector.
2095 std::pair<unsigned, unsigned>
getNextResourceCycle(unsigned PIdx,unsigned Cycles)2096 SchedBoundary::getNextResourceCycle(unsigned PIdx, unsigned Cycles) {
2097 unsigned MinNextUnreserved = InvalidCycle;
2098 unsigned InstanceIdx = 0;
2099 unsigned StartIndex = ReservedCyclesIndex[PIdx];
2100 unsigned NumberOfInstances = SchedModel->getProcResource(PIdx)->NumUnits;
2101 assert(NumberOfInstances > 0 &&
2102 "Cannot have zero instances of a ProcResource");
2103
2104 for (unsigned I = StartIndex, End = StartIndex + NumberOfInstances; I < End;
2105 ++I) {
2106 unsigned NextUnreserved = getNextResourceCycleByInstance(I, Cycles);
2107 if (MinNextUnreserved > NextUnreserved) {
2108 InstanceIdx = I;
2109 MinNextUnreserved = NextUnreserved;
2110 }
2111 }
2112 return std::make_pair(MinNextUnreserved, InstanceIdx);
2113 }
2114
2115 /// Does this SU have a hazard within the current instruction group.
2116 ///
2117 /// The scheduler supports two modes of hazard recognition. The first is the
2118 /// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
2119 /// supports highly complicated in-order reservation tables
2120 /// (ScoreboardHazardRecognizer) and arbitrary target-specific logic.
2121 ///
2122 /// The second is a streamlined mechanism that checks for hazards based on
2123 /// simple counters that the scheduler itself maintains. It explicitly checks
2124 /// for instruction dispatch limitations, including the number of micro-ops that
2125 /// can dispatch per cycle.
2126 ///
2127 /// TODO: Also check whether the SU must start a new group.
checkHazard(SUnit * SU)2128 bool SchedBoundary::checkHazard(SUnit *SU) {
2129 if (HazardRec->isEnabled()
2130 && HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard) {
2131 return true;
2132 }
2133
2134 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
2135 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) {
2136 LLVM_DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops="
2137 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
2138 return true;
2139 }
2140
2141 if (CurrMOps > 0 &&
2142 ((isTop() && SchedModel->mustBeginGroup(SU->getInstr())) ||
2143 (!isTop() && SchedModel->mustEndGroup(SU->getInstr())))) {
2144 LLVM_DEBUG(dbgs() << " hazard: SU(" << SU->NodeNum << ") must "
2145 << (isTop() ? "begin" : "end") << " group\n");
2146 return true;
2147 }
2148
2149 if (SchedModel->hasInstrSchedModel() && SU->hasReservedResource) {
2150 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2151 for (const MCWriteProcResEntry &PE :
2152 make_range(SchedModel->getWriteProcResBegin(SC),
2153 SchedModel->getWriteProcResEnd(SC))) {
2154 unsigned ResIdx = PE.ProcResourceIdx;
2155 unsigned Cycles = PE.Cycles;
2156 unsigned NRCycle, InstanceIdx;
2157 std::tie(NRCycle, InstanceIdx) = getNextResourceCycle(ResIdx, Cycles);
2158 if (NRCycle > CurrCycle) {
2159 #ifndef NDEBUG
2160 MaxObservedStall = std::max(Cycles, MaxObservedStall);
2161 #endif
2162 LLVM_DEBUG(dbgs() << " SU(" << SU->NodeNum << ") "
2163 << SchedModel->getResourceName(ResIdx)
2164 << '[' << InstanceIdx - ReservedCyclesIndex[ResIdx] << ']'
2165 << "=" << NRCycle << "c\n");
2166 return true;
2167 }
2168 }
2169 }
2170 return false;
2171 }
2172
2173 // Find the unscheduled node in ReadySUs with the highest latency.
2174 unsigned SchedBoundary::
findMaxLatency(ArrayRef<SUnit * > ReadySUs)2175 findMaxLatency(ArrayRef<SUnit*> ReadySUs) {
2176 SUnit *LateSU = nullptr;
2177 unsigned RemLatency = 0;
2178 for (SUnit *SU : ReadySUs) {
2179 unsigned L = getUnscheduledLatency(SU);
2180 if (L > RemLatency) {
2181 RemLatency = L;
2182 LateSU = SU;
2183 }
2184 }
2185 if (LateSU) {
2186 LLVM_DEBUG(dbgs() << Available.getName() << " RemLatency SU("
2187 << LateSU->NodeNum << ") " << RemLatency << "c\n");
2188 }
2189 return RemLatency;
2190 }
2191
2192 // Count resources in this zone and the remaining unscheduled
2193 // instruction. Return the max count, scaled. Set OtherCritIdx to the critical
2194 // resource index, or zero if the zone is issue limited.
2195 unsigned SchedBoundary::
getOtherResourceCount(unsigned & OtherCritIdx)2196 getOtherResourceCount(unsigned &OtherCritIdx) {
2197 OtherCritIdx = 0;
2198 if (!SchedModel->hasInstrSchedModel())
2199 return 0;
2200
2201 unsigned OtherCritCount = Rem->RemIssueCount
2202 + (RetiredMOps * SchedModel->getMicroOpFactor());
2203 LLVM_DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: "
2204 << OtherCritCount / SchedModel->getMicroOpFactor() << '\n');
2205 for (unsigned PIdx = 1, PEnd = SchedModel->getNumProcResourceKinds();
2206 PIdx != PEnd; ++PIdx) {
2207 unsigned OtherCount = getResourceCount(PIdx) + Rem->RemainingCounts[PIdx];
2208 if (OtherCount > OtherCritCount) {
2209 OtherCritCount = OtherCount;
2210 OtherCritIdx = PIdx;
2211 }
2212 }
2213 if (OtherCritIdx) {
2214 LLVM_DEBUG(
2215 dbgs() << " " << Available.getName() << " + Remain CritRes: "
2216 << OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx)
2217 << " " << SchedModel->getResourceName(OtherCritIdx) << "\n");
2218 }
2219 return OtherCritCount;
2220 }
2221
releaseNode(SUnit * SU,unsigned ReadyCycle,bool InPQueue,unsigned Idx)2222 void SchedBoundary::releaseNode(SUnit *SU, unsigned ReadyCycle, bool InPQueue,
2223 unsigned Idx) {
2224 assert(SU->getInstr() && "Scheduled SUnit must have instr");
2225
2226 #ifndef NDEBUG
2227 // ReadyCycle was been bumped up to the CurrCycle when this node was
2228 // scheduled, but CurrCycle may have been eagerly advanced immediately after
2229 // scheduling, so may now be greater than ReadyCycle.
2230 if (ReadyCycle > CurrCycle)
2231 MaxObservedStall = std::max(ReadyCycle - CurrCycle, MaxObservedStall);
2232 #endif
2233
2234 if (ReadyCycle < MinReadyCycle)
2235 MinReadyCycle = ReadyCycle;
2236
2237 // Check for interlocks first. For the purpose of other heuristics, an
2238 // instruction that cannot issue appears as if it's not in the ReadyQueue.
2239 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
2240 bool HazardDetected = (!IsBuffered && ReadyCycle > CurrCycle) ||
2241 checkHazard(SU) || (Available.size() >= ReadyListLimit);
2242
2243 if (!HazardDetected) {
2244 Available.push(SU);
2245
2246 if (InPQueue)
2247 Pending.remove(Pending.begin() + Idx);
2248 return;
2249 }
2250
2251 if (!InPQueue)
2252 Pending.push(SU);
2253 }
2254
2255 /// Move the boundary of scheduled code by one cycle.
bumpCycle(unsigned NextCycle)2256 void SchedBoundary::bumpCycle(unsigned NextCycle) {
2257 if (SchedModel->getMicroOpBufferSize() == 0) {
2258 assert(MinReadyCycle < std::numeric_limits<unsigned>::max() &&
2259 "MinReadyCycle uninitialized");
2260 if (MinReadyCycle > NextCycle)
2261 NextCycle = MinReadyCycle;
2262 }
2263 // Update the current micro-ops, which will issue in the next cycle.
2264 unsigned DecMOps = SchedModel->getIssueWidth() * (NextCycle - CurrCycle);
2265 CurrMOps = (CurrMOps <= DecMOps) ? 0 : CurrMOps - DecMOps;
2266
2267 // Decrement DependentLatency based on the next cycle.
2268 if ((NextCycle - CurrCycle) > DependentLatency)
2269 DependentLatency = 0;
2270 else
2271 DependentLatency -= (NextCycle - CurrCycle);
2272
2273 if (!HazardRec->isEnabled()) {
2274 // Bypass HazardRec virtual calls.
2275 CurrCycle = NextCycle;
2276 } else {
2277 // Bypass getHazardType calls in case of long latency.
2278 for (; CurrCycle != NextCycle; ++CurrCycle) {
2279 if (isTop())
2280 HazardRec->AdvanceCycle();
2281 else
2282 HazardRec->RecedeCycle();
2283 }
2284 }
2285 CheckPending = true;
2286 IsResourceLimited =
2287 checkResourceLimit(SchedModel->getLatencyFactor(), getCriticalCount(),
2288 getScheduledLatency(), true);
2289
2290 LLVM_DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName()
2291 << '\n');
2292 }
2293
incExecutedResources(unsigned PIdx,unsigned Count)2294 void SchedBoundary::incExecutedResources(unsigned PIdx, unsigned Count) {
2295 ExecutedResCounts[PIdx] += Count;
2296 if (ExecutedResCounts[PIdx] > MaxExecutedResCount)
2297 MaxExecutedResCount = ExecutedResCounts[PIdx];
2298 }
2299
2300 /// Add the given processor resource to this scheduled zone.
2301 ///
2302 /// \param Cycles indicates the number of consecutive (non-pipelined) cycles
2303 /// during which this resource is consumed.
2304 ///
2305 /// \return the next cycle at which the instruction may execute without
2306 /// oversubscribing resources.
2307 unsigned SchedBoundary::
countResource(unsigned PIdx,unsigned Cycles,unsigned NextCycle)2308 countResource(unsigned PIdx, unsigned Cycles, unsigned NextCycle) {
2309 unsigned Factor = SchedModel->getResourceFactor(PIdx);
2310 unsigned Count = Factor * Cycles;
2311 LLVM_DEBUG(dbgs() << " " << SchedModel->getResourceName(PIdx) << " +"
2312 << Cycles << "x" << Factor << "u\n");
2313
2314 // Update Executed resources counts.
2315 incExecutedResources(PIdx, Count);
2316 assert(Rem->RemainingCounts[PIdx] >= Count && "resource double counted");
2317 Rem->RemainingCounts[PIdx] -= Count;
2318
2319 // Check if this resource exceeds the current critical resource. If so, it
2320 // becomes the critical resource.
2321 if (ZoneCritResIdx != PIdx && (getResourceCount(PIdx) > getCriticalCount())) {
2322 ZoneCritResIdx = PIdx;
2323 LLVM_DEBUG(dbgs() << " *** Critical resource "
2324 << SchedModel->getResourceName(PIdx) << ": "
2325 << getResourceCount(PIdx) / SchedModel->getLatencyFactor()
2326 << "c\n");
2327 }
2328 // For reserved resources, record the highest cycle using the resource.
2329 unsigned NextAvailable, InstanceIdx;
2330 std::tie(NextAvailable, InstanceIdx) = getNextResourceCycle(PIdx, Cycles);
2331 if (NextAvailable > CurrCycle) {
2332 LLVM_DEBUG(dbgs() << " Resource conflict: "
2333 << SchedModel->getResourceName(PIdx)
2334 << '[' << InstanceIdx - ReservedCyclesIndex[PIdx] << ']'
2335 << " reserved until @" << NextAvailable << "\n");
2336 }
2337 return NextAvailable;
2338 }
2339
2340 /// Move the boundary of scheduled code by one SUnit.
bumpNode(SUnit * SU)2341 void SchedBoundary::bumpNode(SUnit *SU) {
2342 // Update the reservation table.
2343 if (HazardRec->isEnabled()) {
2344 if (!isTop() && SU->isCall) {
2345 // Calls are scheduled with their preceding instructions. For bottom-up
2346 // scheduling, clear the pipeline state before emitting.
2347 HazardRec->Reset();
2348 }
2349 HazardRec->EmitInstruction(SU);
2350 // Scheduling an instruction may have made pending instructions available.
2351 CheckPending = true;
2352 }
2353 // checkHazard should prevent scheduling multiple instructions per cycle that
2354 // exceed the issue width.
2355 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2356 unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr());
2357 assert(
2358 (CurrMOps == 0 || (CurrMOps + IncMOps) <= SchedModel->getIssueWidth()) &&
2359 "Cannot schedule this instruction's MicroOps in the current cycle.");
2360
2361 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
2362 LLVM_DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n");
2363
2364 unsigned NextCycle = CurrCycle;
2365 switch (SchedModel->getMicroOpBufferSize()) {
2366 case 0:
2367 assert(ReadyCycle <= CurrCycle && "Broken PendingQueue");
2368 break;
2369 case 1:
2370 if (ReadyCycle > NextCycle) {
2371 NextCycle = ReadyCycle;
2372 LLVM_DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n");
2373 }
2374 break;
2375 default:
2376 // We don't currently model the OOO reorder buffer, so consider all
2377 // scheduled MOps to be "retired". We do loosely model in-order resource
2378 // latency. If this instruction uses an in-order resource, account for any
2379 // likely stall cycles.
2380 if (SU->isUnbuffered && ReadyCycle > NextCycle)
2381 NextCycle = ReadyCycle;
2382 break;
2383 }
2384 RetiredMOps += IncMOps;
2385
2386 // Update resource counts and critical resource.
2387 if (SchedModel->hasInstrSchedModel()) {
2388 unsigned DecRemIssue = IncMOps * SchedModel->getMicroOpFactor();
2389 assert(Rem->RemIssueCount >= DecRemIssue && "MOps double counted");
2390 Rem->RemIssueCount -= DecRemIssue;
2391 if (ZoneCritResIdx) {
2392 // Scale scheduled micro-ops for comparing with the critical resource.
2393 unsigned ScaledMOps =
2394 RetiredMOps * SchedModel->getMicroOpFactor();
2395
2396 // If scaled micro-ops are now more than the previous critical resource by
2397 // a full cycle, then micro-ops issue becomes critical.
2398 if ((int)(ScaledMOps - getResourceCount(ZoneCritResIdx))
2399 >= (int)SchedModel->getLatencyFactor()) {
2400 ZoneCritResIdx = 0;
2401 LLVM_DEBUG(dbgs() << " *** Critical resource NumMicroOps: "
2402 << ScaledMOps / SchedModel->getLatencyFactor()
2403 << "c\n");
2404 }
2405 }
2406 for (TargetSchedModel::ProcResIter
2407 PI = SchedModel->getWriteProcResBegin(SC),
2408 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2409 unsigned RCycle =
2410 countResource(PI->ProcResourceIdx, PI->Cycles, NextCycle);
2411 if (RCycle > NextCycle)
2412 NextCycle = RCycle;
2413 }
2414 if (SU->hasReservedResource) {
2415 // For reserved resources, record the highest cycle using the resource.
2416 // For top-down scheduling, this is the cycle in which we schedule this
2417 // instruction plus the number of cycles the operations reserves the
2418 // resource. For bottom-up is it simply the instruction's cycle.
2419 for (TargetSchedModel::ProcResIter
2420 PI = SchedModel->getWriteProcResBegin(SC),
2421 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2422 unsigned PIdx = PI->ProcResourceIdx;
2423 if (SchedModel->getProcResource(PIdx)->BufferSize == 0) {
2424 unsigned ReservedUntil, InstanceIdx;
2425 std::tie(ReservedUntil, InstanceIdx) = getNextResourceCycle(PIdx, 0);
2426 if (isTop()) {
2427 ReservedCycles[InstanceIdx] =
2428 std::max(ReservedUntil, NextCycle + PI->Cycles);
2429 } else
2430 ReservedCycles[InstanceIdx] = NextCycle;
2431 }
2432 }
2433 }
2434 }
2435 // Update ExpectedLatency and DependentLatency.
2436 unsigned &TopLatency = isTop() ? ExpectedLatency : DependentLatency;
2437 unsigned &BotLatency = isTop() ? DependentLatency : ExpectedLatency;
2438 if (SU->getDepth() > TopLatency) {
2439 TopLatency = SU->getDepth();
2440 LLVM_DEBUG(dbgs() << " " << Available.getName() << " TopLatency SU("
2441 << SU->NodeNum << ") " << TopLatency << "c\n");
2442 }
2443 if (SU->getHeight() > BotLatency) {
2444 BotLatency = SU->getHeight();
2445 LLVM_DEBUG(dbgs() << " " << Available.getName() << " BotLatency SU("
2446 << SU->NodeNum << ") " << BotLatency << "c\n");
2447 }
2448 // If we stall for any reason, bump the cycle.
2449 if (NextCycle > CurrCycle)
2450 bumpCycle(NextCycle);
2451 else
2452 // After updating ZoneCritResIdx and ExpectedLatency, check if we're
2453 // resource limited. If a stall occurred, bumpCycle does this.
2454 IsResourceLimited =
2455 checkResourceLimit(SchedModel->getLatencyFactor(), getCriticalCount(),
2456 getScheduledLatency(), true);
2457
2458 // Update CurrMOps after calling bumpCycle to handle stalls, since bumpCycle
2459 // resets CurrMOps. Loop to handle instructions with more MOps than issue in
2460 // one cycle. Since we commonly reach the max MOps here, opportunistically
2461 // bump the cycle to avoid uselessly checking everything in the readyQ.
2462 CurrMOps += IncMOps;
2463
2464 // Bump the cycle count for issue group constraints.
2465 // This must be done after NextCycle has been adjust for all other stalls.
2466 // Calling bumpCycle(X) will reduce CurrMOps by one issue group and set
2467 // currCycle to X.
2468 if ((isTop() && SchedModel->mustEndGroup(SU->getInstr())) ||
2469 (!isTop() && SchedModel->mustBeginGroup(SU->getInstr()))) {
2470 LLVM_DEBUG(dbgs() << " Bump cycle to " << (isTop() ? "end" : "begin")
2471 << " group\n");
2472 bumpCycle(++NextCycle);
2473 }
2474
2475 while (CurrMOps >= SchedModel->getIssueWidth()) {
2476 LLVM_DEBUG(dbgs() << " *** Max MOps " << CurrMOps << " at cycle "
2477 << CurrCycle << '\n');
2478 bumpCycle(++NextCycle);
2479 }
2480 LLVM_DEBUG(dumpScheduledState());
2481 }
2482
2483 /// Release pending ready nodes in to the available queue. This makes them
2484 /// visible to heuristics.
releasePending()2485 void SchedBoundary::releasePending() {
2486 // If the available queue is empty, it is safe to reset MinReadyCycle.
2487 if (Available.empty())
2488 MinReadyCycle = std::numeric_limits<unsigned>::max();
2489
2490 // Check to see if any of the pending instructions are ready to issue. If
2491 // so, add them to the available queue.
2492 for (unsigned I = 0, E = Pending.size(); I < E; ++I) {
2493 SUnit *SU = *(Pending.begin() + I);
2494 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
2495
2496 if (ReadyCycle < MinReadyCycle)
2497 MinReadyCycle = ReadyCycle;
2498
2499 if (Available.size() >= ReadyListLimit)
2500 break;
2501
2502 releaseNode(SU, ReadyCycle, true, I);
2503 if (E != Pending.size()) {
2504 --I;
2505 --E;
2506 }
2507 }
2508 CheckPending = false;
2509 }
2510
2511 /// Remove SU from the ready set for this boundary.
removeReady(SUnit * SU)2512 void SchedBoundary::removeReady(SUnit *SU) {
2513 if (Available.isInQueue(SU))
2514 Available.remove(Available.find(SU));
2515 else {
2516 assert(Pending.isInQueue(SU) && "bad ready count");
2517 Pending.remove(Pending.find(SU));
2518 }
2519 }
2520
2521 /// If this queue only has one ready candidate, return it. As a side effect,
2522 /// defer any nodes that now hit a hazard, and advance the cycle until at least
2523 /// one node is ready. If multiple instructions are ready, return NULL.
pickOnlyChoice()2524 SUnit *SchedBoundary::pickOnlyChoice() {
2525 if (CheckPending)
2526 releasePending();
2527
2528 // Defer any ready instrs that now have a hazard.
2529 for (ReadyQueue::iterator I = Available.begin(); I != Available.end();) {
2530 if (checkHazard(*I)) {
2531 Pending.push(*I);
2532 I = Available.remove(I);
2533 continue;
2534 }
2535 ++I;
2536 }
2537 for (unsigned i = 0; Available.empty(); ++i) {
2538 // FIXME: Re-enable assert once PR20057 is resolved.
2539 // assert(i <= (HazardRec->getMaxLookAhead() + MaxObservedStall) &&
2540 // "permanent hazard");
2541 (void)i;
2542 bumpCycle(CurrCycle + 1);
2543 releasePending();
2544 }
2545
2546 LLVM_DEBUG(Pending.dump());
2547 LLVM_DEBUG(Available.dump());
2548
2549 if (Available.size() == 1)
2550 return *Available.begin();
2551 return nullptr;
2552 }
2553
2554 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
2555 // This is useful information to dump after bumpNode.
2556 // Note that the Queue contents are more useful before pickNodeFromQueue.
dumpScheduledState() const2557 LLVM_DUMP_METHOD void SchedBoundary::dumpScheduledState() const {
2558 unsigned ResFactor;
2559 unsigned ResCount;
2560 if (ZoneCritResIdx) {
2561 ResFactor = SchedModel->getResourceFactor(ZoneCritResIdx);
2562 ResCount = getResourceCount(ZoneCritResIdx);
2563 } else {
2564 ResFactor = SchedModel->getMicroOpFactor();
2565 ResCount = RetiredMOps * ResFactor;
2566 }
2567 unsigned LFactor = SchedModel->getLatencyFactor();
2568 dbgs() << Available.getName() << " @" << CurrCycle << "c\n"
2569 << " Retired: " << RetiredMOps;
2570 dbgs() << "\n Executed: " << getExecutedCount() / LFactor << "c";
2571 dbgs() << "\n Critical: " << ResCount / LFactor << "c, "
2572 << ResCount / ResFactor << " "
2573 << SchedModel->getResourceName(ZoneCritResIdx)
2574 << "\n ExpectedLatency: " << ExpectedLatency << "c\n"
2575 << (IsResourceLimited ? " - Resource" : " - Latency")
2576 << " limited.\n";
2577 }
2578 #endif
2579
2580 //===----------------------------------------------------------------------===//
2581 // GenericScheduler - Generic implementation of MachineSchedStrategy.
2582 //===----------------------------------------------------------------------===//
2583
2584 void GenericSchedulerBase::SchedCandidate::
initResourceDelta(const ScheduleDAGMI * DAG,const TargetSchedModel * SchedModel)2585 initResourceDelta(const ScheduleDAGMI *DAG,
2586 const TargetSchedModel *SchedModel) {
2587 if (!Policy.ReduceResIdx && !Policy.DemandResIdx)
2588 return;
2589
2590 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2591 for (TargetSchedModel::ProcResIter
2592 PI = SchedModel->getWriteProcResBegin(SC),
2593 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2594 if (PI->ProcResourceIdx == Policy.ReduceResIdx)
2595 ResDelta.CritResources += PI->Cycles;
2596 if (PI->ProcResourceIdx == Policy.DemandResIdx)
2597 ResDelta.DemandedResources += PI->Cycles;
2598 }
2599 }
2600
2601 /// Compute remaining latency. We need this both to determine whether the
2602 /// overall schedule has become latency-limited and whether the instructions
2603 /// outside this zone are resource or latency limited.
2604 ///
2605 /// The "dependent" latency is updated incrementally during scheduling as the
2606 /// max height/depth of scheduled nodes minus the cycles since it was
2607 /// scheduled:
2608 /// DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone
2609 ///
2610 /// The "independent" latency is the max ready queue depth:
2611 /// ILat = max N.depth for N in Available|Pending
2612 ///
2613 /// RemainingLatency is the greater of independent and dependent latency.
2614 ///
2615 /// These computations are expensive, especially in DAGs with many edges, so
2616 /// only do them if necessary.
computeRemLatency(SchedBoundary & CurrZone)2617 static unsigned computeRemLatency(SchedBoundary &CurrZone) {
2618 unsigned RemLatency = CurrZone.getDependentLatency();
2619 RemLatency = std::max(RemLatency,
2620 CurrZone.findMaxLatency(CurrZone.Available.elements()));
2621 RemLatency = std::max(RemLatency,
2622 CurrZone.findMaxLatency(CurrZone.Pending.elements()));
2623 return RemLatency;
2624 }
2625
2626 /// Returns true if the current cycle plus remaning latency is greater than
2627 /// the critical path in the scheduling region.
shouldReduceLatency(const CandPolicy & Policy,SchedBoundary & CurrZone,bool ComputeRemLatency,unsigned & RemLatency) const2628 bool GenericSchedulerBase::shouldReduceLatency(const CandPolicy &Policy,
2629 SchedBoundary &CurrZone,
2630 bool ComputeRemLatency,
2631 unsigned &RemLatency) const {
2632 // The current cycle is already greater than the critical path, so we are
2633 // already latency limited and don't need to compute the remaining latency.
2634 if (CurrZone.getCurrCycle() > Rem.CriticalPath)
2635 return true;
2636
2637 // If we haven't scheduled anything yet, then we aren't latency limited.
2638 if (CurrZone.getCurrCycle() == 0)
2639 return false;
2640
2641 if (ComputeRemLatency)
2642 RemLatency = computeRemLatency(CurrZone);
2643
2644 return RemLatency + CurrZone.getCurrCycle() > Rem.CriticalPath;
2645 }
2646
2647 /// Set the CandPolicy given a scheduling zone given the current resources and
2648 /// latencies inside and outside the zone.
setPolicy(CandPolicy & Policy,bool IsPostRA,SchedBoundary & CurrZone,SchedBoundary * OtherZone)2649 void GenericSchedulerBase::setPolicy(CandPolicy &Policy, bool IsPostRA,
2650 SchedBoundary &CurrZone,
2651 SchedBoundary *OtherZone) {
2652 // Apply preemptive heuristics based on the total latency and resources
2653 // inside and outside this zone. Potential stalls should be considered before
2654 // following this policy.
2655
2656 // Compute the critical resource outside the zone.
2657 unsigned OtherCritIdx = 0;
2658 unsigned OtherCount =
2659 OtherZone ? OtherZone->getOtherResourceCount(OtherCritIdx) : 0;
2660
2661 bool OtherResLimited = false;
2662 unsigned RemLatency = 0;
2663 bool RemLatencyComputed = false;
2664 if (SchedModel->hasInstrSchedModel() && OtherCount != 0) {
2665 RemLatency = computeRemLatency(CurrZone);
2666 RemLatencyComputed = true;
2667 OtherResLimited = checkResourceLimit(SchedModel->getLatencyFactor(),
2668 OtherCount, RemLatency, false);
2669 }
2670
2671 // Schedule aggressively for latency in PostRA mode. We don't check for
2672 // acyclic latency during PostRA, and highly out-of-order processors will
2673 // skip PostRA scheduling.
2674 if (!OtherResLimited &&
2675 (IsPostRA || shouldReduceLatency(Policy, CurrZone, !RemLatencyComputed,
2676 RemLatency))) {
2677 Policy.ReduceLatency |= true;
2678 LLVM_DEBUG(dbgs() << " " << CurrZone.Available.getName()
2679 << " RemainingLatency " << RemLatency << " + "
2680 << CurrZone.getCurrCycle() << "c > CritPath "
2681 << Rem.CriticalPath << "\n");
2682 }
2683 // If the same resource is limiting inside and outside the zone, do nothing.
2684 if (CurrZone.getZoneCritResIdx() == OtherCritIdx)
2685 return;
2686
2687 LLVM_DEBUG(if (CurrZone.isResourceLimited()) {
2688 dbgs() << " " << CurrZone.Available.getName() << " ResourceLimited: "
2689 << SchedModel->getResourceName(CurrZone.getZoneCritResIdx()) << "\n";
2690 } if (OtherResLimited) dbgs()
2691 << " RemainingLimit: "
2692 << SchedModel->getResourceName(OtherCritIdx) << "\n";
2693 if (!CurrZone.isResourceLimited() && !OtherResLimited) dbgs()
2694 << " Latency limited both directions.\n");
2695
2696 if (CurrZone.isResourceLimited() && !Policy.ReduceResIdx)
2697 Policy.ReduceResIdx = CurrZone.getZoneCritResIdx();
2698
2699 if (OtherResLimited)
2700 Policy.DemandResIdx = OtherCritIdx;
2701 }
2702
2703 #ifndef NDEBUG
getReasonStr(GenericSchedulerBase::CandReason Reason)2704 const char *GenericSchedulerBase::getReasonStr(
2705 GenericSchedulerBase::CandReason Reason) {
2706 switch (Reason) {
2707 case NoCand: return "NOCAND ";
2708 case Only1: return "ONLY1 ";
2709 case PhysReg: return "PHYS-REG ";
2710 case RegExcess: return "REG-EXCESS";
2711 case RegCritical: return "REG-CRIT ";
2712 case Stall: return "STALL ";
2713 case Cluster: return "CLUSTER ";
2714 case Weak: return "WEAK ";
2715 case RegMax: return "REG-MAX ";
2716 case ResourceReduce: return "RES-REDUCE";
2717 case ResourceDemand: return "RES-DEMAND";
2718 case TopDepthReduce: return "TOP-DEPTH ";
2719 case TopPathReduce: return "TOP-PATH ";
2720 case BotHeightReduce:return "BOT-HEIGHT";
2721 case BotPathReduce: return "BOT-PATH ";
2722 case NextDefUse: return "DEF-USE ";
2723 case NodeOrder: return "ORDER ";
2724 };
2725 llvm_unreachable("Unknown reason!");
2726 }
2727
traceCandidate(const SchedCandidate & Cand)2728 void GenericSchedulerBase::traceCandidate(const SchedCandidate &Cand) {
2729 PressureChange P;
2730 unsigned ResIdx = 0;
2731 unsigned Latency = 0;
2732 switch (Cand.Reason) {
2733 default:
2734 break;
2735 case RegExcess:
2736 P = Cand.RPDelta.Excess;
2737 break;
2738 case RegCritical:
2739 P = Cand.RPDelta.CriticalMax;
2740 break;
2741 case RegMax:
2742 P = Cand.RPDelta.CurrentMax;
2743 break;
2744 case ResourceReduce:
2745 ResIdx = Cand.Policy.ReduceResIdx;
2746 break;
2747 case ResourceDemand:
2748 ResIdx = Cand.Policy.DemandResIdx;
2749 break;
2750 case TopDepthReduce:
2751 Latency = Cand.SU->getDepth();
2752 break;
2753 case TopPathReduce:
2754 Latency = Cand.SU->getHeight();
2755 break;
2756 case BotHeightReduce:
2757 Latency = Cand.SU->getHeight();
2758 break;
2759 case BotPathReduce:
2760 Latency = Cand.SU->getDepth();
2761 break;
2762 }
2763 dbgs() << " Cand SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
2764 if (P.isValid())
2765 dbgs() << " " << TRI->getRegPressureSetName(P.getPSet())
2766 << ":" << P.getUnitInc() << " ";
2767 else
2768 dbgs() << " ";
2769 if (ResIdx)
2770 dbgs() << " " << SchedModel->getProcResource(ResIdx)->Name << " ";
2771 else
2772 dbgs() << " ";
2773 if (Latency)
2774 dbgs() << " " << Latency << " cycles ";
2775 else
2776 dbgs() << " ";
2777 dbgs() << '\n';
2778 }
2779 #endif
2780
2781 namespace llvm {
2782 /// Return true if this heuristic determines order.
tryLess(int TryVal,int CandVal,GenericSchedulerBase::SchedCandidate & TryCand,GenericSchedulerBase::SchedCandidate & Cand,GenericSchedulerBase::CandReason Reason)2783 bool tryLess(int TryVal, int CandVal,
2784 GenericSchedulerBase::SchedCandidate &TryCand,
2785 GenericSchedulerBase::SchedCandidate &Cand,
2786 GenericSchedulerBase::CandReason Reason) {
2787 if (TryVal < CandVal) {
2788 TryCand.Reason = Reason;
2789 return true;
2790 }
2791 if (TryVal > CandVal) {
2792 if (Cand.Reason > Reason)
2793 Cand.Reason = Reason;
2794 return true;
2795 }
2796 return false;
2797 }
2798
tryGreater(int TryVal,int CandVal,GenericSchedulerBase::SchedCandidate & TryCand,GenericSchedulerBase::SchedCandidate & Cand,GenericSchedulerBase::CandReason Reason)2799 bool tryGreater(int TryVal, int CandVal,
2800 GenericSchedulerBase::SchedCandidate &TryCand,
2801 GenericSchedulerBase::SchedCandidate &Cand,
2802 GenericSchedulerBase::CandReason Reason) {
2803 if (TryVal > CandVal) {
2804 TryCand.Reason = Reason;
2805 return true;
2806 }
2807 if (TryVal < CandVal) {
2808 if (Cand.Reason > Reason)
2809 Cand.Reason = Reason;
2810 return true;
2811 }
2812 return false;
2813 }
2814
tryLatency(GenericSchedulerBase::SchedCandidate & TryCand,GenericSchedulerBase::SchedCandidate & Cand,SchedBoundary & Zone)2815 bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand,
2816 GenericSchedulerBase::SchedCandidate &Cand,
2817 SchedBoundary &Zone) {
2818 if (Zone.isTop()) {
2819 // Prefer the candidate with the lesser depth, but only if one of them has
2820 // depth greater than the total latency scheduled so far, otherwise either
2821 // of them could be scheduled now with no stall.
2822 if (std::max(TryCand.SU->getDepth(), Cand.SU->getDepth()) >
2823 Zone.getScheduledLatency()) {
2824 if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2825 TryCand, Cand, GenericSchedulerBase::TopDepthReduce))
2826 return true;
2827 }
2828 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2829 TryCand, Cand, GenericSchedulerBase::TopPathReduce))
2830 return true;
2831 } else {
2832 // Prefer the candidate with the lesser height, but only if one of them has
2833 // height greater than the total latency scheduled so far, otherwise either
2834 // of them could be scheduled now with no stall.
2835 if (std::max(TryCand.SU->getHeight(), Cand.SU->getHeight()) >
2836 Zone.getScheduledLatency()) {
2837 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2838 TryCand, Cand, GenericSchedulerBase::BotHeightReduce))
2839 return true;
2840 }
2841 if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2842 TryCand, Cand, GenericSchedulerBase::BotPathReduce))
2843 return true;
2844 }
2845 return false;
2846 }
2847 } // end namespace llvm
2848
tracePick(GenericSchedulerBase::CandReason Reason,bool IsTop)2849 static void tracePick(GenericSchedulerBase::CandReason Reason, bool IsTop) {
2850 LLVM_DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ")
2851 << GenericSchedulerBase::getReasonStr(Reason) << '\n');
2852 }
2853
tracePick(const GenericSchedulerBase::SchedCandidate & Cand)2854 static void tracePick(const GenericSchedulerBase::SchedCandidate &Cand) {
2855 tracePick(Cand.Reason, Cand.AtTop);
2856 }
2857
initialize(ScheduleDAGMI * dag)2858 void GenericScheduler::initialize(ScheduleDAGMI *dag) {
2859 assert(dag->hasVRegLiveness() &&
2860 "(PreRA)GenericScheduler needs vreg liveness");
2861 DAG = static_cast<ScheduleDAGMILive*>(dag);
2862 SchedModel = DAG->getSchedModel();
2863 TRI = DAG->TRI;
2864
2865 if (RegionPolicy.ComputeDFSResult)
2866 DAG->computeDFSResult();
2867
2868 Rem.init(DAG, SchedModel);
2869 Top.init(DAG, SchedModel, &Rem);
2870 Bot.init(DAG, SchedModel, &Rem);
2871
2872 // Initialize resource counts.
2873
2874 // Initialize the HazardRecognizers. If itineraries don't exist, are empty, or
2875 // are disabled, then these HazardRecs will be disabled.
2876 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
2877 if (!Top.HazardRec) {
2878 Top.HazardRec =
2879 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2880 Itin, DAG);
2881 }
2882 if (!Bot.HazardRec) {
2883 Bot.HazardRec =
2884 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2885 Itin, DAG);
2886 }
2887 TopCand.SU = nullptr;
2888 BotCand.SU = nullptr;
2889 }
2890
2891 /// Initialize the per-region scheduling policy.
initPolicy(MachineBasicBlock::iterator Begin,MachineBasicBlock::iterator End,unsigned NumRegionInstrs)2892 void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
2893 MachineBasicBlock::iterator End,
2894 unsigned NumRegionInstrs) {
2895 const MachineFunction &MF = *Begin->getMF();
2896 const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
2897
2898 // Avoid setting up the register pressure tracker for small regions to save
2899 // compile time. As a rough heuristic, only track pressure when the number of
2900 // schedulable instructions exceeds half the integer register file.
2901 RegionPolicy.ShouldTrackPressure = true;
2902 for (unsigned VT = MVT::i32; VT > (unsigned)MVT::i1; --VT) {
2903 MVT::SimpleValueType LegalIntVT = (MVT::SimpleValueType)VT;
2904 if (TLI->isTypeLegal(LegalIntVT)) {
2905 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
2906 TLI->getRegClassFor(LegalIntVT));
2907 RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
2908 }
2909 }
2910
2911 // For generic targets, we default to bottom-up, because it's simpler and more
2912 // compile-time optimizations have been implemented in that direction.
2913 RegionPolicy.OnlyBottomUp = true;
2914
2915 // Allow the subtarget to override default policy.
2916 MF.getSubtarget().overrideSchedPolicy(RegionPolicy, NumRegionInstrs);
2917
2918 // After subtarget overrides, apply command line options.
2919 if (!EnableRegPressure) {
2920 RegionPolicy.ShouldTrackPressure = false;
2921 RegionPolicy.ShouldTrackLaneMasks = false;
2922 }
2923
2924 // Check -misched-topdown/bottomup can force or unforce scheduling direction.
2925 // e.g. -misched-bottomup=false allows scheduling in both directions.
2926 assert((!ForceTopDown || !ForceBottomUp) &&
2927 "-misched-topdown incompatible with -misched-bottomup");
2928 if (ForceBottomUp.getNumOccurrences() > 0) {
2929 RegionPolicy.OnlyBottomUp = ForceBottomUp;
2930 if (RegionPolicy.OnlyBottomUp)
2931 RegionPolicy.OnlyTopDown = false;
2932 }
2933 if (ForceTopDown.getNumOccurrences() > 0) {
2934 RegionPolicy.OnlyTopDown = ForceTopDown;
2935 if (RegionPolicy.OnlyTopDown)
2936 RegionPolicy.OnlyBottomUp = false;
2937 }
2938 }
2939
dumpPolicy() const2940 void GenericScheduler::dumpPolicy() const {
2941 // Cannot completely remove virtual function even in release mode.
2942 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
2943 dbgs() << "GenericScheduler RegionPolicy: "
2944 << " ShouldTrackPressure=" << RegionPolicy.ShouldTrackPressure
2945 << " OnlyTopDown=" << RegionPolicy.OnlyTopDown
2946 << " OnlyBottomUp=" << RegionPolicy.OnlyBottomUp
2947 << "\n";
2948 #endif
2949 }
2950
2951 /// Set IsAcyclicLatencyLimited if the acyclic path is longer than the cyclic
2952 /// critical path by more cycles than it takes to drain the instruction buffer.
2953 /// We estimate an upper bounds on in-flight instructions as:
2954 ///
2955 /// CyclesPerIteration = max( CyclicPath, Loop-Resource-Height )
2956 /// InFlightIterations = AcyclicPath / CyclesPerIteration
2957 /// InFlightResources = InFlightIterations * LoopResources
2958 ///
2959 /// TODO: Check execution resources in addition to IssueCount.
checkAcyclicLatency()2960 void GenericScheduler::checkAcyclicLatency() {
2961 if (Rem.CyclicCritPath == 0 || Rem.CyclicCritPath >= Rem.CriticalPath)
2962 return;
2963
2964 // Scaled number of cycles per loop iteration.
2965 unsigned IterCount =
2966 std::max(Rem.CyclicCritPath * SchedModel->getLatencyFactor(),
2967 Rem.RemIssueCount);
2968 // Scaled acyclic critical path.
2969 unsigned AcyclicCount = Rem.CriticalPath * SchedModel->getLatencyFactor();
2970 // InFlightCount = (AcyclicPath / IterCycles) * InstrPerLoop
2971 unsigned InFlightCount =
2972 (AcyclicCount * Rem.RemIssueCount + IterCount-1) / IterCount;
2973 unsigned BufferLimit =
2974 SchedModel->getMicroOpBufferSize() * SchedModel->getMicroOpFactor();
2975
2976 Rem.IsAcyclicLatencyLimited = InFlightCount > BufferLimit;
2977
2978 LLVM_DEBUG(
2979 dbgs() << "IssueCycles="
2980 << Rem.RemIssueCount / SchedModel->getLatencyFactor() << "c "
2981 << "IterCycles=" << IterCount / SchedModel->getLatencyFactor()
2982 << "c NumIters=" << (AcyclicCount + IterCount - 1) / IterCount
2983 << " InFlight=" << InFlightCount / SchedModel->getMicroOpFactor()
2984 << "m BufferLim=" << SchedModel->getMicroOpBufferSize() << "m\n";
2985 if (Rem.IsAcyclicLatencyLimited) dbgs() << " ACYCLIC LATENCY LIMIT\n");
2986 }
2987
registerRoots()2988 void GenericScheduler::registerRoots() {
2989 Rem.CriticalPath = DAG->ExitSU.getDepth();
2990
2991 // Some roots may not feed into ExitSU. Check all of them in case.
2992 for (const SUnit *SU : Bot.Available) {
2993 if (SU->getDepth() > Rem.CriticalPath)
2994 Rem.CriticalPath = SU->getDepth();
2995 }
2996 LLVM_DEBUG(dbgs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << '\n');
2997 if (DumpCriticalPathLength) {
2998 errs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << " \n";
2999 }
3000
3001 if (EnableCyclicPath && SchedModel->getMicroOpBufferSize() > 0) {
3002 Rem.CyclicCritPath = DAG->computeCyclicCriticalPath();
3003 checkAcyclicLatency();
3004 }
3005 }
3006
3007 namespace llvm {
tryPressure(const PressureChange & TryP,const PressureChange & CandP,GenericSchedulerBase::SchedCandidate & TryCand,GenericSchedulerBase::SchedCandidate & Cand,GenericSchedulerBase::CandReason Reason,const TargetRegisterInfo * TRI,const MachineFunction & MF)3008 bool tryPressure(const PressureChange &TryP,
3009 const PressureChange &CandP,
3010 GenericSchedulerBase::SchedCandidate &TryCand,
3011 GenericSchedulerBase::SchedCandidate &Cand,
3012 GenericSchedulerBase::CandReason Reason,
3013 const TargetRegisterInfo *TRI,
3014 const MachineFunction &MF) {
3015 // If one candidate decreases and the other increases, go with it.
3016 // Invalid candidates have UnitInc==0.
3017 if (tryGreater(TryP.getUnitInc() < 0, CandP.getUnitInc() < 0, TryCand, Cand,
3018 Reason)) {
3019 return true;
3020 }
3021 // Do not compare the magnitude of pressure changes between top and bottom
3022 // boundary.
3023 if (Cand.AtTop != TryCand.AtTop)
3024 return false;
3025
3026 // If both candidates affect the same set in the same boundary, go with the
3027 // smallest increase.
3028 unsigned TryPSet = TryP.getPSetOrMax();
3029 unsigned CandPSet = CandP.getPSetOrMax();
3030 if (TryPSet == CandPSet) {
3031 return tryLess(TryP.getUnitInc(), CandP.getUnitInc(), TryCand, Cand,
3032 Reason);
3033 }
3034
3035 int TryRank = TryP.isValid() ? TRI->getRegPressureSetScore(MF, TryPSet) :
3036 std::numeric_limits<int>::max();
3037
3038 int CandRank = CandP.isValid() ? TRI->getRegPressureSetScore(MF, CandPSet) :
3039 std::numeric_limits<int>::max();
3040
3041 // If the candidates are decreasing pressure, reverse priority.
3042 if (TryP.getUnitInc() < 0)
3043 std::swap(TryRank, CandRank);
3044 return tryGreater(TryRank, CandRank, TryCand, Cand, Reason);
3045 }
3046
getWeakLeft(const SUnit * SU,bool isTop)3047 unsigned getWeakLeft(const SUnit *SU, bool isTop) {
3048 return (isTop) ? SU->WeakPredsLeft : SU->WeakSuccsLeft;
3049 }
3050
3051 /// Minimize physical register live ranges. Regalloc wants them adjacent to
3052 /// their physreg def/use.
3053 ///
3054 /// FIXME: This is an unnecessary check on the critical path. Most are root/leaf
3055 /// copies which can be prescheduled. The rest (e.g. x86 MUL) could be bundled
3056 /// with the operation that produces or consumes the physreg. We'll do this when
3057 /// regalloc has support for parallel copies.
biasPhysReg(const SUnit * SU,bool isTop)3058 int biasPhysReg(const SUnit *SU, bool isTop) {
3059 const MachineInstr *MI = SU->getInstr();
3060
3061 if (MI->isCopy()) {
3062 unsigned ScheduledOper = isTop ? 1 : 0;
3063 unsigned UnscheduledOper = isTop ? 0 : 1;
3064 // If we have already scheduled the physreg produce/consumer, immediately
3065 // schedule the copy.
3066 if (Register::isPhysicalRegister(MI->getOperand(ScheduledOper).getReg()))
3067 return 1;
3068 // If the physreg is at the boundary, defer it. Otherwise schedule it
3069 // immediately to free the dependent. We can hoist the copy later.
3070 bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft;
3071 if (Register::isPhysicalRegister(MI->getOperand(UnscheduledOper).getReg()))
3072 return AtBoundary ? -1 : 1;
3073 }
3074
3075 if (MI->isMoveImmediate()) {
3076 // If we have a move immediate and all successors have been assigned, bias
3077 // towards scheduling this later. Make sure all register defs are to
3078 // physical registers.
3079 bool DoBias = true;
3080 for (const MachineOperand &Op : MI->defs()) {
3081 if (Op.isReg() && !Register::isPhysicalRegister(Op.getReg())) {
3082 DoBias = false;
3083 break;
3084 }
3085 }
3086
3087 if (DoBias)
3088 return isTop ? -1 : 1;
3089 }
3090
3091 return 0;
3092 }
3093 } // end namespace llvm
3094
initCandidate(SchedCandidate & Cand,SUnit * SU,bool AtTop,const RegPressureTracker & RPTracker,RegPressureTracker & TempTracker)3095 void GenericScheduler::initCandidate(SchedCandidate &Cand, SUnit *SU,
3096 bool AtTop,
3097 const RegPressureTracker &RPTracker,
3098 RegPressureTracker &TempTracker) {
3099 Cand.SU = SU;
3100 Cand.AtTop = AtTop;
3101 if (DAG->isTrackingPressure()) {
3102 if (AtTop) {
3103 TempTracker.getMaxDownwardPressureDelta(
3104 Cand.SU->getInstr(),
3105 Cand.RPDelta,
3106 DAG->getRegionCriticalPSets(),
3107 DAG->getRegPressure().MaxSetPressure);
3108 } else {
3109 if (VerifyScheduling) {
3110 TempTracker.getMaxUpwardPressureDelta(
3111 Cand.SU->getInstr(),
3112 &DAG->getPressureDiff(Cand.SU),
3113 Cand.RPDelta,
3114 DAG->getRegionCriticalPSets(),
3115 DAG->getRegPressure().MaxSetPressure);
3116 } else {
3117 RPTracker.getUpwardPressureDelta(
3118 Cand.SU->getInstr(),
3119 DAG->getPressureDiff(Cand.SU),
3120 Cand.RPDelta,
3121 DAG->getRegionCriticalPSets(),
3122 DAG->getRegPressure().MaxSetPressure);
3123 }
3124 }
3125 }
3126 LLVM_DEBUG(if (Cand.RPDelta.Excess.isValid()) dbgs()
3127 << " Try SU(" << Cand.SU->NodeNum << ") "
3128 << TRI->getRegPressureSetName(Cand.RPDelta.Excess.getPSet()) << ":"
3129 << Cand.RPDelta.Excess.getUnitInc() << "\n");
3130 }
3131
3132 /// Apply a set of heuristics to a new candidate. Heuristics are currently
3133 /// hierarchical. This may be more efficient than a graduated cost model because
3134 /// we don't need to evaluate all aspects of the model for each node in the
3135 /// queue. But it's really done to make the heuristics easier to debug and
3136 /// statistically analyze.
3137 ///
3138 /// \param Cand provides the policy and current best candidate.
3139 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
3140 /// \param Zone describes the scheduled zone that we are extending, or nullptr
3141 // if Cand is from a different zone than TryCand.
tryCandidate(SchedCandidate & Cand,SchedCandidate & TryCand,SchedBoundary * Zone) const3142 void GenericScheduler::tryCandidate(SchedCandidate &Cand,
3143 SchedCandidate &TryCand,
3144 SchedBoundary *Zone) const {
3145 // Initialize the candidate if needed.
3146 if (!Cand.isValid()) {
3147 TryCand.Reason = NodeOrder;
3148 return;
3149 }
3150
3151 // Bias PhysReg Defs and copies to their uses and defined respectively.
3152 if (tryGreater(biasPhysReg(TryCand.SU, TryCand.AtTop),
3153 biasPhysReg(Cand.SU, Cand.AtTop), TryCand, Cand, PhysReg))
3154 return;
3155
3156 // Avoid exceeding the target's limit.
3157 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.Excess,
3158 Cand.RPDelta.Excess,
3159 TryCand, Cand, RegExcess, TRI,
3160 DAG->MF))
3161 return;
3162
3163 // Avoid increasing the max critical pressure in the scheduled region.
3164 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CriticalMax,
3165 Cand.RPDelta.CriticalMax,
3166 TryCand, Cand, RegCritical, TRI,
3167 DAG->MF))
3168 return;
3169
3170 // We only compare a subset of features when comparing nodes between
3171 // Top and Bottom boundary. Some properties are simply incomparable, in many
3172 // other instances we should only override the other boundary if something
3173 // is a clear good pick on one boundary. Skip heuristics that are more
3174 // "tie-breaking" in nature.
3175 bool SameBoundary = Zone != nullptr;
3176 if (SameBoundary) {
3177 // For loops that are acyclic path limited, aggressively schedule for
3178 // latency. Within an single cycle, whenever CurrMOps > 0, allow normal
3179 // heuristics to take precedence.
3180 if (Rem.IsAcyclicLatencyLimited && !Zone->getCurrMOps() &&
3181 tryLatency(TryCand, Cand, *Zone))
3182 return;
3183
3184 // Prioritize instructions that read unbuffered resources by stall cycles.
3185 if (tryLess(Zone->getLatencyStallCycles(TryCand.SU),
3186 Zone->getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
3187 return;
3188 }
3189
3190 // Keep clustered nodes together to encourage downstream peephole
3191 // optimizations which may reduce resource requirements.
3192 //
3193 // This is a best effort to set things up for a post-RA pass. Optimizations
3194 // like generating loads of multiple registers should ideally be done within
3195 // the scheduler pass by combining the loads during DAG postprocessing.
3196 const SUnit *CandNextClusterSU =
3197 Cand.AtTop ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
3198 const SUnit *TryCandNextClusterSU =
3199 TryCand.AtTop ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
3200 if (tryGreater(TryCand.SU == TryCandNextClusterSU,
3201 Cand.SU == CandNextClusterSU,
3202 TryCand, Cand, Cluster))
3203 return;
3204
3205 if (SameBoundary) {
3206 // Weak edges are for clustering and other constraints.
3207 if (tryLess(getWeakLeft(TryCand.SU, TryCand.AtTop),
3208 getWeakLeft(Cand.SU, Cand.AtTop),
3209 TryCand, Cand, Weak))
3210 return;
3211 }
3212
3213 // Avoid increasing the max pressure of the entire region.
3214 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CurrentMax,
3215 Cand.RPDelta.CurrentMax,
3216 TryCand, Cand, RegMax, TRI,
3217 DAG->MF))
3218 return;
3219
3220 if (SameBoundary) {
3221 // Avoid critical resource consumption and balance the schedule.
3222 TryCand.initResourceDelta(DAG, SchedModel);
3223 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
3224 TryCand, Cand, ResourceReduce))
3225 return;
3226 if (tryGreater(TryCand.ResDelta.DemandedResources,
3227 Cand.ResDelta.DemandedResources,
3228 TryCand, Cand, ResourceDemand))
3229 return;
3230
3231 // Avoid serializing long latency dependence chains.
3232 // For acyclic path limited loops, latency was already checked above.
3233 if (!RegionPolicy.DisableLatencyHeuristic && TryCand.Policy.ReduceLatency &&
3234 !Rem.IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, *Zone))
3235 return;
3236
3237 // Fall through to original instruction order.
3238 if ((Zone->isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum)
3239 || (!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
3240 TryCand.Reason = NodeOrder;
3241 }
3242 }
3243 }
3244
3245 /// Pick the best candidate from the queue.
3246 ///
3247 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
3248 /// DAG building. To adjust for the current scheduling location we need to
3249 /// maintain the number of vreg uses remaining to be top-scheduled.
pickNodeFromQueue(SchedBoundary & Zone,const CandPolicy & ZonePolicy,const RegPressureTracker & RPTracker,SchedCandidate & Cand)3250 void GenericScheduler::pickNodeFromQueue(SchedBoundary &Zone,
3251 const CandPolicy &ZonePolicy,
3252 const RegPressureTracker &RPTracker,
3253 SchedCandidate &Cand) {
3254 // getMaxPressureDelta temporarily modifies the tracker.
3255 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
3256
3257 ReadyQueue &Q = Zone.Available;
3258 for (SUnit *SU : Q) {
3259
3260 SchedCandidate TryCand(ZonePolicy);
3261 initCandidate(TryCand, SU, Zone.isTop(), RPTracker, TempTracker);
3262 // Pass SchedBoundary only when comparing nodes from the same boundary.
3263 SchedBoundary *ZoneArg = Cand.AtTop == TryCand.AtTop ? &Zone : nullptr;
3264 tryCandidate(Cand, TryCand, ZoneArg);
3265 if (TryCand.Reason != NoCand) {
3266 // Initialize resource delta if needed in case future heuristics query it.
3267 if (TryCand.ResDelta == SchedResourceDelta())
3268 TryCand.initResourceDelta(DAG, SchedModel);
3269 Cand.setBest(TryCand);
3270 LLVM_DEBUG(traceCandidate(Cand));
3271 }
3272 }
3273 }
3274
3275 /// Pick the best candidate node from either the top or bottom queue.
pickNodeBidirectional(bool & IsTopNode)3276 SUnit *GenericScheduler::pickNodeBidirectional(bool &IsTopNode) {
3277 // Schedule as far as possible in the direction of no choice. This is most
3278 // efficient, but also provides the best heuristics for CriticalPSets.
3279 if (SUnit *SU = Bot.pickOnlyChoice()) {
3280 IsTopNode = false;
3281 tracePick(Only1, false);
3282 return SU;
3283 }
3284 if (SUnit *SU = Top.pickOnlyChoice()) {
3285 IsTopNode = true;
3286 tracePick(Only1, true);
3287 return SU;
3288 }
3289 // Set the bottom-up policy based on the state of the current bottom zone and
3290 // the instructions outside the zone, including the top zone.
3291 CandPolicy BotPolicy;
3292 setPolicy(BotPolicy, /*IsPostRA=*/false, Bot, &Top);
3293 // Set the top-down policy based on the state of the current top zone and
3294 // the instructions outside the zone, including the bottom zone.
3295 CandPolicy TopPolicy;
3296 setPolicy(TopPolicy, /*IsPostRA=*/false, Top, &Bot);
3297
3298 // See if BotCand is still valid (because we previously scheduled from Top).
3299 LLVM_DEBUG(dbgs() << "Picking from Bot:\n");
3300 if (!BotCand.isValid() || BotCand.SU->isScheduled ||
3301 BotCand.Policy != BotPolicy) {
3302 BotCand.reset(CandPolicy());
3303 pickNodeFromQueue(Bot, BotPolicy, DAG->getBotRPTracker(), BotCand);
3304 assert(BotCand.Reason != NoCand && "failed to find the first candidate");
3305 } else {
3306 LLVM_DEBUG(traceCandidate(BotCand));
3307 #ifndef NDEBUG
3308 if (VerifyScheduling) {
3309 SchedCandidate TCand;
3310 TCand.reset(CandPolicy());
3311 pickNodeFromQueue(Bot, BotPolicy, DAG->getBotRPTracker(), TCand);
3312 assert(TCand.SU == BotCand.SU &&
3313 "Last pick result should correspond to re-picking right now");
3314 }
3315 #endif
3316 }
3317
3318 // Check if the top Q has a better candidate.
3319 LLVM_DEBUG(dbgs() << "Picking from Top:\n");
3320 if (!TopCand.isValid() || TopCand.SU->isScheduled ||
3321 TopCand.Policy != TopPolicy) {
3322 TopCand.reset(CandPolicy());
3323 pickNodeFromQueue(Top, TopPolicy, DAG->getTopRPTracker(), TopCand);
3324 assert(TopCand.Reason != NoCand && "failed to find the first candidate");
3325 } else {
3326 LLVM_DEBUG(traceCandidate(TopCand));
3327 #ifndef NDEBUG
3328 if (VerifyScheduling) {
3329 SchedCandidate TCand;
3330 TCand.reset(CandPolicy());
3331 pickNodeFromQueue(Top, TopPolicy, DAG->getTopRPTracker(), TCand);
3332 assert(TCand.SU == TopCand.SU &&
3333 "Last pick result should correspond to re-picking right now");
3334 }
3335 #endif
3336 }
3337
3338 // Pick best from BotCand and TopCand.
3339 assert(BotCand.isValid());
3340 assert(TopCand.isValid());
3341 SchedCandidate Cand = BotCand;
3342 TopCand.Reason = NoCand;
3343 tryCandidate(Cand, TopCand, nullptr);
3344 if (TopCand.Reason != NoCand) {
3345 Cand.setBest(TopCand);
3346 LLVM_DEBUG(traceCandidate(Cand));
3347 }
3348
3349 IsTopNode = Cand.AtTop;
3350 tracePick(Cand);
3351 return Cand.SU;
3352 }
3353
3354 /// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
pickNode(bool & IsTopNode)3355 SUnit *GenericScheduler::pickNode(bool &IsTopNode) {
3356 if (DAG->top() == DAG->bottom()) {
3357 assert(Top.Available.empty() && Top.Pending.empty() &&
3358 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
3359 return nullptr;
3360 }
3361 SUnit *SU;
3362 do {
3363 if (RegionPolicy.OnlyTopDown) {
3364 SU = Top.pickOnlyChoice();
3365 if (!SU) {
3366 CandPolicy NoPolicy;
3367 TopCand.reset(NoPolicy);
3368 pickNodeFromQueue(Top, NoPolicy, DAG->getTopRPTracker(), TopCand);
3369 assert(TopCand.Reason != NoCand && "failed to find a candidate");
3370 tracePick(TopCand);
3371 SU = TopCand.SU;
3372 }
3373 IsTopNode = true;
3374 } else if (RegionPolicy.OnlyBottomUp) {
3375 SU = Bot.pickOnlyChoice();
3376 if (!SU) {
3377 CandPolicy NoPolicy;
3378 BotCand.reset(NoPolicy);
3379 pickNodeFromQueue(Bot, NoPolicy, DAG->getBotRPTracker(), BotCand);
3380 assert(BotCand.Reason != NoCand && "failed to find a candidate");
3381 tracePick(BotCand);
3382 SU = BotCand.SU;
3383 }
3384 IsTopNode = false;
3385 } else {
3386 SU = pickNodeBidirectional(IsTopNode);
3387 }
3388 } while (SU->isScheduled);
3389
3390 if (SU->isTopReady())
3391 Top.removeReady(SU);
3392 if (SU->isBottomReady())
3393 Bot.removeReady(SU);
3394
3395 LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
3396 << *SU->getInstr());
3397 return SU;
3398 }
3399
reschedulePhysReg(SUnit * SU,bool isTop)3400 void GenericScheduler::reschedulePhysReg(SUnit *SU, bool isTop) {
3401 MachineBasicBlock::iterator InsertPos = SU->getInstr();
3402 if (!isTop)
3403 ++InsertPos;
3404 SmallVectorImpl<SDep> &Deps = isTop ? SU->Preds : SU->Succs;
3405
3406 // Find already scheduled copies with a single physreg dependence and move
3407 // them just above the scheduled instruction.
3408 for (SDep &Dep : Deps) {
3409 if (Dep.getKind() != SDep::Data ||
3410 !Register::isPhysicalRegister(Dep.getReg()))
3411 continue;
3412 SUnit *DepSU = Dep.getSUnit();
3413 if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)
3414 continue;
3415 MachineInstr *Copy = DepSU->getInstr();
3416 if (!Copy->isCopy() && !Copy->isMoveImmediate())
3417 continue;
3418 LLVM_DEBUG(dbgs() << " Rescheduling physreg copy ";
3419 DAG->dumpNode(*Dep.getSUnit()));
3420 DAG->moveInstruction(Copy, InsertPos);
3421 }
3422 }
3423
3424 /// Update the scheduler's state after scheduling a node. This is the same node
3425 /// that was just returned by pickNode(). However, ScheduleDAGMILive needs to
3426 /// update it's state based on the current cycle before MachineSchedStrategy
3427 /// does.
3428 ///
3429 /// FIXME: Eventually, we may bundle physreg copies rather than rescheduling
3430 /// them here. See comments in biasPhysReg.
schedNode(SUnit * SU,bool IsTopNode)3431 void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
3432 if (IsTopNode) {
3433 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.getCurrCycle());
3434 Top.bumpNode(SU);
3435 if (SU->hasPhysRegUses)
3436 reschedulePhysReg(SU, true);
3437 } else {
3438 SU->BotReadyCycle = std::max(SU->BotReadyCycle, Bot.getCurrCycle());
3439 Bot.bumpNode(SU);
3440 if (SU->hasPhysRegDefs)
3441 reschedulePhysReg(SU, false);
3442 }
3443 }
3444
3445 /// Create the standard converging machine scheduler. This will be used as the
3446 /// default scheduler if the target does not set a default.
createGenericSchedLive(MachineSchedContext * C)3447 ScheduleDAGMILive *llvm::createGenericSchedLive(MachineSchedContext *C) {
3448 ScheduleDAGMILive *DAG =
3449 new ScheduleDAGMILive(C, std::make_unique<GenericScheduler>(C));
3450 // Register DAG post-processors.
3451 //
3452 // FIXME: extend the mutation API to allow earlier mutations to instantiate
3453 // data and pass it to later mutations. Have a single mutation that gathers
3454 // the interesting nodes in one pass.
3455 DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
3456 return DAG;
3457 }
3458
createConvergingSched(MachineSchedContext * C)3459 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
3460 return createGenericSchedLive(C);
3461 }
3462
3463 static MachineSchedRegistry
3464 GenericSchedRegistry("converge", "Standard converging scheduler.",
3465 createConvergingSched);
3466
3467 //===----------------------------------------------------------------------===//
3468 // PostGenericScheduler - Generic PostRA implementation of MachineSchedStrategy.
3469 //===----------------------------------------------------------------------===//
3470
initialize(ScheduleDAGMI * Dag)3471 void PostGenericScheduler::initialize(ScheduleDAGMI *Dag) {
3472 DAG = Dag;
3473 SchedModel = DAG->getSchedModel();
3474 TRI = DAG->TRI;
3475
3476 Rem.init(DAG, SchedModel);
3477 Top.init(DAG, SchedModel, &Rem);
3478 BotRoots.clear();
3479
3480 // Initialize the HazardRecognizers. If itineraries don't exist, are empty,
3481 // or are disabled, then these HazardRecs will be disabled.
3482 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
3483 if (!Top.HazardRec) {
3484 Top.HazardRec =
3485 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
3486 Itin, DAG);
3487 }
3488 }
3489
registerRoots()3490 void PostGenericScheduler::registerRoots() {
3491 Rem.CriticalPath = DAG->ExitSU.getDepth();
3492
3493 // Some roots may not feed into ExitSU. Check all of them in case.
3494 for (const SUnit *SU : BotRoots) {
3495 if (SU->getDepth() > Rem.CriticalPath)
3496 Rem.CriticalPath = SU->getDepth();
3497 }
3498 LLVM_DEBUG(dbgs() << "Critical Path: (PGS-RR) " << Rem.CriticalPath << '\n');
3499 if (DumpCriticalPathLength) {
3500 errs() << "Critical Path(PGS-RR ): " << Rem.CriticalPath << " \n";
3501 }
3502 }
3503
3504 /// Apply a set of heuristics to a new candidate for PostRA scheduling.
3505 ///
3506 /// \param Cand provides the policy and current best candidate.
3507 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
tryCandidate(SchedCandidate & Cand,SchedCandidate & TryCand)3508 void PostGenericScheduler::tryCandidate(SchedCandidate &Cand,
3509 SchedCandidate &TryCand) {
3510 // Initialize the candidate if needed.
3511 if (!Cand.isValid()) {
3512 TryCand.Reason = NodeOrder;
3513 return;
3514 }
3515
3516 // Prioritize instructions that read unbuffered resources by stall cycles.
3517 if (tryLess(Top.getLatencyStallCycles(TryCand.SU),
3518 Top.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
3519 return;
3520
3521 // Keep clustered nodes together.
3522 if (tryGreater(TryCand.SU == DAG->getNextClusterSucc(),
3523 Cand.SU == DAG->getNextClusterSucc(),
3524 TryCand, Cand, Cluster))
3525 return;
3526
3527 // Avoid critical resource consumption and balance the schedule.
3528 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
3529 TryCand, Cand, ResourceReduce))
3530 return;
3531 if (tryGreater(TryCand.ResDelta.DemandedResources,
3532 Cand.ResDelta.DemandedResources,
3533 TryCand, Cand, ResourceDemand))
3534 return;
3535
3536 // Avoid serializing long latency dependence chains.
3537 if (Cand.Policy.ReduceLatency && tryLatency(TryCand, Cand, Top)) {
3538 return;
3539 }
3540
3541 // Fall through to original instruction order.
3542 if (TryCand.SU->NodeNum < Cand.SU->NodeNum)
3543 TryCand.Reason = NodeOrder;
3544 }
3545
pickNodeFromQueue(SchedCandidate & Cand)3546 void PostGenericScheduler::pickNodeFromQueue(SchedCandidate &Cand) {
3547 ReadyQueue &Q = Top.Available;
3548 for (SUnit *SU : Q) {
3549 SchedCandidate TryCand(Cand.Policy);
3550 TryCand.SU = SU;
3551 TryCand.AtTop = true;
3552 TryCand.initResourceDelta(DAG, SchedModel);
3553 tryCandidate(Cand, TryCand);
3554 if (TryCand.Reason != NoCand) {
3555 Cand.setBest(TryCand);
3556 LLVM_DEBUG(traceCandidate(Cand));
3557 }
3558 }
3559 }
3560
3561 /// Pick the next node to schedule.
pickNode(bool & IsTopNode)3562 SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) {
3563 if (DAG->top() == DAG->bottom()) {
3564 assert(Top.Available.empty() && Top.Pending.empty() && "ReadyQ garbage");
3565 return nullptr;
3566 }
3567 SUnit *SU;
3568 do {
3569 SU = Top.pickOnlyChoice();
3570 if (SU) {
3571 tracePick(Only1, true);
3572 } else {
3573 CandPolicy NoPolicy;
3574 SchedCandidate TopCand(NoPolicy);
3575 // Set the top-down policy based on the state of the current top zone and
3576 // the instructions outside the zone, including the bottom zone.
3577 setPolicy(TopCand.Policy, /*IsPostRA=*/true, Top, nullptr);
3578 pickNodeFromQueue(TopCand);
3579 assert(TopCand.Reason != NoCand && "failed to find a candidate");
3580 tracePick(TopCand);
3581 SU = TopCand.SU;
3582 }
3583 } while (SU->isScheduled);
3584
3585 IsTopNode = true;
3586 Top.removeReady(SU);
3587
3588 LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
3589 << *SU->getInstr());
3590 return SU;
3591 }
3592
3593 /// Called after ScheduleDAGMI has scheduled an instruction and updated
3594 /// scheduled/remaining flags in the DAG nodes.
schedNode(SUnit * SU,bool IsTopNode)3595 void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
3596 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.getCurrCycle());
3597 Top.bumpNode(SU);
3598 }
3599
createGenericSchedPostRA(MachineSchedContext * C)3600 ScheduleDAGMI *llvm::createGenericSchedPostRA(MachineSchedContext *C) {
3601 return new ScheduleDAGMI(C, std::make_unique<PostGenericScheduler>(C),
3602 /*RemoveKillFlags=*/true);
3603 }
3604
3605 //===----------------------------------------------------------------------===//
3606 // ILP Scheduler. Currently for experimental analysis of heuristics.
3607 //===----------------------------------------------------------------------===//
3608
3609 namespace {
3610
3611 /// Order nodes by the ILP metric.
3612 struct ILPOrder {
3613 const SchedDFSResult *DFSResult = nullptr;
3614 const BitVector *ScheduledTrees = nullptr;
3615 bool MaximizeILP;
3616
ILPOrder__anon2c8d5d400511::ILPOrder3617 ILPOrder(bool MaxILP) : MaximizeILP(MaxILP) {}
3618
3619 /// Apply a less-than relation on node priority.
3620 ///
3621 /// (Return true if A comes after B in the Q.)
operator ()__anon2c8d5d400511::ILPOrder3622 bool operator()(const SUnit *A, const SUnit *B) const {
3623 unsigned SchedTreeA = DFSResult->getSubtreeID(A);
3624 unsigned SchedTreeB = DFSResult->getSubtreeID(B);
3625 if (SchedTreeA != SchedTreeB) {
3626 // Unscheduled trees have lower priority.
3627 if (ScheduledTrees->test(SchedTreeA) != ScheduledTrees->test(SchedTreeB))
3628 return ScheduledTrees->test(SchedTreeB);
3629
3630 // Trees with shallower connections have have lower priority.
3631 if (DFSResult->getSubtreeLevel(SchedTreeA)
3632 != DFSResult->getSubtreeLevel(SchedTreeB)) {
3633 return DFSResult->getSubtreeLevel(SchedTreeA)
3634 < DFSResult->getSubtreeLevel(SchedTreeB);
3635 }
3636 }
3637 if (MaximizeILP)
3638 return DFSResult->getILP(A) < DFSResult->getILP(B);
3639 else
3640 return DFSResult->getILP(A) > DFSResult->getILP(B);
3641 }
3642 };
3643
3644 /// Schedule based on the ILP metric.
3645 class ILPScheduler : public MachineSchedStrategy {
3646 ScheduleDAGMILive *DAG = nullptr;
3647 ILPOrder Cmp;
3648
3649 std::vector<SUnit*> ReadyQ;
3650
3651 public:
ILPScheduler(bool MaximizeILP)3652 ILPScheduler(bool MaximizeILP) : Cmp(MaximizeILP) {}
3653
initialize(ScheduleDAGMI * dag)3654 void initialize(ScheduleDAGMI *dag) override {
3655 assert(dag->hasVRegLiveness() && "ILPScheduler needs vreg liveness");
3656 DAG = static_cast<ScheduleDAGMILive*>(dag);
3657 DAG->computeDFSResult();
3658 Cmp.DFSResult = DAG->getDFSResult();
3659 Cmp.ScheduledTrees = &DAG->getScheduledTrees();
3660 ReadyQ.clear();
3661 }
3662
registerRoots()3663 void registerRoots() override {
3664 // Restore the heap in ReadyQ with the updated DFS results.
3665 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3666 }
3667
3668 /// Implement MachineSchedStrategy interface.
3669 /// -----------------------------------------
3670
3671 /// Callback to select the highest priority node from the ready Q.
pickNode(bool & IsTopNode)3672 SUnit *pickNode(bool &IsTopNode) override {
3673 if (ReadyQ.empty()) return nullptr;
3674 std::pop_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3675 SUnit *SU = ReadyQ.back();
3676 ReadyQ.pop_back();
3677 IsTopNode = false;
3678 LLVM_DEBUG(dbgs() << "Pick node "
3679 << "SU(" << SU->NodeNum << ") "
3680 << " ILP: " << DAG->getDFSResult()->getILP(SU)
3681 << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU)
3682 << " @"
3683 << DAG->getDFSResult()->getSubtreeLevel(
3684 DAG->getDFSResult()->getSubtreeID(SU))
3685 << '\n'
3686 << "Scheduling " << *SU->getInstr());
3687 return SU;
3688 }
3689
3690 /// Scheduler callback to notify that a new subtree is scheduled.
scheduleTree(unsigned SubtreeID)3691 void scheduleTree(unsigned SubtreeID) override {
3692 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3693 }
3694
3695 /// Callback after a node is scheduled. Mark a newly scheduled tree, notify
3696 /// DFSResults, and resort the priority Q.
schedNode(SUnit * SU,bool IsTopNode)3697 void schedNode(SUnit *SU, bool IsTopNode) override {
3698 assert(!IsTopNode && "SchedDFSResult needs bottom-up");
3699 }
3700
releaseTopNode(SUnit *)3701 void releaseTopNode(SUnit *) override { /*only called for top roots*/ }
3702
releaseBottomNode(SUnit * SU)3703 void releaseBottomNode(SUnit *SU) override {
3704 ReadyQ.push_back(SU);
3705 std::push_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3706 }
3707 };
3708
3709 } // end anonymous namespace
3710
createILPMaxScheduler(MachineSchedContext * C)3711 static ScheduleDAGInstrs *createILPMaxScheduler(MachineSchedContext *C) {
3712 return new ScheduleDAGMILive(C, std::make_unique<ILPScheduler>(true));
3713 }
createILPMinScheduler(MachineSchedContext * C)3714 static ScheduleDAGInstrs *createILPMinScheduler(MachineSchedContext *C) {
3715 return new ScheduleDAGMILive(C, std::make_unique<ILPScheduler>(false));
3716 }
3717
3718 static MachineSchedRegistry ILPMaxRegistry(
3719 "ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler);
3720 static MachineSchedRegistry ILPMinRegistry(
3721 "ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler);
3722
3723 //===----------------------------------------------------------------------===//
3724 // Machine Instruction Shuffler for Correctness Testing
3725 //===----------------------------------------------------------------------===//
3726
3727 #ifndef NDEBUG
3728 namespace {
3729
3730 /// Apply a less-than relation on the node order, which corresponds to the
3731 /// instruction order prior to scheduling. IsReverse implements greater-than.
3732 template<bool IsReverse>
3733 struct SUnitOrder {
operator ()__anon2c8d5d400611::SUnitOrder3734 bool operator()(SUnit *A, SUnit *B) const {
3735 if (IsReverse)
3736 return A->NodeNum > B->NodeNum;
3737 else
3738 return A->NodeNum < B->NodeNum;
3739 }
3740 };
3741
3742 /// Reorder instructions as much as possible.
3743 class InstructionShuffler : public MachineSchedStrategy {
3744 bool IsAlternating;
3745 bool IsTopDown;
3746
3747 // Using a less-than relation (SUnitOrder<false>) for the TopQ priority
3748 // gives nodes with a higher number higher priority causing the latest
3749 // instructions to be scheduled first.
3750 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false>>
3751 TopQ;
3752
3753 // When scheduling bottom-up, use greater-than as the queue priority.
3754 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true>>
3755 BottomQ;
3756
3757 public:
InstructionShuffler(bool alternate,bool topdown)3758 InstructionShuffler(bool alternate, bool topdown)
3759 : IsAlternating(alternate), IsTopDown(topdown) {}
3760
initialize(ScheduleDAGMI *)3761 void initialize(ScheduleDAGMI*) override {
3762 TopQ.clear();
3763 BottomQ.clear();
3764 }
3765
3766 /// Implement MachineSchedStrategy interface.
3767 /// -----------------------------------------
3768
pickNode(bool & IsTopNode)3769 SUnit *pickNode(bool &IsTopNode) override {
3770 SUnit *SU;
3771 if (IsTopDown) {
3772 do {
3773 if (TopQ.empty()) return nullptr;
3774 SU = TopQ.top();
3775 TopQ.pop();
3776 } while (SU->isScheduled);
3777 IsTopNode = true;
3778 } else {
3779 do {
3780 if (BottomQ.empty()) return nullptr;
3781 SU = BottomQ.top();
3782 BottomQ.pop();
3783 } while (SU->isScheduled);
3784 IsTopNode = false;
3785 }
3786 if (IsAlternating)
3787 IsTopDown = !IsTopDown;
3788 return SU;
3789 }
3790
schedNode(SUnit * SU,bool IsTopNode)3791 void schedNode(SUnit *SU, bool IsTopNode) override {}
3792
releaseTopNode(SUnit * SU)3793 void releaseTopNode(SUnit *SU) override {
3794 TopQ.push(SU);
3795 }
releaseBottomNode(SUnit * SU)3796 void releaseBottomNode(SUnit *SU) override {
3797 BottomQ.push(SU);
3798 }
3799 };
3800
3801 } // end anonymous namespace
3802
createInstructionShuffler(MachineSchedContext * C)3803 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
3804 bool Alternate = !ForceTopDown && !ForceBottomUp;
3805 bool TopDown = !ForceBottomUp;
3806 assert((TopDown || !ForceTopDown) &&
3807 "-misched-topdown incompatible with -misched-bottomup");
3808 return new ScheduleDAGMILive(
3809 C, std::make_unique<InstructionShuffler>(Alternate, TopDown));
3810 }
3811
3812 static MachineSchedRegistry ShufflerRegistry(
3813 "shuffle", "Shuffle machine instructions alternating directions",
3814 createInstructionShuffler);
3815 #endif // !NDEBUG
3816
3817 //===----------------------------------------------------------------------===//
3818 // GraphWriter support for ScheduleDAGMILive.
3819 //===----------------------------------------------------------------------===//
3820
3821 #ifndef NDEBUG
3822 namespace llvm {
3823
3824 template<> struct GraphTraits<
3825 ScheduleDAGMI*> : public GraphTraits<ScheduleDAG*> {};
3826
3827 template<>
3828 struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
DOTGraphTraitsllvm::DOTGraphTraits3829 DOTGraphTraits(bool isSimple = false) : DefaultDOTGraphTraits(isSimple) {}
3830
getGraphNamellvm::DOTGraphTraits3831 static std::string getGraphName(const ScheduleDAG *G) {
3832 return std::string(G->MF.getName());
3833 }
3834
renderGraphFromBottomUpllvm::DOTGraphTraits3835 static bool renderGraphFromBottomUp() {
3836 return true;
3837 }
3838
isNodeHiddenllvm::DOTGraphTraits3839 static bool isNodeHidden(const SUnit *Node, const ScheduleDAG *G) {
3840 if (ViewMISchedCutoff == 0)
3841 return false;
3842 return (Node->Preds.size() > ViewMISchedCutoff
3843 || Node->Succs.size() > ViewMISchedCutoff);
3844 }
3845
3846 /// If you want to override the dot attributes printed for a particular
3847 /// edge, override this method.
getEdgeAttributesllvm::DOTGraphTraits3848 static std::string getEdgeAttributes(const SUnit *Node,
3849 SUnitIterator EI,
3850 const ScheduleDAG *Graph) {
3851 if (EI.isArtificialDep())
3852 return "color=cyan,style=dashed";
3853 if (EI.isCtrlDep())
3854 return "color=blue,style=dashed";
3855 return "";
3856 }
3857
getNodeLabelllvm::DOTGraphTraits3858 static std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *G) {
3859 std::string Str;
3860 raw_string_ostream SS(Str);
3861 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G);
3862 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ?
3863 static_cast<const ScheduleDAGMILive*>(G)->getDFSResult() : nullptr;
3864 SS << "SU:" << SU->NodeNum;
3865 if (DFS)
3866 SS << " I:" << DFS->getNumInstrs(SU);
3867 return SS.str();
3868 }
3869
getNodeDescriptionllvm::DOTGraphTraits3870 static std::string getNodeDescription(const SUnit *SU, const ScheduleDAG *G) {
3871 return G->getGraphNodeLabel(SU);
3872 }
3873
getNodeAttributesllvm::DOTGraphTraits3874 static std::string getNodeAttributes(const SUnit *N, const ScheduleDAG *G) {
3875 std::string Str("shape=Mrecord");
3876 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G);
3877 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ?
3878 static_cast<const ScheduleDAGMILive*>(G)->getDFSResult() : nullptr;
3879 if (DFS) {
3880 Str += ",style=filled,fillcolor=\"#";
3881 Str += DOT::getColorString(DFS->getSubtreeID(N));
3882 Str += '"';
3883 }
3884 return Str;
3885 }
3886 };
3887
3888 } // end namespace llvm
3889 #endif // NDEBUG
3890
3891 /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
3892 /// rendered using 'dot'.
viewGraph(const Twine & Name,const Twine & Title)3893 void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) {
3894 #ifndef NDEBUG
3895 ViewGraph(this, Name, false, Title);
3896 #else
3897 errs() << "ScheduleDAGMI::viewGraph is only available in debug builds on "
3898 << "systems with Graphviz or gv!\n";
3899 #endif // NDEBUG
3900 }
3901
3902 /// Out-of-line implementation with no arguments is handy for gdb.
viewGraph()3903 void ScheduleDAGMI::viewGraph() {
3904 viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName());
3905 }
3906