1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides ARM specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "ARMMCTargetDesc.h"
14 #include "ARMAddressingModes.h"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMMCAsmInfo.h"
18 #include "TargetInfo/ARMTargetInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/DebugInfo/CodeView/CodeView.h"
21 #include "llvm/MC/MCAsmBackend.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCELFStreamer.h"
24 #include "llvm/MC/MCInstrAnalysis.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCObjectWriter.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/MC/MCSubtargetInfo.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/TargetParser.h"
32 #include "llvm/Support/TargetRegistry.h"
33
34 using namespace llvm;
35
36 #define GET_REGINFO_MC_DESC
37 #include "ARMGenRegisterInfo.inc"
38
getMCRDeprecationInfo(MCInst & MI,const MCSubtargetInfo & STI,std::string & Info)39 static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
40 std::string &Info) {
41 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
42 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
43 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
44 // Checks for the deprecated CP15ISB encoding:
45 // mcr p15, #0, rX, c7, c5, #4
46 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
47 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
48 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
49 Info = "deprecated since v7, use 'isb'";
50 return true;
51 }
52
53 // Checks for the deprecated CP15DSB encoding:
54 // mcr p15, #0, rX, c7, c10, #4
55 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
56 Info = "deprecated since v7, use 'dsb'";
57 return true;
58 }
59 }
60 // Checks for the deprecated CP15DMB encoding:
61 // mcr p15, #0, rX, c7, c10, #5
62 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
63 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
64 Info = "deprecated since v7, use 'dmb'";
65 return true;
66 }
67 }
68 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
69 ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
70 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
71 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
72 "point instructions";
73 return true;
74 }
75 return false;
76 }
77
getMRCDeprecationInfo(MCInst & MI,const MCSubtargetInfo & STI,std::string & Info)78 static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
79 std::string &Info) {
80 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
81 ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
82 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
83 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
84 "point instructions";
85 return true;
86 }
87 return false;
88 }
89
getITDeprecationInfo(MCInst & MI,const MCSubtargetInfo & STI,std::string & Info)90 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
91 std::string &Info) {
92 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
93 MI.getOperand(1).getImm() != 8) {
94 Info = "applying IT instruction to more than one subsequent instruction is "
95 "deprecated";
96 return true;
97 }
98
99 return false;
100 }
101
getARMStoreDeprecationInfo(MCInst & MI,const MCSubtargetInfo & STI,std::string & Info)102 static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
103 std::string &Info) {
104 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
105 "cannot predicate thumb instructions");
106
107 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
108 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
109 assert(MI.getOperand(OI).isReg() && "expected register");
110 if (MI.getOperand(OI).getReg() == ARM::SP ||
111 MI.getOperand(OI).getReg() == ARM::PC) {
112 Info = "use of SP or PC in the list is deprecated";
113 return true;
114 }
115 }
116 return false;
117 }
118
getARMLoadDeprecationInfo(MCInst & MI,const MCSubtargetInfo & STI,std::string & Info)119 static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
120 std::string &Info) {
121 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
122 "cannot predicate thumb instructions");
123
124 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
125 bool ListContainsPC = false, ListContainsLR = false;
126 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
127 assert(MI.getOperand(OI).isReg() && "expected register");
128 switch (MI.getOperand(OI).getReg()) {
129 default:
130 break;
131 case ARM::LR:
132 ListContainsLR = true;
133 break;
134 case ARM::PC:
135 ListContainsPC = true;
136 break;
137 case ARM::SP:
138 Info = "use of SP in the list is deprecated";
139 return true;
140 }
141 }
142
143 if (ListContainsPC && ListContainsLR) {
144 Info = "use of LR and PC simultaneously in the list is deprecated";
145 return true;
146 }
147
148 return false;
149 }
150
151 #define GET_INSTRINFO_MC_DESC
152 #include "ARMGenInstrInfo.inc"
153
154 #define GET_SUBTARGETINFO_MC_DESC
155 #include "ARMGenSubtargetInfo.inc"
156
ParseARMTriple(const Triple & TT,StringRef CPU)157 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
158 std::string ARMArchFeature;
159
160 ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName());
161 if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic"))
162 ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();
163
164 if (TT.isThumb()) {
165 if (!ARMArchFeature.empty())
166 ARMArchFeature += ",";
167 ARMArchFeature += "+thumb-mode,+v4t";
168 }
169
170 if (TT.isOSNaCl()) {
171 if (!ARMArchFeature.empty())
172 ARMArchFeature += ",";
173 ARMArchFeature += "+nacl-trap";
174 }
175
176 if (TT.isOSWindows()) {
177 if (!ARMArchFeature.empty())
178 ARMArchFeature += ",";
179 ARMArchFeature += "+noarm";
180 }
181
182 return ARMArchFeature;
183 }
184
isPredicated(const MCInst & MI,const MCInstrInfo * MCII)185 bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
186 const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
187 int PredOpIdx = Desc.findFirstPredOperandIdx();
188 return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
189 }
190
isCPSRDefined(const MCInst & MI,const MCInstrInfo * MCII)191 bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) {
192 const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
193 for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
194 const MCOperand &MO = MI.getOperand(I);
195 if (MO.isReg() && MO.getReg() == ARM::CPSR &&
196 Desc.OpInfo[I].isOptionalDef())
197 return true;
198 }
199 return false;
200 }
201
createARMMCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)202 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
203 StringRef CPU, StringRef FS) {
204 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
205 if (!FS.empty()) {
206 if (!ArchFS.empty())
207 ArchFS = (Twine(ArchFS) + "," + FS).str();
208 else
209 ArchFS = std::string(FS);
210 }
211
212 return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
213 }
214
createARMMCInstrInfo()215 static MCInstrInfo *createARMMCInstrInfo() {
216 MCInstrInfo *X = new MCInstrInfo();
217 InitARMMCInstrInfo(X);
218 return X;
219 }
220
initLLVMToCVRegMapping(MCRegisterInfo * MRI)221 void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
222 // Mapping from CodeView to MC register id.
223 static const struct {
224 codeview::RegisterId CVReg;
225 MCPhysReg Reg;
226 } RegMap[] = {
227 {codeview::RegisterId::ARM_R0, ARM::R0},
228 {codeview::RegisterId::ARM_R1, ARM::R1},
229 {codeview::RegisterId::ARM_R2, ARM::R2},
230 {codeview::RegisterId::ARM_R3, ARM::R3},
231 {codeview::RegisterId::ARM_R4, ARM::R4},
232 {codeview::RegisterId::ARM_R5, ARM::R5},
233 {codeview::RegisterId::ARM_R6, ARM::R6},
234 {codeview::RegisterId::ARM_R7, ARM::R7},
235 {codeview::RegisterId::ARM_R8, ARM::R8},
236 {codeview::RegisterId::ARM_R9, ARM::R9},
237 {codeview::RegisterId::ARM_R10, ARM::R10},
238 {codeview::RegisterId::ARM_R11, ARM::R11},
239 {codeview::RegisterId::ARM_R12, ARM::R12},
240 {codeview::RegisterId::ARM_SP, ARM::SP},
241 {codeview::RegisterId::ARM_LR, ARM::LR},
242 {codeview::RegisterId::ARM_PC, ARM::PC},
243 {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
244 {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
245 {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
246 {codeview::RegisterId::ARM_FS0, ARM::S0},
247 {codeview::RegisterId::ARM_FS1, ARM::S1},
248 {codeview::RegisterId::ARM_FS2, ARM::S2},
249 {codeview::RegisterId::ARM_FS3, ARM::S3},
250 {codeview::RegisterId::ARM_FS4, ARM::S4},
251 {codeview::RegisterId::ARM_FS5, ARM::S5},
252 {codeview::RegisterId::ARM_FS6, ARM::S6},
253 {codeview::RegisterId::ARM_FS7, ARM::S7},
254 {codeview::RegisterId::ARM_FS8, ARM::S8},
255 {codeview::RegisterId::ARM_FS9, ARM::S9},
256 {codeview::RegisterId::ARM_FS10, ARM::S10},
257 {codeview::RegisterId::ARM_FS11, ARM::S11},
258 {codeview::RegisterId::ARM_FS12, ARM::S12},
259 {codeview::RegisterId::ARM_FS13, ARM::S13},
260 {codeview::RegisterId::ARM_FS14, ARM::S14},
261 {codeview::RegisterId::ARM_FS15, ARM::S15},
262 {codeview::RegisterId::ARM_FS16, ARM::S16},
263 {codeview::RegisterId::ARM_FS17, ARM::S17},
264 {codeview::RegisterId::ARM_FS18, ARM::S18},
265 {codeview::RegisterId::ARM_FS19, ARM::S19},
266 {codeview::RegisterId::ARM_FS20, ARM::S20},
267 {codeview::RegisterId::ARM_FS21, ARM::S21},
268 {codeview::RegisterId::ARM_FS22, ARM::S22},
269 {codeview::RegisterId::ARM_FS23, ARM::S23},
270 {codeview::RegisterId::ARM_FS24, ARM::S24},
271 {codeview::RegisterId::ARM_FS25, ARM::S25},
272 {codeview::RegisterId::ARM_FS26, ARM::S26},
273 {codeview::RegisterId::ARM_FS27, ARM::S27},
274 {codeview::RegisterId::ARM_FS28, ARM::S28},
275 {codeview::RegisterId::ARM_FS29, ARM::S29},
276 {codeview::RegisterId::ARM_FS30, ARM::S30},
277 {codeview::RegisterId::ARM_FS31, ARM::S31},
278 {codeview::RegisterId::ARM_ND0, ARM::D0},
279 {codeview::RegisterId::ARM_ND1, ARM::D1},
280 {codeview::RegisterId::ARM_ND2, ARM::D2},
281 {codeview::RegisterId::ARM_ND3, ARM::D3},
282 {codeview::RegisterId::ARM_ND4, ARM::D4},
283 {codeview::RegisterId::ARM_ND5, ARM::D5},
284 {codeview::RegisterId::ARM_ND6, ARM::D6},
285 {codeview::RegisterId::ARM_ND7, ARM::D7},
286 {codeview::RegisterId::ARM_ND8, ARM::D8},
287 {codeview::RegisterId::ARM_ND9, ARM::D9},
288 {codeview::RegisterId::ARM_ND10, ARM::D10},
289 {codeview::RegisterId::ARM_ND11, ARM::D11},
290 {codeview::RegisterId::ARM_ND12, ARM::D12},
291 {codeview::RegisterId::ARM_ND13, ARM::D13},
292 {codeview::RegisterId::ARM_ND14, ARM::D14},
293 {codeview::RegisterId::ARM_ND15, ARM::D15},
294 {codeview::RegisterId::ARM_ND16, ARM::D16},
295 {codeview::RegisterId::ARM_ND17, ARM::D17},
296 {codeview::RegisterId::ARM_ND18, ARM::D18},
297 {codeview::RegisterId::ARM_ND19, ARM::D19},
298 {codeview::RegisterId::ARM_ND20, ARM::D20},
299 {codeview::RegisterId::ARM_ND21, ARM::D21},
300 {codeview::RegisterId::ARM_ND22, ARM::D22},
301 {codeview::RegisterId::ARM_ND23, ARM::D23},
302 {codeview::RegisterId::ARM_ND24, ARM::D24},
303 {codeview::RegisterId::ARM_ND25, ARM::D25},
304 {codeview::RegisterId::ARM_ND26, ARM::D26},
305 {codeview::RegisterId::ARM_ND27, ARM::D27},
306 {codeview::RegisterId::ARM_ND28, ARM::D28},
307 {codeview::RegisterId::ARM_ND29, ARM::D29},
308 {codeview::RegisterId::ARM_ND30, ARM::D30},
309 {codeview::RegisterId::ARM_ND31, ARM::D31},
310 {codeview::RegisterId::ARM_NQ0, ARM::Q0},
311 {codeview::RegisterId::ARM_NQ1, ARM::Q1},
312 {codeview::RegisterId::ARM_NQ2, ARM::Q2},
313 {codeview::RegisterId::ARM_NQ3, ARM::Q3},
314 {codeview::RegisterId::ARM_NQ4, ARM::Q4},
315 {codeview::RegisterId::ARM_NQ5, ARM::Q5},
316 {codeview::RegisterId::ARM_NQ6, ARM::Q6},
317 {codeview::RegisterId::ARM_NQ7, ARM::Q7},
318 {codeview::RegisterId::ARM_NQ8, ARM::Q8},
319 {codeview::RegisterId::ARM_NQ9, ARM::Q9},
320 {codeview::RegisterId::ARM_NQ10, ARM::Q10},
321 {codeview::RegisterId::ARM_NQ11, ARM::Q11},
322 {codeview::RegisterId::ARM_NQ12, ARM::Q12},
323 {codeview::RegisterId::ARM_NQ13, ARM::Q13},
324 {codeview::RegisterId::ARM_NQ14, ARM::Q14},
325 {codeview::RegisterId::ARM_NQ15, ARM::Q15},
326 };
327 for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
328 MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
329 }
330
createARMMCRegisterInfo(const Triple & Triple)331 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
332 MCRegisterInfo *X = new MCRegisterInfo();
333 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
334 ARM_MC::initLLVMToCVRegMapping(X);
335 return X;
336 }
337
createARMMCAsmInfo(const MCRegisterInfo & MRI,const Triple & TheTriple,const MCTargetOptions & Options)338 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
339 const Triple &TheTriple,
340 const MCTargetOptions &Options) {
341 MCAsmInfo *MAI;
342 if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
343 MAI = new ARMMCAsmInfoDarwin(TheTriple);
344 else if (TheTriple.isWindowsMSVCEnvironment())
345 MAI = new ARMCOFFMCAsmInfoMicrosoft();
346 else if (TheTriple.isOSWindows())
347 MAI = new ARMCOFFMCAsmInfoGNU();
348 else
349 MAI = new ARMELFMCAsmInfo(TheTriple);
350
351 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
352 MAI->addInitialFrameState(MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0));
353
354 return MAI;
355 }
356
createELFStreamer(const Triple & T,MCContext & Ctx,std::unique_ptr<MCAsmBackend> && MAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter,bool RelaxAll)357 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
358 std::unique_ptr<MCAsmBackend> &&MAB,
359 std::unique_ptr<MCObjectWriter> &&OW,
360 std::unique_ptr<MCCodeEmitter> &&Emitter,
361 bool RelaxAll) {
362 return createARMELFStreamer(
363 Ctx, std::move(MAB), std::move(OW), std::move(Emitter), false,
364 (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb),
365 T.isAndroid());
366 }
367
368 static MCStreamer *
createARMMachOStreamer(MCContext & Ctx,std::unique_ptr<MCAsmBackend> && MAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter,bool RelaxAll,bool DWARFMustBeAtTheEnd)369 createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
370 std::unique_ptr<MCObjectWriter> &&OW,
371 std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
372 bool DWARFMustBeAtTheEnd) {
373 return createMachOStreamer(Ctx, std::move(MAB), std::move(OW),
374 std::move(Emitter), false, DWARFMustBeAtTheEnd);
375 }
376
createARMMCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)377 static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
378 unsigned SyntaxVariant,
379 const MCAsmInfo &MAI,
380 const MCInstrInfo &MII,
381 const MCRegisterInfo &MRI) {
382 if (SyntaxVariant == 0)
383 return new ARMInstPrinter(MAI, MII, MRI);
384 return nullptr;
385 }
386
createARMMCRelocationInfo(const Triple & TT,MCContext & Ctx)387 static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
388 MCContext &Ctx) {
389 if (TT.isOSBinFormatMachO())
390 return createARMMachORelocationInfo(Ctx);
391 // Default to the stock relocation info.
392 return llvm::createMCRelocationInfo(TT, Ctx);
393 }
394
395 namespace {
396
397 class ARMMCInstrAnalysis : public MCInstrAnalysis {
398 public:
ARMMCInstrAnalysis(const MCInstrInfo * Info)399 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
400
isUnconditionalBranch(const MCInst & Inst) const401 bool isUnconditionalBranch(const MCInst &Inst) const override {
402 // BCCs with the "always" predicate are unconditional branches.
403 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
404 return true;
405 return MCInstrAnalysis::isUnconditionalBranch(Inst);
406 }
407
isConditionalBranch(const MCInst & Inst) const408 bool isConditionalBranch(const MCInst &Inst) const override {
409 // BCCs with the "always" predicate are unconditional branches.
410 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
411 return false;
412 return MCInstrAnalysis::isConditionalBranch(Inst);
413 }
414
evaluateBranch(const MCInst & Inst,uint64_t Addr,uint64_t Size,uint64_t & Target) const415 bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
416 uint64_t Size, uint64_t &Target) const override {
417 // We only handle PCRel branches for now.
418 if (Inst.getNumOperands() == 0 ||
419 Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=
420 MCOI::OPERAND_PCREL)
421 return false;
422
423 int64_t Imm = Inst.getOperand(0).getImm();
424 Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
425 return true;
426 }
427 };
428
429 class ThumbMCInstrAnalysis : public ARMMCInstrAnalysis {
430 public:
ThumbMCInstrAnalysis(const MCInstrInfo * Info)431 ThumbMCInstrAnalysis(const MCInstrInfo *Info) : ARMMCInstrAnalysis(Info) {}
432
evaluateBranch(const MCInst & Inst,uint64_t Addr,uint64_t Size,uint64_t & Target) const433 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
434 uint64_t &Target) const override {
435 unsigned OpId;
436 switch (Inst.getOpcode()) {
437 default:
438 OpId = 0;
439 if (Inst.getNumOperands() == 0)
440 return false;
441 break;
442 case ARM::MVE_WLSTP_8:
443 case ARM::MVE_WLSTP_16:
444 case ARM::MVE_WLSTP_32:
445 case ARM::MVE_WLSTP_64:
446 case ARM::t2WLS:
447 case ARM::MVE_LETP:
448 case ARM::t2LEUpdate:
449 OpId = 2;
450 break;
451 case ARM::t2LE:
452 OpId = 1;
453 break;
454 }
455
456 // We only handle PCRel branches for now.
457 if (Info->get(Inst.getOpcode()).OpInfo[OpId].OperandType !=
458 MCOI::OPERAND_PCREL)
459 return false;
460
461 // In Thumb mode the PC is always off by 4 bytes.
462 Target = Addr + Inst.getOperand(OpId).getImm() + 4;
463 return true;
464 }
465 };
466
467 }
468
createARMMCInstrAnalysis(const MCInstrInfo * Info)469 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
470 return new ARMMCInstrAnalysis(Info);
471 }
472
createThumbMCInstrAnalysis(const MCInstrInfo * Info)473 static MCInstrAnalysis *createThumbMCInstrAnalysis(const MCInstrInfo *Info) {
474 return new ThumbMCInstrAnalysis(Info);
475 }
476
isCDECoproc(size_t Coproc,const MCSubtargetInfo & STI)477 bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) {
478 // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
479 // to rely on feature bits.
480 if (Coproc >= 8)
481 return false;
482 return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc];
483 }
484
485 // Force static initialization.
LLVMInitializeARMTargetMC()486 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC() {
487 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
488 &getTheThumbLETarget(), &getTheThumbBETarget()}) {
489 // Register the MC asm info.
490 RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
491
492 // Register the MC instruction info.
493 TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo);
494
495 // Register the MC register info.
496 TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo);
497
498 // Register the MC subtarget info.
499 TargetRegistry::RegisterMCSubtargetInfo(*T,
500 ARM_MC::createARMMCSubtargetInfo);
501
502 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
503 TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer);
504 TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer);
505
506 // Register the obj target streamer.
507 TargetRegistry::RegisterObjectTargetStreamer(*T,
508 createARMObjectTargetStreamer);
509
510 // Register the asm streamer.
511 TargetRegistry::RegisterAsmTargetStreamer(*T, createARMTargetAsmStreamer);
512
513 // Register the null TargetStreamer.
514 TargetRegistry::RegisterNullTargetStreamer(*T, createARMNullTargetStreamer);
515
516 // Register the MCInstPrinter.
517 TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter);
518
519 // Register the MC relocation info.
520 TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo);
521 }
522
523 // Register the MC instruction analyzer.
524 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget()})
525 TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis);
526 for (Target *T : {&getTheThumbLETarget(), &getTheThumbBETarget()})
527 TargetRegistry::RegisterMCInstrAnalysis(*T, createThumbMCInstrAnalysis);
528
529 for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) {
530 TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter);
531 TargetRegistry::RegisterMCAsmBackend(*T, createARMLEAsmBackend);
532 }
533 for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) {
534 TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter);
535 TargetRegistry::RegisterMCAsmBackend(*T, createARMBEAsmBackend);
536 }
537 }
538